./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix055_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix055_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 49e528b42e7d64c645b3746e744daaad6dd6ce41 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 21:20:22,379 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 21:20:22,380 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 21:20:22,388 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 21:20:22,388 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 21:20:22,389 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 21:20:22,390 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 21:20:22,391 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 21:20:22,392 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 21:20:22,393 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 21:20:22,393 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 21:20:22,394 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 21:20:22,394 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 21:20:22,395 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 21:20:22,396 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 21:20:22,396 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 21:20:22,397 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 21:20:22,398 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 21:20:22,399 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 21:20:22,400 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 21:20:22,401 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 21:20:22,402 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 21:20:22,403 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 21:20:22,403 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 21:20:22,405 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 21:20:22,405 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 21:20:22,405 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 21:20:22,406 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 21:20:22,406 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 21:20:22,406 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 21:20:22,407 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 21:20:22,407 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 21:20:22,407 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 21:20:22,408 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 21:20:22,408 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 21:20:22,409 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 21:20:22,409 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 21:20:22,409 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 21:20:22,409 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 21:20:22,410 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 21:20:22,410 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 21:20:22,411 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 21:20:22,421 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 21:20:22,421 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 21:20:22,422 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 21:20:22,422 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 21:20:22,422 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 21:20:22,423 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 21:20:22,423 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 21:20:22,423 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 21:20:22,423 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 21:20:22,423 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 21:20:22,424 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 21:20:22,424 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 21:20:22,425 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 21:20:22,425 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 21:20:22,425 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 21:20:22,426 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 49e528b42e7d64c645b3746e744daaad6dd6ce41 [2019-12-07 21:20:22,524 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 21:20:22,535 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 21:20:22,538 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 21:20:22,539 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 21:20:22,540 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 21:20:22,540 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/mix055_power.opt.i [2019-12-07 21:20:22,582 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/data/8e1d9fc0f/9caaffc879834e4abc8ac4acdd2f72ab/FLAG1a72295fc [2019-12-07 21:20:22,954 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 21:20:22,954 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/sv-benchmarks/c/pthread-wmm/mix055_power.opt.i [2019-12-07 21:20:22,964 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/data/8e1d9fc0f/9caaffc879834e4abc8ac4acdd2f72ab/FLAG1a72295fc [2019-12-07 21:20:22,973 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/data/8e1d9fc0f/9caaffc879834e4abc8ac4acdd2f72ab [2019-12-07 21:20:22,975 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 21:20:22,976 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 21:20:22,976 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 21:20:22,976 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 21:20:22,979 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 21:20:22,979 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 09:20:22" (1/1) ... [2019-12-07 21:20:22,981 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a2ff042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:22, skipping insertion in model container [2019-12-07 21:20:22,981 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 09:20:22" (1/1) ... [2019-12-07 21:20:22,985 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 21:20:23,023 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 21:20:23,269 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 21:20:23,276 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 21:20:23,317 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 21:20:23,362 INFO L208 MainTranslator]: Completed translation [2019-12-07 21:20:23,362 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23 WrapperNode [2019-12-07 21:20:23,362 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 21:20:23,363 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 21:20:23,363 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 21:20:23,363 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 21:20:23,368 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,381 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,402 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 21:20:23,402 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 21:20:23,402 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 21:20:23,402 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 21:20:23,409 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,409 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,412 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,412 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,419 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,422 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,424 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... [2019-12-07 21:20:23,428 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 21:20:23,428 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 21:20:23,428 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 21:20:23,428 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 21:20:23,429 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 21:20:23,471 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 21:20:23,471 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 21:20:23,471 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 21:20:23,471 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 21:20:23,472 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 21:20:23,472 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 21:20:23,472 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 21:20:23,472 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 21:20:23,473 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 21:20:23,828 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 21:20:23,828 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 21:20:23,829 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 09:20:23 BoogieIcfgContainer [2019-12-07 21:20:23,829 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 21:20:23,830 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 21:20:23,830 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 21:20:23,832 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 21:20:23,832 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 09:20:22" (1/3) ... [2019-12-07 21:20:23,832 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@160c534a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 09:20:23, skipping insertion in model container [2019-12-07 21:20:23,832 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 09:20:23" (2/3) ... [2019-12-07 21:20:23,833 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@160c534a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 09:20:23, skipping insertion in model container [2019-12-07 21:20:23,833 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 09:20:23" (3/3) ... [2019-12-07 21:20:23,834 INFO L109 eAbstractionObserver]: Analyzing ICFG mix055_power.opt.i [2019-12-07 21:20:23,840 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 21:20:23,840 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 21:20:23,845 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 21:20:23,845 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 21:20:23,869 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,869 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,869 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,869 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,870 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,871 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,871 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,871 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,871 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,871 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,872 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,872 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,872 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,872 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,872 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,874 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,874 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,874 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,874 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,874 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,877 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,877 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,878 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,879 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,879 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,879 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,879 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,879 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,880 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,880 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,880 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,880 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,880 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,881 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,882 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,882 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,882 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,882 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,882 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,883 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,883 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,883 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,883 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 21:20:23,899 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 21:20:23,915 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 21:20:23,915 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 21:20:23,916 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 21:20:23,916 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 21:20:23,916 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 21:20:23,916 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 21:20:23,916 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 21:20:23,916 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 21:20:23,927 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 207 transitions [2019-12-07 21:20:23,928 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 21:20:23,983 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 21:20:23,983 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 21:20:23,992 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 21:20:24,003 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 21:20:24,031 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 21:20:24,031 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 21:20:24,035 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 21:20:24,047 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 21:20:24,047 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 21:20:26,866 WARN L192 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 93 [2019-12-07 21:20:26,961 INFO L206 etLargeBlockEncoding]: Checked pairs total: 50860 [2019-12-07 21:20:26,962 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 21:20:26,964 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 97 transitions [2019-12-07 21:20:28,819 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34622 states. [2019-12-07 21:20:28,820 INFO L276 IsEmpty]: Start isEmpty. Operand 34622 states. [2019-12-07 21:20:28,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 21:20:28,825 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:28,825 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:28,826 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:28,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:28,829 INFO L82 PathProgramCache]: Analyzing trace with hash 1893967926, now seen corresponding path program 1 times [2019-12-07 21:20:28,835 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:28,835 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176157415] [2019-12-07 21:20:28,835 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:28,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:28,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:28,988 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176157415] [2019-12-07 21:20:28,988 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:28,988 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 21:20:28,989 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525585938] [2019-12-07 21:20:28,992 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 21:20:28,992 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:29,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 21:20:29,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:29,003 INFO L87 Difference]: Start difference. First operand 34622 states. Second operand 3 states. [2019-12-07 21:20:29,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:29,332 INFO L93 Difference]: Finished difference Result 34366 states and 145832 transitions. [2019-12-07 21:20:29,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 21:20:29,333 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 21:20:29,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:29,556 INFO L225 Difference]: With dead ends: 34366 [2019-12-07 21:20:29,557 INFO L226 Difference]: Without dead ends: 33694 [2019-12-07 21:20:29,557 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:29,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33694 states. [2019-12-07 21:20:30,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33694 to 33694. [2019-12-07 21:20:30,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33694 states. [2019-12-07 21:20:30,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33694 states to 33694 states and 143088 transitions. [2019-12-07 21:20:30,635 INFO L78 Accepts]: Start accepts. Automaton has 33694 states and 143088 transitions. Word has length 9 [2019-12-07 21:20:30,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:30,636 INFO L462 AbstractCegarLoop]: Abstraction has 33694 states and 143088 transitions. [2019-12-07 21:20:30,636 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 21:20:30,636 INFO L276 IsEmpty]: Start isEmpty. Operand 33694 states and 143088 transitions. [2019-12-07 21:20:30,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 21:20:30,641 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:30,641 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:30,642 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:30,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:30,642 INFO L82 PathProgramCache]: Analyzing trace with hash 706074371, now seen corresponding path program 1 times [2019-12-07 21:20:30,642 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:30,642 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574095241] [2019-12-07 21:20:30,642 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:30,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:30,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:30,699 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574095241] [2019-12-07 21:20:30,699 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:30,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 21:20:30,700 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418827494] [2019-12-07 21:20:30,701 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 21:20:30,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:30,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 21:20:30,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 21:20:30,701 INFO L87 Difference]: Start difference. First operand 33694 states and 143088 transitions. Second operand 4 states. [2019-12-07 21:20:31,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:31,317 INFO L93 Difference]: Finished difference Result 52350 states and 214840 transitions. [2019-12-07 21:20:31,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 21:20:31,318 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 21:20:31,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:31,577 INFO L225 Difference]: With dead ends: 52350 [2019-12-07 21:20:31,577 INFO L226 Difference]: Without dead ends: 52322 [2019-12-07 21:20:31,578 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:31,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52322 states. [2019-12-07 21:20:32,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52322 to 47546. [2019-12-07 21:20:32,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47546 states. [2019-12-07 21:20:32,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47546 states to 47546 states and 197076 transitions. [2019-12-07 21:20:32,688 INFO L78 Accepts]: Start accepts. Automaton has 47546 states and 197076 transitions. Word has length 15 [2019-12-07 21:20:32,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:32,688 INFO L462 AbstractCegarLoop]: Abstraction has 47546 states and 197076 transitions. [2019-12-07 21:20:32,688 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 21:20:32,688 INFO L276 IsEmpty]: Start isEmpty. Operand 47546 states and 197076 transitions. [2019-12-07 21:20:32,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 21:20:32,690 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:32,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:32,690 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:32,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:32,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1899832342, now seen corresponding path program 1 times [2019-12-07 21:20:32,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:32,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670346236] [2019-12-07 21:20:32,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:32,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:32,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:32,737 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670346236] [2019-12-07 21:20:32,737 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:32,737 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 21:20:32,737 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172521735] [2019-12-07 21:20:32,738 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 21:20:32,738 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:32,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 21:20:32,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 21:20:32,738 INFO L87 Difference]: Start difference. First operand 47546 states and 197076 transitions. Second operand 4 states. [2019-12-07 21:20:33,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:33,205 INFO L93 Difference]: Finished difference Result 58566 states and 240916 transitions. [2019-12-07 21:20:33,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 21:20:33,206 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 21:20:33,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:33,345 INFO L225 Difference]: With dead ends: 58566 [2019-12-07 21:20:33,346 INFO L226 Difference]: Without dead ends: 58566 [2019-12-07 21:20:33,346 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:33,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58566 states. [2019-12-07 21:20:34,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58566 to 52262. [2019-12-07 21:20:34,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52262 states. [2019-12-07 21:20:34,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52262 states to 52262 states and 216300 transitions. [2019-12-07 21:20:34,554 INFO L78 Accepts]: Start accepts. Automaton has 52262 states and 216300 transitions. Word has length 15 [2019-12-07 21:20:34,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:34,555 INFO L462 AbstractCegarLoop]: Abstraction has 52262 states and 216300 transitions. [2019-12-07 21:20:34,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 21:20:34,555 INFO L276 IsEmpty]: Start isEmpty. Operand 52262 states and 216300 transitions. [2019-12-07 21:20:34,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 21:20:34,567 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:34,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:34,567 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:34,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:34,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1099673125, now seen corresponding path program 1 times [2019-12-07 21:20:34,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:34,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915141402] [2019-12-07 21:20:34,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:34,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:34,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:34,637 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915141402] [2019-12-07 21:20:34,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:34,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 21:20:34,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382011639] [2019-12-07 21:20:34,638 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 21:20:34,638 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:34,638 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 21:20:34,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 21:20:34,639 INFO L87 Difference]: Start difference. First operand 52262 states and 216300 transitions. Second operand 4 states. [2019-12-07 21:20:34,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:34,801 INFO L93 Difference]: Finished difference Result 41984 states and 159713 transitions. [2019-12-07 21:20:34,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 21:20:34,802 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2019-12-07 21:20:34,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:34,880 INFO L225 Difference]: With dead ends: 41984 [2019-12-07 21:20:34,880 INFO L226 Difference]: Without dead ends: 40876 [2019-12-07 21:20:34,881 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:35,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40876 states. [2019-12-07 21:20:35,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40876 to 40876. [2019-12-07 21:20:35,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40876 states. [2019-12-07 21:20:35,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40876 states to 40876 states and 156237 transitions. [2019-12-07 21:20:35,707 INFO L78 Accepts]: Start accepts. Automaton has 40876 states and 156237 transitions. Word has length 21 [2019-12-07 21:20:35,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:35,707 INFO L462 AbstractCegarLoop]: Abstraction has 40876 states and 156237 transitions. [2019-12-07 21:20:35,708 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 21:20:35,708 INFO L276 IsEmpty]: Start isEmpty. Operand 40876 states and 156237 transitions. [2019-12-07 21:20:35,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 21:20:35,715 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:35,715 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:35,715 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:35,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:35,716 INFO L82 PathProgramCache]: Analyzing trace with hash 637645513, now seen corresponding path program 1 times [2019-12-07 21:20:35,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:35,716 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015819924] [2019-12-07 21:20:35,716 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:35,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:35,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:35,764 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015819924] [2019-12-07 21:20:35,764 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:35,764 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 21:20:35,764 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834386280] [2019-12-07 21:20:35,764 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 21:20:35,764 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:35,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 21:20:35,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:35,765 INFO L87 Difference]: Start difference. First operand 40876 states and 156237 transitions. Second operand 5 states. [2019-12-07 21:20:36,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:36,178 INFO L93 Difference]: Finished difference Result 54396 states and 204140 transitions. [2019-12-07 21:20:36,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 21:20:36,179 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 21:20:36,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:36,288 INFO L225 Difference]: With dead ends: 54396 [2019-12-07 21:20:36,289 INFO L226 Difference]: Without dead ends: 54375 [2019-12-07 21:20:36,289 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 21:20:36,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54375 states. [2019-12-07 21:20:37,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54375 to 41122. [2019-12-07 21:20:37,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41122 states. [2019-12-07 21:20:37,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41122 states to 41122 states and 156869 transitions. [2019-12-07 21:20:37,203 INFO L78 Accepts]: Start accepts. Automaton has 41122 states and 156869 transitions. Word has length 22 [2019-12-07 21:20:37,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:37,203 INFO L462 AbstractCegarLoop]: Abstraction has 41122 states and 156869 transitions. [2019-12-07 21:20:37,203 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 21:20:37,203 INFO L276 IsEmpty]: Start isEmpty. Operand 41122 states and 156869 transitions. [2019-12-07 21:20:37,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 21:20:37,225 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:37,226 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:37,226 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:37,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:37,226 INFO L82 PathProgramCache]: Analyzing trace with hash -2027557007, now seen corresponding path program 1 times [2019-12-07 21:20:37,226 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:37,226 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440402333] [2019-12-07 21:20:37,226 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:37,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:37,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:37,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440402333] [2019-12-07 21:20:37,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:37,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 21:20:37,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382127818] [2019-12-07 21:20:37,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 21:20:37,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:37,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 21:20:37,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:37,256 INFO L87 Difference]: Start difference. First operand 41122 states and 156869 transitions. Second operand 3 states. [2019-12-07 21:20:37,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:37,466 INFO L93 Difference]: Finished difference Result 51974 states and 196153 transitions. [2019-12-07 21:20:37,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 21:20:37,467 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2019-12-07 21:20:37,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:37,572 INFO L225 Difference]: With dead ends: 51974 [2019-12-07 21:20:37,572 INFO L226 Difference]: Without dead ends: 51974 [2019-12-07 21:20:37,572 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:37,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51974 states. [2019-12-07 21:20:38,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51974 to 45309. [2019-12-07 21:20:38,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45309 states. [2019-12-07 21:20:38,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45309 states to 45309 states and 172388 transitions. [2019-12-07 21:20:38,504 INFO L78 Accepts]: Start accepts. Automaton has 45309 states and 172388 transitions. Word has length 30 [2019-12-07 21:20:38,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:38,505 INFO L462 AbstractCegarLoop]: Abstraction has 45309 states and 172388 transitions. [2019-12-07 21:20:38,505 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 21:20:38,505 INFO L276 IsEmpty]: Start isEmpty. Operand 45309 states and 172388 transitions. [2019-12-07 21:20:38,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 21:20:38,528 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:38,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:38,528 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:38,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:38,528 INFO L82 PathProgramCache]: Analyzing trace with hash -2027793723, now seen corresponding path program 1 times [2019-12-07 21:20:38,528 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:38,528 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639583960] [2019-12-07 21:20:38,528 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:38,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:38,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:38,575 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639583960] [2019-12-07 21:20:38,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:38,575 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 21:20:38,576 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051663644] [2019-12-07 21:20:38,576 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 21:20:38,576 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:38,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 21:20:38,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:38,576 INFO L87 Difference]: Start difference. First operand 45309 states and 172388 transitions. Second operand 5 states. [2019-12-07 21:20:38,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:38,657 INFO L93 Difference]: Finished difference Result 19765 states and 62245 transitions. [2019-12-07 21:20:38,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 21:20:38,657 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2019-12-07 21:20:38,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:38,680 INFO L225 Difference]: With dead ends: 19765 [2019-12-07 21:20:38,681 INFO L226 Difference]: Without dead ends: 18889 [2019-12-07 21:20:38,681 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 21:20:38,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18889 states. [2019-12-07 21:20:38,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18889 to 18889. [2019-12-07 21:20:38,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18889 states. [2019-12-07 21:20:38,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18889 states to 18889 states and 59447 transitions. [2019-12-07 21:20:38,946 INFO L78 Accepts]: Start accepts. Automaton has 18889 states and 59447 transitions. Word has length 30 [2019-12-07 21:20:38,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:38,947 INFO L462 AbstractCegarLoop]: Abstraction has 18889 states and 59447 transitions. [2019-12-07 21:20:38,947 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 21:20:38,947 INFO L276 IsEmpty]: Start isEmpty. Operand 18889 states and 59447 transitions. [2019-12-07 21:20:38,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 21:20:38,956 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:38,956 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:38,956 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:38,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:38,956 INFO L82 PathProgramCache]: Analyzing trace with hash -1945851485, now seen corresponding path program 1 times [2019-12-07 21:20:38,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:38,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249389266] [2019-12-07 21:20:38,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:38,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:39,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:39,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249389266] [2019-12-07 21:20:39,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:39,007 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 21:20:39,007 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382795795] [2019-12-07 21:20:39,008 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 21:20:39,008 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:39,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 21:20:39,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 21:20:39,008 INFO L87 Difference]: Start difference. First operand 18889 states and 59447 transitions. Second operand 6 states. [2019-12-07 21:20:39,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:39,064 INFO L93 Difference]: Finished difference Result 3470 states and 8793 transitions. [2019-12-07 21:20:39,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 21:20:39,065 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2019-12-07 21:20:39,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:39,068 INFO L225 Difference]: With dead ends: 3470 [2019-12-07 21:20:39,068 INFO L226 Difference]: Without dead ends: 3101 [2019-12-07 21:20:39,068 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 21:20:39,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3101 states. [2019-12-07 21:20:39,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3101 to 3101. [2019-12-07 21:20:39,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3101 states. [2019-12-07 21:20:39,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3101 states to 3101 states and 7755 transitions. [2019-12-07 21:20:39,100 INFO L78 Accepts]: Start accepts. Automaton has 3101 states and 7755 transitions. Word has length 31 [2019-12-07 21:20:39,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:39,100 INFO L462 AbstractCegarLoop]: Abstraction has 3101 states and 7755 transitions. [2019-12-07 21:20:39,100 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 21:20:39,100 INFO L276 IsEmpty]: Start isEmpty. Operand 3101 states and 7755 transitions. [2019-12-07 21:20:39,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 21:20:39,103 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:39,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:39,104 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:39,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:39,104 INFO L82 PathProgramCache]: Analyzing trace with hash -476238483, now seen corresponding path program 1 times [2019-12-07 21:20:39,104 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:39,104 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480629167] [2019-12-07 21:20:39,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:39,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:39,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:39,170 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480629167] [2019-12-07 21:20:39,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:39,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 21:20:39,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416664371] [2019-12-07 21:20:39,171 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 21:20:39,171 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:39,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 21:20:39,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 21:20:39,172 INFO L87 Difference]: Start difference. First operand 3101 states and 7755 transitions. Second operand 7 states. [2019-12-07 21:20:39,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:39,240 INFO L93 Difference]: Finished difference Result 1342 states and 3750 transitions. [2019-12-07 21:20:39,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 21:20:39,241 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 43 [2019-12-07 21:20:39,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:39,242 INFO L225 Difference]: With dead ends: 1342 [2019-12-07 21:20:39,242 INFO L226 Difference]: Without dead ends: 1293 [2019-12-07 21:20:39,242 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 21:20:39,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-12-07 21:20:39,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 1181. [2019-12-07 21:20:39,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1181 states. [2019-12-07 21:20:39,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 3334 transitions. [2019-12-07 21:20:39,254 INFO L78 Accepts]: Start accepts. Automaton has 1181 states and 3334 transitions. Word has length 43 [2019-12-07 21:20:39,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:39,254 INFO L462 AbstractCegarLoop]: Abstraction has 1181 states and 3334 transitions. [2019-12-07 21:20:39,254 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 21:20:39,254 INFO L276 IsEmpty]: Start isEmpty. Operand 1181 states and 3334 transitions. [2019-12-07 21:20:39,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 21:20:39,256 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:39,256 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:39,256 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:39,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:39,256 INFO L82 PathProgramCache]: Analyzing trace with hash -409088440, now seen corresponding path program 1 times [2019-12-07 21:20:39,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:39,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523652983] [2019-12-07 21:20:39,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:39,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:39,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:39,315 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523652983] [2019-12-07 21:20:39,316 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:39,316 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 21:20:39,316 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168373165] [2019-12-07 21:20:39,316 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 21:20:39,316 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:39,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 21:20:39,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 21:20:39,317 INFO L87 Difference]: Start difference. First operand 1181 states and 3334 transitions. Second operand 5 states. [2019-12-07 21:20:39,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:39,458 INFO L93 Difference]: Finished difference Result 1666 states and 4696 transitions. [2019-12-07 21:20:39,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 21:20:39,458 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 21:20:39,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:39,460 INFO L225 Difference]: With dead ends: 1666 [2019-12-07 21:20:39,460 INFO L226 Difference]: Without dead ends: 1666 [2019-12-07 21:20:39,460 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 21:20:39,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1666 states. [2019-12-07 21:20:39,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1666 to 1470. [2019-12-07 21:20:39,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1470 states. [2019-12-07 21:20:39,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1470 states to 1470 states and 4144 transitions. [2019-12-07 21:20:39,476 INFO L78 Accepts]: Start accepts. Automaton has 1470 states and 4144 transitions. Word has length 58 [2019-12-07 21:20:39,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:39,476 INFO L462 AbstractCegarLoop]: Abstraction has 1470 states and 4144 transitions. [2019-12-07 21:20:39,476 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 21:20:39,476 INFO L276 IsEmpty]: Start isEmpty. Operand 1470 states and 4144 transitions. [2019-12-07 21:20:39,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 21:20:39,478 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:39,478 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:39,478 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:39,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:39,478 INFO L82 PathProgramCache]: Analyzing trace with hash -2087231872, now seen corresponding path program 2 times [2019-12-07 21:20:39,478 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:39,479 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052831502] [2019-12-07 21:20:39,479 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:39,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:39,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:39,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052831502] [2019-12-07 21:20:39,542 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:39,542 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 21:20:39,542 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146390482] [2019-12-07 21:20:39,543 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 21:20:39,543 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:39,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 21:20:39,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 21:20:39,543 INFO L87 Difference]: Start difference. First operand 1470 states and 4144 transitions. Second operand 6 states. [2019-12-07 21:20:39,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:39,731 INFO L93 Difference]: Finished difference Result 1745 states and 4788 transitions. [2019-12-07 21:20:39,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 21:20:39,732 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 21:20:39,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:39,734 INFO L225 Difference]: With dead ends: 1745 [2019-12-07 21:20:39,734 INFO L226 Difference]: Without dead ends: 1745 [2019-12-07 21:20:39,734 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 21:20:39,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1745 states. [2019-12-07 21:20:39,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1745 to 1522. [2019-12-07 21:20:39,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1522 states. [2019-12-07 21:20:39,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1522 states to 1522 states and 4220 transitions. [2019-12-07 21:20:39,749 INFO L78 Accepts]: Start accepts. Automaton has 1522 states and 4220 transitions. Word has length 58 [2019-12-07 21:20:39,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:39,749 INFO L462 AbstractCegarLoop]: Abstraction has 1522 states and 4220 transitions. [2019-12-07 21:20:39,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 21:20:39,749 INFO L276 IsEmpty]: Start isEmpty. Operand 1522 states and 4220 transitions. [2019-12-07 21:20:39,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 21:20:39,751 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:39,751 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:39,751 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:39,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:39,751 INFO L82 PathProgramCache]: Analyzing trace with hash -893148506, now seen corresponding path program 3 times [2019-12-07 21:20:39,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:39,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805815482] [2019-12-07 21:20:39,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:39,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:39,823 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805815482] [2019-12-07 21:20:39,823 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:39,824 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 21:20:39,824 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252862991] [2019-12-07 21:20:39,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 21:20:39,824 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:39,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 21:20:39,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 21:20:39,824 INFO L87 Difference]: Start difference. First operand 1522 states and 4220 transitions. Second operand 6 states. [2019-12-07 21:20:39,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:39,976 INFO L93 Difference]: Finished difference Result 2004 states and 5532 transitions. [2019-12-07 21:20:39,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 21:20:39,976 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 21:20:39,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:39,978 INFO L225 Difference]: With dead ends: 2004 [2019-12-07 21:20:39,978 INFO L226 Difference]: Without dead ends: 2004 [2019-12-07 21:20:39,978 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 21:20:39,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2004 states. [2019-12-07 21:20:39,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2004 to 1550. [2019-12-07 21:20:39,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1550 states. [2019-12-07 21:20:39,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 1550 states and 4300 transitions. [2019-12-07 21:20:39,994 INFO L78 Accepts]: Start accepts. Automaton has 1550 states and 4300 transitions. Word has length 58 [2019-12-07 21:20:39,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:39,994 INFO L462 AbstractCegarLoop]: Abstraction has 1550 states and 4300 transitions. [2019-12-07 21:20:39,994 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 21:20:39,994 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 4300 transitions. [2019-12-07 21:20:39,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 21:20:39,996 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:39,996 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:39,996 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:39,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:39,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1236108060, now seen corresponding path program 4 times [2019-12-07 21:20:39,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:39,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513468691] [2019-12-07 21:20:39,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:40,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:40,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:40,032 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513468691] [2019-12-07 21:20:40,032 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:40,032 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 21:20:40,032 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356860394] [2019-12-07 21:20:40,032 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 21:20:40,032 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:40,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 21:20:40,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:40,032 INFO L87 Difference]: Start difference. First operand 1550 states and 4300 transitions. Second operand 3 states. [2019-12-07 21:20:40,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:40,043 INFO L93 Difference]: Finished difference Result 1442 states and 3964 transitions. [2019-12-07 21:20:40,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 21:20:40,044 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-12-07 21:20:40,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:40,045 INFO L225 Difference]: With dead ends: 1442 [2019-12-07 21:20:40,045 INFO L226 Difference]: Without dead ends: 1442 [2019-12-07 21:20:40,045 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:40,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1442 states. [2019-12-07 21:20:40,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1442 to 1442. [2019-12-07 21:20:40,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1442 states. [2019-12-07 21:20:40,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1442 states to 1442 states and 3964 transitions. [2019-12-07 21:20:40,059 INFO L78 Accepts]: Start accepts. Automaton has 1442 states and 3964 transitions. Word has length 58 [2019-12-07 21:20:40,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:40,059 INFO L462 AbstractCegarLoop]: Abstraction has 1442 states and 3964 transitions. [2019-12-07 21:20:40,059 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 21:20:40,060 INFO L276 IsEmpty]: Start isEmpty. Operand 1442 states and 3964 transitions. [2019-12-07 21:20:40,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 21:20:40,061 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:40,061 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:40,062 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:40,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:40,062 INFO L82 PathProgramCache]: Analyzing trace with hash -465324325, now seen corresponding path program 1 times [2019-12-07 21:20:40,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:40,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978722443] [2019-12-07 21:20:40,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:40,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:40,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:40,108 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978722443] [2019-12-07 21:20:40,108 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:40,108 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 21:20:40,108 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778132683] [2019-12-07 21:20:40,109 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 21:20:40,109 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:40,109 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 21:20:40,109 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:40,109 INFO L87 Difference]: Start difference. First operand 1442 states and 3964 transitions. Second operand 3 states. [2019-12-07 21:20:40,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:40,148 INFO L93 Difference]: Finished difference Result 1441 states and 3962 transitions. [2019-12-07 21:20:40,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 21:20:40,149 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 21:20:40,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:40,151 INFO L225 Difference]: With dead ends: 1441 [2019-12-07 21:20:40,151 INFO L226 Difference]: Without dead ends: 1441 [2019-12-07 21:20:40,151 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 21:20:40,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1441 states. [2019-12-07 21:20:40,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1441 to 1160. [2019-12-07 21:20:40,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1160 states. [2019-12-07 21:20:40,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1160 states to 1160 states and 3188 transitions. [2019-12-07 21:20:40,169 INFO L78 Accepts]: Start accepts. Automaton has 1160 states and 3188 transitions. Word has length 59 [2019-12-07 21:20:40,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:40,169 INFO L462 AbstractCegarLoop]: Abstraction has 1160 states and 3188 transitions. [2019-12-07 21:20:40,169 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 21:20:40,169 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 3188 transitions. [2019-12-07 21:20:40,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:40,171 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:40,172 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:40,172 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:40,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:40,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1056994783, now seen corresponding path program 1 times [2019-12-07 21:20:40,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:40,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982634919] [2019-12-07 21:20:40,173 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:40,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:40,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:40,410 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982634919] [2019-12-07 21:20:40,411 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:40,411 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 21:20:40,411 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836702649] [2019-12-07 21:20:40,411 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 21:20:40,411 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:40,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 21:20:40,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2019-12-07 21:20:40,412 INFO L87 Difference]: Start difference. First operand 1160 states and 3188 transitions. Second operand 13 states. [2019-12-07 21:20:40,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:40,828 INFO L93 Difference]: Finished difference Result 2509 states and 6329 transitions. [2019-12-07 21:20:40,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 21:20:40,828 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2019-12-07 21:20:40,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:40,830 INFO L225 Difference]: With dead ends: 2509 [2019-12-07 21:20:40,830 INFO L226 Difference]: Without dead ends: 1797 [2019-12-07 21:20:40,830 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=414, Unknown=0, NotChecked=0, Total=552 [2019-12-07 21:20:40,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1797 states. [2019-12-07 21:20:40,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1797 to 1160. [2019-12-07 21:20:40,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1160 states. [2019-12-07 21:20:40,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1160 states to 1160 states and 3150 transitions. [2019-12-07 21:20:40,844 INFO L78 Accepts]: Start accepts. Automaton has 1160 states and 3150 transitions. Word has length 60 [2019-12-07 21:20:40,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:40,844 INFO L462 AbstractCegarLoop]: Abstraction has 1160 states and 3150 transitions. [2019-12-07 21:20:40,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 21:20:40,844 INFO L276 IsEmpty]: Start isEmpty. Operand 1160 states and 3150 transitions. [2019-12-07 21:20:40,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:40,845 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:40,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:40,846 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:40,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:40,846 INFO L82 PathProgramCache]: Analyzing trace with hash -869219965, now seen corresponding path program 2 times [2019-12-07 21:20:40,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:40,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798759258] [2019-12-07 21:20:40,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:40,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:40,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:40,973 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798759258] [2019-12-07 21:20:40,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:40,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 21:20:40,974 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697916507] [2019-12-07 21:20:40,974 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 21:20:40,974 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:40,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 21:20:40,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2019-12-07 21:20:40,974 INFO L87 Difference]: Start difference. First operand 1160 states and 3150 transitions. Second operand 11 states. [2019-12-07 21:20:41,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:41,223 INFO L93 Difference]: Finished difference Result 1966 states and 4928 transitions. [2019-12-07 21:20:41,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 21:20:41,223 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 60 [2019-12-07 21:20:41,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:41,225 INFO L225 Difference]: With dead ends: 1966 [2019-12-07 21:20:41,225 INFO L226 Difference]: Without dead ends: 1480 [2019-12-07 21:20:41,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=255, Unknown=0, NotChecked=0, Total=342 [2019-12-07 21:20:41,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1480 states. [2019-12-07 21:20:41,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1480 to 1020. [2019-12-07 21:20:41,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1020 states. [2019-12-07 21:20:41,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1020 states to 1020 states and 2717 transitions. [2019-12-07 21:20:41,237 INFO L78 Accepts]: Start accepts. Automaton has 1020 states and 2717 transitions. Word has length 60 [2019-12-07 21:20:41,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:41,238 INFO L462 AbstractCegarLoop]: Abstraction has 1020 states and 2717 transitions. [2019-12-07 21:20:41,238 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 21:20:41,238 INFO L276 IsEmpty]: Start isEmpty. Operand 1020 states and 2717 transitions. [2019-12-07 21:20:41,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:41,239 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:41,239 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:41,239 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:41,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:41,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1968443931, now seen corresponding path program 3 times [2019-12-07 21:20:41,240 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:41,240 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284173627] [2019-12-07 21:20:41,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:41,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:41,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:41,418 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284173627] [2019-12-07 21:20:41,418 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:41,418 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 21:20:41,419 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489975490] [2019-12-07 21:20:41,419 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 21:20:41,419 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:41,419 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 21:20:41,419 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 21:20:41,419 INFO L87 Difference]: Start difference. First operand 1020 states and 2717 transitions. Second operand 13 states. [2019-12-07 21:20:41,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:41,823 INFO L93 Difference]: Finished difference Result 2575 states and 6195 transitions. [2019-12-07 21:20:41,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 21:20:41,823 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2019-12-07 21:20:41,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:41,824 INFO L225 Difference]: With dead ends: 2575 [2019-12-07 21:20:41,824 INFO L226 Difference]: Without dead ends: 796 [2019-12-07 21:20:41,824 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2019-12-07 21:20:41,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 796 states. [2019-12-07 21:20:41,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 796 to 571. [2019-12-07 21:20:41,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 571 states. [2019-12-07 21:20:41,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 571 states to 571 states and 1223 transitions. [2019-12-07 21:20:41,830 INFO L78 Accepts]: Start accepts. Automaton has 571 states and 1223 transitions. Word has length 60 [2019-12-07 21:20:41,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:41,830 INFO L462 AbstractCegarLoop]: Abstraction has 571 states and 1223 transitions. [2019-12-07 21:20:41,830 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 21:20:41,830 INFO L276 IsEmpty]: Start isEmpty. Operand 571 states and 1223 transitions. [2019-12-07 21:20:41,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:41,831 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:41,831 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:41,831 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:41,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:41,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1222711449, now seen corresponding path program 4 times [2019-12-07 21:20:41,831 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:41,831 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347236882] [2019-12-07 21:20:41,831 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:41,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:41,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:41,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347236882] [2019-12-07 21:20:41,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:41,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 21:20:41,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15139784] [2019-12-07 21:20:41,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 21:20:41,909 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:41,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 21:20:41,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 21:20:41,910 INFO L87 Difference]: Start difference. First operand 571 states and 1223 transitions. Second operand 6 states. [2019-12-07 21:20:41,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:41,959 INFO L93 Difference]: Finished difference Result 809 states and 1670 transitions. [2019-12-07 21:20:41,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 21:20:41,959 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 60 [2019-12-07 21:20:41,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:41,960 INFO L225 Difference]: With dead ends: 809 [2019-12-07 21:20:41,960 INFO L226 Difference]: Without dead ends: 239 [2019-12-07 21:20:41,960 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 21:20:41,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2019-12-07 21:20:41,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 215. [2019-12-07 21:20:41,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2019-12-07 21:20:41,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 364 transitions. [2019-12-07 21:20:41,962 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 364 transitions. Word has length 60 [2019-12-07 21:20:41,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:41,962 INFO L462 AbstractCegarLoop]: Abstraction has 215 states and 364 transitions. [2019-12-07 21:20:41,962 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 21:20:41,962 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 364 transitions. [2019-12-07 21:20:41,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:41,963 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:41,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:41,963 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:41,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:41,963 INFO L82 PathProgramCache]: Analyzing trace with hash 424334393, now seen corresponding path program 5 times [2019-12-07 21:20:41,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:41,963 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34863440] [2019-12-07 21:20:41,963 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:41,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:42,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:42,122 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34863440] [2019-12-07 21:20:42,122 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:42,122 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 21:20:42,122 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175011779] [2019-12-07 21:20:42,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 21:20:42,123 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:42,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 21:20:42,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 21:20:42,123 INFO L87 Difference]: Start difference. First operand 215 states and 364 transitions. Second operand 13 states. [2019-12-07 21:20:42,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:42,440 INFO L93 Difference]: Finished difference Result 382 states and 637 transitions. [2019-12-07 21:20:42,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 21:20:42,440 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2019-12-07 21:20:42,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:42,440 INFO L225 Difference]: With dead ends: 382 [2019-12-07 21:20:42,440 INFO L226 Difference]: Without dead ends: 349 [2019-12-07 21:20:42,441 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=85, Invalid=421, Unknown=0, NotChecked=0, Total=506 [2019-12-07 21:20:42,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2019-12-07 21:20:42,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 315. [2019-12-07 21:20:42,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-12-07 21:20:42,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 535 transitions. [2019-12-07 21:20:42,443 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 535 transitions. Word has length 60 [2019-12-07 21:20:42,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:42,444 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 535 transitions. [2019-12-07 21:20:42,444 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 21:20:42,444 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 535 transitions. [2019-12-07 21:20:42,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:42,444 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:42,444 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:42,444 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:42,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:42,445 INFO L82 PathProgramCache]: Analyzing trace with hash -1214438793, now seen corresponding path program 6 times [2019-12-07 21:20:42,445 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:42,445 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455344089] [2019-12-07 21:20:42,445 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:42,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 21:20:42,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 21:20:42,672 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455344089] [2019-12-07 21:20:42,672 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 21:20:42,672 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 21:20:42,672 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316662169] [2019-12-07 21:20:42,673 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 21:20:42,673 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 21:20:42,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 21:20:42,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=225, Unknown=0, NotChecked=0, Total=272 [2019-12-07 21:20:42,673 INFO L87 Difference]: Start difference. First operand 315 states and 535 transitions. Second operand 17 states. [2019-12-07 21:20:43,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 21:20:43,180 INFO L93 Difference]: Finished difference Result 478 states and 787 transitions. [2019-12-07 21:20:43,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 21:20:43,181 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2019-12-07 21:20:43,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 21:20:43,181 INFO L225 Difference]: With dead ends: 478 [2019-12-07 21:20:43,181 INFO L226 Difference]: Without dead ends: 445 [2019-12-07 21:20:43,182 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=201, Invalid=921, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 21:20:43,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2019-12-07 21:20:43,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 323. [2019-12-07 21:20:43,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 323 states. [2019-12-07 21:20:43,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 549 transitions. [2019-12-07 21:20:43,184 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 549 transitions. Word has length 60 [2019-12-07 21:20:43,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 21:20:43,184 INFO L462 AbstractCegarLoop]: Abstraction has 323 states and 549 transitions. [2019-12-07 21:20:43,184 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 21:20:43,185 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 549 transitions. [2019-12-07 21:20:43,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 21:20:43,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 21:20:43,185 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 21:20:43,185 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 21:20:43,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 21:20:43,185 INFO L82 PathProgramCache]: Analyzing trace with hash -1750352957, now seen corresponding path program 7 times [2019-12-07 21:20:43,185 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 21:20:43,186 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219736605] [2019-12-07 21:20:43,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 21:20:43,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 21:20:43,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 21:20:43,259 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 21:20:43,260 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 21:20:43,262 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= v_~z$w_buff0~0_106 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1461~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1461~0.base_22|) |v_ULTIMATE.start_main_~#t1461~0.offset_17| 0)) |v_#memory_int_27|) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= v_~z$read_delayed_var~0.offset_7 0) (= |v_ULTIMATE.start_main_~#t1461~0.offset_17| 0) (= v_~z$r_buff1_thd0~0_244 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t1461~0.base_22| 4) |v_#length_31|) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1461~0.base_22|) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1461~0.base_22| 1)) (= v_~y~0_41 0) (= v_~x~0_54 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1461~0.base_22|) 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t1464~0.base=|v_ULTIMATE.start_main_~#t1464~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_~#t1461~0.base=|v_ULTIMATE.start_main_~#t1461~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ULTIMATE.start_main_~#t1463~0.offset=|v_ULTIMATE.start_main_~#t1463~0.offset_17|, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ULTIMATE.start_main_~#t1464~0.offset=|v_ULTIMATE.start_main_~#t1464~0.offset_16|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ULTIMATE.start_main_~#t1462~0.base=|v_ULTIMATE.start_main_~#t1462~0.base_23|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, ULTIMATE.start_main_~#t1462~0.offset=|v_ULTIMATE.start_main_~#t1462~0.offset_18|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t1463~0.base=|v_ULTIMATE.start_main_~#t1463~0.base_20|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89, ULTIMATE.start_main_~#t1461~0.offset=|v_ULTIMATE.start_main_~#t1461~0.offset_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1464~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t1461~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t1463~0.offset, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ULTIMATE.start_main_~#t1464~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1462~0.base, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1462~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1463~0.base, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1461~0.offset] because there is no mapped edge [2019-12-07 21:20:43,263 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1462~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1462~0.base_13|) |v_ULTIMATE.start_main_~#t1462~0.offset_11| 1)) |v_#memory_int_19|) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1462~0.base_13| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1462~0.base_13|) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1462~0.base_13|)) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1462~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1462~0.base_13| 0)) (= |v_ULTIMATE.start_main_~#t1462~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t1462~0.base=|v_ULTIMATE.start_main_~#t1462~0.base_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1462~0.offset=|v_ULTIMATE.start_main_~#t1462~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1462~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1462~0.offset] because there is no mapped edge [2019-12-07 21:20:43,263 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= |v_ULTIMATE.start_main_~#t1463~0.offset_10| 0) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1463~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1463~0.base_10|) |v_ULTIMATE.start_main_~#t1463~0.offset_10| 2)) |v_#memory_int_15|) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1463~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t1463~0.base_10| 0)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1463~0.base_10| 4) |v_#length_19|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1463~0.base_10|) 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1463~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1463~0.base=|v_ULTIMATE.start_main_~#t1463~0.base_10|, ULTIMATE.start_main_~#t1463~0.offset=|v_ULTIMATE.start_main_~#t1463~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_19|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1463~0.base, ULTIMATE.start_main_~#t1463~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 21:20:43,263 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1464~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1464~0.base_11|) |v_ULTIMATE.start_main_~#t1464~0.offset_10| 3)) |v_#memory_int_17|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1464~0.base_11|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1464~0.base_11| 4)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1464~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1464~0.base_11|)) (= |v_ULTIMATE.start_main_~#t1464~0.offset_10| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1464~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1464~0.base=|v_ULTIMATE.start_main_~#t1464~0.base_11|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1464~0.offset=|v_ULTIMATE.start_main_~#t1464~0.offset_10|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1464~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1464~0.offset, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 21:20:43,264 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= ~z$r_buff0_thd1~0_In320321837 ~z$r_buff1_thd1~0_Out320321837) (= ~z$r_buff0_thd3~0_In320321837 ~z$r_buff1_thd3~0_Out320321837) (= ~z$r_buff0_thd2~0_In320321837 ~z$r_buff1_thd2~0_Out320321837) (= ~a~0_In320321837 ~__unbuffered_p3_EAX~0_Out320321837) (= ~z$r_buff1_thd0~0_Out320321837 ~z$r_buff0_thd0~0_In320321837) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837)) (= 1 ~z$r_buff0_thd4~0_Out320321837) (= ~z$r_buff1_thd4~0_Out320321837 ~z$r_buff0_thd4~0_In320321837)) InVars {~a~0=~a~0_In320321837, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In320321837, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In320321837, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In320321837, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In320321837, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In320321837} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out320321837, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out320321837, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out320321837, ~a~0=~a~0_In320321837, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In320321837, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out320321837, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out320321837, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out320321837, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out320321837, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In320321837, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In320321837, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In320321837} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 21:20:43,265 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 21:20:43,265 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 21:20:43,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In346650962 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In346650962 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite11_Out346650962|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In346650962 |P3Thread1of1ForFork3_#t~ite11_Out346650962|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In346650962, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In346650962} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In346650962, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In346650962, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out346650962|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 21:20:43,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-229793340 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-229793340 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-229793340 |P2Thread1of1ForFork2_#t~ite3_Out-229793340|)) (and (or .cse1 .cse0) (= ~z~0_In-229793340 |P2Thread1of1ForFork2_#t~ite3_Out-229793340|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-229793340, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-229793340, ~z$w_buff1~0=~z$w_buff1~0_In-229793340, ~z~0=~z~0_In-229793340} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-229793340|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-229793340, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-229793340, ~z$w_buff1~0=~z$w_buff1~0_In-229793340, ~z~0=~z~0_In-229793340} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 21:20:43,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 21:20:43,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd4~0_In-1263106093 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1263106093 256))) (.cse2 (= (mod ~z$r_buff0_thd4~0_In-1263106093 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1263106093 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out-1263106093|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1263106093 |P3Thread1of1ForFork3_#t~ite12_Out-1263106093|) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1263106093, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263106093, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1263106093, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263106093} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1263106093, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263106093, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1263106093, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263106093, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out-1263106093|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 21:20:43,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse1 (= ~z$r_buff0_thd4~0_Out-1357544543 ~z$r_buff0_thd4~0_In-1357544543)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1357544543 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In-1357544543 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse2) (= ~z$r_buff0_thd4~0_Out-1357544543 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1357544543, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1357544543} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1357544543, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-1357544543, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out-1357544543|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 21:20:43,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-242904203 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd4~0_In-242904203 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In-242904203 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-242904203 256) 0))) (or (and (= |P3Thread1of1ForFork3_#t~ite14_Out-242904203| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork3_#t~ite14_Out-242904203| ~z$r_buff1_thd4~0_In-242904203) (or .cse3 .cse2)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-242904203, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-242904203, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-242904203, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-242904203} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-242904203, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-242904203, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-242904203|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-242904203, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-242904203} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 21:20:43,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 21:20:43,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-418598319 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-418598319 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-418598319 |P2Thread1of1ForFork2_#t~ite5_Out-418598319|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite5_Out-418598319|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-418598319, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-418598319} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out-418598319|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-418598319, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-418598319} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 21:20:43,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In-254036009 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-254036009 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-254036009 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-254036009 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite6_Out-254036009|)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite6_Out-254036009| ~z$w_buff1_used~0_In-254036009) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-254036009, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254036009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254036009, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254036009} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-254036009|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-254036009, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254036009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254036009, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254036009} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 21:20:43,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-999654839 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-999654839 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite7_Out-999654839| ~z$r_buff0_thd3~0_In-999654839)) (and (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-999654839|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-999654839, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-999654839} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-999654839, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-999654839, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-999654839|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 21:20:43,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-924216434 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-924216434 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-924216434 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-924216434 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite8_Out-924216434| ~z$r_buff1_thd3~0_In-924216434) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite8_Out-924216434| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-924216434, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-924216434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-924216434, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-924216434} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-924216434, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-924216434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-924216434, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-924216434, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-924216434|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 21:20:43,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 21:20:43,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 21:20:43,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1231597935 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1231597935 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite19_Out1231597935| ~z$w_buff1~0_In1231597935) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out1231597935| ~z~0_In1231597935)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1231597935, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1231597935, ~z$w_buff1~0=~z$w_buff1~0_In1231597935, ~z~0=~z~0_In1231597935} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out1231597935|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1231597935, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1231597935, ~z$w_buff1~0=~z$w_buff1~0_In1231597935, ~z~0=~z~0_In1231597935} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 21:20:43,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 21:20:43,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1812340280 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1812340280 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1812340280| ~z$w_buff0_used~0_In-1812340280)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-1812340280| 0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1812340280, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1812340280} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1812340280, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1812340280, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1812340280|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 21:20:43,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1875131632 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1875131632 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1875131632 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-1875131632 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-1875131632 |ULTIMATE.start_main_#t~ite22_Out-1875131632|)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-1875131632|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1875131632, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1875131632, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1875131632, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1875131632} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1875131632, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1875131632, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1875131632, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1875131632, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1875131632|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 21:20:43,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In1791257897 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1791257897 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite23_Out1791257897| 0) (not .cse1)) (and (= ~z$r_buff0_thd0~0_In1791257897 |ULTIMATE.start_main_#t~ite23_Out1791257897|) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1791257897, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1791257897} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1791257897, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1791257897, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1791257897|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 21:20:43,270 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-1457795909 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In-1457795909 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1457795909 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In-1457795909 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite24_Out-1457795909| ~z$r_buff1_thd0~0_In-1457795909) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite24_Out-1457795909| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1457795909, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1457795909, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1457795909, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1457795909} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1457795909, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1457795909, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1457795909, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1457795909|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1457795909} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 21:20:43,271 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-861566914 256)))) (or (and (= |ULTIMATE.start_main_#t~ite34_Out-861566914| ~z$w_buff1~0_In-861566914) (= |ULTIMATE.start_main_#t~ite33_In-861566914| |ULTIMATE.start_main_#t~ite33_Out-861566914|) (not .cse0)) (and (= ~z$w_buff1~0_In-861566914 |ULTIMATE.start_main_#t~ite33_Out-861566914|) (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In-861566914 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-861566914 256)) .cse1) (and (= (mod ~z$r_buff1_thd0~0_In-861566914 256) 0) .cse1) (= (mod ~z$w_buff0_used~0_In-861566914 256) 0))) .cse0 (= |ULTIMATE.start_main_#t~ite34_Out-861566914| |ULTIMATE.start_main_#t~ite33_Out-861566914|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-861566914, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-861566914, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-861566914, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-861566914, ~z$w_buff1~0=~z$w_buff1~0_In-861566914, ~weak$$choice2~0=~weak$$choice2~0_In-861566914, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In-861566914|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-861566914, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-861566914, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-861566914, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-861566914, ~z$w_buff1~0=~z$w_buff1~0_In-861566914, ~weak$$choice2~0=~weak$$choice2~0_In-861566914, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-861566914|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out-861566914|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 21:20:43,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1155815033 256) 0))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite39_Out1155815033| ~z$w_buff1_used~0_In1155815033) (= |ULTIMATE.start_main_#t~ite39_Out1155815033| |ULTIMATE.start_main_#t~ite40_Out1155815033|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1155815033 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In1155815033 256)) (and (= 0 (mod ~z$r_buff1_thd0~0_In1155815033 256)) .cse1) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In1155815033 256)))))) (and (= ~z$w_buff1_used~0_In1155815033 |ULTIMATE.start_main_#t~ite40_Out1155815033|) (= |ULTIMATE.start_main_#t~ite39_In1155815033| |ULTIMATE.start_main_#t~ite39_Out1155815033|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1155815033, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1155815033, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In1155815033|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1155815033, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1155815033, ~weak$$choice2~0=~weak$$choice2~0_In1155815033} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1155815033, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out1155815033|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1155815033|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1155815033, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1155815033, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1155815033, ~weak$$choice2~0=~weak$$choice2~0_In1155815033} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 21:20:43,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 21:20:43,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In464611352 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite45_In464611352| |ULTIMATE.start_main_#t~ite45_Out464611352|) (= ~z$r_buff1_thd0~0_In464611352 |ULTIMATE.start_main_#t~ite46_Out464611352|)) (and (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In464611352 256) 0))) (or (and .cse1 (= (mod ~z$r_buff1_thd0~0_In464611352 256) 0)) (and .cse1 (= (mod ~z$w_buff1_used~0_In464611352 256) 0)) (= 0 (mod ~z$w_buff0_used~0_In464611352 256)))) (= |ULTIMATE.start_main_#t~ite46_Out464611352| |ULTIMATE.start_main_#t~ite45_Out464611352|) (= ~z$r_buff1_thd0~0_In464611352 |ULTIMATE.start_main_#t~ite45_Out464611352|) .cse0))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In464611352, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464611352, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In464611352, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464611352, ~weak$$choice2~0=~weak$$choice2~0_In464611352, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In464611352|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In464611352, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464611352, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In464611352, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464611352, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out464611352|, ~weak$$choice2~0=~weak$$choice2~0_In464611352, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out464611352|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 21:20:43,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 21:20:43,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 21:20:43,339 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 09:20:43 BasicIcfg [2019-12-07 21:20:43,339 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 21:20:43,339 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 21:20:43,339 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 21:20:43,339 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 21:20:43,340 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 09:20:23" (3/4) ... [2019-12-07 21:20:43,341 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 21:20:43,342 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= v_~z$w_buff0~0_106 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1461~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1461~0.base_22|) |v_ULTIMATE.start_main_~#t1461~0.offset_17| 0)) |v_#memory_int_27|) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= v_~z$read_delayed_var~0.offset_7 0) (= |v_ULTIMATE.start_main_~#t1461~0.offset_17| 0) (= v_~z$r_buff1_thd0~0_244 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t1461~0.base_22| 4) |v_#length_31|) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1461~0.base_22|) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1461~0.base_22| 1)) (= v_~y~0_41 0) (= v_~x~0_54 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1461~0.base_22|) 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t1464~0.base=|v_ULTIMATE.start_main_~#t1464~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_~#t1461~0.base=|v_ULTIMATE.start_main_~#t1461~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ULTIMATE.start_main_~#t1463~0.offset=|v_ULTIMATE.start_main_~#t1463~0.offset_17|, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ULTIMATE.start_main_~#t1464~0.offset=|v_ULTIMATE.start_main_~#t1464~0.offset_16|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ULTIMATE.start_main_~#t1462~0.base=|v_ULTIMATE.start_main_~#t1462~0.base_23|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, ULTIMATE.start_main_~#t1462~0.offset=|v_ULTIMATE.start_main_~#t1462~0.offset_18|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t1463~0.base=|v_ULTIMATE.start_main_~#t1463~0.base_20|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89, ULTIMATE.start_main_~#t1461~0.offset=|v_ULTIMATE.start_main_~#t1461~0.offset_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1464~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t1461~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t1463~0.offset, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ULTIMATE.start_main_~#t1464~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1462~0.base, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1462~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1463~0.base, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1461~0.offset] because there is no mapped edge [2019-12-07 21:20:43,342 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1462~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1462~0.base_13|) |v_ULTIMATE.start_main_~#t1462~0.offset_11| 1)) |v_#memory_int_19|) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1462~0.base_13| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1462~0.base_13|) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1462~0.base_13|)) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1462~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1462~0.base_13| 0)) (= |v_ULTIMATE.start_main_~#t1462~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t1462~0.base=|v_ULTIMATE.start_main_~#t1462~0.base_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1462~0.offset=|v_ULTIMATE.start_main_~#t1462~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1462~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1462~0.offset] because there is no mapped edge [2019-12-07 21:20:43,342 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= |v_ULTIMATE.start_main_~#t1463~0.offset_10| 0) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1463~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1463~0.base_10|) |v_ULTIMATE.start_main_~#t1463~0.offset_10| 2)) |v_#memory_int_15|) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1463~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t1463~0.base_10| 0)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1463~0.base_10| 4) |v_#length_19|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1463~0.base_10|) 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1463~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1463~0.base=|v_ULTIMATE.start_main_~#t1463~0.base_10|, ULTIMATE.start_main_~#t1463~0.offset=|v_ULTIMATE.start_main_~#t1463~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_19|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1463~0.base, ULTIMATE.start_main_~#t1463~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 21:20:43,342 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1464~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1464~0.base_11|) |v_ULTIMATE.start_main_~#t1464~0.offset_10| 3)) |v_#memory_int_17|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1464~0.base_11|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1464~0.base_11| 4)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1464~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1464~0.base_11|)) (= |v_ULTIMATE.start_main_~#t1464~0.offset_10| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1464~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1464~0.base=|v_ULTIMATE.start_main_~#t1464~0.base_11|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1464~0.offset=|v_ULTIMATE.start_main_~#t1464~0.offset_10|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1464~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1464~0.offset, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 21:20:43,343 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= ~z$r_buff0_thd1~0_In320321837 ~z$r_buff1_thd1~0_Out320321837) (= ~z$r_buff0_thd3~0_In320321837 ~z$r_buff1_thd3~0_Out320321837) (= ~z$r_buff0_thd2~0_In320321837 ~z$r_buff1_thd2~0_Out320321837) (= ~a~0_In320321837 ~__unbuffered_p3_EAX~0_Out320321837) (= ~z$r_buff1_thd0~0_Out320321837 ~z$r_buff0_thd0~0_In320321837) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837)) (= 1 ~z$r_buff0_thd4~0_Out320321837) (= ~z$r_buff1_thd4~0_Out320321837 ~z$r_buff0_thd4~0_In320321837)) InVars {~a~0=~a~0_In320321837, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In320321837, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In320321837, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In320321837, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In320321837, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In320321837} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In320321837, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out320321837, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out320321837, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out320321837, ~a~0=~a~0_In320321837, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In320321837, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out320321837, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out320321837, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out320321837, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out320321837, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In320321837, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In320321837, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In320321837} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 21:20:43,343 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 21:20:43,343 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 21:20:43,344 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In346650962 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In346650962 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite11_Out346650962|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In346650962 |P3Thread1of1ForFork3_#t~ite11_Out346650962|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In346650962, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In346650962} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In346650962, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In346650962, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out346650962|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 21:20:43,344 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-229793340 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-229793340 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-229793340 |P2Thread1of1ForFork2_#t~ite3_Out-229793340|)) (and (or .cse1 .cse0) (= ~z~0_In-229793340 |P2Thread1of1ForFork2_#t~ite3_Out-229793340|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-229793340, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-229793340, ~z$w_buff1~0=~z$w_buff1~0_In-229793340, ~z~0=~z~0_In-229793340} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-229793340|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-229793340, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-229793340, ~z$w_buff1~0=~z$w_buff1~0_In-229793340, ~z~0=~z~0_In-229793340} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 21:20:43,344 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 21:20:43,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd4~0_In-1263106093 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1263106093 256))) (.cse2 (= (mod ~z$r_buff0_thd4~0_In-1263106093 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1263106093 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out-1263106093|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1263106093 |P3Thread1of1ForFork3_#t~ite12_Out-1263106093|) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1263106093, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263106093, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1263106093, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263106093} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1263106093, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263106093, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1263106093, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263106093, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out-1263106093|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 21:20:43,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse1 (= ~z$r_buff0_thd4~0_Out-1357544543 ~z$r_buff0_thd4~0_In-1357544543)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1357544543 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In-1357544543 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse2) (= ~z$r_buff0_thd4~0_Out-1357544543 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1357544543, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1357544543} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1357544543, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-1357544543, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out-1357544543|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 21:20:43,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-242904203 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd4~0_In-242904203 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In-242904203 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-242904203 256) 0))) (or (and (= |P3Thread1of1ForFork3_#t~ite14_Out-242904203| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork3_#t~ite14_Out-242904203| ~z$r_buff1_thd4~0_In-242904203) (or .cse3 .cse2)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-242904203, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-242904203, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-242904203, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-242904203} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-242904203, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-242904203, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-242904203|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-242904203, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-242904203} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 21:20:43,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 21:20:43,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-418598319 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-418598319 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-418598319 |P2Thread1of1ForFork2_#t~ite5_Out-418598319|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite5_Out-418598319|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-418598319, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-418598319} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out-418598319|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-418598319, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-418598319} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 21:20:43,346 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In-254036009 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-254036009 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-254036009 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-254036009 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite6_Out-254036009|)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite6_Out-254036009| ~z$w_buff1_used~0_In-254036009) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-254036009, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254036009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254036009, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254036009} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-254036009|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-254036009, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254036009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254036009, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254036009} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 21:20:43,346 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-999654839 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-999654839 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite7_Out-999654839| ~z$r_buff0_thd3~0_In-999654839)) (and (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-999654839|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-999654839, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-999654839} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-999654839, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-999654839, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-999654839|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 21:20:43,346 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-924216434 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-924216434 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-924216434 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-924216434 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite8_Out-924216434| ~z$r_buff1_thd3~0_In-924216434) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite8_Out-924216434| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-924216434, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-924216434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-924216434, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-924216434} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-924216434, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-924216434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-924216434, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-924216434, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-924216434|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 21:20:43,346 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 21:20:43,347 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 21:20:43,347 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1231597935 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1231597935 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite19_Out1231597935| ~z$w_buff1~0_In1231597935) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out1231597935| ~z~0_In1231597935)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1231597935, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1231597935, ~z$w_buff1~0=~z$w_buff1~0_In1231597935, ~z~0=~z~0_In1231597935} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out1231597935|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1231597935, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1231597935, ~z$w_buff1~0=~z$w_buff1~0_In1231597935, ~z~0=~z~0_In1231597935} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 21:20:43,347 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 21:20:43,347 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1812340280 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1812340280 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1812340280| ~z$w_buff0_used~0_In-1812340280)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-1812340280| 0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1812340280, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1812340280} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1812340280, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1812340280, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1812340280|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 21:20:43,347 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1875131632 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1875131632 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1875131632 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-1875131632 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-1875131632 |ULTIMATE.start_main_#t~ite22_Out-1875131632|)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-1875131632|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1875131632, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1875131632, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1875131632, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1875131632} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1875131632, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1875131632, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1875131632, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1875131632, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1875131632|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 21:20:43,348 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In1791257897 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1791257897 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite23_Out1791257897| 0) (not .cse1)) (and (= ~z$r_buff0_thd0~0_In1791257897 |ULTIMATE.start_main_#t~ite23_Out1791257897|) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1791257897, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1791257897} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1791257897, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1791257897, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1791257897|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 21:20:43,348 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-1457795909 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In-1457795909 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1457795909 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In-1457795909 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite24_Out-1457795909| ~z$r_buff1_thd0~0_In-1457795909) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite24_Out-1457795909| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1457795909, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1457795909, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1457795909, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1457795909} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1457795909, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1457795909, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1457795909, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1457795909|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1457795909} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 21:20:43,349 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-861566914 256)))) (or (and (= |ULTIMATE.start_main_#t~ite34_Out-861566914| ~z$w_buff1~0_In-861566914) (= |ULTIMATE.start_main_#t~ite33_In-861566914| |ULTIMATE.start_main_#t~ite33_Out-861566914|) (not .cse0)) (and (= ~z$w_buff1~0_In-861566914 |ULTIMATE.start_main_#t~ite33_Out-861566914|) (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In-861566914 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-861566914 256)) .cse1) (and (= (mod ~z$r_buff1_thd0~0_In-861566914 256) 0) .cse1) (= (mod ~z$w_buff0_used~0_In-861566914 256) 0))) .cse0 (= |ULTIMATE.start_main_#t~ite34_Out-861566914| |ULTIMATE.start_main_#t~ite33_Out-861566914|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-861566914, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-861566914, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-861566914, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-861566914, ~z$w_buff1~0=~z$w_buff1~0_In-861566914, ~weak$$choice2~0=~weak$$choice2~0_In-861566914, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In-861566914|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-861566914, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-861566914, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-861566914, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-861566914, ~z$w_buff1~0=~z$w_buff1~0_In-861566914, ~weak$$choice2~0=~weak$$choice2~0_In-861566914, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-861566914|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out-861566914|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 21:20:43,350 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1155815033 256) 0))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite39_Out1155815033| ~z$w_buff1_used~0_In1155815033) (= |ULTIMATE.start_main_#t~ite39_Out1155815033| |ULTIMATE.start_main_#t~ite40_Out1155815033|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1155815033 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In1155815033 256)) (and (= 0 (mod ~z$r_buff1_thd0~0_In1155815033 256)) .cse1) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In1155815033 256)))))) (and (= ~z$w_buff1_used~0_In1155815033 |ULTIMATE.start_main_#t~ite40_Out1155815033|) (= |ULTIMATE.start_main_#t~ite39_In1155815033| |ULTIMATE.start_main_#t~ite39_Out1155815033|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1155815033, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1155815033, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In1155815033|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1155815033, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1155815033, ~weak$$choice2~0=~weak$$choice2~0_In1155815033} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1155815033, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out1155815033|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1155815033|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1155815033, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1155815033, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1155815033, ~weak$$choice2~0=~weak$$choice2~0_In1155815033} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 21:20:43,351 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 21:20:43,351 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In464611352 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite45_In464611352| |ULTIMATE.start_main_#t~ite45_Out464611352|) (= ~z$r_buff1_thd0~0_In464611352 |ULTIMATE.start_main_#t~ite46_Out464611352|)) (and (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In464611352 256) 0))) (or (and .cse1 (= (mod ~z$r_buff1_thd0~0_In464611352 256) 0)) (and .cse1 (= (mod ~z$w_buff1_used~0_In464611352 256) 0)) (= 0 (mod ~z$w_buff0_used~0_In464611352 256)))) (= |ULTIMATE.start_main_#t~ite46_Out464611352| |ULTIMATE.start_main_#t~ite45_Out464611352|) (= ~z$r_buff1_thd0~0_In464611352 |ULTIMATE.start_main_#t~ite45_Out464611352|) .cse0))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In464611352, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464611352, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In464611352, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464611352, ~weak$$choice2~0=~weak$$choice2~0_In464611352, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In464611352|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In464611352, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464611352, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In464611352, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464611352, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out464611352|, ~weak$$choice2~0=~weak$$choice2~0_In464611352, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out464611352|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 21:20:43,351 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 21:20:43,351 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 21:20:43,415 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_dc67ebed-30ba-4891-b440-4fc4e47d6a14/bin/utaipan/witness.graphml [2019-12-07 21:20:43,415 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 21:20:43,416 INFO L168 Benchmark]: Toolchain (without parser) took 20440.51 ms. Allocated memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: 1.8 GB). Free memory was 930.8 MB in the beginning and 1.4 GB in the end (delta: -493.8 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,417 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 952.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 21:20:43,417 INFO L168 Benchmark]: CACSL2BoogieTranslator took 386.33 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 149.9 MB). Free memory was 930.8 MB in the beginning and 1.1 GB in the end (delta: -181.5 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,417 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.02 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 21:20:43,417 INFO L168 Benchmark]: Boogie Preprocessor took 25.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,418 INFO L168 Benchmark]: RCFGBuilder took 401.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,418 INFO L168 Benchmark]: TraceAbstraction took 19509.07 ms. Allocated memory was 1.2 GB in the beginning and 2.8 GB in the end (delta: 1.6 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -408.1 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,419 INFO L168 Benchmark]: Witness Printer took 75.82 ms. Allocated memory is still 2.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 40.5 MB). Peak memory consumption was 40.5 MB. Max. memory is 11.5 GB. [2019-12-07 21:20:43,420 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 952.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 386.33 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 149.9 MB). Free memory was 930.8 MB in the beginning and 1.1 GB in the end (delta: -181.5 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.02 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 401.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19509.07 ms. Allocated memory was 1.2 GB in the beginning and 2.8 GB in the end (delta: 1.6 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -408.1 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 75.82 ms. Allocated memory is still 2.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 40.5 MB). Peak memory consumption was 40.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 179 ProgramPointsBefore, 91 ProgramPointsAfterwards, 207 TransitionsBefore, 97 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 7 FixpointIterations, 35 TrivialSequentialCompositions, 50 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 35 ConcurrentYvCompositions, 27 ChoiceCompositions, 4846 VarBasedMoverChecksPositive, 179 VarBasedMoverChecksNegative, 25 SemBasedMoverChecksPositive, 208 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.6s, 0 MoverChecksTotal, 50860 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L823] FCALL, FORK 0 pthread_create(&t1461, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1462, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1463, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] FCALL, FORK 0 pthread_create(&t1464, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L784] 4 z$w_buff1 = z$w_buff0 [L785] 4 z$w_buff0 = 2 [L786] 4 z$w_buff1_used = z$w_buff0_used [L787] 4 z$w_buff0_used = (_Bool)1 [L800] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L764] 3 y = 1 [L767] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L800] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L770] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L801] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L802] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L772] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L773] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L831] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L837] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L838] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L839] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L842] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L843] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L844] 0 z$flush_delayed = weak$$choice2 [L845] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L847] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L848] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L849] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L849] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L850] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L852] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L853] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p1_EAX == 0 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 19.3s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 5.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2353 SDtfs, 3322 SDslu, 7036 SDs, 0 SdLazy, 3449 SolverSat, 297 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 221 GetRequests, 30 SyntacticMatches, 11 SemanticMatches, 180 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 469 ImplicationChecksByTransitivity, 1.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52262occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.4s AutomataMinimizationTime, 20 MinimizatonAttempts, 33766 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 927 NumberOfCodeBlocks, 927 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 847 ConstructedInterpolants, 0 QuantifiedInterpolants, 208348 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...