./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix055_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix055_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ca5d595ad7dfb7b4d09671c163507440fc4a1de2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:16:18,711 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:16:18,712 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:16:18,720 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:16:18,720 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:16:18,721 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:16:18,722 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:16:18,723 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:16:18,724 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:16:18,725 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:16:18,725 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:16:18,726 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:16:18,727 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:16:18,727 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:16:18,728 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:16:18,729 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:16:18,729 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:16:18,730 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:16:18,731 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:16:18,733 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:16:18,734 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:16:18,735 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:16:18,735 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:16:18,736 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:16:18,738 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:16:18,738 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:16:18,738 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:16:18,738 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:16:18,739 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:16:18,739 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:16:18,739 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:16:18,740 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:16:18,740 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:16:18,741 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:16:18,741 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:16:18,741 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:16:18,742 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:16:18,742 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:16:18,742 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:16:18,742 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:16:18,743 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:16:18,743 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 14:16:18,754 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:16:18,754 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:16:18,754 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 14:16:18,755 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 14:16:18,755 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 14:16:18,756 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 14:16:18,756 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 14:16:18,756 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 14:16:18,756 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 14:16:18,756 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 14:16:18,757 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:16:18,757 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:16:18,757 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:16:18,757 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:16:18,757 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:16:18,757 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:16:18,758 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:16:18,759 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:16:18,759 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:16:18,759 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:16:18,759 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:16:18,759 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:16:18,759 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:16:18,759 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 14:16:18,760 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ca5d595ad7dfb7b4d09671c163507440fc4a1de2 [2019-12-07 14:16:18,858 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:16:18,865 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:16:18,867 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:16:18,868 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:16:18,868 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:16:18,869 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/mix055_rmo.opt.i [2019-12-07 14:16:18,908 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/data/686668664/87d21850afea49bca8d0e005cb25b23a/FLAGa70771fe3 [2019-12-07 14:16:19,386 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:16:19,386 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/sv-benchmarks/c/pthread-wmm/mix055_rmo.opt.i [2019-12-07 14:16:19,397 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/data/686668664/87d21850afea49bca8d0e005cb25b23a/FLAGa70771fe3 [2019-12-07 14:16:19,406 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/data/686668664/87d21850afea49bca8d0e005cb25b23a [2019-12-07 14:16:19,408 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:16:19,409 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:16:19,409 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:16:19,410 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:16:19,412 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:16:19,413 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,415 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25138a46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19, skipping insertion in model container [2019-12-07 14:16:19,416 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,420 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:16:19,457 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:16:19,729 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:16:19,737 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:16:19,781 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:16:19,829 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:16:19,830 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19 WrapperNode [2019-12-07 14:16:19,830 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:16:19,830 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:16:19,831 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:16:19,831 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:16:19,837 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,851 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,876 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:16:19,877 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:16:19,877 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:16:19,877 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:16:19,884 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,884 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,887 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,888 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,895 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,898 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,900 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... [2019-12-07 14:16:19,904 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:16:19,904 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:16:19,904 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:16:19,904 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:16:19,905 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:16:19,955 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 14:16:19,955 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 14:16:19,955 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 14:16:19,955 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 14:16:19,955 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 14:16:19,955 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 14:16:19,956 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 14:16:19,956 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 14:16:19,956 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 14:16:19,956 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 14:16:19,956 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 14:16:19,956 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 14:16:19,956 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 14:16:19,957 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:16:19,957 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:16:19,958 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 14:16:20,332 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:16:20,332 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 14:16:20,333 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:16:20 BoogieIcfgContainer [2019-12-07 14:16:20,333 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:16:20,334 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:16:20,334 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:16:20,336 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:16:20,336 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:16:19" (1/3) ... [2019-12-07 14:16:20,336 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@74cf5f4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:16:20, skipping insertion in model container [2019-12-07 14:16:20,337 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:16:19" (2/3) ... [2019-12-07 14:16:20,337 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@74cf5f4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:16:20, skipping insertion in model container [2019-12-07 14:16:20,337 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:16:20" (3/3) ... [2019-12-07 14:16:20,338 INFO L109 eAbstractionObserver]: Analyzing ICFG mix055_rmo.opt.i [2019-12-07 14:16:20,344 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 14:16:20,344 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:16:20,349 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 14:16:20,350 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 14:16:20,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,375 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,375 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,376 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,383 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,384 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,384 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,384 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,384 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,385 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,386 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,387 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,388 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,388 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,388 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,388 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,388 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:16:20,405 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 14:16:20,419 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:16:20,419 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:16:20,419 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:16:20,419 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:16:20,419 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:16:20,420 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:16:20,420 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:16:20,420 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:16:20,430 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 207 transitions [2019-12-07 14:16:20,432 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 14:16:20,483 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 14:16:20,483 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:16:20,493 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 14:16:20,504 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 14:16:20,532 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 14:16:20,532 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:16:20,536 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 14:16:20,547 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 14:16:20,548 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 14:16:23,314 WARN L192 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 93 [2019-12-07 14:16:23,410 INFO L206 etLargeBlockEncoding]: Checked pairs total: 50860 [2019-12-07 14:16:23,410 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 14:16:23,412 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 97 transitions [2019-12-07 14:16:25,266 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34622 states. [2019-12-07 14:16:25,267 INFO L276 IsEmpty]: Start isEmpty. Operand 34622 states. [2019-12-07 14:16:25,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 14:16:25,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:25,273 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:25,273 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:25,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:25,277 INFO L82 PathProgramCache]: Analyzing trace with hash 1893967926, now seen corresponding path program 1 times [2019-12-07 14:16:25,283 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:25,283 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761090328] [2019-12-07 14:16:25,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:25,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:25,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:25,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761090328] [2019-12-07 14:16:25,449 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:25,449 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 14:16:25,450 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449053600] [2019-12-07 14:16:25,453 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:16:25,453 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:25,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:16:25,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:25,464 INFO L87 Difference]: Start difference. First operand 34622 states. Second operand 3 states. [2019-12-07 14:16:25,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:25,848 INFO L93 Difference]: Finished difference Result 34366 states and 145832 transitions. [2019-12-07 14:16:25,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:16:25,849 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 14:16:25,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:26,031 INFO L225 Difference]: With dead ends: 34366 [2019-12-07 14:16:26,031 INFO L226 Difference]: Without dead ends: 33694 [2019-12-07 14:16:26,032 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:26,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33694 states. [2019-12-07 14:16:26,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33694 to 33694. [2019-12-07 14:16:26,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33694 states. [2019-12-07 14:16:27,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33694 states to 33694 states and 143088 transitions. [2019-12-07 14:16:27,026 INFO L78 Accepts]: Start accepts. Automaton has 33694 states and 143088 transitions. Word has length 9 [2019-12-07 14:16:27,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:27,027 INFO L462 AbstractCegarLoop]: Abstraction has 33694 states and 143088 transitions. [2019-12-07 14:16:27,027 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:16:27,027 INFO L276 IsEmpty]: Start isEmpty. Operand 33694 states and 143088 transitions. [2019-12-07 14:16:27,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 14:16:27,032 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:27,033 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:27,033 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:27,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:27,033 INFO L82 PathProgramCache]: Analyzing trace with hash 706074371, now seen corresponding path program 1 times [2019-12-07 14:16:27,033 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:27,033 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498849382] [2019-12-07 14:16:27,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:27,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:27,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:27,090 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498849382] [2019-12-07 14:16:27,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:27,091 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:16:27,091 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904453723] [2019-12-07 14:16:27,092 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:16:27,092 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:27,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:16:27,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:16:27,093 INFO L87 Difference]: Start difference. First operand 33694 states and 143088 transitions. Second operand 4 states. [2019-12-07 14:16:27,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:27,605 INFO L93 Difference]: Finished difference Result 52350 states and 214840 transitions. [2019-12-07 14:16:27,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:16:27,606 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 14:16:27,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:27,779 INFO L225 Difference]: With dead ends: 52350 [2019-12-07 14:16:27,780 INFO L226 Difference]: Without dead ends: 52322 [2019-12-07 14:16:27,780 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:28,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52322 states. [2019-12-07 14:16:28,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52322 to 47546. [2019-12-07 14:16:28,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47546 states. [2019-12-07 14:16:28,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47546 states to 47546 states and 197076 transitions. [2019-12-07 14:16:28,946 INFO L78 Accepts]: Start accepts. Automaton has 47546 states and 197076 transitions. Word has length 15 [2019-12-07 14:16:28,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:28,946 INFO L462 AbstractCegarLoop]: Abstraction has 47546 states and 197076 transitions. [2019-12-07 14:16:28,947 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:16:28,947 INFO L276 IsEmpty]: Start isEmpty. Operand 47546 states and 197076 transitions. [2019-12-07 14:16:28,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 14:16:28,949 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:28,949 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:28,949 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:28,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:28,949 INFO L82 PathProgramCache]: Analyzing trace with hash -1899832342, now seen corresponding path program 1 times [2019-12-07 14:16:28,949 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:28,950 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465194060] [2019-12-07 14:16:28,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:28,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:28,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:28,996 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465194060] [2019-12-07 14:16:28,996 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:28,996 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:16:28,996 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439861866] [2019-12-07 14:16:28,997 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:16:28,997 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:28,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:16:28,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:16:28,997 INFO L87 Difference]: Start difference. First operand 47546 states and 197076 transitions. Second operand 4 states. [2019-12-07 14:16:29,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:29,487 INFO L93 Difference]: Finished difference Result 58566 states and 240916 transitions. [2019-12-07 14:16:29,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:16:29,488 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 14:16:29,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:29,619 INFO L225 Difference]: With dead ends: 58566 [2019-12-07 14:16:29,619 INFO L226 Difference]: Without dead ends: 58566 [2019-12-07 14:16:29,619 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:29,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58566 states. [2019-12-07 14:16:30,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58566 to 52262. [2019-12-07 14:16:30,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52262 states. [2019-12-07 14:16:30,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52262 states to 52262 states and 216300 transitions. [2019-12-07 14:16:30,878 INFO L78 Accepts]: Start accepts. Automaton has 52262 states and 216300 transitions. Word has length 15 [2019-12-07 14:16:30,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:30,878 INFO L462 AbstractCegarLoop]: Abstraction has 52262 states and 216300 transitions. [2019-12-07 14:16:30,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:16:30,878 INFO L276 IsEmpty]: Start isEmpty. Operand 52262 states and 216300 transitions. [2019-12-07 14:16:30,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 14:16:30,891 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:30,891 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:30,891 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:30,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:30,891 INFO L82 PathProgramCache]: Analyzing trace with hash -1099673125, now seen corresponding path program 1 times [2019-12-07 14:16:30,892 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:30,892 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539093609] [2019-12-07 14:16:30,892 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:30,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:30,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:30,954 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539093609] [2019-12-07 14:16:30,954 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:30,954 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:16:30,955 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833463785] [2019-12-07 14:16:30,955 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:16:30,955 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:30,955 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:16:30,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:16:30,956 INFO L87 Difference]: Start difference. First operand 52262 states and 216300 transitions. Second operand 4 states. [2019-12-07 14:16:31,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:31,110 INFO L93 Difference]: Finished difference Result 41984 states and 159713 transitions. [2019-12-07 14:16:31,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:16:31,111 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2019-12-07 14:16:31,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:31,194 INFO L225 Difference]: With dead ends: 41984 [2019-12-07 14:16:31,194 INFO L226 Difference]: Without dead ends: 40876 [2019-12-07 14:16:31,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:31,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40876 states. [2019-12-07 14:16:32,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40876 to 40876. [2019-12-07 14:16:32,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40876 states. [2019-12-07 14:16:32,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40876 states to 40876 states and 156237 transitions. [2019-12-07 14:16:32,122 INFO L78 Accepts]: Start accepts. Automaton has 40876 states and 156237 transitions. Word has length 21 [2019-12-07 14:16:32,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:32,122 INFO L462 AbstractCegarLoop]: Abstraction has 40876 states and 156237 transitions. [2019-12-07 14:16:32,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:16:32,123 INFO L276 IsEmpty]: Start isEmpty. Operand 40876 states and 156237 transitions. [2019-12-07 14:16:32,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 14:16:32,130 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:32,130 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:32,130 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:32,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:32,130 INFO L82 PathProgramCache]: Analyzing trace with hash 637645513, now seen corresponding path program 1 times [2019-12-07 14:16:32,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:32,131 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425258487] [2019-12-07 14:16:32,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:32,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:32,196 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425258487] [2019-12-07 14:16:32,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:32,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:16:32,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558727648] [2019-12-07 14:16:32,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:16:32,197 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:32,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:16:32,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:32,197 INFO L87 Difference]: Start difference. First operand 40876 states and 156237 transitions. Second operand 5 states. [2019-12-07 14:16:32,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:32,628 INFO L93 Difference]: Finished difference Result 54396 states and 204140 transitions. [2019-12-07 14:16:32,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:16:32,628 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 14:16:32,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:32,738 INFO L225 Difference]: With dead ends: 54396 [2019-12-07 14:16:32,738 INFO L226 Difference]: Without dead ends: 54375 [2019-12-07 14:16:32,739 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:16:32,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54375 states. [2019-12-07 14:16:33,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54375 to 41122. [2019-12-07 14:16:33,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41122 states. [2019-12-07 14:16:33,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41122 states to 41122 states and 156869 transitions. [2019-12-07 14:16:33,782 INFO L78 Accepts]: Start accepts. Automaton has 41122 states and 156869 transitions. Word has length 22 [2019-12-07 14:16:33,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:33,783 INFO L462 AbstractCegarLoop]: Abstraction has 41122 states and 156869 transitions. [2019-12-07 14:16:33,783 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:16:33,783 INFO L276 IsEmpty]: Start isEmpty. Operand 41122 states and 156869 transitions. [2019-12-07 14:16:33,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 14:16:33,806 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:33,806 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:33,806 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:33,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:33,806 INFO L82 PathProgramCache]: Analyzing trace with hash -2027557007, now seen corresponding path program 1 times [2019-12-07 14:16:33,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:33,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449794315] [2019-12-07 14:16:33,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:33,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:33,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:33,843 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449794315] [2019-12-07 14:16:33,843 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:33,843 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:16:33,843 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926933339] [2019-12-07 14:16:33,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:16:33,844 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:33,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:16:33,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:33,844 INFO L87 Difference]: Start difference. First operand 41122 states and 156869 transitions. Second operand 3 states. [2019-12-07 14:16:34,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:34,055 INFO L93 Difference]: Finished difference Result 51974 states and 196153 transitions. [2019-12-07 14:16:34,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:16:34,055 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2019-12-07 14:16:34,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:34,161 INFO L225 Difference]: With dead ends: 51974 [2019-12-07 14:16:34,161 INFO L226 Difference]: Without dead ends: 51974 [2019-12-07 14:16:34,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:34,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51974 states. [2019-12-07 14:16:34,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51974 to 45309. [2019-12-07 14:16:34,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45309 states. [2019-12-07 14:16:35,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45309 states to 45309 states and 172388 transitions. [2019-12-07 14:16:35,060 INFO L78 Accepts]: Start accepts. Automaton has 45309 states and 172388 transitions. Word has length 30 [2019-12-07 14:16:35,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:35,060 INFO L462 AbstractCegarLoop]: Abstraction has 45309 states and 172388 transitions. [2019-12-07 14:16:35,060 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:16:35,060 INFO L276 IsEmpty]: Start isEmpty. Operand 45309 states and 172388 transitions. [2019-12-07 14:16:35,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 14:16:35,084 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:35,085 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:35,085 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:35,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:35,085 INFO L82 PathProgramCache]: Analyzing trace with hash -2027793723, now seen corresponding path program 1 times [2019-12-07 14:16:35,085 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:35,085 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333624804] [2019-12-07 14:16:35,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:35,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:35,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:35,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333624804] [2019-12-07 14:16:35,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:35,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:16:35,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021780400] [2019-12-07 14:16:35,141 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:16:35,141 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:35,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:16:35,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:35,142 INFO L87 Difference]: Start difference. First operand 45309 states and 172388 transitions. Second operand 5 states. [2019-12-07 14:16:35,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:35,231 INFO L93 Difference]: Finished difference Result 19765 states and 62245 transitions. [2019-12-07 14:16:35,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:16:35,232 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2019-12-07 14:16:35,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:35,255 INFO L225 Difference]: With dead ends: 19765 [2019-12-07 14:16:35,256 INFO L226 Difference]: Without dead ends: 18889 [2019-12-07 14:16:35,256 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:35,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18889 states. [2019-12-07 14:16:35,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18889 to 18889. [2019-12-07 14:16:35,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18889 states. [2019-12-07 14:16:35,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18889 states to 18889 states and 59447 transitions. [2019-12-07 14:16:35,634 INFO L78 Accepts]: Start accepts. Automaton has 18889 states and 59447 transitions. Word has length 30 [2019-12-07 14:16:35,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:35,635 INFO L462 AbstractCegarLoop]: Abstraction has 18889 states and 59447 transitions. [2019-12-07 14:16:35,635 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:16:35,635 INFO L276 IsEmpty]: Start isEmpty. Operand 18889 states and 59447 transitions. [2019-12-07 14:16:35,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 14:16:35,644 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:35,644 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:35,644 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:35,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:35,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1945851485, now seen corresponding path program 1 times [2019-12-07 14:16:35,644 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:35,644 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834226841] [2019-12-07 14:16:35,644 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:35,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:35,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:35,705 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834226841] [2019-12-07 14:16:35,705 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:35,705 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:16:35,705 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507486712] [2019-12-07 14:16:35,706 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:16:35,706 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:35,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:16:35,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:16:35,706 INFO L87 Difference]: Start difference. First operand 18889 states and 59447 transitions. Second operand 6 states. [2019-12-07 14:16:35,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:35,766 INFO L93 Difference]: Finished difference Result 3470 states and 8793 transitions. [2019-12-07 14:16:35,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:16:35,766 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2019-12-07 14:16:35,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:35,770 INFO L225 Difference]: With dead ends: 3470 [2019-12-07 14:16:35,770 INFO L226 Difference]: Without dead ends: 3101 [2019-12-07 14:16:35,770 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:16:35,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3101 states. [2019-12-07 14:16:35,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3101 to 3101. [2019-12-07 14:16:35,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3101 states. [2019-12-07 14:16:35,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3101 states to 3101 states and 7755 transitions. [2019-12-07 14:16:35,807 INFO L78 Accepts]: Start accepts. Automaton has 3101 states and 7755 transitions. Word has length 31 [2019-12-07 14:16:35,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:35,807 INFO L462 AbstractCegarLoop]: Abstraction has 3101 states and 7755 transitions. [2019-12-07 14:16:35,807 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:16:35,807 INFO L276 IsEmpty]: Start isEmpty. Operand 3101 states and 7755 transitions. [2019-12-07 14:16:35,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 14:16:35,810 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:35,810 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:35,810 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:35,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:35,810 INFO L82 PathProgramCache]: Analyzing trace with hash -476238483, now seen corresponding path program 1 times [2019-12-07 14:16:35,811 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:35,811 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86569528] [2019-12-07 14:16:35,811 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:35,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:35,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:35,881 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86569528] [2019-12-07 14:16:35,881 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:35,881 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:16:35,881 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411149655] [2019-12-07 14:16:35,882 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:16:35,882 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:35,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:16:35,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:35,882 INFO L87 Difference]: Start difference. First operand 3101 states and 7755 transitions. Second operand 7 states. [2019-12-07 14:16:35,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:35,947 INFO L93 Difference]: Finished difference Result 1342 states and 3750 transitions. [2019-12-07 14:16:35,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:16:35,948 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 43 [2019-12-07 14:16:35,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:35,949 INFO L225 Difference]: With dead ends: 1342 [2019-12-07 14:16:35,949 INFO L226 Difference]: Without dead ends: 1293 [2019-12-07 14:16:35,949 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:16:35,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-12-07 14:16:35,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 1181. [2019-12-07 14:16:35,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1181 states. [2019-12-07 14:16:35,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 3334 transitions. [2019-12-07 14:16:35,961 INFO L78 Accepts]: Start accepts. Automaton has 1181 states and 3334 transitions. Word has length 43 [2019-12-07 14:16:35,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:35,961 INFO L462 AbstractCegarLoop]: Abstraction has 1181 states and 3334 transitions. [2019-12-07 14:16:35,961 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:16:35,961 INFO L276 IsEmpty]: Start isEmpty. Operand 1181 states and 3334 transitions. [2019-12-07 14:16:35,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:16:35,963 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:35,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:35,963 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:35,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:35,963 INFO L82 PathProgramCache]: Analyzing trace with hash -409088440, now seen corresponding path program 1 times [2019-12-07 14:16:35,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:35,964 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390112835] [2019-12-07 14:16:35,964 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:35,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:36,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:36,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [390112835] [2019-12-07 14:16:36,022 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:36,022 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:16:36,022 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310892052] [2019-12-07 14:16:36,023 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:16:36,023 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:36,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:16:36,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:36,023 INFO L87 Difference]: Start difference. First operand 1181 states and 3334 transitions. Second operand 5 states. [2019-12-07 14:16:36,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:36,188 INFO L93 Difference]: Finished difference Result 1666 states and 4696 transitions. [2019-12-07 14:16:36,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:16:36,188 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 14:16:36,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:36,191 INFO L225 Difference]: With dead ends: 1666 [2019-12-07 14:16:36,191 INFO L226 Difference]: Without dead ends: 1666 [2019-12-07 14:16:36,191 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:36,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1666 states. [2019-12-07 14:16:36,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1666 to 1470. [2019-12-07 14:16:36,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1470 states. [2019-12-07 14:16:36,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1470 states to 1470 states and 4144 transitions. [2019-12-07 14:16:36,213 INFO L78 Accepts]: Start accepts. Automaton has 1470 states and 4144 transitions. Word has length 58 [2019-12-07 14:16:36,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:36,214 INFO L462 AbstractCegarLoop]: Abstraction has 1470 states and 4144 transitions. [2019-12-07 14:16:36,214 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:16:36,214 INFO L276 IsEmpty]: Start isEmpty. Operand 1470 states and 4144 transitions. [2019-12-07 14:16:36,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:16:36,217 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:36,217 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:36,217 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:36,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:36,217 INFO L82 PathProgramCache]: Analyzing trace with hash -2087231872, now seen corresponding path program 2 times [2019-12-07 14:16:36,217 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:36,217 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124623163] [2019-12-07 14:16:36,217 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:36,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:36,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:36,285 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124623163] [2019-12-07 14:16:36,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:36,285 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:16:36,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851128758] [2019-12-07 14:16:36,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:16:36,286 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:36,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:16:36,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:16:36,286 INFO L87 Difference]: Start difference. First operand 1470 states and 4144 transitions. Second operand 6 states. [2019-12-07 14:16:36,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:36,480 INFO L93 Difference]: Finished difference Result 1745 states and 4788 transitions. [2019-12-07 14:16:36,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:16:36,481 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 14:16:36,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:36,482 INFO L225 Difference]: With dead ends: 1745 [2019-12-07 14:16:36,482 INFO L226 Difference]: Without dead ends: 1745 [2019-12-07 14:16:36,483 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:36,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1745 states. [2019-12-07 14:16:36,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1745 to 1522. [2019-12-07 14:16:36,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1522 states. [2019-12-07 14:16:36,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1522 states to 1522 states and 4220 transitions. [2019-12-07 14:16:36,498 INFO L78 Accepts]: Start accepts. Automaton has 1522 states and 4220 transitions. Word has length 58 [2019-12-07 14:16:36,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:36,498 INFO L462 AbstractCegarLoop]: Abstraction has 1522 states and 4220 transitions. [2019-12-07 14:16:36,498 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:16:36,498 INFO L276 IsEmpty]: Start isEmpty. Operand 1522 states and 4220 transitions. [2019-12-07 14:16:36,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:16:36,500 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:36,500 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:36,500 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:36,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:36,500 INFO L82 PathProgramCache]: Analyzing trace with hash -893148506, now seen corresponding path program 3 times [2019-12-07 14:16:36,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:36,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155469135] [2019-12-07 14:16:36,501 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:36,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:36,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:36,570 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155469135] [2019-12-07 14:16:36,570 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:36,570 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:16:36,570 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91290882] [2019-12-07 14:16:36,571 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:16:36,571 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:36,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:16:36,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:16:36,571 INFO L87 Difference]: Start difference. First operand 1522 states and 4220 transitions. Second operand 6 states. [2019-12-07 14:16:36,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:36,726 INFO L93 Difference]: Finished difference Result 2004 states and 5532 transitions. [2019-12-07 14:16:36,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 14:16:36,726 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 14:16:36,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:36,728 INFO L225 Difference]: With dead ends: 2004 [2019-12-07 14:16:36,728 INFO L226 Difference]: Without dead ends: 2004 [2019-12-07 14:16:36,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:16:36,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2004 states. [2019-12-07 14:16:36,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2004 to 1550. [2019-12-07 14:16:36,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1550 states. [2019-12-07 14:16:36,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 1550 states and 4300 transitions. [2019-12-07 14:16:36,744 INFO L78 Accepts]: Start accepts. Automaton has 1550 states and 4300 transitions. Word has length 58 [2019-12-07 14:16:36,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:36,744 INFO L462 AbstractCegarLoop]: Abstraction has 1550 states and 4300 transitions. [2019-12-07 14:16:36,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:16:36,744 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 4300 transitions. [2019-12-07 14:16:36,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:16:36,746 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:36,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:36,747 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:36,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:36,747 INFO L82 PathProgramCache]: Analyzing trace with hash -1236108060, now seen corresponding path program 4 times [2019-12-07 14:16:36,747 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:36,747 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075224523] [2019-12-07 14:16:36,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:36,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:36,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:36,819 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075224523] [2019-12-07 14:16:36,819 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:36,819 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 14:16:36,819 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274752791] [2019-12-07 14:16:36,820 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:16:36,820 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:36,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:16:36,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:36,820 INFO L87 Difference]: Start difference. First operand 1550 states and 4300 transitions. Second operand 7 states. [2019-12-07 14:16:37,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:37,099 INFO L93 Difference]: Finished difference Result 2218 states and 6110 transitions. [2019-12-07 14:16:37,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:16:37,099 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 58 [2019-12-07 14:16:37,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:37,101 INFO L225 Difference]: With dead ends: 2218 [2019-12-07 14:16:37,102 INFO L226 Difference]: Without dead ends: 2218 [2019-12-07 14:16:37,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 8 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:16:37,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2218 states. [2019-12-07 14:16:37,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2218 to 1550. [2019-12-07 14:16:37,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1550 states. [2019-12-07 14:16:37,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 1550 states and 4300 transitions. [2019-12-07 14:16:37,121 INFO L78 Accepts]: Start accepts. Automaton has 1550 states and 4300 transitions. Word has length 58 [2019-12-07 14:16:37,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:37,122 INFO L462 AbstractCegarLoop]: Abstraction has 1550 states and 4300 transitions. [2019-12-07 14:16:37,122 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:16:37,122 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 4300 transitions. [2019-12-07 14:16:37,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:16:37,124 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:37,124 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:37,124 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:37,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:37,124 INFO L82 PathProgramCache]: Analyzing trace with hash -465324325, now seen corresponding path program 1 times [2019-12-07 14:16:37,125 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:37,125 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5465371] [2019-12-07 14:16:37,125 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:37,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:37,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:37,170 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5465371] [2019-12-07 14:16:37,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:37,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:16:37,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379234607] [2019-12-07 14:16:37,171 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:16:37,171 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:37,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:16:37,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:37,171 INFO L87 Difference]: Start difference. First operand 1550 states and 4300 transitions. Second operand 3 states. [2019-12-07 14:16:37,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:37,200 INFO L93 Difference]: Finished difference Result 1549 states and 4298 transitions. [2019-12-07 14:16:37,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:16:37,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 14:16:37,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:37,203 INFO L225 Difference]: With dead ends: 1549 [2019-12-07 14:16:37,203 INFO L226 Difference]: Without dead ends: 1549 [2019-12-07 14:16:37,203 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:37,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1549 states. [2019-12-07 14:16:37,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1549 to 1220. [2019-12-07 14:16:37,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1220 states. [2019-12-07 14:16:37,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 1220 states and 3384 transitions. [2019-12-07 14:16:37,223 INFO L78 Accepts]: Start accepts. Automaton has 1220 states and 3384 transitions. Word has length 59 [2019-12-07 14:16:37,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:37,224 INFO L462 AbstractCegarLoop]: Abstraction has 1220 states and 3384 transitions. [2019-12-07 14:16:37,224 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:16:37,224 INFO L276 IsEmpty]: Start isEmpty. Operand 1220 states and 3384 transitions. [2019-12-07 14:16:37,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:16:37,226 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:37,226 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:37,226 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:37,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:37,227 INFO L82 PathProgramCache]: Analyzing trace with hash -1494660078, now seen corresponding path program 1 times [2019-12-07 14:16:37,227 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:37,227 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434723258] [2019-12-07 14:16:37,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:37,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:37,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:37,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434723258] [2019-12-07 14:16:37,329 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:37,329 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:16:37,329 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28235293] [2019-12-07 14:16:37,330 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:16:37,330 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:37,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:16:37,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:37,330 INFO L87 Difference]: Start difference. First operand 1220 states and 3384 transitions. Second operand 7 states. [2019-12-07 14:16:37,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:37,412 INFO L93 Difference]: Finished difference Result 2350 states and 6053 transitions. [2019-12-07 14:16:37,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 14:16:37,412 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2019-12-07 14:16:37,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:37,414 INFO L225 Difference]: With dead ends: 2350 [2019-12-07 14:16:37,414 INFO L226 Difference]: Without dead ends: 1584 [2019-12-07 14:16:37,414 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:16:37,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1584 states. [2019-12-07 14:16:37,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1584 to 1074. [2019-12-07 14:16:37,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1074 states. [2019-12-07 14:16:37,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1074 states to 1074 states and 2890 transitions. [2019-12-07 14:16:37,425 INFO L78 Accepts]: Start accepts. Automaton has 1074 states and 2890 transitions. Word has length 59 [2019-12-07 14:16:37,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:37,426 INFO L462 AbstractCegarLoop]: Abstraction has 1074 states and 2890 transitions. [2019-12-07 14:16:37,426 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:16:37,426 INFO L276 IsEmpty]: Start isEmpty. Operand 1074 states and 2890 transitions. [2019-12-07 14:16:37,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:16:37,427 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:37,427 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:37,427 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:37,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:37,427 INFO L82 PathProgramCache]: Analyzing trace with hash 353850156, now seen corresponding path program 2 times [2019-12-07 14:16:37,427 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:37,427 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311306965] [2019-12-07 14:16:37,428 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:37,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:37,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:37,466 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311306965] [2019-12-07 14:16:37,466 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:37,466 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:16:37,467 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965445596] [2019-12-07 14:16:37,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:16:37,467 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:37,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:16:37,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:37,467 INFO L87 Difference]: Start difference. First operand 1074 states and 2890 transitions. Second operand 3 states. [2019-12-07 14:16:37,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:37,478 INFO L93 Difference]: Finished difference Result 1020 states and 2717 transitions. [2019-12-07 14:16:37,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:16:37,478 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 14:16:37,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:37,479 INFO L225 Difference]: With dead ends: 1020 [2019-12-07 14:16:37,479 INFO L226 Difference]: Without dead ends: 1020 [2019-12-07 14:16:37,479 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:16:37,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1020 states. [2019-12-07 14:16:37,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1020 to 1020. [2019-12-07 14:16:37,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1020 states. [2019-12-07 14:16:37,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1020 states to 1020 states and 2717 transitions. [2019-12-07 14:16:37,488 INFO L78 Accepts]: Start accepts. Automaton has 1020 states and 2717 transitions. Word has length 59 [2019-12-07 14:16:37,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:37,489 INFO L462 AbstractCegarLoop]: Abstraction has 1020 states and 2717 transitions. [2019-12-07 14:16:37,489 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:16:37,489 INFO L276 IsEmpty]: Start isEmpty. Operand 1020 states and 2717 transitions. [2019-12-07 14:16:37,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:16:37,490 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:37,490 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:37,490 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:37,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:37,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1968443931, now seen corresponding path program 1 times [2019-12-07 14:16:37,490 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:37,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019698081] [2019-12-07 14:16:37,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:37,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:37,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:37,647 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019698081] [2019-12-07 14:16:37,647 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:37,647 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 14:16:37,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765381670] [2019-12-07 14:16:37,647 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:16:37,647 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:37,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:16:37,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:16:37,648 INFO L87 Difference]: Start difference. First operand 1020 states and 2717 transitions. Second operand 13 states. [2019-12-07 14:16:38,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:38,027 INFO L93 Difference]: Finished difference Result 2575 states and 6195 transitions. [2019-12-07 14:16:38,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:16:38,027 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2019-12-07 14:16:38,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:38,028 INFO L225 Difference]: With dead ends: 2575 [2019-12-07 14:16:38,028 INFO L226 Difference]: Without dead ends: 796 [2019-12-07 14:16:38,028 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2019-12-07 14:16:38,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 796 states. [2019-12-07 14:16:38,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 796 to 571. [2019-12-07 14:16:38,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 571 states. [2019-12-07 14:16:38,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 571 states to 571 states and 1223 transitions. [2019-12-07 14:16:38,034 INFO L78 Accepts]: Start accepts. Automaton has 571 states and 1223 transitions. Word has length 60 [2019-12-07 14:16:38,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:38,034 INFO L462 AbstractCegarLoop]: Abstraction has 571 states and 1223 transitions. [2019-12-07 14:16:38,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:16:38,034 INFO L276 IsEmpty]: Start isEmpty. Operand 571 states and 1223 transitions. [2019-12-07 14:16:38,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:16:38,035 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:38,035 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:38,035 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:38,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:38,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1222711449, now seen corresponding path program 2 times [2019-12-07 14:16:38,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:38,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662312252] [2019-12-07 14:16:38,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:38,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:38,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:38,097 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662312252] [2019-12-07 14:16:38,097 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:38,097 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:16:38,097 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516237049] [2019-12-07 14:16:38,097 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:16:38,098 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:38,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:16:38,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:16:38,098 INFO L87 Difference]: Start difference. First operand 571 states and 1223 transitions. Second operand 5 states. [2019-12-07 14:16:38,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:38,128 INFO L93 Difference]: Finished difference Result 755 states and 1538 transitions. [2019-12-07 14:16:38,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:16:38,128 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 60 [2019-12-07 14:16:38,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:38,129 INFO L225 Difference]: With dead ends: 755 [2019-12-07 14:16:38,129 INFO L226 Difference]: Without dead ends: 215 [2019-12-07 14:16:38,129 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:16:38,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2019-12-07 14:16:38,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 215. [2019-12-07 14:16:38,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2019-12-07 14:16:38,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 364 transitions. [2019-12-07 14:16:38,131 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 364 transitions. Word has length 60 [2019-12-07 14:16:38,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:38,131 INFO L462 AbstractCegarLoop]: Abstraction has 215 states and 364 transitions. [2019-12-07 14:16:38,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:16:38,131 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 364 transitions. [2019-12-07 14:16:38,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:16:38,132 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:38,132 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:38,132 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:38,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:38,132 INFO L82 PathProgramCache]: Analyzing trace with hash 424334393, now seen corresponding path program 3 times [2019-12-07 14:16:38,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:38,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019708492] [2019-12-07 14:16:38,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:38,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:38,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:38,306 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019708492] [2019-12-07 14:16:38,307 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:38,307 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 14:16:38,307 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536195733] [2019-12-07 14:16:38,307 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 14:16:38,307 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:38,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 14:16:38,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:16:38,307 INFO L87 Difference]: Start difference. First operand 215 states and 364 transitions. Second operand 14 states. [2019-12-07 14:16:39,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:39,095 INFO L93 Difference]: Finished difference Result 390 states and 652 transitions. [2019-12-07 14:16:39,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:16:39,095 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2019-12-07 14:16:39,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:39,095 INFO L225 Difference]: With dead ends: 390 [2019-12-07 14:16:39,095 INFO L226 Difference]: Without dead ends: 357 [2019-12-07 14:16:39,096 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=106, Invalid=494, Unknown=0, NotChecked=0, Total=600 [2019-12-07 14:16:39,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2019-12-07 14:16:39,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 315. [2019-12-07 14:16:39,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-12-07 14:16:39,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 535 transitions. [2019-12-07 14:16:39,098 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 535 transitions. Word has length 60 [2019-12-07 14:16:39,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:39,098 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 535 transitions. [2019-12-07 14:16:39,099 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 14:16:39,099 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 535 transitions. [2019-12-07 14:16:39,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:16:39,099 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:39,099 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:39,099 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:39,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:39,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1214438793, now seen corresponding path program 4 times [2019-12-07 14:16:39,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:39,100 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927627430] [2019-12-07 14:16:39,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:39,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:16:39,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:16:39,390 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927627430] [2019-12-07 14:16:39,390 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:16:39,390 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 14:16:39,390 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384720320] [2019-12-07 14:16:39,390 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 14:16:39,390 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:16:39,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 14:16:39,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2019-12-07 14:16:39,391 INFO L87 Difference]: Start difference. First operand 315 states and 535 transitions. Second operand 16 states. [2019-12-07 14:16:39,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:16:39,842 INFO L93 Difference]: Finished difference Result 470 states and 772 transitions. [2019-12-07 14:16:39,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 14:16:39,842 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 60 [2019-12-07 14:16:39,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:16:39,842 INFO L225 Difference]: With dead ends: 470 [2019-12-07 14:16:39,843 INFO L226 Difference]: Without dead ends: 437 [2019-12-07 14:16:39,843 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 6 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=157, Invalid=773, Unknown=0, NotChecked=0, Total=930 [2019-12-07 14:16:39,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states. [2019-12-07 14:16:39,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 323. [2019-12-07 14:16:39,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 323 states. [2019-12-07 14:16:39,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 549 transitions. [2019-12-07 14:16:39,846 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 549 transitions. Word has length 60 [2019-12-07 14:16:39,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:16:39,846 INFO L462 AbstractCegarLoop]: Abstraction has 323 states and 549 transitions. [2019-12-07 14:16:39,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 14:16:39,846 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 549 transitions. [2019-12-07 14:16:39,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:16:39,847 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:16:39,847 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:16:39,847 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:16:39,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:16:39,847 INFO L82 PathProgramCache]: Analyzing trace with hash -1750352957, now seen corresponding path program 5 times [2019-12-07 14:16:39,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:16:39,847 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070014886] [2019-12-07 14:16:39,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:16:39,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:16:39,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:16:39,940 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 14:16:39,940 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:16:39,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t1477~0.base_22| 4) |v_#length_31|) (= v_~z$w_buff0~0_106 0) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= 0 |v_ULTIMATE.start_main_~#t1477~0.offset_17|) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1477~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1477~0.base_22|) |v_ULTIMATE.start_main_~#t1477~0.offset_17| 0)) |v_#memory_int_27|) (= v_~z$read_delayed_var~0.offset_7 0) (= v_~z$r_buff1_thd0~0_244 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1477~0.base_22|) 0) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1477~0.base_22|) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= v_~y~0_41 0) (= v_~x~0_54 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1477~0.base_22| 1)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t1480~0.offset=|v_ULTIMATE.start_main_~#t1480~0.offset_16|, ULTIMATE.start_main_~#t1479~0.base=|v_ULTIMATE.start_main_~#t1479~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_~#t1477~0.base=|v_ULTIMATE.start_main_~#t1477~0.base_22|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ULTIMATE.start_main_~#t1477~0.offset=|v_ULTIMATE.start_main_~#t1477~0.offset_17|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_~#t1478~0.base=|v_ULTIMATE.start_main_~#t1478~0.base_23|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ULTIMATE.start_main_~#t1480~0.base=|v_ULTIMATE.start_main_~#t1480~0.base_20|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ULTIMATE.start_main_~#t1479~0.offset=|v_ULTIMATE.start_main_~#t1479~0.offset_17|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1478~0.offset=|v_ULTIMATE.start_main_~#t1478~0.offset_18|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1480~0.offset, ULTIMATE.start_main_~#t1479~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1477~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1477~0.offset, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1478~0.base, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1480~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t1479~0.offset, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1478~0.offset, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 14:16:39,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1478~0.base_13|) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1478~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1478~0.base_13|) |v_ULTIMATE.start_main_~#t1478~0.offset_11| 1)) |v_#memory_int_19|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1478~0.base_13|) 0) (= 0 |v_ULTIMATE.start_main_~#t1478~0.offset_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1478~0.base_13|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1478~0.base_13| 1) |v_#valid_46|) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1478~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t1478~0.base=|v_ULTIMATE.start_main_~#t1478~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1478~0.offset=|v_ULTIMATE.start_main_~#t1478~0.offset_11|, #length=|v_#length_23|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1478~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1478~0.offset, #length] because there is no mapped edge [2019-12-07 14:16:39,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1479~0.offset_10|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1479~0.base_10| 4) |v_#length_19|) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1479~0.base_10| 1)) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1479~0.base_10|) 0) (not (= 0 |v_ULTIMATE.start_main_~#t1479~0.base_10|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1479~0.base_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1479~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1479~0.base_10|) |v_ULTIMATE.start_main_~#t1479~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1479~0.base=|v_ULTIMATE.start_main_~#t1479~0.base_10|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1479~0.offset=|v_ULTIMATE.start_main_~#t1479~0.offset_10|, #length=|v_#length_19|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1479~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1479~0.offset, #length] because there is no mapped edge [2019-12-07 14:16:39,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1480~0.base_11| 1)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1480~0.base_11|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1480~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t1480~0.base_11| 0)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1480~0.base_11| 4)) (= |v_ULTIMATE.start_main_~#t1480~0.offset_10| 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1480~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1480~0.base_11|) |v_ULTIMATE.start_main_~#t1480~0.offset_10| 3)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t1480~0.base=|v_ULTIMATE.start_main_~#t1480~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1480~0.offset=|v_ULTIMATE.start_main_~#t1480~0.offset_10|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1480~0.base, ULTIMATE.start_main_~#t1480~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 14:16:39,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= ~z$r_buff1_thd3~0_Out87378247 ~z$r_buff0_thd3~0_In87378247) (= ~__unbuffered_p3_EAX~0_Out87378247 ~a~0_In87378247) (= ~z$r_buff0_thd4~0_Out87378247 1) (= ~z$r_buff0_thd1~0_In87378247 ~z$r_buff1_thd1~0_Out87378247) (= ~z$r_buff1_thd2~0_Out87378247 ~z$r_buff0_thd2~0_In87378247) (= ~z$r_buff1_thd4~0_Out87378247 ~z$r_buff0_thd4~0_In87378247) (= ~z$r_buff0_thd0~0_In87378247 ~z$r_buff1_thd0~0_Out87378247) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247))) InVars {~a~0=~a~0_In87378247, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In87378247, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In87378247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In87378247} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out87378247, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out87378247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out87378247, ~a~0=~a~0_In87378247, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In87378247, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out87378247, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out87378247, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out87378247, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In87378247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In87378247} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 14:16:39,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 14:16:39,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 14:16:39,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In738906220 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In738906220 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite11_Out738906220| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In738906220 |P3Thread1of1ForFork3_#t~ite11_Out738906220|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In738906220, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In738906220} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In738906220, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In738906220, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out738906220|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 14:16:39,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In468501137 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In468501137 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite3_Out468501137| ~z~0_In468501137) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite3_Out468501137| ~z$w_buff1~0_In468501137)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In468501137, ~z$w_buff1_used~0=~z$w_buff1_used~0_In468501137, ~z$w_buff1~0=~z$w_buff1~0_In468501137, ~z~0=~z~0_In468501137} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out468501137|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In468501137, ~z$w_buff1_used~0=~z$w_buff1_used~0_In468501137, ~z$w_buff1~0=~z$w_buff1~0_In468501137, ~z~0=~z~0_In468501137} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:16:39,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 14:16:39,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd4~0_In464690363 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In464690363 256))) (.cse1 (= (mod ~z$r_buff0_thd4~0_In464690363 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In464690363 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out464690363|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$w_buff1_used~0_In464690363 |P3Thread1of1ForFork3_#t~ite12_Out464690363|)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In464690363, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464690363, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In464690363, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464690363} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In464690363, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464690363, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In464690363, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464690363, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out464690363|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 14:16:39,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse0 (= ~z$r_buff0_thd4~0_Out1624176545 ~z$r_buff0_thd4~0_In1624176545)) (.cse2 (= (mod ~z$r_buff0_thd4~0_In1624176545 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1624176545 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse2) (= 0 ~z$r_buff0_thd4~0_Out1624176545) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1624176545, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1624176545} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1624176545, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out1624176545, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out1624176545|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 14:16:39,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd4~0_In-1329984439 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1329984439 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1329984439 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In-1329984439 256)))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite14_Out-1329984439|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~z$r_buff1_thd4~0_In-1329984439 |P3Thread1of1ForFork3_#t~ite14_Out-1329984439|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1329984439, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1329984439, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1329984439, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1329984439} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1329984439, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1329984439, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-1329984439|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1329984439, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1329984439} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 14:16:39,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 14:16:39,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1815220762 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1815220762 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite5_Out1815220762| 0)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite5_Out1815220762| ~z$w_buff0_used~0_In1815220762)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1815220762, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1815220762} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out1815220762|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1815220762, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1815220762} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:16:39,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-381938767 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-381938767 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-381938767 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-381938767 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-381938767 |P2Thread1of1ForFork2_#t~ite6_Out-381938767|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite6_Out-381938767|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-381938767, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-381938767, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-381938767, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-381938767} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-381938767|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-381938767, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-381938767, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-381938767, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-381938767} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:16:39,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1664371069 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1664371069 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-1664371069|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1664371069 |P2Thread1of1ForFork2_#t~ite7_Out-1664371069|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1664371069, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1664371069} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1664371069, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1664371069, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-1664371069|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:16:39,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-458252686 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-458252686 256))) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-458252686 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-458252686 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd3~0_In-458252686 |P2Thread1of1ForFork2_#t~ite8_Out-458252686|)) (and (= |P2Thread1of1ForFork2_#t~ite8_Out-458252686| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-458252686, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-458252686, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-458252686, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-458252686} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-458252686, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-458252686, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-458252686, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-458252686, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-458252686|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:16:39,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:16:39,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 14:16:39,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In654803641 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In654803641 256)))) (or (and (= ~z~0_In654803641 |ULTIMATE.start_main_#t~ite19_Out654803641|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In654803641 |ULTIMATE.start_main_#t~ite19_Out654803641|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In654803641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In654803641, ~z$w_buff1~0=~z$w_buff1~0_In654803641, ~z~0=~z~0_In654803641} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out654803641|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In654803641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In654803641, ~z$w_buff1~0=~z$w_buff1~0_In654803641, ~z~0=~z~0_In654803641} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:16:39,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:16:39,953 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-1430865490 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1430865490 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1430865490| ~z$w_buff0_used~0_In-1430865490)) (and (= |ULTIMATE.start_main_#t~ite21_Out-1430865490| 0) (not .cse0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1430865490, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1430865490} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1430865490, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1430865490, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1430865490|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:16:39,953 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1119753704 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1119753704 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1119753704 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1119753704 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out-1119753704| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1119753704 |ULTIMATE.start_main_#t~ite22_Out-1119753704|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1119753704, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119753704, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1119753704, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119753704} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1119753704, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119753704, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1119753704, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119753704, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1119753704|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:16:39,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1987622913 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1987622913 256) 0))) (or (and (= ~z$r_buff0_thd0~0_In1987622913 |ULTIMATE.start_main_#t~ite23_Out1987622913|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite23_Out1987622913| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1987622913, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1987622913} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1987622913, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1987622913, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1987622913|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:16:39,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In457397129 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In457397129 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In457397129 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In457397129 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite24_Out457397129| ~z$r_buff1_thd0~0_In457397129)) (and (= |ULTIMATE.start_main_#t~ite24_Out457397129| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In457397129, ~z$w_buff0_used~0=~z$w_buff0_used~0_In457397129, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In457397129, ~z$w_buff1_used~0=~z$w_buff1_used~0_In457397129} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In457397129, ~z$w_buff0_used~0=~z$w_buff0_used~0_In457397129, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In457397129, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out457397129|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In457397129} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 14:16:39,956 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In123947471 256)))) (or (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In123947471 256) 0))) (or (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In123947471 256))) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In123947471 256))) (= (mod ~z$w_buff0_used~0_In123947471 256) 0))) (= |ULTIMATE.start_main_#t~ite34_Out123947471| |ULTIMATE.start_main_#t~ite33_Out123947471|) (= ~z$w_buff1~0_In123947471 |ULTIMATE.start_main_#t~ite33_Out123947471|)) (and (not .cse0) (= ~z$w_buff1~0_In123947471 |ULTIMATE.start_main_#t~ite34_Out123947471|) (= |ULTIMATE.start_main_#t~ite33_In123947471| |ULTIMATE.start_main_#t~ite33_Out123947471|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In123947471, ~z$w_buff0_used~0=~z$w_buff0_used~0_In123947471, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In123947471, ~z$w_buff1_used~0=~z$w_buff1_used~0_In123947471, ~z$w_buff1~0=~z$w_buff1~0_In123947471, ~weak$$choice2~0=~weak$$choice2~0_In123947471, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In123947471|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In123947471, ~z$w_buff0_used~0=~z$w_buff0_used~0_In123947471, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In123947471, ~z$w_buff1_used~0=~z$w_buff1_used~0_In123947471, ~z$w_buff1~0=~z$w_buff1~0_In123947471, ~weak$$choice2~0=~weak$$choice2~0_In123947471, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out123947471|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out123947471|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 14:16:39,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-1266046541 256)))) (or (and (= ~z$w_buff1_used~0_In-1266046541 |ULTIMATE.start_main_#t~ite39_Out-1266046541|) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1266046541 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In-1266046541 256)) (and (= 0 (mod ~z$w_buff1_used~0_In-1266046541 256)) .cse0) (and (= (mod ~z$r_buff1_thd0~0_In-1266046541 256) 0) .cse0))) .cse1 (= |ULTIMATE.start_main_#t~ite40_Out-1266046541| |ULTIMATE.start_main_#t~ite39_Out-1266046541|)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite39_In-1266046541| |ULTIMATE.start_main_#t~ite39_Out-1266046541|) (= |ULTIMATE.start_main_#t~ite40_Out-1266046541| ~z$w_buff1_used~0_In-1266046541)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1266046541, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1266046541|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~weak$$choice2~0=~weak$$choice2~0_In-1266046541} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1266046541, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1266046541|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1266046541|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~weak$$choice2~0=~weak$$choice2~0_In-1266046541} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 14:16:39,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:16:39,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In1100538828 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out1100538828| |ULTIMATE.start_main_#t~ite46_Out1100538828|) (= |ULTIMATE.start_main_#t~ite45_Out1100538828| ~z$r_buff1_thd0~0_In1100538828) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In1100538828 256)))) (or (and (= 0 (mod ~z$w_buff1_used~0_In1100538828 256)) .cse0) (and (= 0 (mod ~z$r_buff1_thd0~0_In1100538828 256)) .cse0) (= 0 (mod ~z$w_buff0_used~0_In1100538828 256)))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite45_In1100538828| |ULTIMATE.start_main_#t~ite45_Out1100538828|) (= |ULTIMATE.start_main_#t~ite46_Out1100538828| ~z$r_buff1_thd0~0_In1100538828)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1100538828, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1100538828, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1100538828, ~weak$$choice2~0=~weak$$choice2~0_In1100538828, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1100538828|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1100538828, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1100538828, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1100538828, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1100538828|, ~weak$$choice2~0=~weak$$choice2~0_In1100538828, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1100538828|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 14:16:39,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:16:39,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:16:40,014 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:16:40 BasicIcfg [2019-12-07 14:16:40,014 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:16:40,014 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:16:40,014 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:16:40,014 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:16:40,015 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:16:20" (3/4) ... [2019-12-07 14:16:40,016 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:16:40,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t1477~0.base_22| 4) |v_#length_31|) (= v_~z$w_buff0~0_106 0) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= 0 |v_ULTIMATE.start_main_~#t1477~0.offset_17|) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1477~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1477~0.base_22|) |v_ULTIMATE.start_main_~#t1477~0.offset_17| 0)) |v_#memory_int_27|) (= v_~z$read_delayed_var~0.offset_7 0) (= v_~z$r_buff1_thd0~0_244 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1477~0.base_22|) 0) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1477~0.base_22|) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= v_~y~0_41 0) (= v_~x~0_54 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1477~0.base_22| 1)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t1480~0.offset=|v_ULTIMATE.start_main_~#t1480~0.offset_16|, ULTIMATE.start_main_~#t1479~0.base=|v_ULTIMATE.start_main_~#t1479~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_~#t1477~0.base=|v_ULTIMATE.start_main_~#t1477~0.base_22|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ULTIMATE.start_main_~#t1477~0.offset=|v_ULTIMATE.start_main_~#t1477~0.offset_17|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_~#t1478~0.base=|v_ULTIMATE.start_main_~#t1478~0.base_23|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ULTIMATE.start_main_~#t1480~0.base=|v_ULTIMATE.start_main_~#t1480~0.base_20|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ULTIMATE.start_main_~#t1479~0.offset=|v_ULTIMATE.start_main_~#t1479~0.offset_17|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1478~0.offset=|v_ULTIMATE.start_main_~#t1478~0.offset_18|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1480~0.offset, ULTIMATE.start_main_~#t1479~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1477~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1477~0.offset, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1478~0.base, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1480~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t1479~0.offset, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1478~0.offset, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 14:16:40,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1478~0.base_13|) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1478~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1478~0.base_13|) |v_ULTIMATE.start_main_~#t1478~0.offset_11| 1)) |v_#memory_int_19|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1478~0.base_13|) 0) (= 0 |v_ULTIMATE.start_main_~#t1478~0.offset_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1478~0.base_13|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1478~0.base_13| 1) |v_#valid_46|) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1478~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t1478~0.base=|v_ULTIMATE.start_main_~#t1478~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1478~0.offset=|v_ULTIMATE.start_main_~#t1478~0.offset_11|, #length=|v_#length_23|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1478~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1478~0.offset, #length] because there is no mapped edge [2019-12-07 14:16:40,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1479~0.offset_10|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1479~0.base_10| 4) |v_#length_19|) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1479~0.base_10| 1)) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1479~0.base_10|) 0) (not (= 0 |v_ULTIMATE.start_main_~#t1479~0.base_10|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1479~0.base_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1479~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1479~0.base_10|) |v_ULTIMATE.start_main_~#t1479~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1479~0.base=|v_ULTIMATE.start_main_~#t1479~0.base_10|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1479~0.offset=|v_ULTIMATE.start_main_~#t1479~0.offset_10|, #length=|v_#length_19|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1479~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1479~0.offset, #length] because there is no mapped edge [2019-12-07 14:16:40,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1480~0.base_11| 1)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1480~0.base_11|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1480~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t1480~0.base_11| 0)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1480~0.base_11| 4)) (= |v_ULTIMATE.start_main_~#t1480~0.offset_10| 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1480~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1480~0.base_11|) |v_ULTIMATE.start_main_~#t1480~0.offset_10| 3)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t1480~0.base=|v_ULTIMATE.start_main_~#t1480~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1480~0.offset=|v_ULTIMATE.start_main_~#t1480~0.offset_10|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1480~0.base, ULTIMATE.start_main_~#t1480~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 14:16:40,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= ~z$r_buff1_thd3~0_Out87378247 ~z$r_buff0_thd3~0_In87378247) (= ~__unbuffered_p3_EAX~0_Out87378247 ~a~0_In87378247) (= ~z$r_buff0_thd4~0_Out87378247 1) (= ~z$r_buff0_thd1~0_In87378247 ~z$r_buff1_thd1~0_Out87378247) (= ~z$r_buff1_thd2~0_Out87378247 ~z$r_buff0_thd2~0_In87378247) (= ~z$r_buff1_thd4~0_Out87378247 ~z$r_buff0_thd4~0_In87378247) (= ~z$r_buff0_thd0~0_In87378247 ~z$r_buff1_thd0~0_Out87378247) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247))) InVars {~a~0=~a~0_In87378247, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In87378247, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In87378247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In87378247} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In87378247, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out87378247, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out87378247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out87378247, ~a~0=~a~0_In87378247, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In87378247, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out87378247, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out87378247, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out87378247, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In87378247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In87378247} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 14:16:40,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 14:16:40,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 14:16:40,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In738906220 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In738906220 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite11_Out738906220| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In738906220 |P3Thread1of1ForFork3_#t~ite11_Out738906220|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In738906220, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In738906220} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In738906220, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In738906220, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out738906220|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 14:16:40,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In468501137 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In468501137 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite3_Out468501137| ~z~0_In468501137) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite3_Out468501137| ~z$w_buff1~0_In468501137)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In468501137, ~z$w_buff1_used~0=~z$w_buff1_used~0_In468501137, ~z$w_buff1~0=~z$w_buff1~0_In468501137, ~z~0=~z~0_In468501137} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out468501137|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In468501137, ~z$w_buff1_used~0=~z$w_buff1_used~0_In468501137, ~z$w_buff1~0=~z$w_buff1~0_In468501137, ~z~0=~z~0_In468501137} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:16:40,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 14:16:40,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd4~0_In464690363 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In464690363 256))) (.cse1 (= (mod ~z$r_buff0_thd4~0_In464690363 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In464690363 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out464690363|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$w_buff1_used~0_In464690363 |P3Thread1of1ForFork3_#t~ite12_Out464690363|)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In464690363, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464690363, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In464690363, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464690363} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In464690363, ~z$w_buff0_used~0=~z$w_buff0_used~0_In464690363, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In464690363, ~z$w_buff1_used~0=~z$w_buff1_used~0_In464690363, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out464690363|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 14:16:40,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse0 (= ~z$r_buff0_thd4~0_Out1624176545 ~z$r_buff0_thd4~0_In1624176545)) (.cse2 (= (mod ~z$r_buff0_thd4~0_In1624176545 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1624176545 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse2) (= 0 ~z$r_buff0_thd4~0_Out1624176545) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1624176545, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1624176545} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1624176545, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out1624176545, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out1624176545|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 14:16:40,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd4~0_In-1329984439 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1329984439 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1329984439 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In-1329984439 256)))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite14_Out-1329984439|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~z$r_buff1_thd4~0_In-1329984439 |P3Thread1of1ForFork3_#t~ite14_Out-1329984439|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1329984439, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1329984439, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1329984439, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1329984439} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-1329984439, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1329984439, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-1329984439|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1329984439, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1329984439} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 14:16:40,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 14:16:40,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1815220762 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1815220762 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite5_Out1815220762| 0)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite5_Out1815220762| ~z$w_buff0_used~0_In1815220762)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1815220762, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1815220762} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out1815220762|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1815220762, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1815220762} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:16:40,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-381938767 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-381938767 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-381938767 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-381938767 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-381938767 |P2Thread1of1ForFork2_#t~ite6_Out-381938767|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite6_Out-381938767|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-381938767, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-381938767, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-381938767, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-381938767} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-381938767|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-381938767, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-381938767, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-381938767, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-381938767} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1664371069 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1664371069 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-1664371069|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1664371069 |P2Thread1of1ForFork2_#t~ite7_Out-1664371069|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1664371069, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1664371069} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1664371069, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1664371069, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-1664371069|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-458252686 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-458252686 256))) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-458252686 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-458252686 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd3~0_In-458252686 |P2Thread1of1ForFork2_#t~ite8_Out-458252686|)) (and (= |P2Thread1of1ForFork2_#t~ite8_Out-458252686| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-458252686, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-458252686, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-458252686, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-458252686} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-458252686, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-458252686, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-458252686, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-458252686, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-458252686|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In654803641 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In654803641 256)))) (or (and (= ~z~0_In654803641 |ULTIMATE.start_main_#t~ite19_Out654803641|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In654803641 |ULTIMATE.start_main_#t~ite19_Out654803641|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In654803641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In654803641, ~z$w_buff1~0=~z$w_buff1~0_In654803641, ~z~0=~z~0_In654803641} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out654803641|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In654803641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In654803641, ~z$w_buff1~0=~z$w_buff1~0_In654803641, ~z~0=~z~0_In654803641} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:16:40,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:16:40,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-1430865490 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1430865490 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1430865490| ~z$w_buff0_used~0_In-1430865490)) (and (= |ULTIMATE.start_main_#t~ite21_Out-1430865490| 0) (not .cse0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1430865490, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1430865490} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1430865490, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1430865490, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1430865490|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:16:40,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1119753704 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1119753704 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1119753704 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1119753704 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out-1119753704| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1119753704 |ULTIMATE.start_main_#t~ite22_Out-1119753704|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1119753704, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119753704, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1119753704, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119753704} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1119753704, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119753704, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1119753704, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119753704, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1119753704|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:16:40,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1987622913 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1987622913 256) 0))) (or (and (= ~z$r_buff0_thd0~0_In1987622913 |ULTIMATE.start_main_#t~ite23_Out1987622913|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite23_Out1987622913| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1987622913, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1987622913} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1987622913, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1987622913, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1987622913|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:16:40,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In457397129 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In457397129 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In457397129 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In457397129 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite24_Out457397129| ~z$r_buff1_thd0~0_In457397129)) (and (= |ULTIMATE.start_main_#t~ite24_Out457397129| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In457397129, ~z$w_buff0_used~0=~z$w_buff0_used~0_In457397129, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In457397129, ~z$w_buff1_used~0=~z$w_buff1_used~0_In457397129} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In457397129, ~z$w_buff0_used~0=~z$w_buff0_used~0_In457397129, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In457397129, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out457397129|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In457397129} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 14:16:40,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In123947471 256)))) (or (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In123947471 256) 0))) (or (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In123947471 256))) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In123947471 256))) (= (mod ~z$w_buff0_used~0_In123947471 256) 0))) (= |ULTIMATE.start_main_#t~ite34_Out123947471| |ULTIMATE.start_main_#t~ite33_Out123947471|) (= ~z$w_buff1~0_In123947471 |ULTIMATE.start_main_#t~ite33_Out123947471|)) (and (not .cse0) (= ~z$w_buff1~0_In123947471 |ULTIMATE.start_main_#t~ite34_Out123947471|) (= |ULTIMATE.start_main_#t~ite33_In123947471| |ULTIMATE.start_main_#t~ite33_Out123947471|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In123947471, ~z$w_buff0_used~0=~z$w_buff0_used~0_In123947471, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In123947471, ~z$w_buff1_used~0=~z$w_buff1_used~0_In123947471, ~z$w_buff1~0=~z$w_buff1~0_In123947471, ~weak$$choice2~0=~weak$$choice2~0_In123947471, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In123947471|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In123947471, ~z$w_buff0_used~0=~z$w_buff0_used~0_In123947471, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In123947471, ~z$w_buff1_used~0=~z$w_buff1_used~0_In123947471, ~z$w_buff1~0=~z$w_buff1~0_In123947471, ~weak$$choice2~0=~weak$$choice2~0_In123947471, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out123947471|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out123947471|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 14:16:40,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-1266046541 256)))) (or (and (= ~z$w_buff1_used~0_In-1266046541 |ULTIMATE.start_main_#t~ite39_Out-1266046541|) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1266046541 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In-1266046541 256)) (and (= 0 (mod ~z$w_buff1_used~0_In-1266046541 256)) .cse0) (and (= (mod ~z$r_buff1_thd0~0_In-1266046541 256) 0) .cse0))) .cse1 (= |ULTIMATE.start_main_#t~ite40_Out-1266046541| |ULTIMATE.start_main_#t~ite39_Out-1266046541|)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite39_In-1266046541| |ULTIMATE.start_main_#t~ite39_Out-1266046541|) (= |ULTIMATE.start_main_#t~ite40_Out-1266046541| ~z$w_buff1_used~0_In-1266046541)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1266046541, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1266046541|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~weak$$choice2~0=~weak$$choice2~0_In-1266046541} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1266046541, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1266046541|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1266046541|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~weak$$choice2~0=~weak$$choice2~0_In-1266046541} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 14:16:40,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:16:40,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In1100538828 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out1100538828| |ULTIMATE.start_main_#t~ite46_Out1100538828|) (= |ULTIMATE.start_main_#t~ite45_Out1100538828| ~z$r_buff1_thd0~0_In1100538828) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In1100538828 256)))) (or (and (= 0 (mod ~z$w_buff1_used~0_In1100538828 256)) .cse0) (and (= 0 (mod ~z$r_buff1_thd0~0_In1100538828 256)) .cse0) (= 0 (mod ~z$w_buff0_used~0_In1100538828 256)))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite45_In1100538828| |ULTIMATE.start_main_#t~ite45_Out1100538828|) (= |ULTIMATE.start_main_#t~ite46_Out1100538828| ~z$r_buff1_thd0~0_In1100538828)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1100538828, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1100538828, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1100538828, ~weak$$choice2~0=~weak$$choice2~0_In1100538828, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1100538828|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1100538828, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1100538828, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1100538828, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1100538828|, ~weak$$choice2~0=~weak$$choice2~0_In1100538828, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1100538828|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 14:16:40,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:16:40,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:16:40,078 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_f2be606b-21ff-4ed6-9904-2ef3ec43338f/bin/utaipan/witness.graphml [2019-12-07 14:16:40,078 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:16:40,079 INFO L168 Benchmark]: Toolchain (without parser) took 20670.69 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.5 GB). Free memory was 932.6 MB in the beginning and 412.0 MB in the end (delta: 520.6 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,079 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 955.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:16:40,080 INFO L168 Benchmark]: CACSL2BoogieTranslator took 420.71 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 93.8 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -128.9 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,080 INFO L168 Benchmark]: Boogie Procedure Inliner took 46.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,080 INFO L168 Benchmark]: Boogie Preprocessor took 27.17 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:16:40,081 INFO L168 Benchmark]: RCFGBuilder took 429.46 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.3 MB in the end (delta: 51.4 MB). Peak memory consumption was 51.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,081 INFO L168 Benchmark]: TraceAbstraction took 19679.96 ms. Allocated memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 999.3 MB in the beginning and 420.3 MB in the end (delta: 579.0 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,081 INFO L168 Benchmark]: Witness Printer took 64.15 ms. Allocated memory is still 2.5 GB. Free memory was 420.3 MB in the beginning and 412.0 MB in the end (delta: 8.3 MB). Peak memory consumption was 8.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:16:40,082 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 955.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 420.71 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 93.8 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -128.9 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 46.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.17 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 429.46 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.3 MB in the end (delta: 51.4 MB). Peak memory consumption was 51.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19679.96 ms. Allocated memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 999.3 MB in the beginning and 420.3 MB in the end (delta: 579.0 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. * Witness Printer took 64.15 ms. Allocated memory is still 2.5 GB. Free memory was 420.3 MB in the beginning and 412.0 MB in the end (delta: 8.3 MB). Peak memory consumption was 8.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 179 ProgramPointsBefore, 91 ProgramPointsAfterwards, 207 TransitionsBefore, 97 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 7 FixpointIterations, 35 TrivialSequentialCompositions, 50 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 35 ConcurrentYvCompositions, 27 ChoiceCompositions, 4846 VarBasedMoverChecksPositive, 179 VarBasedMoverChecksNegative, 25 SemBasedMoverChecksPositive, 208 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.6s, 0 MoverChecksTotal, 50860 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L823] FCALL, FORK 0 pthread_create(&t1477, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1478, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1479, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] FCALL, FORK 0 pthread_create(&t1480, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L784] 4 z$w_buff1 = z$w_buff0 [L785] 4 z$w_buff0 = 2 [L786] 4 z$w_buff1_used = z$w_buff0_used [L787] 4 z$w_buff0_used = (_Bool)1 [L800] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L764] 3 y = 1 [L767] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L800] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L770] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L801] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L802] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L772] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L773] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L831] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L837] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L838] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L839] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L842] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L843] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L844] 0 z$flush_delayed = weak$$choice2 [L845] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L847] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L848] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L849] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L849] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L850] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L852] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L853] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p1_EAX == 0 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 19.5s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 5.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2372 SDtfs, 2955 SDslu, 6293 SDs, 0 SdLazy, 3160 SolverSat, 278 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 217 GetRequests, 38 SyntacticMatches, 20 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 352 ImplicationChecksByTransitivity, 1.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52262occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.8s AutomataMinimizationTime, 20 MinimizatonAttempts, 33871 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 925 NumberOfCodeBlocks, 925 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 845 ConstructedInterpolants, 0 QuantifiedInterpolants, 168344 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...