./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix055_tso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix055_tso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 805b104b9103953ae096e78912e1fcf9c4789fac .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:15:48,088 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:15:48,089 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:15:48,098 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:15:48,098 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:15:48,099 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:15:48,100 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:15:48,101 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:15:48,103 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:15:48,104 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:15:48,104 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:15:48,105 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:15:48,106 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:15:48,107 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:15:48,107 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:15:48,108 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:15:48,109 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:15:48,110 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:15:48,112 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:15:48,113 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:15:48,115 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:15:48,116 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:15:48,117 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:15:48,117 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:15:48,119 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:15:48,119 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:15:48,120 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:15:48,120 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:15:48,121 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:15:48,121 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:15:48,122 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:15:48,122 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:15:48,123 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:15:48,123 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:15:48,124 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:15:48,124 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:15:48,125 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:15:48,125 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:15:48,125 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:15:48,126 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:15:48,126 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:15:48,127 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 12:15:48,139 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:15:48,139 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:15:48,140 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 12:15:48,140 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 12:15:48,140 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 12:15:48,140 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 12:15:48,140 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 12:15:48,141 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 12:15:48,141 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 12:15:48,141 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 12:15:48,141 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 12:15:48,141 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 12:15:48,141 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 12:15:48,142 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 12:15:48,142 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 12:15:48,142 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:15:48,142 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 12:15:48,142 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:15:48,143 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 12:15:48,144 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:15:48,144 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 12:15:48,144 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 12:15:48,145 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 12:15:48,145 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 12:15:48,145 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:15:48,145 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 12:15:48,145 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 805b104b9103953ae096e78912e1fcf9c4789fac [2019-12-07 12:15:48,247 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:15:48,256 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:15:48,258 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:15:48,259 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:15:48,259 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:15:48,260 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/mix055_tso.opt.i [2019-12-07 12:15:48,297 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/data/fdbd3cb89/891b1f8f4f4b4e97a5e7ae8b41a82f19/FLAG396c8a3fa [2019-12-07 12:15:48,756 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:15:48,757 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/sv-benchmarks/c/pthread-wmm/mix055_tso.opt.i [2019-12-07 12:15:48,769 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/data/fdbd3cb89/891b1f8f4f4b4e97a5e7ae8b41a82f19/FLAG396c8a3fa [2019-12-07 12:15:49,281 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/data/fdbd3cb89/891b1f8f4f4b4e97a5e7ae8b41a82f19 [2019-12-07 12:15:49,283 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:15:49,285 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:15:49,285 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:15:49,285 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:15:49,289 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:15:49,289 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,292 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27a7eda1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49, skipping insertion in model container [2019-12-07 12:15:49,292 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,299 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:15:49,331 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:15:49,579 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:15:49,587 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:15:49,630 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:15:49,675 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:15:49,676 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49 WrapperNode [2019-12-07 12:15:49,676 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:15:49,677 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:15:49,677 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:15:49,677 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:15:49,683 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,697 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,724 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:15:49,724 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:15:49,724 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:15:49,724 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:15:49,733 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,733 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,737 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,738 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,747 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,750 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,753 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... [2019-12-07 12:15:49,757 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:15:49,757 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:15:49,758 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:15:49,758 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:15:49,758 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 12:15:49,805 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 12:15:49,805 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 12:15:49,805 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 12:15:49,806 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 12:15:49,806 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 12:15:49,806 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 12:15:49,806 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 12:15:49,806 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:15:49,806 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:15:49,807 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 12:15:50,172 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:15:50,172 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 12:15:50,173 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:15:50 BoogieIcfgContainer [2019-12-07 12:15:50,173 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:15:50,174 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 12:15:50,174 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 12:15:50,176 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 12:15:50,176 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 12:15:49" (1/3) ... [2019-12-07 12:15:50,177 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1694610 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:15:50, skipping insertion in model container [2019-12-07 12:15:50,177 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:15:49" (2/3) ... [2019-12-07 12:15:50,178 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1694610 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:15:50, skipping insertion in model container [2019-12-07 12:15:50,178 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:15:50" (3/3) ... [2019-12-07 12:15:50,179 INFO L109 eAbstractionObserver]: Analyzing ICFG mix055_tso.opt.i [2019-12-07 12:15:50,185 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 12:15:50,186 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 12:15:50,190 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 12:15:50,191 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 12:15:50,215 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,215 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,215 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,215 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,217 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,218 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,219 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,220 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,221 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,222 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,223 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,224 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:15:50,241 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 12:15:50,254 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 12:15:50,254 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 12:15:50,254 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 12:15:50,254 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:15:50,254 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:15:50,254 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 12:15:50,254 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:15:50,254 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 12:15:50,265 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 207 transitions [2019-12-07 12:15:50,266 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 12:15:50,329 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 12:15:50,329 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 12:15:50,342 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 12:15:50,353 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 207 transitions [2019-12-07 12:15:50,381 INFO L134 PetriNetUnfolder]: 41/203 cut-off events. [2019-12-07 12:15:50,381 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 12:15:50,385 INFO L76 FinitePrefix]: Finished finitePrefix Result has 216 conditions, 203 events. 41/203 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 12/172 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 12:15:50,397 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 12:15:50,398 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 12:15:53,159 WARN L192 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 93 [2019-12-07 12:15:53,251 INFO L206 etLargeBlockEncoding]: Checked pairs total: 50860 [2019-12-07 12:15:53,251 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 12:15:53,254 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 97 transitions [2019-12-07 12:15:55,079 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34622 states. [2019-12-07 12:15:55,080 INFO L276 IsEmpty]: Start isEmpty. Operand 34622 states. [2019-12-07 12:15:55,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 12:15:55,085 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:15:55,085 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:15:55,085 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:15:55,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:15:55,089 INFO L82 PathProgramCache]: Analyzing trace with hash 1893967926, now seen corresponding path program 1 times [2019-12-07 12:15:55,095 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:15:55,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025177883] [2019-12-07 12:15:55,095 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:15:55,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:15:55,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:15:55,247 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025177883] [2019-12-07 12:15:55,247 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:15:55,248 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 12:15:55,248 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808878200] [2019-12-07 12:15:55,251 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:15:55,251 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:15:55,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:15:55,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:15:55,262 INFO L87 Difference]: Start difference. First operand 34622 states. Second operand 3 states. [2019-12-07 12:15:55,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:15:55,651 INFO L93 Difference]: Finished difference Result 34366 states and 145832 transitions. [2019-12-07 12:15:55,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:15:55,653 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 12:15:55,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:15:55,867 INFO L225 Difference]: With dead ends: 34366 [2019-12-07 12:15:55,868 INFO L226 Difference]: Without dead ends: 33694 [2019-12-07 12:15:55,868 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:15:56,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33694 states. [2019-12-07 12:15:56,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33694 to 33694. [2019-12-07 12:15:56,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33694 states. [2019-12-07 12:15:56,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33694 states to 33694 states and 143088 transitions. [2019-12-07 12:15:56,865 INFO L78 Accepts]: Start accepts. Automaton has 33694 states and 143088 transitions. Word has length 9 [2019-12-07 12:15:56,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:15:56,866 INFO L462 AbstractCegarLoop]: Abstraction has 33694 states and 143088 transitions. [2019-12-07 12:15:56,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:15:56,866 INFO L276 IsEmpty]: Start isEmpty. Operand 33694 states and 143088 transitions. [2019-12-07 12:15:56,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 12:15:56,871 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:15:56,871 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:15:56,871 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:15:56,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:15:56,871 INFO L82 PathProgramCache]: Analyzing trace with hash 706074371, now seen corresponding path program 1 times [2019-12-07 12:15:56,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:15:56,872 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343015382] [2019-12-07 12:15:56,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:15:56,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:15:56,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:15:56,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343015382] [2019-12-07 12:15:56,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:15:56,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:15:56,934 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408211732] [2019-12-07 12:15:56,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:15:56,935 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:15:56,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:15:56,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:15:56,935 INFO L87 Difference]: Start difference. First operand 33694 states and 143088 transitions. Second operand 4 states. [2019-12-07 12:15:57,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:15:57,344 INFO L93 Difference]: Finished difference Result 52350 states and 214840 transitions. [2019-12-07 12:15:57,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:15:57,345 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 12:15:57,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:15:57,743 INFO L225 Difference]: With dead ends: 52350 [2019-12-07 12:15:57,744 INFO L226 Difference]: Without dead ends: 52322 [2019-12-07 12:15:57,744 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:15:58,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52322 states. [2019-12-07 12:15:58,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52322 to 47546. [2019-12-07 12:15:58,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47546 states. [2019-12-07 12:15:58,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47546 states to 47546 states and 197076 transitions. [2019-12-07 12:15:58,834 INFO L78 Accepts]: Start accepts. Automaton has 47546 states and 197076 transitions. Word has length 15 [2019-12-07 12:15:58,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:15:58,834 INFO L462 AbstractCegarLoop]: Abstraction has 47546 states and 197076 transitions. [2019-12-07 12:15:58,834 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:15:58,835 INFO L276 IsEmpty]: Start isEmpty. Operand 47546 states and 197076 transitions. [2019-12-07 12:15:58,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 12:15:58,837 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:15:58,837 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:15:58,837 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:15:58,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:15:58,837 INFO L82 PathProgramCache]: Analyzing trace with hash -1899832342, now seen corresponding path program 1 times [2019-12-07 12:15:58,837 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:15:58,837 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402856810] [2019-12-07 12:15:58,837 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:15:58,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:15:58,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:15:58,887 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402856810] [2019-12-07 12:15:58,887 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:15:58,887 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:15:58,887 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532432030] [2019-12-07 12:15:58,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:15:58,888 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:15:58,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:15:58,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:15:58,888 INFO L87 Difference]: Start difference. First operand 47546 states and 197076 transitions. Second operand 4 states. [2019-12-07 12:15:59,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:15:59,222 INFO L93 Difference]: Finished difference Result 58566 states and 240916 transitions. [2019-12-07 12:15:59,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:15:59,222 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 12:15:59,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:15:59,345 INFO L225 Difference]: With dead ends: 58566 [2019-12-07 12:15:59,345 INFO L226 Difference]: Without dead ends: 58566 [2019-12-07 12:15:59,346 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:15:59,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58566 states. [2019-12-07 12:16:00,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58566 to 52262. [2019-12-07 12:16:00,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52262 states. [2019-12-07 12:16:00,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52262 states to 52262 states and 216300 transitions. [2019-12-07 12:16:00,580 INFO L78 Accepts]: Start accepts. Automaton has 52262 states and 216300 transitions. Word has length 15 [2019-12-07 12:16:00,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:00,580 INFO L462 AbstractCegarLoop]: Abstraction has 52262 states and 216300 transitions. [2019-12-07 12:16:00,581 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:16:00,581 INFO L276 IsEmpty]: Start isEmpty. Operand 52262 states and 216300 transitions. [2019-12-07 12:16:00,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 12:16:00,590 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:00,590 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:00,590 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:00,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:00,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1099673125, now seen corresponding path program 1 times [2019-12-07 12:16:00,591 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:00,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243996774] [2019-12-07 12:16:00,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:00,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:00,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:00,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243996774] [2019-12-07 12:16:00,643 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:00,643 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:16:00,644 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948431350] [2019-12-07 12:16:00,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:16:00,644 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:00,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:16:00,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:16:00,644 INFO L87 Difference]: Start difference. First operand 52262 states and 216300 transitions. Second operand 4 states. [2019-12-07 12:16:00,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:00,949 INFO L93 Difference]: Finished difference Result 41984 states and 159713 transitions. [2019-12-07 12:16:00,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 12:16:00,950 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2019-12-07 12:16:00,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:01,027 INFO L225 Difference]: With dead ends: 41984 [2019-12-07 12:16:01,028 INFO L226 Difference]: Without dead ends: 40876 [2019-12-07 12:16:01,028 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:16:01,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40876 states. [2019-12-07 12:16:01,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40876 to 40876. [2019-12-07 12:16:01,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40876 states. [2019-12-07 12:16:01,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40876 states to 40876 states and 156237 transitions. [2019-12-07 12:16:01,748 INFO L78 Accepts]: Start accepts. Automaton has 40876 states and 156237 transitions. Word has length 21 [2019-12-07 12:16:01,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:01,748 INFO L462 AbstractCegarLoop]: Abstraction has 40876 states and 156237 transitions. [2019-12-07 12:16:01,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:16:01,749 INFO L276 IsEmpty]: Start isEmpty. Operand 40876 states and 156237 transitions. [2019-12-07 12:16:01,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 12:16:01,755 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:01,755 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:01,755 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:01,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:01,755 INFO L82 PathProgramCache]: Analyzing trace with hash 637645513, now seen corresponding path program 1 times [2019-12-07 12:16:01,755 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:01,755 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937628802] [2019-12-07 12:16:01,755 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:01,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:01,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:01,812 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937628802] [2019-12-07 12:16:01,812 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:01,812 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:16:01,812 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947277229] [2019-12-07 12:16:01,813 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:16:01,813 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:01,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:16:01,813 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:16:01,813 INFO L87 Difference]: Start difference. First operand 40876 states and 156237 transitions. Second operand 5 states. [2019-12-07 12:16:02,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:02,237 INFO L93 Difference]: Finished difference Result 54396 states and 204140 transitions. [2019-12-07 12:16:02,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 12:16:02,237 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 12:16:02,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:02,344 INFO L225 Difference]: With dead ends: 54396 [2019-12-07 12:16:02,345 INFO L226 Difference]: Without dead ends: 54375 [2019-12-07 12:16:02,345 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:16:02,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54375 states. [2019-12-07 12:16:03,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54375 to 41122. [2019-12-07 12:16:03,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41122 states. [2019-12-07 12:16:03,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41122 states to 41122 states and 156869 transitions. [2019-12-07 12:16:03,262 INFO L78 Accepts]: Start accepts. Automaton has 41122 states and 156869 transitions. Word has length 22 [2019-12-07 12:16:03,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:03,263 INFO L462 AbstractCegarLoop]: Abstraction has 41122 states and 156869 transitions. [2019-12-07 12:16:03,263 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:16:03,263 INFO L276 IsEmpty]: Start isEmpty. Operand 41122 states and 156869 transitions. [2019-12-07 12:16:03,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 12:16:03,285 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:03,285 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:03,285 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:03,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:03,285 INFO L82 PathProgramCache]: Analyzing trace with hash -2027557007, now seen corresponding path program 1 times [2019-12-07 12:16:03,286 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:03,286 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675599646] [2019-12-07 12:16:03,286 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:03,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:03,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:03,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675599646] [2019-12-07 12:16:03,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:03,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:16:03,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622335280] [2019-12-07 12:16:03,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:16:03,314 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:03,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:16:03,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:03,314 INFO L87 Difference]: Start difference. First operand 41122 states and 156869 transitions. Second operand 3 states. [2019-12-07 12:16:03,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:03,521 INFO L93 Difference]: Finished difference Result 51974 states and 196153 transitions. [2019-12-07 12:16:03,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:16:03,522 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2019-12-07 12:16:03,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:03,631 INFO L225 Difference]: With dead ends: 51974 [2019-12-07 12:16:03,631 INFO L226 Difference]: Without dead ends: 51974 [2019-12-07 12:16:03,631 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:03,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51974 states. [2019-12-07 12:16:04,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51974 to 45309. [2019-12-07 12:16:04,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45309 states. [2019-12-07 12:16:04,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45309 states to 45309 states and 172388 transitions. [2019-12-07 12:16:04,571 INFO L78 Accepts]: Start accepts. Automaton has 45309 states and 172388 transitions. Word has length 30 [2019-12-07 12:16:04,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:04,572 INFO L462 AbstractCegarLoop]: Abstraction has 45309 states and 172388 transitions. [2019-12-07 12:16:04,572 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:16:04,572 INFO L276 IsEmpty]: Start isEmpty. Operand 45309 states and 172388 transitions. [2019-12-07 12:16:04,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 12:16:04,593 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:04,594 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:04,594 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:04,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:04,594 INFO L82 PathProgramCache]: Analyzing trace with hash -2027793723, now seen corresponding path program 1 times [2019-12-07 12:16:04,594 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:04,594 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177869334] [2019-12-07 12:16:04,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:04,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:04,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:04,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177869334] [2019-12-07 12:16:04,643 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:04,643 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 12:16:04,643 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105894820] [2019-12-07 12:16:04,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:16:04,644 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:04,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:16:04,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:16:04,644 INFO L87 Difference]: Start difference. First operand 45309 states and 172388 transitions. Second operand 5 states. [2019-12-07 12:16:04,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:04,736 INFO L93 Difference]: Finished difference Result 19765 states and 62245 transitions. [2019-12-07 12:16:04,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:16:04,737 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2019-12-07 12:16:04,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:04,759 INFO L225 Difference]: With dead ends: 19765 [2019-12-07 12:16:04,760 INFO L226 Difference]: Without dead ends: 18889 [2019-12-07 12:16:04,760 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:04,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18889 states. [2019-12-07 12:16:04,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18889 to 18889. [2019-12-07 12:16:04,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18889 states. [2019-12-07 12:16:05,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18889 states to 18889 states and 59447 transitions. [2019-12-07 12:16:05,022 INFO L78 Accepts]: Start accepts. Automaton has 18889 states and 59447 transitions. Word has length 30 [2019-12-07 12:16:05,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:05,022 INFO L462 AbstractCegarLoop]: Abstraction has 18889 states and 59447 transitions. [2019-12-07 12:16:05,022 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:16:05,022 INFO L276 IsEmpty]: Start isEmpty. Operand 18889 states and 59447 transitions. [2019-12-07 12:16:05,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 12:16:05,030 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:05,030 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:05,030 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:05,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:05,030 INFO L82 PathProgramCache]: Analyzing trace with hash -1945851485, now seen corresponding path program 1 times [2019-12-07 12:16:05,030 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:05,031 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615404095] [2019-12-07 12:16:05,031 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:05,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:05,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:05,080 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615404095] [2019-12-07 12:16:05,081 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:05,081 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:16:05,081 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915220578] [2019-12-07 12:16:05,081 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:16:05,081 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:05,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:16:05,081 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:16:05,081 INFO L87 Difference]: Start difference. First operand 18889 states and 59447 transitions. Second operand 6 states. [2019-12-07 12:16:05,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:05,132 INFO L93 Difference]: Finished difference Result 3470 states and 8793 transitions. [2019-12-07 12:16:05,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:16:05,133 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2019-12-07 12:16:05,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:05,135 INFO L225 Difference]: With dead ends: 3470 [2019-12-07 12:16:05,135 INFO L226 Difference]: Without dead ends: 3101 [2019-12-07 12:16:05,136 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:16:05,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3101 states. [2019-12-07 12:16:05,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3101 to 3101. [2019-12-07 12:16:05,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3101 states. [2019-12-07 12:16:05,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3101 states to 3101 states and 7755 transitions. [2019-12-07 12:16:05,164 INFO L78 Accepts]: Start accepts. Automaton has 3101 states and 7755 transitions. Word has length 31 [2019-12-07 12:16:05,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:05,164 INFO L462 AbstractCegarLoop]: Abstraction has 3101 states and 7755 transitions. [2019-12-07 12:16:05,164 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:16:05,165 INFO L276 IsEmpty]: Start isEmpty. Operand 3101 states and 7755 transitions. [2019-12-07 12:16:05,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 12:16:05,167 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:05,167 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:05,168 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:05,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:05,168 INFO L82 PathProgramCache]: Analyzing trace with hash -476238483, now seen corresponding path program 1 times [2019-12-07 12:16:05,168 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:05,168 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194389815] [2019-12-07 12:16:05,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:05,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:05,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:05,222 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194389815] [2019-12-07 12:16:05,222 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:05,222 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:16:05,222 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380767501] [2019-12-07 12:16:05,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 12:16:05,223 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:05,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:16:05,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:05,223 INFO L87 Difference]: Start difference. First operand 3101 states and 7755 transitions. Second operand 7 states. [2019-12-07 12:16:05,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:05,286 INFO L93 Difference]: Finished difference Result 1342 states and 3750 transitions. [2019-12-07 12:16:05,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:16:05,287 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 43 [2019-12-07 12:16:05,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:05,288 INFO L225 Difference]: With dead ends: 1342 [2019-12-07 12:16:05,288 INFO L226 Difference]: Without dead ends: 1293 [2019-12-07 12:16:05,288 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 12:16:05,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-12-07 12:16:05,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 1181. [2019-12-07 12:16:05,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1181 states. [2019-12-07 12:16:05,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 3334 transitions. [2019-12-07 12:16:05,301 INFO L78 Accepts]: Start accepts. Automaton has 1181 states and 3334 transitions. Word has length 43 [2019-12-07 12:16:05,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:05,301 INFO L462 AbstractCegarLoop]: Abstraction has 1181 states and 3334 transitions. [2019-12-07 12:16:05,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 12:16:05,301 INFO L276 IsEmpty]: Start isEmpty. Operand 1181 states and 3334 transitions. [2019-12-07 12:16:05,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 12:16:05,303 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:05,303 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:05,303 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:05,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:05,303 INFO L82 PathProgramCache]: Analyzing trace with hash -409088440, now seen corresponding path program 1 times [2019-12-07 12:16:05,303 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:05,303 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940252506] [2019-12-07 12:16:05,303 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:05,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:05,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:05,360 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940252506] [2019-12-07 12:16:05,361 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:05,361 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:16:05,361 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510593339] [2019-12-07 12:16:05,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:16:05,361 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:05,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:16:05,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:16:05,361 INFO L87 Difference]: Start difference. First operand 1181 states and 3334 transitions. Second operand 5 states. [2019-12-07 12:16:05,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:05,496 INFO L93 Difference]: Finished difference Result 1666 states and 4696 transitions. [2019-12-07 12:16:05,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:16:05,496 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 12:16:05,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:05,498 INFO L225 Difference]: With dead ends: 1666 [2019-12-07 12:16:05,498 INFO L226 Difference]: Without dead ends: 1666 [2019-12-07 12:16:05,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:05,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1666 states. [2019-12-07 12:16:05,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1666 to 1470. [2019-12-07 12:16:05,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1470 states. [2019-12-07 12:16:05,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1470 states to 1470 states and 4144 transitions. [2019-12-07 12:16:05,514 INFO L78 Accepts]: Start accepts. Automaton has 1470 states and 4144 transitions. Word has length 58 [2019-12-07 12:16:05,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:05,514 INFO L462 AbstractCegarLoop]: Abstraction has 1470 states and 4144 transitions. [2019-12-07 12:16:05,514 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:16:05,514 INFO L276 IsEmpty]: Start isEmpty. Operand 1470 states and 4144 transitions. [2019-12-07 12:16:05,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 12:16:05,516 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:05,516 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:05,516 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:05,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:05,516 INFO L82 PathProgramCache]: Analyzing trace with hash -2087231872, now seen corresponding path program 2 times [2019-12-07 12:16:05,517 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:05,517 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62442839] [2019-12-07 12:16:05,517 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:05,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:05,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:05,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62442839] [2019-12-07 12:16:05,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:05,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:16:05,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605994832] [2019-12-07 12:16:05,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:16:05,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:05,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:16:05,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:16:05,581 INFO L87 Difference]: Start difference. First operand 1470 states and 4144 transitions. Second operand 6 states. [2019-12-07 12:16:05,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:05,770 INFO L93 Difference]: Finished difference Result 1745 states and 4788 transitions. [2019-12-07 12:16:05,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:16:05,770 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 12:16:05,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:05,772 INFO L225 Difference]: With dead ends: 1745 [2019-12-07 12:16:05,772 INFO L226 Difference]: Without dead ends: 1745 [2019-12-07 12:16:05,772 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:05,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1745 states. [2019-12-07 12:16:05,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1745 to 1522. [2019-12-07 12:16:05,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1522 states. [2019-12-07 12:16:05,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1522 states to 1522 states and 4220 transitions. [2019-12-07 12:16:05,787 INFO L78 Accepts]: Start accepts. Automaton has 1522 states and 4220 transitions. Word has length 58 [2019-12-07 12:16:05,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:05,787 INFO L462 AbstractCegarLoop]: Abstraction has 1522 states and 4220 transitions. [2019-12-07 12:16:05,787 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:16:05,787 INFO L276 IsEmpty]: Start isEmpty. Operand 1522 states and 4220 transitions. [2019-12-07 12:16:05,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 12:16:05,789 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:05,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:05,789 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:05,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:05,789 INFO L82 PathProgramCache]: Analyzing trace with hash -893148506, now seen corresponding path program 3 times [2019-12-07 12:16:05,789 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:05,789 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883813667] [2019-12-07 12:16:05,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:05,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:05,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:05,852 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883813667] [2019-12-07 12:16:05,853 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:05,853 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:16:05,853 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219596387] [2019-12-07 12:16:05,853 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:16:05,853 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:05,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:16:05,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:16:05,854 INFO L87 Difference]: Start difference. First operand 1522 states and 4220 transitions. Second operand 6 states. [2019-12-07 12:16:06,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,001 INFO L93 Difference]: Finished difference Result 2004 states and 5532 transitions. [2019-12-07 12:16:06,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 12:16:06,002 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 12:16:06,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,004 INFO L225 Difference]: With dead ends: 2004 [2019-12-07 12:16:06,004 INFO L226 Difference]: Without dead ends: 2004 [2019-12-07 12:16:06,004 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:16:06,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2004 states. [2019-12-07 12:16:06,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2004 to 1550. [2019-12-07 12:16:06,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1550 states. [2019-12-07 12:16:06,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 1550 states and 4300 transitions. [2019-12-07 12:16:06,021 INFO L78 Accepts]: Start accepts. Automaton has 1550 states and 4300 transitions. Word has length 58 [2019-12-07 12:16:06,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,021 INFO L462 AbstractCegarLoop]: Abstraction has 1550 states and 4300 transitions. [2019-12-07 12:16:06,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:16:06,021 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 4300 transitions. [2019-12-07 12:16:06,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 12:16:06,023 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,023 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,023 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,023 INFO L82 PathProgramCache]: Analyzing trace with hash -1236108060, now seen corresponding path program 4 times [2019-12-07 12:16:06,024 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,024 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666111228] [2019-12-07 12:16:06,024 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666111228] [2019-12-07 12:16:06,103 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,103 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 12:16:06,103 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320290860] [2019-12-07 12:16:06,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 12:16:06,104 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:16:06,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:06,104 INFO L87 Difference]: Start difference. First operand 1550 states and 4300 transitions. Second operand 7 states. [2019-12-07 12:16:06,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,346 INFO L93 Difference]: Finished difference Result 2218 states and 6110 transitions. [2019-12-07 12:16:06,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 12:16:06,347 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 58 [2019-12-07 12:16:06,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,350 INFO L225 Difference]: With dead ends: 2218 [2019-12-07 12:16:06,350 INFO L226 Difference]: Without dead ends: 2218 [2019-12-07 12:16:06,350 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 8 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 12:16:06,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2218 states. [2019-12-07 12:16:06,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2218 to 1550. [2019-12-07 12:16:06,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1550 states. [2019-12-07 12:16:06,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 1550 states and 4300 transitions. [2019-12-07 12:16:06,376 INFO L78 Accepts]: Start accepts. Automaton has 1550 states and 4300 transitions. Word has length 58 [2019-12-07 12:16:06,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,377 INFO L462 AbstractCegarLoop]: Abstraction has 1550 states and 4300 transitions. [2019-12-07 12:16:06,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 12:16:06,377 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 4300 transitions. [2019-12-07 12:16:06,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 12:16:06,379 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,380 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,380 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,380 INFO L82 PathProgramCache]: Analyzing trace with hash -465324325, now seen corresponding path program 1 times [2019-12-07 12:16:06,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440309757] [2019-12-07 12:16:06,381 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440309757] [2019-12-07 12:16:06,432 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,432 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:16:06,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120541462] [2019-12-07 12:16:06,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:16:06,432 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:16:06,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:06,433 INFO L87 Difference]: Start difference. First operand 1550 states and 4300 transitions. Second operand 3 states. [2019-12-07 12:16:06,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,464 INFO L93 Difference]: Finished difference Result 1549 states and 4298 transitions. [2019-12-07 12:16:06,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:16:06,465 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 12:16:06,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,467 INFO L225 Difference]: With dead ends: 1549 [2019-12-07 12:16:06,467 INFO L226 Difference]: Without dead ends: 1549 [2019-12-07 12:16:06,467 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:06,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1549 states. [2019-12-07 12:16:06,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1549 to 1220. [2019-12-07 12:16:06,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1220 states. [2019-12-07 12:16:06,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 1220 states and 3384 transitions. [2019-12-07 12:16:06,486 INFO L78 Accepts]: Start accepts. Automaton has 1220 states and 3384 transitions. Word has length 59 [2019-12-07 12:16:06,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,486 INFO L462 AbstractCegarLoop]: Abstraction has 1220 states and 3384 transitions. [2019-12-07 12:16:06,486 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:16:06,486 INFO L276 IsEmpty]: Start isEmpty. Operand 1220 states and 3384 transitions. [2019-12-07 12:16:06,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 12:16:06,488 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,488 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,488 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,488 INFO L82 PathProgramCache]: Analyzing trace with hash -1494660078, now seen corresponding path program 1 times [2019-12-07 12:16:06,488 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446460816] [2019-12-07 12:16:06,489 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,584 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446460816] [2019-12-07 12:16:06,584 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:16:06,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256268575] [2019-12-07 12:16:06,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 12:16:06,585 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:16:06,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:16:06,586 INFO L87 Difference]: Start difference. First operand 1220 states and 3384 transitions. Second operand 7 states. [2019-12-07 12:16:06,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,676 INFO L93 Difference]: Finished difference Result 2350 states and 6053 transitions. [2019-12-07 12:16:06,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 12:16:06,676 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2019-12-07 12:16:06,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,678 INFO L225 Difference]: With dead ends: 2350 [2019-12-07 12:16:06,678 INFO L226 Difference]: Without dead ends: 1584 [2019-12-07 12:16:06,678 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 12:16:06,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1584 states. [2019-12-07 12:16:06,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1584 to 1074. [2019-12-07 12:16:06,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1074 states. [2019-12-07 12:16:06,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1074 states to 1074 states and 2890 transitions. [2019-12-07 12:16:06,691 INFO L78 Accepts]: Start accepts. Automaton has 1074 states and 2890 transitions. Word has length 59 [2019-12-07 12:16:06,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,691 INFO L462 AbstractCegarLoop]: Abstraction has 1074 states and 2890 transitions. [2019-12-07 12:16:06,691 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 12:16:06,691 INFO L276 IsEmpty]: Start isEmpty. Operand 1074 states and 2890 transitions. [2019-12-07 12:16:06,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 12:16:06,692 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,692 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,693 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,693 INFO L82 PathProgramCache]: Analyzing trace with hash 353850156, now seen corresponding path program 2 times [2019-12-07 12:16:06,693 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,693 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246967059] [2019-12-07 12:16:06,693 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,758 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246967059] [2019-12-07 12:16:06,759 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,759 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:16:06,759 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868397412] [2019-12-07 12:16:06,759 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:16:06,759 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:16:06,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:16:06,759 INFO L87 Difference]: Start difference. First operand 1074 states and 2890 transitions. Second operand 6 states. [2019-12-07 12:16:06,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,802 INFO L93 Difference]: Finished difference Result 1615 states and 4063 transitions. [2019-12-07 12:16:06,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:16:06,803 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2019-12-07 12:16:06,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,803 INFO L225 Difference]: With dead ends: 1615 [2019-12-07 12:16:06,803 INFO L226 Difference]: Without dead ends: 598 [2019-12-07 12:16:06,804 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:16:06,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states. [2019-12-07 12:16:06,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 598. [2019-12-07 12:16:06,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 598 states. [2019-12-07 12:16:06,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 598 states and 1296 transitions. [2019-12-07 12:16:06,809 INFO L78 Accepts]: Start accepts. Automaton has 598 states and 1296 transitions. Word has length 59 [2019-12-07 12:16:06,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,809 INFO L462 AbstractCegarLoop]: Abstraction has 598 states and 1296 transitions. [2019-12-07 12:16:06,809 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:16:06,809 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 1296 transitions. [2019-12-07 12:16:06,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 12:16:06,810 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,810 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,810 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,810 INFO L82 PathProgramCache]: Analyzing trace with hash -290303176, now seen corresponding path program 3 times [2019-12-07 12:16:06,810 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,810 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213530336] [2019-12-07 12:16:06,810 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,883 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213530336] [2019-12-07 12:16:06,883 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,883 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:16:06,883 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930638957] [2019-12-07 12:16:06,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:16:06,883 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:16:06,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:16:06,884 INFO L87 Difference]: Start difference. First operand 598 states and 1296 transitions. Second operand 6 states. [2019-12-07 12:16:06,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,925 INFO L93 Difference]: Finished difference Result 873 states and 1833 transitions. [2019-12-07 12:16:06,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:16:06,925 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2019-12-07 12:16:06,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,926 INFO L225 Difference]: With dead ends: 873 [2019-12-07 12:16:06,926 INFO L226 Difference]: Without dead ends: 266 [2019-12-07 12:16:06,926 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 12:16:06,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2019-12-07 12:16:06,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 234. [2019-12-07 12:16:06,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2019-12-07 12:16:06,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 404 transitions. [2019-12-07 12:16:06,928 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 404 transitions. Word has length 59 [2019-12-07 12:16:06,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,928 INFO L462 AbstractCegarLoop]: Abstraction has 234 states and 404 transitions. [2019-12-07 12:16:06,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:16:06,928 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 404 transitions. [2019-12-07 12:16:06,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 12:16:06,929 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,929 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,929 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,929 INFO L82 PathProgramCache]: Analyzing trace with hash 1190950608, now seen corresponding path program 4 times [2019-12-07 12:16:06,929 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,929 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116634847] [2019-12-07 12:16:06,929 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:06,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:06,960 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116634847] [2019-12-07 12:16:06,960 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:06,960 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:16:06,960 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142791733] [2019-12-07 12:16:06,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:16:06,960 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:06,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:16:06,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:06,961 INFO L87 Difference]: Start difference. First operand 234 states and 404 transitions. Second operand 3 states. [2019-12-07 12:16:06,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:06,968 INFO L93 Difference]: Finished difference Result 215 states and 364 transitions. [2019-12-07 12:16:06,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:16:06,968 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 12:16:06,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:06,969 INFO L225 Difference]: With dead ends: 215 [2019-12-07 12:16:06,969 INFO L226 Difference]: Without dead ends: 215 [2019-12-07 12:16:06,969 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:16:06,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2019-12-07 12:16:06,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 215. [2019-12-07 12:16:06,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2019-12-07 12:16:06,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 364 transitions. [2019-12-07 12:16:06,971 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 364 transitions. Word has length 59 [2019-12-07 12:16:06,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:06,971 INFO L462 AbstractCegarLoop]: Abstraction has 215 states and 364 transitions. [2019-12-07 12:16:06,971 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:16:06,971 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 364 transitions. [2019-12-07 12:16:06,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 12:16:06,971 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:06,971 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:06,972 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:06,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:06,972 INFO L82 PathProgramCache]: Analyzing trace with hash 424334393, now seen corresponding path program 1 times [2019-12-07 12:16:06,972 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:06,972 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585579318] [2019-12-07 12:16:06,972 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:06,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:07,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:07,160 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585579318] [2019-12-07 12:16:07,160 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:07,160 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 12:16:07,160 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814718807] [2019-12-07 12:16:07,160 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 12:16:07,160 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:07,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 12:16:07,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-12-07 12:16:07,161 INFO L87 Difference]: Start difference. First operand 215 states and 364 transitions. Second operand 14 states. [2019-12-07 12:16:07,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:07,495 INFO L93 Difference]: Finished difference Result 390 states and 652 transitions. [2019-12-07 12:16:07,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 12:16:07,495 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2019-12-07 12:16:07,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:07,496 INFO L225 Difference]: With dead ends: 390 [2019-12-07 12:16:07,496 INFO L226 Difference]: Without dead ends: 357 [2019-12-07 12:16:07,496 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=106, Invalid=494, Unknown=0, NotChecked=0, Total=600 [2019-12-07 12:16:07,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2019-12-07 12:16:07,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 315. [2019-12-07 12:16:07,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-12-07 12:16:07,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 535 transitions. [2019-12-07 12:16:07,499 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 535 transitions. Word has length 60 [2019-12-07 12:16:07,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:07,499 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 535 transitions. [2019-12-07 12:16:07,499 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 12:16:07,499 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 535 transitions. [2019-12-07 12:16:07,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 12:16:07,500 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:07,500 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:07,500 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:07,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:07,500 INFO L82 PathProgramCache]: Analyzing trace with hash -1214438793, now seen corresponding path program 2 times [2019-12-07 12:16:07,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:07,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701055259] [2019-12-07 12:16:07,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:07,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:16:07,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:16:07,685 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701055259] [2019-12-07 12:16:07,685 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:16:07,686 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 12:16:07,686 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837653396] [2019-12-07 12:16:07,686 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 12:16:07,686 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 12:16:07,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 12:16:07,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 12:16:07,686 INFO L87 Difference]: Start difference. First operand 315 states and 535 transitions. Second operand 13 states. [2019-12-07 12:16:07,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:16:07,985 INFO L93 Difference]: Finished difference Result 418 states and 688 transitions. [2019-12-07 12:16:07,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 12:16:07,985 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 60 [2019-12-07 12:16:07,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:16:07,985 INFO L225 Difference]: With dead ends: 418 [2019-12-07 12:16:07,985 INFO L226 Difference]: Without dead ends: 385 [2019-12-07 12:16:07,986 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=106, Invalid=446, Unknown=0, NotChecked=0, Total=552 [2019-12-07 12:16:07,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states. [2019-12-07 12:16:07,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 323. [2019-12-07 12:16:07,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 323 states. [2019-12-07 12:16:07,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 549 transitions. [2019-12-07 12:16:07,988 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 549 transitions. Word has length 60 [2019-12-07 12:16:07,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:16:07,988 INFO L462 AbstractCegarLoop]: Abstraction has 323 states and 549 transitions. [2019-12-07 12:16:07,988 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 12:16:07,989 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 549 transitions. [2019-12-07 12:16:07,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 12:16:07,989 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:16:07,989 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:16:07,989 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:16:07,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:16:07,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1750352957, now seen corresponding path program 3 times [2019-12-07 12:16:07,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 12:16:07,990 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483388021] [2019-12-07 12:16:07,990 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:16:08,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:16:08,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:16:08,056 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 12:16:08,056 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 12:16:08,058 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= v_~z$w_buff0~0_106 0) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1485~0.base_22| 1)) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= v_~z$read_delayed_var~0.offset_7 0) (= v_~z$r_buff1_thd0~0_244 0) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1485~0.base_22|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1485~0.base_22|)) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1485~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1485~0.base_22|) |v_ULTIMATE.start_main_~#t1485~0.offset_17| 0)) |v_#memory_int_27|) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= 0 |v_ULTIMATE.start_main_~#t1485~0.offset_17|) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= v_~y~0_41 0) (= v_~x~0_54 0) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t1485~0.base_22| 4)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ULTIMATE.start_main_~#t1485~0.base=|v_ULTIMATE.start_main_~#t1485~0.base_22|, ULTIMATE.start_main_~#t1488~0.base=|v_ULTIMATE.start_main_~#t1488~0.base_20|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ULTIMATE.start_main_~#t1486~0.offset=|v_ULTIMATE.start_main_~#t1486~0.offset_18|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_~#t1485~0.offset=|v_ULTIMATE.start_main_~#t1485~0.offset_17|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ULTIMATE.start_main_~#t1487~0.offset=|v_ULTIMATE.start_main_~#t1487~0.offset_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ULTIMATE.start_main_~#t1487~0.base=|v_ULTIMATE.start_main_~#t1487~0.base_20|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ULTIMATE.start_main_~#t1486~0.base=|v_ULTIMATE.start_main_~#t1486~0.base_23|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1488~0.offset=|v_ULTIMATE.start_main_~#t1488~0.offset_16|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ULTIMATE.start_main_~#t1485~0.base, ULTIMATE.start_main_~#t1488~0.base, ~__unbuffered_p1_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t1486~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_~#t1485~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ULTIMATE.start_main_~#t1487~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t1487~0.base, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1486~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1488~0.offset, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 12:16:08,059 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1486~0.base_13| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1486~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1486~0.base_13|)) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1486~0.base_13| 1)) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1486~0.base_13|)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1486~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1486~0.base_13|) |v_ULTIMATE.start_main_~#t1486~0.offset_11| 1)) |v_#memory_int_19|) (= 0 |v_ULTIMATE.start_main_~#t1486~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t1486~0.base=|v_ULTIMATE.start_main_~#t1486~0.base_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1486~0.offset=|v_ULTIMATE.start_main_~#t1486~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1486~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1486~0.offset] because there is no mapped edge [2019-12-07 12:16:08,059 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1487~0.base_10|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1487~0.base_10|) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1487~0.base_10| 4)) (= (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1487~0.base_10| 1) |v_#valid_40|) (not (= |v_ULTIMATE.start_main_~#t1487~0.base_10| 0)) (= 0 |v_ULTIMATE.start_main_~#t1487~0.offset_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1487~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1487~0.base_10|) |v_ULTIMATE.start_main_~#t1487~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1487~0.offset=|v_ULTIMATE.start_main_~#t1487~0.offset_10|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1487~0.base=|v_ULTIMATE.start_main_~#t1487~0.base_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1487~0.offset, #length, ULTIMATE.start_main_~#t1487~0.base] because there is no mapped edge [2019-12-07 12:16:08,060 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1488~0.base_11|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1488~0.base_11| 4)) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1488~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1488~0.base_11| 0)) (= 0 |v_ULTIMATE.start_main_~#t1488~0.offset_10|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1488~0.base_11|) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1488~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1488~0.base_11|) |v_ULTIMATE.start_main_~#t1488~0.offset_10| 3)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1488~0.base=|v_ULTIMATE.start_main_~#t1488~0.base_11|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1488~0.offset=|v_ULTIMATE.start_main_~#t1488~0.offset_10|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1488~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1488~0.offset, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 12:16:08,060 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= 1 ~z$r_buff0_thd4~0_Out875920522) (= ~z$r_buff0_thd1~0_In875920522 ~z$r_buff1_thd1~0_Out875920522) (= ~z$r_buff1_thd4~0_Out875920522 ~z$r_buff0_thd4~0_In875920522) (= ~z$r_buff1_thd0~0_Out875920522 ~z$r_buff0_thd0~0_In875920522) (= ~a~0_In875920522 ~__unbuffered_p3_EAX~0_Out875920522) (= ~z$r_buff0_thd2~0_In875920522 ~z$r_buff1_thd2~0_Out875920522) (= ~z$r_buff0_thd3~0_In875920522 ~z$r_buff1_thd3~0_Out875920522) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522))) InVars {~a~0=~a~0_In875920522, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In875920522, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out875920522, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out875920522, ~a~0=~a~0_In875920522, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In875920522, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out875920522, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out875920522, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out875920522, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 12:16:08,061 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 12:16:08,061 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 12:16:08,061 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-1189064342 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite11_Out-1189064342| ~z$w_buff0_used~0_In-1189064342) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork3_#t~ite11_Out-1189064342| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1189064342, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out-1189064342|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 12:16:08,062 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1412388756 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-1412388756 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1412388756 |P2Thread1of1ForFork2_#t~ite3_Out-1412388756|)) (and (not .cse0) (= ~z$w_buff1~0_In-1412388756 |P2Thread1of1ForFork2_#t~ite3_Out-1412388756|) (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1412388756, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1412388756, ~z$w_buff1~0=~z$w_buff1~0_In-1412388756, ~z~0=~z~0_In-1412388756} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-1412388756|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1412388756, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1412388756, ~z$w_buff1~0=~z$w_buff1~0_In-1412388756, ~z~0=~z~0_In-1412388756} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 12:16:08,062 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 12:16:08,062 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd4~0_In2048722628 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In2048722628 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd4~0_In2048722628 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In2048722628 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite12_Out2048722628| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In2048722628 |P3Thread1of1ForFork3_#t~ite12_Out2048722628|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2048722628, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2048722628, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2048722628, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2048722628} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2048722628, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2048722628, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2048722628, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2048722628, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out2048722628|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 12:16:08,062 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse0 (= ~z$r_buff0_thd4~0_Out-989057550 ~z$r_buff0_thd4~0_In-989057550)) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-989057550 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-989057550 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= ~z$r_buff0_thd4~0_Out-989057550 0) (not .cse1) (not .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-989057550, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-989057550} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-989057550, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-989057550, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out-989057550|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 12:16:08,062 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd4~0_In-2039380594 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-2039380594 256))) (.cse3 (= (mod ~z$r_buff0_thd4~0_In-2039380594 256) 0))) (or (and (= |P3Thread1of1ForFork3_#t~ite14_Out-2039380594| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~z$r_buff1_thd4~0_In-2039380594 |P3Thread1of1ForFork3_#t~ite14_Out-2039380594|)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-2039380594, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2039380594, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-2039380594, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2039380594, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-2039380594|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 12:16:08,063 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 12:16:08,063 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-80802922 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-80802922 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite5_Out-80802922| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite5_Out-80802922| ~z$w_buff0_used~0_In-80802922)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-80802922, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-80802922} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out-80802922|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-80802922, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-80802922} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 12:16:08,063 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In1794859058 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In1794859058 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1794859058 256))) (.cse3 (= (mod ~z$r_buff0_thd3~0_In1794859058 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite6_Out1794859058| 0)) (and (= |P2Thread1of1ForFork2_#t~ite6_Out1794859058| ~z$w_buff1_used~0_In1794859058) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1794859058, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1794859058, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1794859058, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1794859058} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out1794859058|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1794859058, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1794859058, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1794859058, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1794859058} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 12:16:08,063 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In1228209859 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1228209859 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite7_Out1228209859| ~z$r_buff0_thd3~0_In1228209859) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite7_Out1228209859| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1228209859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1228209859} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1228209859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1228209859, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out1228209859|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In1680523031 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In1680523031 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1680523031 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In1680523031 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd3~0_In1680523031 |P2Thread1of1ForFork2_#t~ite8_Out1680523031|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite8_Out1680523031|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1680523031, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1680523031, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1680523031, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1680523031} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1680523031, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1680523031, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1680523031, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1680523031, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out1680523031|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In898880708 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In898880708 256) 0))) (or (and (or .cse0 .cse1) (= ~z~0_In898880708 |ULTIMATE.start_main_#t~ite19_Out898880708|)) (and (= ~z$w_buff1~0_In898880708 |ULTIMATE.start_main_#t~ite19_Out898880708|) (not .cse0) (not .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In898880708, ~z$w_buff1_used~0=~z$w_buff1_used~0_In898880708, ~z$w_buff1~0=~z$w_buff1~0_In898880708, ~z~0=~z~0_In898880708} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out898880708|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In898880708, ~z$w_buff1_used~0=~z$w_buff1_used~0_In898880708, ~z$w_buff1~0=~z$w_buff1~0_In898880708, ~z~0=~z~0_In898880708} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 12:16:08,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1500518232 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-1500518232| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1500518232| ~z$w_buff0_used~0_In-1500518232)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1500518232, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1500518232, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1500518232|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 12:16:08,065 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1299200421 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1299200421 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1299200421 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1299200421 256)))) (or (and (= ~z$w_buff1_used~0_In-1299200421 |ULTIMATE.start_main_#t~ite22_Out-1299200421|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite22_Out-1299200421| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1299200421, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1299200421, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1299200421, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1299200421} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1299200421, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1299200421, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1299200421, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1299200421, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1299200421|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 12:16:08,065 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1242086709 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1242086709 |ULTIMATE.start_main_#t~ite23_Out-1242086709|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out-1242086709|) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1242086709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1242086709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1242086709|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 12:16:08,065 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1778705683 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1778705683 256))) (.cse2 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1778705683, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1778705683, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1778705683, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1778705683, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 12:16:08,067 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-612522564 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite34_Out-612522564| ~z$w_buff1~0_In-612522564) (not .cse0) (= |ULTIMATE.start_main_#t~ite33_In-612522564| |ULTIMATE.start_main_#t~ite33_Out-612522564|)) (and (= ~z$w_buff1~0_In-612522564 |ULTIMATE.start_main_#t~ite33_Out-612522564|) (= |ULTIMATE.start_main_#t~ite34_Out-612522564| |ULTIMATE.start_main_#t~ite33_Out-612522564|) .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-612522564 256)))) (or (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In-612522564 256))) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-612522564 256) 0)) (= (mod ~z$w_buff0_used~0_In-612522564 256) 0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-612522564, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$w_buff1~0=~z$w_buff1~0_In-612522564, ~weak$$choice2~0=~weak$$choice2~0_In-612522564, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In-612522564|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-612522564, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$w_buff1~0=~z$w_buff1~0_In-612522564, ~weak$$choice2~0=~weak$$choice2~0_In-612522564, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-612522564|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out-612522564|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 12:16:08,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-928969378 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite40_Out-928969378| ~z$w_buff1_used~0_In-928969378) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_In-928969378| |ULTIMATE.start_main_#t~ite39_Out-928969378|)) (and .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-928969378 256)))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-928969378 256)) .cse1) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-928969378 256) 0)) (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (= |ULTIMATE.start_main_#t~ite39_Out-928969378| ~z$w_buff1_used~0_In-928969378) (= |ULTIMATE.start_main_#t~ite40_Out-928969378| |ULTIMATE.start_main_#t~ite39_Out-928969378|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-928969378, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-928969378|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~weak$$choice2~0=~weak$$choice2~0_In-928969378} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-928969378, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-928969378|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~weak$$choice2~0=~weak$$choice2~0_In-928969378} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 12:16:08,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 12:16:08,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1921554792 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In-1921554792 |ULTIMATE.start_main_#t~ite45_Out-1921554792|) .cse0 (= |ULTIMATE.start_main_#t~ite46_Out-1921554792| |ULTIMATE.start_main_#t~ite45_Out-1921554792|) (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In-1921554792 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256)) .cse1) (and (= 0 (mod ~z$r_buff1_thd0~0_In-1921554792 256)) .cse1) (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))))) (and (= ~z$r_buff1_thd0~0_In-1921554792 |ULTIMATE.start_main_#t~ite46_Out-1921554792|) (not .cse0) (= |ULTIMATE.start_main_#t~ite45_In-1921554792| |ULTIMATE.start_main_#t~ite45_Out-1921554792|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1921554792, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~weak$$choice2~0=~weak$$choice2~0_In-1921554792, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1921554792|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1921554792, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1921554792|, ~weak$$choice2~0=~weak$$choice2~0_In-1921554792, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1921554792|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 12:16:08,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 12:16:08,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 12:16:08,119 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 12:16:08 BasicIcfg [2019-12-07 12:16:08,119 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 12:16:08,120 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:16:08,120 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:16:08,120 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:16:08,120 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:15:50" (3/4) ... [2019-12-07 12:16:08,122 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 12:16:08,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_72| 0 0))) (and (= v_~z$w_buff0~0_106 0) (= v_~z$r_buff0_thd2~0_89 0) (= v_~main$tmp_guard0~0_30 0) (= |v_#NULL.offset_6| 0) (= 0 v_~z$r_buff1_thd1~0_90) (< 0 |v_#StackHeapBarrier_21|) (= v_~a~0_108 0) (= v_~z$w_buff0_used~0_517 0) (= |v_#valid_70| (store .cse0 |v_ULTIMATE.start_main_~#t1485~0.base_22| 1)) (= v_~z$r_buff0_thd0~0_321 0) (= 0 v_~__unbuffered_p1_EAX~0_34) (= v_~z$read_delayed_var~0.offset_7 0) (= v_~z$r_buff1_thd0~0_244 0) (= 0 v_~z$w_buff1~0_99) (= 0 |v_#NULL.base_6|) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1485~0.base_22|) (= 0 v_~z$r_buff1_thd2~0_90) (= v_~z$read_delayed_var~0.base_7 0) (= 0 v_~z$flush_delayed~0_47) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_147) (= 0 v_~z$r_buff1_thd4~0_142) (= 0 v_~z$r_buff1_thd3~0_154) (= 0 v_~weak$$choice0~0_24) (= v_~__unbuffered_cnt~0_141 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1485~0.base_22|)) (= v_~z$w_buff1_used~0_308 0) (= 0 v_~__unbuffered_p3_EAX~0_99) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1485~0.base_22| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1485~0.base_22|) |v_ULTIMATE.start_main_~#t1485~0.offset_17| 0)) |v_#memory_int_27|) (= v_~weak$$choice2~0_108 0) (= v_~z$r_buff0_thd1~0_89 0) (= 0 v_~z$r_buff0_thd4~0_241) (= 0 |v_ULTIMATE.start_main_~#t1485~0.offset_17|) (= v_~z~0_160 0) (= v_~z$mem_tmp~0_28 0) (= v_~y~0_41 0) (= v_~x~0_54 0) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t1485~0.base_22| 4)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_72|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_90, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_55|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_30|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_19|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_42|, ~a~0=v_~a~0_108, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_321, ULTIMATE.start_main_~#t1485~0.base=|v_ULTIMATE.start_main_~#t1485~0.base_22|, ULTIMATE.start_main_~#t1488~0.base=|v_ULTIMATE.start_main_~#t1488~0.base_20|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_34, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_241, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_99, #length=|v_#length_31|, ULTIMATE.start_main_~#t1486~0.offset=|v_ULTIMATE.start_main_~#t1486~0.offset_18|, ~z$mem_tmp~0=v_~z$mem_tmp~0_28, ULTIMATE.start_main_~#t1485~0.offset=|v_ULTIMATE.start_main_~#t1485~0.offset_17|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_96|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_33|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_308, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_30|, ~z$flush_delayed~0=v_~z$flush_delayed~0_47, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_33|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_32|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_141|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_90, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_147, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_54, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_142, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ~z$w_buff1~0=v_~z$w_buff1~0_99, ULTIMATE.start_main_~#t1487~0.offset=|v_ULTIMATE.start_main_~#t1487~0.offset_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_29|, ULTIMATE.start_main_~#t1487~0.base=|v_ULTIMATE.start_main_~#t1487~0.base_20|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_105|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_35|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_244, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_41|, ~y~0=v_~y~0_41, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_89, ULTIMATE.start_main_~#t1486~0.base=|v_ULTIMATE.start_main_~#t1486~0.base_23|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_517, ~z$w_buff0~0=v_~z$w_buff0~0_106, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_41|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_154, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_31|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_91|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_30|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_34|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_27|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_70|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1488~0.offset=|v_ULTIMATE.start_main_~#t1488~0.offset_16|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_89} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ULTIMATE.start_main_~#t1485~0.base, ULTIMATE.start_main_~#t1488~0.base, ~__unbuffered_p1_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t1486~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_~#t1485~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ULTIMATE.start_main_~#t1487~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t1487~0.base, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1486~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1488~0.offset, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 12:16:08,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L823-1-->L825: Formula: (and (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1486~0.base_13| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1486~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1486~0.base_13|)) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1486~0.base_13| 1)) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1486~0.base_13|)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1486~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1486~0.base_13|) |v_ULTIMATE.start_main_~#t1486~0.offset_11| 1)) |v_#memory_int_19|) (= 0 |v_ULTIMATE.start_main_~#t1486~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t1486~0.base=|v_ULTIMATE.start_main_~#t1486~0.base_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1486~0.offset=|v_ULTIMATE.start_main_~#t1486~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1486~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1486~0.offset] because there is no mapped edge [2019-12-07 12:16:08,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] L825-1-->L827: Formula: (and (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1487~0.base_10|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1487~0.base_10|) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1487~0.base_10| 4)) (= (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1487~0.base_10| 1) |v_#valid_40|) (not (= |v_ULTIMATE.start_main_~#t1487~0.base_10| 0)) (= 0 |v_ULTIMATE.start_main_~#t1487~0.offset_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1487~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1487~0.base_10|) |v_ULTIMATE.start_main_~#t1487~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1487~0.offset=|v_ULTIMATE.start_main_~#t1487~0.offset_10|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1487~0.base=|v_ULTIMATE.start_main_~#t1487~0.base_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1487~0.offset, #length, ULTIMATE.start_main_~#t1487~0.base] because there is no mapped edge [2019-12-07 12:16:08,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L827-1-->L829: Formula: (and (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1488~0.base_11|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1488~0.base_11| 4)) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1488~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1488~0.base_11| 0)) (= 0 |v_ULTIMATE.start_main_~#t1488~0.offset_10|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1488~0.base_11|) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1488~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1488~0.base_11|) |v_ULTIMATE.start_main_~#t1488~0.offset_10| 3)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1488~0.base=|v_ULTIMATE.start_main_~#t1488~0.base_11|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1488~0.offset=|v_ULTIMATE.start_main_~#t1488~0.offset_10|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1488~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1488~0.offset, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 12:16:08,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L4-->L800: Formula: (and (= 1 ~z$r_buff0_thd4~0_Out875920522) (= ~z$r_buff0_thd1~0_In875920522 ~z$r_buff1_thd1~0_Out875920522) (= ~z$r_buff1_thd4~0_Out875920522 ~z$r_buff0_thd4~0_In875920522) (= ~z$r_buff1_thd0~0_Out875920522 ~z$r_buff0_thd0~0_In875920522) (= ~a~0_In875920522 ~__unbuffered_p3_EAX~0_Out875920522) (= ~z$r_buff0_thd2~0_In875920522 ~z$r_buff1_thd2~0_Out875920522) (= ~z$r_buff0_thd3~0_In875920522 ~z$r_buff1_thd3~0_Out875920522) (not (= 0 P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522))) InVars {~a~0=~a~0_In875920522, P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In875920522, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=P3Thread1of1ForFork3___VERIFIER_assert_~expression_In875920522, ~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_Out875920522, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_Out875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_Out875920522, ~a~0=~a~0_In875920522, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In875920522, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_Out875920522, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_Out875920522, ~__unbuffered_p3_EAX~0=~__unbuffered_p3_EAX~0_Out875920522, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 12:16:08,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_7|) (= v_P0Thread1of1ForFork0_~arg.base_17 |v_P0Thread1of1ForFork0_#in~arg.base_19|) (= |v_P0Thread1of1ForFork0_#res.offset_7| 0) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_P0Thread1of1ForFork0_~arg.offset_17 |v_P0Thread1of1ForFork0_#in~arg.offset_19|) (= v_~x~0_32 1) (= v_~a~0_41 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81} OutVars{~a~0=v_~a~0_41, P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_19|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_7|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_19|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_17, ~x~0=v_~x~0_32, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_17} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 12:16:08,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [748] [748] P1ENTRY-->P1EXIT: Formula: (and (= v_~y~0_32 v_~__unbuffered_p1_EAX~0_23) (= |v_P1Thread1of1ForFork1_#in~arg.offset_19| v_P1Thread1of1ForFork1_~arg.offset_17) (= v_P1Thread1of1ForFork1_~arg.base_17 |v_P1Thread1of1ForFork1_#in~arg.base_19|) (= 0 |v_P1Thread1of1ForFork1_#res.base_9|) (= v_~x~0_41 2) (= v_~__unbuffered_cnt~0_115 (+ v_~__unbuffered_cnt~0_116 1)) (= |v_P1Thread1of1ForFork1_#res.offset_9| 0)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_116, ~y~0=v_~y~0_32} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_17, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_9|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_23, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_17, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_19|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_115, ~y~0=v_~y~0_32, ~x~0=v_~x~0_41, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_p1_EAX~0, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 12:16:08,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L801-->L801-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-1189064342 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite11_Out-1189064342| ~z$w_buff0_used~0_In-1189064342) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork3_#t~ite11_Out-1189064342| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1189064342, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out-1189064342|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 12:16:08,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L770-2-->L770-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1412388756 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-1412388756 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1412388756 |P2Thread1of1ForFork2_#t~ite3_Out-1412388756|)) (and (not .cse0) (= ~z$w_buff1~0_In-1412388756 |P2Thread1of1ForFork2_#t~ite3_Out-1412388756|) (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1412388756, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1412388756, ~z$w_buff1~0=~z$w_buff1~0_In-1412388756, ~z~0=~z~0_In-1412388756} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-1412388756|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1412388756, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1412388756, ~z$w_buff1~0=~z$w_buff1~0_In-1412388756, ~z~0=~z~0_In-1412388756} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 12:16:08,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L770-4-->L771: Formula: (= |v_P2Thread1of1ForFork2_#t~ite3_12| v_~z~0_35) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_12|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_11|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_11|, ~z~0=v_~z~0_35} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 12:16:08,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L802-->L802-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd4~0_In2048722628 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In2048722628 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd4~0_In2048722628 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In2048722628 256)))) (or (and (= |P3Thread1of1ForFork3_#t~ite12_Out2048722628| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In2048722628 |P3Thread1of1ForFork3_#t~ite12_Out2048722628|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2048722628, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2048722628, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2048722628, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2048722628} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2048722628, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2048722628, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2048722628, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2048722628, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out2048722628|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 12:16:08,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L803-->L804: Formula: (let ((.cse0 (= ~z$r_buff0_thd4~0_Out-989057550 ~z$r_buff0_thd4~0_In-989057550)) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-989057550 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-989057550 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= ~z$r_buff0_thd4~0_Out-989057550 0) (not .cse1) (not .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-989057550, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-989057550} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-989057550, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-989057550, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out-989057550|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 12:16:08,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L804-->L804-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd4~0_In-2039380594 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-2039380594 256))) (.cse3 (= (mod ~z$r_buff0_thd4~0_In-2039380594 256) 0))) (or (and (= |P3Thread1of1ForFork3_#t~ite14_Out-2039380594| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~z$r_buff1_thd4~0_In-2039380594 |P3Thread1of1ForFork3_#t~ite14_Out-2039380594|)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-2039380594, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2039380594, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-2039380594, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2039380594, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out-2039380594|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 12:16:08,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [747] [747] L804-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_109 (+ v_~__unbuffered_cnt~0_110 1)) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_84) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_110} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_84, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 12:16:08,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L771-->L771-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-80802922 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-80802922 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite5_Out-80802922| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite5_Out-80802922| ~z$w_buff0_used~0_In-80802922)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-80802922, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-80802922} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out-80802922|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-80802922, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-80802922} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 12:16:08,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L772-->L772-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In1794859058 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In1794859058 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1794859058 256))) (.cse3 (= (mod ~z$r_buff0_thd3~0_In1794859058 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite6_Out1794859058| 0)) (and (= |P2Thread1of1ForFork2_#t~ite6_Out1794859058| ~z$w_buff1_used~0_In1794859058) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1794859058, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1794859058, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1794859058, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1794859058} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out1794859058|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1794859058, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1794859058, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1794859058, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1794859058} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 12:16:08,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L773-->L773-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In1228209859 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1228209859 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite7_Out1228209859| ~z$r_buff0_thd3~0_In1228209859) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite7_Out1228209859| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1228209859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1228209859} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1228209859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1228209859, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out1228209859|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L774-->L774-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In1680523031 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In1680523031 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1680523031 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In1680523031 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd3~0_In1680523031 |P2Thread1of1ForFork2_#t~ite8_Out1680523031|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite8_Out1680523031|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1680523031, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1680523031, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1680523031, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1680523031} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1680523031, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1680523031, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1680523031, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1680523031, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out1680523031|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L774-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite8_42| v_~z$r_buff1_thd3~0_126) (= v_~__unbuffered_cnt~0_125 (+ v_~__unbuffered_cnt~0_126 1)) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_42|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_126, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_125, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_41|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L833-->L835-2: Formula: (and (or (= 0 (mod v_~z$w_buff0_used~0_104 256)) (= (mod v_~z$r_buff0_thd0~0_62 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_62, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In898880708 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In898880708 256) 0))) (or (and (or .cse0 .cse1) (= ~z~0_In898880708 |ULTIMATE.start_main_#t~ite19_Out898880708|)) (and (= ~z$w_buff1~0_In898880708 |ULTIMATE.start_main_#t~ite19_Out898880708|) (not .cse0) (not .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In898880708, ~z$w_buff1_used~0=~z$w_buff1_used~0_In898880708, ~z$w_buff1~0=~z$w_buff1~0_In898880708, ~z~0=~z~0_In898880708} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out898880708|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In898880708, ~z$w_buff1_used~0=~z$w_buff1_used~0_In898880708, ~z$w_buff1~0=~z$w_buff1~0_In898880708, ~z~0=~z~0_In898880708} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L835-4-->L836: Formula: (= v_~z~0_32 |v_ULTIMATE.start_main_#t~ite19_7|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_6|, ~z~0=v_~z~0_32, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 12:16:08,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L836-->L836-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1500518232 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-1500518232| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-1500518232| ~z$w_buff0_used~0_In-1500518232)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1500518232, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1500518232, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1500518232|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 12:16:08,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1299200421 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1299200421 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1299200421 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1299200421 256)))) (or (and (= ~z$w_buff1_used~0_In-1299200421 |ULTIMATE.start_main_#t~ite22_Out-1299200421|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite22_Out-1299200421| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1299200421, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1299200421, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1299200421, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1299200421} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1299200421, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1299200421, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1299200421, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1299200421, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1299200421|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 12:16:08,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L838-->L838-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1242086709 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1242086709 |ULTIMATE.start_main_#t~ite23_Out-1242086709|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out-1242086709|) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1242086709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1242086709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1242086709|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 12:16:08,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L839-->L839-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1778705683 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1778705683 256))) (.cse2 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1778705683, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1778705683, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1778705683, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1778705683, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 12:16:08,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L848-->L848-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-612522564 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite34_Out-612522564| ~z$w_buff1~0_In-612522564) (not .cse0) (= |ULTIMATE.start_main_#t~ite33_In-612522564| |ULTIMATE.start_main_#t~ite33_Out-612522564|)) (and (= ~z$w_buff1~0_In-612522564 |ULTIMATE.start_main_#t~ite33_Out-612522564|) (= |ULTIMATE.start_main_#t~ite34_Out-612522564| |ULTIMATE.start_main_#t~ite33_Out-612522564|) .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-612522564 256)))) (or (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In-612522564 256))) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-612522564 256) 0)) (= (mod ~z$w_buff0_used~0_In-612522564 256) 0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-612522564, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$w_buff1~0=~z$w_buff1~0_In-612522564, ~weak$$choice2~0=~weak$$choice2~0_In-612522564, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In-612522564|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-612522564, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$w_buff1~0=~z$w_buff1~0_In-612522564, ~weak$$choice2~0=~weak$$choice2~0_In-612522564, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-612522564|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out-612522564|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 12:16:08,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-->L850-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-928969378 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite40_Out-928969378| ~z$w_buff1_used~0_In-928969378) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_In-928969378| |ULTIMATE.start_main_#t~ite39_Out-928969378|)) (and .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-928969378 256)))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-928969378 256)) .cse1) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-928969378 256) 0)) (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (= |ULTIMATE.start_main_#t~ite39_Out-928969378| ~z$w_buff1_used~0_In-928969378) (= |ULTIMATE.start_main_#t~ite40_Out-928969378| |ULTIMATE.start_main_#t~ite39_Out-928969378|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-928969378, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-928969378|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~weak$$choice2~0=~weak$$choice2~0_In-928969378} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-928969378, ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-928969378|, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~weak$$choice2~0=~weak$$choice2~0_In-928969378} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 12:16:08,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L851-->L852: Formula: (and (= v_~z$r_buff0_thd0~0_135 v_~z$r_buff0_thd0~0_134) (not (= (mod v_~weak$$choice2~0_41 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_135, ~weak$$choice2~0=v_~weak$$choice2~0_41} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_14|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_134, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_41, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 12:16:08,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L852-->L852-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1921554792 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In-1921554792 |ULTIMATE.start_main_#t~ite45_Out-1921554792|) .cse0 (= |ULTIMATE.start_main_#t~ite46_Out-1921554792| |ULTIMATE.start_main_#t~ite45_Out-1921554792|) (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In-1921554792 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256)) .cse1) (and (= 0 (mod ~z$r_buff1_thd0~0_In-1921554792 256)) .cse1) (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))))) (and (= ~z$r_buff1_thd0~0_In-1921554792 |ULTIMATE.start_main_#t~ite46_Out-1921554792|) (not .cse0) (= |ULTIMATE.start_main_#t~ite45_In-1921554792| |ULTIMATE.start_main_#t~ite45_Out-1921554792|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1921554792, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~weak$$choice2~0=~weak$$choice2~0_In-1921554792, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1921554792|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1921554792, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1921554792|, ~weak$$choice2~0=~weak$$choice2~0_In-1921554792, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1921554792|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 12:16:08,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L854-->L4: Formula: (and (= 0 v_~z$flush_delayed~0_38) (not (= (mod v_~z$flush_delayed~0_39 256) 0)) (= v_~z$mem_tmp~0_25 v_~z~0_127) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_12 256))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_39} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_25, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~z$flush_delayed~0=v_~z$flush_delayed~0_38, ~z~0=v_~z~0_127, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 12:16:08,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 12:16:08,182 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_36e14702-c71a-465b-a4eb-805abaad658f/bin/utaipan/witness.graphml [2019-12-07 12:16:08,183 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:16:08,184 INFO L168 Benchmark]: Toolchain (without parser) took 18899.44 ms. Allocated memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: 1.7 GB). Free memory was 930.8 MB in the beginning and 409.1 MB in the end (delta: 521.7 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,184 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 952.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:16:08,184 INFO L168 Benchmark]: CACSL2BoogieTranslator took 391.01 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.4 MB). Free memory was 930.8 MB in the beginning and 1.1 GB in the end (delta: -132.8 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,185 INFO L168 Benchmark]: Boogie Procedure Inliner took 47.24 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,185 INFO L168 Benchmark]: Boogie Preprocessor took 33.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:16:08,185 INFO L168 Benchmark]: RCFGBuilder took 415.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.1 MB). Peak memory consumption was 54.1 MB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,185 INFO L168 Benchmark]: TraceAbstraction took 17945.76 ms. Allocated memory was 1.1 GB in the beginning and 2.8 GB in the end (delta: 1.6 GB). Free memory was 1.0 GB in the beginning and 450.2 MB in the end (delta: 553.8 MB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,185 INFO L168 Benchmark]: Witness Printer took 63.01 ms. Allocated memory is still 2.8 GB. Free memory was 450.2 MB in the beginning and 409.1 MB in the end (delta: 41.1 MB). Peak memory consumption was 41.1 MB. Max. memory is 11.5 GB. [2019-12-07 12:16:08,187 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 952.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 391.01 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.4 MB). Free memory was 930.8 MB in the beginning and 1.1 GB in the end (delta: -132.8 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 47.24 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 33.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 415.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.1 MB). Peak memory consumption was 54.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 17945.76 ms. Allocated memory was 1.1 GB in the beginning and 2.8 GB in the end (delta: 1.6 GB). Free memory was 1.0 GB in the beginning and 450.2 MB in the end (delta: 553.8 MB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. * Witness Printer took 63.01 ms. Allocated memory is still 2.8 GB. Free memory was 450.2 MB in the beginning and 409.1 MB in the end (delta: 41.1 MB). Peak memory consumption was 41.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 179 ProgramPointsBefore, 91 ProgramPointsAfterwards, 207 TransitionsBefore, 97 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 7 FixpointIterations, 35 TrivialSequentialCompositions, 50 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 35 ConcurrentYvCompositions, 27 ChoiceCompositions, 4846 VarBasedMoverChecksPositive, 179 VarBasedMoverChecksNegative, 25 SemBasedMoverChecksPositive, 208 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 50860 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L823] FCALL, FORK 0 pthread_create(&t1485, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1486, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1487, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] FCALL, FORK 0 pthread_create(&t1488, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L784] 4 z$w_buff1 = z$w_buff0 [L785] 4 z$w_buff0 = 2 [L786] 4 z$w_buff1_used = z$w_buff0_used [L787] 4 z$w_buff0_used = (_Bool)1 [L800] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L764] 3 y = 1 [L767] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L800] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L770] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L801] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L802] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L772] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L773] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L831] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L837] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L838] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L839] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L842] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L843] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L844] 0 z$flush_delayed = weak$$choice2 [L845] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L847] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L848] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L849] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L849] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L850] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L852] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L853] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p1_EAX == 0 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p1_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 17.8s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 4.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2318 SDtfs, 2710 SDslu, 5465 SDs, 0 SdLazy, 2557 SolverSat, 238 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 189 GetRequests, 36 SyntacticMatches, 17 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 194 ImplicationChecksByTransitivity, 1.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52262occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.3s AutomataMinimizationTime, 20 MinimizatonAttempts, 33626 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 923 NumberOfCodeBlocks, 923 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 843 ConstructedInterpolants, 0 QuantifiedInterpolants, 163555 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...