./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f0dece396cd7469c799cbf4d57488b0c57de53d3 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:26:18,937 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:26:18,938 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:26:18,945 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:26:18,946 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:26:18,946 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:26:18,947 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:26:18,949 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:26:18,950 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:26:18,950 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:26:18,951 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:26:18,952 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:26:18,952 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:26:18,953 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:26:18,953 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:26:18,954 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:26:18,955 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:26:18,955 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:26:18,957 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:26:18,959 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:26:18,960 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:26:18,960 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:26:18,961 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:26:18,962 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:26:18,963 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:26:18,964 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:26:18,964 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:26:18,964 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:26:18,964 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:26:18,965 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:26:18,965 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:26:18,966 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:26:18,966 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:26:18,966 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:26:18,967 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:26:18,967 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:26:18,968 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:26:18,968 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:26:18,968 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:26:18,968 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:26:18,969 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:26:18,969 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 16:26:18,979 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:26:18,980 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:26:18,980 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 16:26:18,980 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 16:26:18,980 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 16:26:18,981 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 16:26:18,981 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 16:26:18,982 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 16:26:18,982 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 16:26:18,982 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:26:18,982 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:26:18,982 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:26:18,983 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:26:18,984 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:26:18,984 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 16:26:18,984 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:26:18,985 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:26:18,985 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:26:18,985 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 16:26:18,985 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f0dece396cd7469c799cbf4d57488b0c57de53d3 [2019-12-07 16:26:19,082 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:26:19,090 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:26:19,092 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:26:19,093 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:26:19,094 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:26:19,094 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i [2019-12-07 16:26:19,132 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/data/95feb230c/6620ef0732444bc7b10b1b21f1c16288/FLAG5f23f5a32 [2019-12-07 16:26:19,604 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:26:19,605 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i [2019-12-07 16:26:19,615 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/data/95feb230c/6620ef0732444bc7b10b1b21f1c16288/FLAG5f23f5a32 [2019-12-07 16:26:19,625 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/data/95feb230c/6620ef0732444bc7b10b1b21f1c16288 [2019-12-07 16:26:19,627 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:26:19,628 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:26:19,628 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:26:19,628 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:26:19,631 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:26:19,631 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:26:19" (1/1) ... [2019-12-07 16:26:19,633 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25138a46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:19, skipping insertion in model container [2019-12-07 16:26:19,633 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:26:19" (1/1) ... [2019-12-07 16:26:19,638 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:26:19,666 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:26:19,910 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:26:19,917 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:26:19,964 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:26:20,015 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:26:20,015 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20 WrapperNode [2019-12-07 16:26:20,015 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:26:20,016 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:26:20,016 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:26:20,016 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:26:20,022 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,036 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,058 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:26:20,058 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:26:20,058 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:26:20,058 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:26:20,065 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,065 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,068 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,069 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,076 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,079 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,081 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... [2019-12-07 16:26:20,084 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:26:20,085 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:26:20,085 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:26:20,085 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:26:20,085 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:26:20,132 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 16:26:20,133 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 16:26:20,133 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 16:26:20,133 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 16:26:20,133 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 16:26:20,134 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:26:20,134 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:26:20,135 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 16:26:20,496 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:26:20,497 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 16:26:20,497 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:26:20 BoogieIcfgContainer [2019-12-07 16:26:20,498 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:26:20,498 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:26:20,498 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:26:20,500 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:26:20,500 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:26:19" (1/3) ... [2019-12-07 16:26:20,501 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6845d000 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:26:20, skipping insertion in model container [2019-12-07 16:26:20,501 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:26:20" (2/3) ... [2019-12-07 16:26:20,501 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6845d000 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:26:20, skipping insertion in model container [2019-12-07 16:26:20,501 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:26:20" (3/3) ... [2019-12-07 16:26:20,502 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_pso.opt.i [2019-12-07 16:26:20,508 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 16:26:20,509 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:26:20,513 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 16:26:20,514 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,538 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,539 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,540 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,541 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,542 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:26:20,560 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 16:26:20,572 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:26:20,572 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:26:20,572 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:26:20,572 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:26:20,572 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:26:20,572 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:26:20,573 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:26:20,573 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:26:20,584 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 16:26:20,585 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:26:20,638 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:26:20,638 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:26:20,648 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:26:20,663 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:26:20,694 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:26:20,694 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:26:20,699 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:26:20,715 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 16:26:20,716 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 16:26:23,514 WARN L192 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 16:26:23,600 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 16:26:23,601 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 16:26:23,603 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 16:26:38,384 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 16:26:38,385 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 16:26:38,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 16:26:38,389 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:26:38,389 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 16:26:38,390 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:26:38,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:26:38,394 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 16:26:38,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:26:38,400 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948232153] [2019-12-07 16:26:38,400 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:26:38,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:26:38,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:26:38,529 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948232153] [2019-12-07 16:26:38,529 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:26:38,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 16:26:38,530 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283383501] [2019-12-07 16:26:38,533 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:26:38,533 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:26:38,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:26:38,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:26:38,543 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 16:26:39,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:26:39,307 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 16:26:39,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:26:39,309 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 16:26:39,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:26:39,900 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 16:26:39,900 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 16:26:39,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:26:43,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 16:26:46,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 16:26:46,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 16:26:46,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 16:26:46,650 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 16:26:46,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:26:46,651 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 16:26:46,651 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:26:46,651 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 16:26:46,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 16:26:46,654 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:26:46,654 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:26:46,654 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:26:46,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:26:46,655 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 16:26:46,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:26:46,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365495039] [2019-12-07 16:26:46,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:26:46,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:26:46,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:26:46,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365495039] [2019-12-07 16:26:46,719 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:26:46,719 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:26:46,719 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224132108] [2019-12-07 16:26:46,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:26:46,721 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:26:46,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:26:46,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:26:46,721 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 16:26:47,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:26:47,956 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 16:26:47,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:26:47,957 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 16:26:47,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:26:48,389 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 16:26:48,389 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 16:26:48,390 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:26:52,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 16:26:56,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 16:26:56,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 16:26:56,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 16:26:56,983 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 16:26:56,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:26:56,983 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 16:26:56,984 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:26:56,984 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 16:26:56,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:26:56,988 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:26:56,989 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:26:56,989 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:26:56,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:26:56,989 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 16:26:56,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:26:56,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651463273] [2019-12-07 16:26:56,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:26:57,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:26:57,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:26:57,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651463273] [2019-12-07 16:26:57,050 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:26:57,050 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:26:57,050 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445385807] [2019-12-07 16:26:57,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:26:57,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:26:57,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:26:57,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:26:57,051 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 16:26:58,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:26:58,480 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 16:26:58,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:26:58,481 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:26:58,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:26:59,059 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 16:26:59,060 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 16:26:59,060 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:27:04,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 16:27:08,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 16:27:08,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 16:27:09,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 16:27:09,350 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 16:27:09,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:27:09,351 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 16:27:09,351 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:27:09,351 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 16:27:09,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:27:09,353 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:27:09,354 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:27:09,354 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:27:09,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:27:09,354 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 16:27:09,354 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:27:09,354 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431013519] [2019-12-07 16:27:09,354 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:27:09,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:27:09,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:27:09,403 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431013519] [2019-12-07 16:27:09,404 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:27:09,404 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:27:09,404 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162893145] [2019-12-07 16:27:09,404 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:27:09,404 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:27:09,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:27:09,405 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:27:09,405 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 16:27:11,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:27:11,051 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 16:27:11,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:27:11,052 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:27:11,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:27:11,657 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 16:27:11,657 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 16:27:11,657 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:27:16,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 16:27:19,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 16:27:19,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 16:27:20,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 16:27:20,701 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 16:27:20,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:27:20,701 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 16:27:20,701 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:27:20,701 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 16:27:20,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:27:20,721 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:27:20,721 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:27:20,721 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:27:20,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:27:20,721 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 16:27:20,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:27:20,721 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239002240] [2019-12-07 16:27:20,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:27:20,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:27:20,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:27:20,766 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239002240] [2019-12-07 16:27:20,766 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:27:20,767 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:27:20,767 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373699979] [2019-12-07 16:27:20,767 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:27:20,767 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:27:20,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:27:20,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:27:20,768 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 16:27:22,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:27:22,266 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 16:27:22,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:27:22,267 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:27:22,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:27:23,015 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 16:27:23,015 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 16:27:23,015 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:27:31,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 16:27:34,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 16:27:34,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 16:27:35,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 16:27:35,557 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 16:27:35,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:27:35,558 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 16:27:35,558 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:27:35,558 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 16:27:35,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:27:35,571 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:27:35,571 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:27:35,571 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:27:35,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:27:35,571 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 16:27:35,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:27:35,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731592684] [2019-12-07 16:27:35,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:27:35,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:27:35,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:27:35,612 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731592684] [2019-12-07 16:27:35,612 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:27:35,612 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:27:35,613 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868248671] [2019-12-07 16:27:35,613 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:27:35,613 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:27:35,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:27:35,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:27:35,614 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 5 states. [2019-12-07 16:27:37,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:27:37,278 INFO L93 Difference]: Finished difference Result 326371 states and 1320375 transitions. [2019-12-07 16:27:37,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:27:37,278 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:27:37,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:27:38,526 INFO L225 Difference]: With dead ends: 326371 [2019-12-07 16:27:38,526 INFO L226 Difference]: Without dead ends: 326224 [2019-12-07 16:27:38,527 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:27:44,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326224 states. [2019-12-07 16:27:50,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326224 to 227768. [2019-12-07 16:27:50,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227768 states. [2019-12-07 16:27:51,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227768 states to 227768 states and 938858 transitions. [2019-12-07 16:27:51,437 INFO L78 Accepts]: Start accepts. Automaton has 227768 states and 938858 transitions. Word has length 19 [2019-12-07 16:27:51,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:27:51,437 INFO L462 AbstractCegarLoop]: Abstraction has 227768 states and 938858 transitions. [2019-12-07 16:27:51,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:27:51,437 INFO L276 IsEmpty]: Start isEmpty. Operand 227768 states and 938858 transitions. [2019-12-07 16:27:51,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:27:51,451 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:27:51,451 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:27:51,451 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:27:51,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:27:51,452 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 16:27:51,452 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:27:51,452 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028249157] [2019-12-07 16:27:51,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:27:51,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:27:51,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:27:51,493 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028249157] [2019-12-07 16:27:51,494 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:27:51,494 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:27:51,494 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62232522] [2019-12-07 16:27:51,494 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:27:51,494 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:27:51,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:27:51,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:27:51,494 INFO L87 Difference]: Start difference. First operand 227768 states and 938858 transitions. Second operand 5 states. [2019-12-07 16:27:53,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:27:53,395 INFO L93 Difference]: Finished difference Result 330156 states and 1338658 transitions. [2019-12-07 16:27:53,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:27:53,395 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:27:53,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:27:54,753 INFO L225 Difference]: With dead ends: 330156 [2019-12-07 16:27:54,753 INFO L226 Difference]: Without dead ends: 330093 [2019-12-07 16:27:54,754 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:28:01,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330093 states. [2019-12-07 16:28:04,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330093 to 245714. [2019-12-07 16:28:04,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245714 states. [2019-12-07 16:28:05,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245714 states to 245714 states and 1011495 transitions. [2019-12-07 16:28:05,329 INFO L78 Accepts]: Start accepts. Automaton has 245714 states and 1011495 transitions. Word has length 19 [2019-12-07 16:28:05,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:05,329 INFO L462 AbstractCegarLoop]: Abstraction has 245714 states and 1011495 transitions. [2019-12-07 16:28:05,329 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:28:05,329 INFO L276 IsEmpty]: Start isEmpty. Operand 245714 states and 1011495 transitions. [2019-12-07 16:28:05,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 16:28:05,389 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:05,389 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:05,389 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:05,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:05,389 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 16:28:05,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:05,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237737433] [2019-12-07 16:28:05,389 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:05,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:05,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:05,451 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237737433] [2019-12-07 16:28:05,451 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:05,451 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:28:05,451 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423681856] [2019-12-07 16:28:05,451 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:28:05,452 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:05,452 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:28:05,452 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:28:05,452 INFO L87 Difference]: Start difference. First operand 245714 states and 1011495 transitions. Second operand 6 states. [2019-12-07 16:28:07,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:07,692 INFO L93 Difference]: Finished difference Result 293437 states and 1194200 transitions. [2019-12-07 16:28:07,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 16:28:07,693 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 16:28:07,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:08,446 INFO L225 Difference]: With dead ends: 293437 [2019-12-07 16:28:08,446 INFO L226 Difference]: Without dead ends: 293290 [2019-12-07 16:28:08,447 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 16:28:17,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293290 states. [2019-12-07 16:28:20,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293290 to 203000. [2019-12-07 16:28:20,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203000 states. [2019-12-07 16:28:20,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203000 states to 203000 states and 839373 transitions. [2019-12-07 16:28:20,870 INFO L78 Accepts]: Start accepts. Automaton has 203000 states and 839373 transitions. Word has length 25 [2019-12-07 16:28:20,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:20,870 INFO L462 AbstractCegarLoop]: Abstraction has 203000 states and 839373 transitions. [2019-12-07 16:28:20,870 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:28:20,870 INFO L276 IsEmpty]: Start isEmpty. Operand 203000 states and 839373 transitions. [2019-12-07 16:28:20,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 16:28:20,943 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:20,943 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:20,943 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:20,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:20,943 INFO L82 PathProgramCache]: Analyzing trace with hash -826573092, now seen corresponding path program 1 times [2019-12-07 16:28:20,943 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:20,943 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830381397] [2019-12-07 16:28:20,943 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:20,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:20,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:20,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830381397] [2019-12-07 16:28:20,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:20,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:20,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563522118] [2019-12-07 16:28:20,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:20,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:20,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:20,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:20,975 INFO L87 Difference]: Start difference. First operand 203000 states and 839373 transitions. Second operand 3 states. [2019-12-07 16:28:21,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:21,087 INFO L93 Difference]: Finished difference Result 41735 states and 134919 transitions. [2019-12-07 16:28:21,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:21,088 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 16:28:21,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:21,148 INFO L225 Difference]: With dead ends: 41735 [2019-12-07 16:28:21,149 INFO L226 Difference]: Without dead ends: 41735 [2019-12-07 16:28:21,149 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:21,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41735 states. [2019-12-07 16:28:21,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41735 to 41735. [2019-12-07 16:28:21,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41735 states. [2019-12-07 16:28:21,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41735 states to 41735 states and 134919 transitions. [2019-12-07 16:28:21,777 INFO L78 Accepts]: Start accepts. Automaton has 41735 states and 134919 transitions. Word has length 27 [2019-12-07 16:28:21,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:21,778 INFO L462 AbstractCegarLoop]: Abstraction has 41735 states and 134919 transitions. [2019-12-07 16:28:21,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:21,778 INFO L276 IsEmpty]: Start isEmpty. Operand 41735 states and 134919 transitions. [2019-12-07 16:28:21,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 16:28:21,797 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:21,797 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:21,797 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:21,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:21,797 INFO L82 PathProgramCache]: Analyzing trace with hash -181038669, now seen corresponding path program 1 times [2019-12-07 16:28:21,798 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:21,798 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454149563] [2019-12-07 16:28:21,798 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:21,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:21,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:21,834 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454149563] [2019-12-07 16:28:21,834 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:21,834 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:28:21,834 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189749748] [2019-12-07 16:28:21,834 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:28:21,835 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:21,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:28:21,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:28:21,835 INFO L87 Difference]: Start difference. First operand 41735 states and 134919 transitions. Second operand 4 states. [2019-12-07 16:28:21,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:21,860 INFO L93 Difference]: Finished difference Result 7949 states and 21432 transitions. [2019-12-07 16:28:21,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:28:21,861 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 16:28:21,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:21,868 INFO L225 Difference]: With dead ends: 7949 [2019-12-07 16:28:21,868 INFO L226 Difference]: Without dead ends: 7949 [2019-12-07 16:28:21,869 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:28:21,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7949 states. [2019-12-07 16:28:21,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7949 to 7837. [2019-12-07 16:28:21,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7837 states. [2019-12-07 16:28:21,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7837 states to 7837 states and 21112 transitions. [2019-12-07 16:28:21,951 INFO L78 Accepts]: Start accepts. Automaton has 7837 states and 21112 transitions. Word has length 39 [2019-12-07 16:28:21,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:21,951 INFO L462 AbstractCegarLoop]: Abstraction has 7837 states and 21112 transitions. [2019-12-07 16:28:21,951 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:28:21,952 INFO L276 IsEmpty]: Start isEmpty. Operand 7837 states and 21112 transitions. [2019-12-07 16:28:21,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 16:28:21,957 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:21,957 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:21,958 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:21,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:21,958 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 16:28:21,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:21,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074380082] [2019-12-07 16:28:21,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:21,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:22,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:22,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074380082] [2019-12-07 16:28:22,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:22,010 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:28:22,010 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332698276] [2019-12-07 16:28:22,010 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:28:22,010 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:22,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:28:22,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:22,011 INFO L87 Difference]: Start difference. First operand 7837 states and 21112 transitions. Second operand 5 states. [2019-12-07 16:28:22,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:22,033 INFO L93 Difference]: Finished difference Result 5331 states and 15289 transitions. [2019-12-07 16:28:22,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:28:22,033 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 16:28:22,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:22,039 INFO L225 Difference]: With dead ends: 5331 [2019-12-07 16:28:22,039 INFO L226 Difference]: Without dead ends: 5331 [2019-12-07 16:28:22,039 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:22,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2019-12-07 16:28:22,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 4967. [2019-12-07 16:28:22,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4967 states. [2019-12-07 16:28:22,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4967 states to 4967 states and 14305 transitions. [2019-12-07 16:28:22,100 INFO L78 Accepts]: Start accepts. Automaton has 4967 states and 14305 transitions. Word has length 51 [2019-12-07 16:28:22,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:22,100 INFO L462 AbstractCegarLoop]: Abstraction has 4967 states and 14305 transitions. [2019-12-07 16:28:22,100 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:28:22,100 INFO L276 IsEmpty]: Start isEmpty. Operand 4967 states and 14305 transitions. [2019-12-07 16:28:22,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:28:22,104 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:22,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:22,104 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:22,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:22,104 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 16:28:22,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:22,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105952366] [2019-12-07 16:28:22,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:22,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:22,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:22,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105952366] [2019-12-07 16:28:22,161 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:22,162 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:28:22,162 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753406967] [2019-12-07 16:28:22,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:28:22,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:22,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:28:22,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:22,163 INFO L87 Difference]: Start difference. First operand 4967 states and 14305 transitions. Second operand 5 states. [2019-12-07 16:28:22,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:22,339 INFO L93 Difference]: Finished difference Result 7558 states and 21570 transitions. [2019-12-07 16:28:22,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:28:22,339 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 16:28:22,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:22,346 INFO L225 Difference]: With dead ends: 7558 [2019-12-07 16:28:22,346 INFO L226 Difference]: Without dead ends: 7558 [2019-12-07 16:28:22,346 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:28:22,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7558 states. [2019-12-07 16:28:22,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7558 to 6659. [2019-12-07 16:28:22,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6659 states. [2019-12-07 16:28:22,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6659 states to 6659 states and 19091 transitions. [2019-12-07 16:28:22,709 INFO L78 Accepts]: Start accepts. Automaton has 6659 states and 19091 transitions. Word has length 65 [2019-12-07 16:28:22,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:22,709 INFO L462 AbstractCegarLoop]: Abstraction has 6659 states and 19091 transitions. [2019-12-07 16:28:22,709 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:28:22,709 INFO L276 IsEmpty]: Start isEmpty. Operand 6659 states and 19091 transitions. [2019-12-07 16:28:22,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:28:22,713 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:22,713 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:22,714 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:22,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:22,714 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 16:28:22,714 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:22,714 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767578973] [2019-12-07 16:28:22,714 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:22,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:22,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:22,788 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767578973] [2019-12-07 16:28:22,788 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:22,788 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:22,788 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395352286] [2019-12-07 16:28:22,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:22,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:22,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:22,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:22,789 INFO L87 Difference]: Start difference. First operand 6659 states and 19091 transitions. Second operand 3 states. [2019-12-07 16:28:22,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:22,807 INFO L93 Difference]: Finished difference Result 6289 states and 17750 transitions. [2019-12-07 16:28:22,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:22,807 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 16:28:22,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:22,812 INFO L225 Difference]: With dead ends: 6289 [2019-12-07 16:28:22,812 INFO L226 Difference]: Without dead ends: 6289 [2019-12-07 16:28:22,812 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:22,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6289 states. [2019-12-07 16:28:22,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6289 to 6133. [2019-12-07 16:28:22,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6133 states. [2019-12-07 16:28:22,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6133 states to 6133 states and 17320 transitions. [2019-12-07 16:28:22,886 INFO L78 Accepts]: Start accepts. Automaton has 6133 states and 17320 transitions. Word has length 65 [2019-12-07 16:28:22,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:22,886 INFO L462 AbstractCegarLoop]: Abstraction has 6133 states and 17320 transitions. [2019-12-07 16:28:22,886 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:22,886 INFO L276 IsEmpty]: Start isEmpty. Operand 6133 states and 17320 transitions. [2019-12-07 16:28:22,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:22,890 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:22,890 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:22,890 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:22,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:22,890 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 16:28:22,891 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:22,891 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270601818] [2019-12-07 16:28:22,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:22,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:22,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:22,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270601818] [2019-12-07 16:28:22,953 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:22,953 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:28:22,953 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802950387] [2019-12-07 16:28:22,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:28:22,954 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:22,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:28:22,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:22,954 INFO L87 Difference]: Start difference. First operand 6133 states and 17320 transitions. Second operand 5 states. [2019-12-07 16:28:23,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:23,143 INFO L93 Difference]: Finished difference Result 8712 states and 24399 transitions. [2019-12-07 16:28:23,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 16:28:23,143 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 16:28:23,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:23,150 INFO L225 Difference]: With dead ends: 8712 [2019-12-07 16:28:23,150 INFO L226 Difference]: Without dead ends: 8712 [2019-12-07 16:28:23,151 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:28:23,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8712 states. [2019-12-07 16:28:23,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8712 to 6784. [2019-12-07 16:28:23,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6784 states. [2019-12-07 16:28:23,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6784 states to 6784 states and 19209 transitions. [2019-12-07 16:28:23,240 INFO L78 Accepts]: Start accepts. Automaton has 6784 states and 19209 transitions. Word has length 66 [2019-12-07 16:28:23,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:23,240 INFO L462 AbstractCegarLoop]: Abstraction has 6784 states and 19209 transitions. [2019-12-07 16:28:23,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:28:23,240 INFO L276 IsEmpty]: Start isEmpty. Operand 6784 states and 19209 transitions. [2019-12-07 16:28:23,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:23,245 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:23,245 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:23,245 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:23,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:23,245 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 16:28:23,245 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:23,245 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946225581] [2019-12-07 16:28:23,245 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:23,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:23,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:23,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946225581] [2019-12-07 16:28:23,461 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:23,461 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:28:23,462 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812001260] [2019-12-07 16:28:23,462 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:28:23,462 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:23,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:28:23,462 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:28:23,462 INFO L87 Difference]: Start difference. First operand 6784 states and 19209 transitions. Second operand 13 states. [2019-12-07 16:28:23,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:23,930 INFO L93 Difference]: Finished difference Result 15281 states and 43257 transitions. [2019-12-07 16:28:23,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 16:28:23,931 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2019-12-07 16:28:23,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:23,937 INFO L225 Difference]: With dead ends: 15281 [2019-12-07 16:28:23,937 INFO L226 Difference]: Without dead ends: 7828 [2019-12-07 16:28:23,938 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=145, Invalid=455, Unknown=0, NotChecked=0, Total=600 [2019-12-07 16:28:23,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7828 states. [2019-12-07 16:28:24,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7828 to 6415. [2019-12-07 16:28:24,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6415 states. [2019-12-07 16:28:24,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6415 states to 6415 states and 18105 transitions. [2019-12-07 16:28:24,017 INFO L78 Accepts]: Start accepts. Automaton has 6415 states and 18105 transitions. Word has length 66 [2019-12-07 16:28:24,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:24,017 INFO L462 AbstractCegarLoop]: Abstraction has 6415 states and 18105 transitions. [2019-12-07 16:28:24,017 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:28:24,018 INFO L276 IsEmpty]: Start isEmpty. Operand 6415 states and 18105 transitions. [2019-12-07 16:28:24,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:24,021 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:24,022 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:24,022 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:24,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:24,022 INFO L82 PathProgramCache]: Analyzing trace with hash -806353662, now seen corresponding path program 3 times [2019-12-07 16:28:24,022 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:24,022 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407801583] [2019-12-07 16:28:24,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:24,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:24,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:24,088 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407801583] [2019-12-07 16:28:24,088 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:24,088 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:28:24,088 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894654963] [2019-12-07 16:28:24,089 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:28:24,089 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:24,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:28:24,089 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:28:24,089 INFO L87 Difference]: Start difference. First operand 6415 states and 18105 transitions. Second operand 6 states. [2019-12-07 16:28:24,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:24,393 INFO L93 Difference]: Finished difference Result 9213 states and 25620 transitions. [2019-12-07 16:28:24,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 16:28:24,393 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 16:28:24,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:24,400 INFO L225 Difference]: With dead ends: 9213 [2019-12-07 16:28:24,400 INFO L226 Difference]: Without dead ends: 9213 [2019-12-07 16:28:24,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 16:28:24,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9213 states. [2019-12-07 16:28:24,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9213 to 6830. [2019-12-07 16:28:24,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6830 states. [2019-12-07 16:28:24,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6830 states to 6830 states and 19261 transitions. [2019-12-07 16:28:24,491 INFO L78 Accepts]: Start accepts. Automaton has 6830 states and 19261 transitions. Word has length 66 [2019-12-07 16:28:24,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:24,491 INFO L462 AbstractCegarLoop]: Abstraction has 6830 states and 19261 transitions. [2019-12-07 16:28:24,491 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:28:24,491 INFO L276 IsEmpty]: Start isEmpty. Operand 6830 states and 19261 transitions. [2019-12-07 16:28:24,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:24,495 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:24,496 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:24,496 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:24,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:24,496 INFO L82 PathProgramCache]: Analyzing trace with hash 1549059410, now seen corresponding path program 4 times [2019-12-07 16:28:24,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:24,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748165671] [2019-12-07 16:28:24,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:24,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:24,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:24,587 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748165671] [2019-12-07 16:28:24,587 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:24,587 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 16:28:24,587 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686059785] [2019-12-07 16:28:24,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 16:28:24,588 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:24,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 16:28:24,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:28:24,588 INFO L87 Difference]: Start difference. First operand 6830 states and 19261 transitions. Second operand 9 states. [2019-12-07 16:28:25,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:25,065 INFO L93 Difference]: Finished difference Result 11724 states and 32586 transitions. [2019-12-07 16:28:25,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 16:28:25,065 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 16:28:25,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:25,074 INFO L225 Difference]: With dead ends: 11724 [2019-12-07 16:28:25,074 INFO L226 Difference]: Without dead ends: 11724 [2019-12-07 16:28:25,075 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=160, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:28:25,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11724 states. [2019-12-07 16:28:25,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11724 to 7479. [2019-12-07 16:28:25,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7479 states. [2019-12-07 16:28:25,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7479 states to 7479 states and 21056 transitions. [2019-12-07 16:28:25,180 INFO L78 Accepts]: Start accepts. Automaton has 7479 states and 21056 transitions. Word has length 66 [2019-12-07 16:28:25,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:25,181 INFO L462 AbstractCegarLoop]: Abstraction has 7479 states and 21056 transitions. [2019-12-07 16:28:25,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 16:28:25,181 INFO L276 IsEmpty]: Start isEmpty. Operand 7479 states and 21056 transitions. [2019-12-07 16:28:25,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:25,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:25,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:25,186 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:25,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:25,186 INFO L82 PathProgramCache]: Analyzing trace with hash 479477378, now seen corresponding path program 5 times [2019-12-07 16:28:25,186 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:25,186 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053847998] [2019-12-07 16:28:25,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:25,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:25,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:25,285 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053847998] [2019-12-07 16:28:25,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:25,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 16:28:25,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649927492] [2019-12-07 16:28:25,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 16:28:25,286 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:25,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 16:28:25,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:28:25,286 INFO L87 Difference]: Start difference. First operand 7479 states and 21056 transitions. Second operand 10 states. [2019-12-07 16:28:26,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:26,104 INFO L93 Difference]: Finished difference Result 12163 states and 33776 transitions. [2019-12-07 16:28:26,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 16:28:26,105 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 16:28:26,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:26,115 INFO L225 Difference]: With dead ends: 12163 [2019-12-07 16:28:26,115 INFO L226 Difference]: Without dead ends: 12163 [2019-12-07 16:28:26,115 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2019-12-07 16:28:26,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12163 states. [2019-12-07 16:28:26,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12163 to 8091. [2019-12-07 16:28:26,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8091 states. [2019-12-07 16:28:26,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8091 states to 8091 states and 22798 transitions. [2019-12-07 16:28:26,233 INFO L78 Accepts]: Start accepts. Automaton has 8091 states and 22798 transitions. Word has length 66 [2019-12-07 16:28:26,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:26,233 INFO L462 AbstractCegarLoop]: Abstraction has 8091 states and 22798 transitions. [2019-12-07 16:28:26,233 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 16:28:26,233 INFO L276 IsEmpty]: Start isEmpty. Operand 8091 states and 22798 transitions. [2019-12-07 16:28:26,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:28:26,238 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:26,239 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:26,239 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:26,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:26,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1795321204, now seen corresponding path program 6 times [2019-12-07 16:28:26,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:26,239 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569535629] [2019-12-07 16:28:26,239 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:26,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:26,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:26,271 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569535629] [2019-12-07 16:28:26,271 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:26,271 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:26,271 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9855943] [2019-12-07 16:28:26,272 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:26,272 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:26,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:26,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:26,272 INFO L87 Difference]: Start difference. First operand 8091 states and 22798 transitions. Second operand 3 states. [2019-12-07 16:28:26,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:26,321 INFO L93 Difference]: Finished difference Result 8090 states and 22796 transitions. [2019-12-07 16:28:26,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:26,321 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 16:28:26,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:26,329 INFO L225 Difference]: With dead ends: 8090 [2019-12-07 16:28:26,329 INFO L226 Difference]: Without dead ends: 8090 [2019-12-07 16:28:26,329 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:26,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8090 states. [2019-12-07 16:28:26,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8090 to 5115. [2019-12-07 16:28:26,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5115 states. [2019-12-07 16:28:26,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5115 states to 5115 states and 14500 transitions. [2019-12-07 16:28:26,405 INFO L78 Accepts]: Start accepts. Automaton has 5115 states and 14500 transitions. Word has length 66 [2019-12-07 16:28:26,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:26,406 INFO L462 AbstractCegarLoop]: Abstraction has 5115 states and 14500 transitions. [2019-12-07 16:28:26,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:26,406 INFO L276 IsEmpty]: Start isEmpty. Operand 5115 states and 14500 transitions. [2019-12-07 16:28:26,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 16:28:26,409 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:26,409 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:26,409 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:26,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:26,410 INFO L82 PathProgramCache]: Analyzing trace with hash 1374418208, now seen corresponding path program 1 times [2019-12-07 16:28:26,410 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:26,410 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863831417] [2019-12-07 16:28:26,410 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:26,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:26,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:26,440 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863831417] [2019-12-07 16:28:26,440 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:26,441 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:26,441 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911573829] [2019-12-07 16:28:26,441 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:26,441 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:26,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:26,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:26,441 INFO L87 Difference]: Start difference. First operand 5115 states and 14500 transitions. Second operand 3 states. [2019-12-07 16:28:26,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:26,458 INFO L93 Difference]: Finished difference Result 4739 states and 13191 transitions. [2019-12-07 16:28:26,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:26,458 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 16:28:26,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:26,462 INFO L225 Difference]: With dead ends: 4739 [2019-12-07 16:28:26,462 INFO L226 Difference]: Without dead ends: 4739 [2019-12-07 16:28:26,462 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:26,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4739 states. [2019-12-07 16:28:26,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4739 to 4174. [2019-12-07 16:28:26,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 16:28:26,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 16:28:26,620 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 67 [2019-12-07 16:28:26,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:26,621 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 16:28:26,621 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:26,621 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 16:28:26,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:26,624 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:26,624 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:26,624 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:26,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:26,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 1 times [2019-12-07 16:28:26,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:26,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526534485] [2019-12-07 16:28:26,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:26,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:26,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:26,773 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526534485] [2019-12-07 16:28:26,773 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:26,773 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 16:28:26,773 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48083227] [2019-12-07 16:28:26,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 16:28:26,774 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:26,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 16:28:26,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 16:28:26,774 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 12 states. [2019-12-07 16:28:27,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:27,022 INFO L93 Difference]: Finished difference Result 7786 states and 21631 transitions. [2019-12-07 16:28:27,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 16:28:27,023 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 68 [2019-12-07 16:28:27,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:27,028 INFO L225 Difference]: With dead ends: 7786 [2019-12-07 16:28:27,028 INFO L226 Difference]: Without dead ends: 7027 [2019-12-07 16:28:27,029 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=308, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:28:27,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7027 states. [2019-12-07 16:28:27,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7027 to 5351. [2019-12-07 16:28:27,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5351 states. [2019-12-07 16:28:27,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 14810 transitions. [2019-12-07 16:28:27,096 INFO L78 Accepts]: Start accepts. Automaton has 5351 states and 14810 transitions. Word has length 68 [2019-12-07 16:28:27,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:27,096 INFO L462 AbstractCegarLoop]: Abstraction has 5351 states and 14810 transitions. [2019-12-07 16:28:27,096 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 16:28:27,096 INFO L276 IsEmpty]: Start isEmpty. Operand 5351 states and 14810 transitions. [2019-12-07 16:28:27,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:27,099 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:27,100 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:27,100 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:27,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:27,100 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 2 times [2019-12-07 16:28:27,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:27,100 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38335580] [2019-12-07 16:28:27,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:27,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:27,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:27,271 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38335580] [2019-12-07 16:28:27,271 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:27,271 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:28:27,271 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045452893] [2019-12-07 16:28:27,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:28:27,271 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:27,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:28:27,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:28:27,272 INFO L87 Difference]: Start difference. First operand 5351 states and 14810 transitions. Second operand 13 states. [2019-12-07 16:28:27,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:27,734 INFO L93 Difference]: Finished difference Result 8219 states and 22676 transitions. [2019-12-07 16:28:27,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 16:28:27,734 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:28:27,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:27,740 INFO L225 Difference]: With dead ends: 8219 [2019-12-07 16:28:27,740 INFO L226 Difference]: Without dead ends: 7712 [2019-12-07 16:28:27,741 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2019-12-07 16:28:27,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7712 states. [2019-12-07 16:28:27,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7712 to 5640. [2019-12-07 16:28:27,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5640 states. [2019-12-07 16:28:27,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 15625 transitions. [2019-12-07 16:28:27,815 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 15625 transitions. Word has length 68 [2019-12-07 16:28:27,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:27,815 INFO L462 AbstractCegarLoop]: Abstraction has 5640 states and 15625 transitions. [2019-12-07 16:28:27,815 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:28:27,815 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 15625 transitions. [2019-12-07 16:28:27,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:27,819 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:27,819 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:27,819 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:27,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:27,820 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 3 times [2019-12-07 16:28:27,820 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:27,820 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175458349] [2019-12-07 16:28:27,820 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:27,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:28,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:28,046 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175458349] [2019-12-07 16:28:28,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:28,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 16:28:28,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753368969] [2019-12-07 16:28:28,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 16:28:28,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:28,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 16:28:28,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=175, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:28:28,048 INFO L87 Difference]: Start difference. First operand 5640 states and 15625 transitions. Second operand 15 states. [2019-12-07 16:28:28,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:28,786 INFO L93 Difference]: Finished difference Result 10829 states and 30026 transitions. [2019-12-07 16:28:28,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 16:28:28,786 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 16:28:28,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:28,795 INFO L225 Difference]: With dead ends: 10829 [2019-12-07 16:28:28,795 INFO L226 Difference]: Without dead ends: 10364 [2019-12-07 16:28:28,796 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 393 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=355, Invalid=1367, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 16:28:28,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10364 states. [2019-12-07 16:28:28,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10364 to 5924. [2019-12-07 16:28:28,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5924 states. [2019-12-07 16:28:28,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5924 states to 5924 states and 16416 transitions. [2019-12-07 16:28:28,882 INFO L78 Accepts]: Start accepts. Automaton has 5924 states and 16416 transitions. Word has length 68 [2019-12-07 16:28:28,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:28,882 INFO L462 AbstractCegarLoop]: Abstraction has 5924 states and 16416 transitions. [2019-12-07 16:28:28,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 16:28:28,882 INFO L276 IsEmpty]: Start isEmpty. Operand 5924 states and 16416 transitions. [2019-12-07 16:28:28,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:28,885 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:28,885 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:28,886 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:28,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:28,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1379923308, now seen corresponding path program 4 times [2019-12-07 16:28:28,886 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:28,886 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395572600] [2019-12-07 16:28:28,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:28,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:29,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:29,281 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395572600] [2019-12-07 16:28:29,281 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:29,281 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 16:28:29,281 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062495262] [2019-12-07 16:28:29,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 16:28:29,282 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:29,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 16:28:29,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:28:29,282 INFO L87 Difference]: Start difference. First operand 5924 states and 16416 transitions. Second operand 20 states. [2019-12-07 16:28:31,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:31,448 INFO L93 Difference]: Finished difference Result 17748 states and 48607 transitions. [2019-12-07 16:28:31,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 16:28:31,448 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 16:28:31,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:31,463 INFO L225 Difference]: With dead ends: 17748 [2019-12-07 16:28:31,463 INFO L226 Difference]: Without dead ends: 17599 [2019-12-07 16:28:31,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1004 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=572, Invalid=3210, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 16:28:31,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17599 states. [2019-12-07 16:28:31,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17599 to 6232. [2019-12-07 16:28:31,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6232 states. [2019-12-07 16:28:31,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6232 states to 6232 states and 17322 transitions. [2019-12-07 16:28:31,684 INFO L78 Accepts]: Start accepts. Automaton has 6232 states and 17322 transitions. Word has length 68 [2019-12-07 16:28:31,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:31,684 INFO L462 AbstractCegarLoop]: Abstraction has 6232 states and 17322 transitions. [2019-12-07 16:28:31,684 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 16:28:31,684 INFO L276 IsEmpty]: Start isEmpty. Operand 6232 states and 17322 transitions. [2019-12-07 16:28:31,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:31,688 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:31,688 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:31,688 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:31,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:31,688 INFO L82 PathProgramCache]: Analyzing trace with hash 556311610, now seen corresponding path program 5 times [2019-12-07 16:28:31,689 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:31,689 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187498133] [2019-12-07 16:28:31,689 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:31,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:31,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:31,885 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187498133] [2019-12-07 16:28:31,886 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:31,886 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 16:28:31,886 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826309450] [2019-12-07 16:28:31,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 16:28:31,886 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:31,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 16:28:31,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:28:31,886 INFO L87 Difference]: Start difference. First operand 6232 states and 17322 transitions. Second operand 15 states. [2019-12-07 16:28:32,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:32,648 INFO L93 Difference]: Finished difference Result 10664 states and 29541 transitions. [2019-12-07 16:28:32,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 16:28:32,648 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 16:28:32,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:32,657 INFO L225 Difference]: With dead ends: 10664 [2019-12-07 16:28:32,657 INFO L226 Difference]: Without dead ends: 10571 [2019-12-07 16:28:32,657 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 429 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=360, Invalid=1446, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 16:28:32,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10571 states. [2019-12-07 16:28:32,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10571 to 6028. [2019-12-07 16:28:32,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6028 states. [2019-12-07 16:28:32,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6028 states to 6028 states and 16712 transitions. [2019-12-07 16:28:32,742 INFO L78 Accepts]: Start accepts. Automaton has 6028 states and 16712 transitions. Word has length 68 [2019-12-07 16:28:32,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:32,742 INFO L462 AbstractCegarLoop]: Abstraction has 6028 states and 16712 transitions. [2019-12-07 16:28:32,742 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 16:28:32,742 INFO L276 IsEmpty]: Start isEmpty. Operand 6028 states and 16712 transitions. [2019-12-07 16:28:32,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:32,746 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:32,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:32,746 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:32,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:32,747 INFO L82 PathProgramCache]: Analyzing trace with hash 547029688, now seen corresponding path program 6 times [2019-12-07 16:28:32,747 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:32,747 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948880497] [2019-12-07 16:28:32,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:32,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:32,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:32,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [948880497] [2019-12-07 16:28:32,983 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:32,984 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 16:28:32,984 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98571585] [2019-12-07 16:28:32,984 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 16:28:32,984 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:32,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 16:28:32,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-12-07 16:28:32,984 INFO L87 Difference]: Start difference. First operand 6028 states and 16712 transitions. Second operand 14 states. [2019-12-07 16:28:33,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:33,702 INFO L93 Difference]: Finished difference Result 11629 states and 32085 transitions. [2019-12-07 16:28:33,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 16:28:33,702 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 16:28:33,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:33,711 INFO L225 Difference]: With dead ends: 11629 [2019-12-07 16:28:33,711 INFO L226 Difference]: Without dead ends: 11122 [2019-12-07 16:28:33,712 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=163, Invalid=707, Unknown=0, NotChecked=0, Total=870 [2019-12-07 16:28:33,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11122 states. [2019-12-07 16:28:33,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11122 to 6348. [2019-12-07 16:28:33,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6348 states. [2019-12-07 16:28:33,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6348 states to 6348 states and 17649 transitions. [2019-12-07 16:28:33,803 INFO L78 Accepts]: Start accepts. Automaton has 6348 states and 17649 transitions. Word has length 68 [2019-12-07 16:28:33,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:33,803 INFO L462 AbstractCegarLoop]: Abstraction has 6348 states and 17649 transitions. [2019-12-07 16:28:33,803 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 16:28:33,803 INFO L276 IsEmpty]: Start isEmpty. Operand 6348 states and 17649 transitions. [2019-12-07 16:28:33,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:33,807 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:33,807 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:33,807 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:33,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:33,807 INFO L82 PathProgramCache]: Analyzing trace with hash 2134146816, now seen corresponding path program 7 times [2019-12-07 16:28:33,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:33,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66535824] [2019-12-07 16:28:33,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:33,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:34,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:34,000 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66535824] [2019-12-07 16:28:34,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:34,000 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 16:28:34,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95383146] [2019-12-07 16:28:34,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 16:28:34,001 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 16:28:34,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 16:28:34,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:28:34,001 INFO L87 Difference]: Start difference. First operand 6348 states and 17649 transitions. Second operand 15 states. [2019-12-07 16:28:34,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:34,777 INFO L93 Difference]: Finished difference Result 9603 states and 26339 transitions. [2019-12-07 16:28:34,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 16:28:34,777 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 16:28:34,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:34,785 INFO L225 Difference]: With dead ends: 9603 [2019-12-07 16:28:34,785 INFO L226 Difference]: Without dead ends: 9060 [2019-12-07 16:28:34,786 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=342, Invalid=1298, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 16:28:34,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9060 states. [2019-12-07 16:28:34,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9060 to 5556. [2019-12-07 16:28:34,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5556 states. [2019-12-07 16:28:34,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5556 states to 5556 states and 15323 transitions. [2019-12-07 16:28:34,862 INFO L78 Accepts]: Start accepts. Automaton has 5556 states and 15323 transitions. Word has length 68 [2019-12-07 16:28:34,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:34,862 INFO L462 AbstractCegarLoop]: Abstraction has 5556 states and 15323 transitions. [2019-12-07 16:28:34,862 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 16:28:34,862 INFO L276 IsEmpty]: Start isEmpty. Operand 5556 states and 15323 transitions. [2019-12-07 16:28:34,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:28:34,865 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:34,866 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:34,866 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:34,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:34,866 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 8 times [2019-12-07 16:28:34,866 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 16:28:34,866 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331440716] [2019-12-07 16:28:34,866 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:34,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:28:34,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:28:34,932 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 16:28:34,932 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:28:34,934 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23|) |v_ULTIMATE.start_main_~#t1970~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1970~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1970~0.base_23|) (= 0 v_~z$flush_delayed~0_41) (= 0 |v_ULTIMATE.start_main_~#t1970~0.offset_17|) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23|) 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23| 1) |v_#valid_64|) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_~#t1970~0.base=|v_ULTIMATE.start_main_~#t1970~0.base_23|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_~#t1970~0.offset=|v_ULTIMATE.start_main_~#t1970~0.offset_17|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_20|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1970~0.base, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_~#t1970~0.offset, ULTIMATE.start_main_~#t1971~0.base, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1972~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:28:34,935 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11|) |v_ULTIMATE.start_main_~#t1971~0.offset_10| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1971~0.offset_10|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1971~0.base_11|) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1971~0.base_11| 4) |v_#length_17|) (not (= 0 |v_ULTIMATE.start_main_~#t1971~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1971~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:28:34,935 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:28:34,936 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1972~0.base_12|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12|) |v_ULTIMATE.start_main_~#t1972~0.offset_10| 2))) (not (= |v_ULTIMATE.start_main_~#t1972~0.base_12| 0)) (= 0 |v_ULTIMATE.start_main_~#t1972~0.offset_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1972~0.base_12| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1972~0.base] because there is no mapped edge [2019-12-07 16:28:34,936 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In2113920738 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In2113920738 256)))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out2113920738| ~z$w_buff0_used~0_In2113920738)) (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out2113920738| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2113920738, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2113920738} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out2113920738|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2113920738, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2113920738} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:28:34,936 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd1~0_In1437096939 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1437096939 256))) (.cse3 (= (mod ~z$r_buff0_thd1~0_In1437096939 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1437096939 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1437096939|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In1437096939 |P0Thread1of1ForFork0_#t~ite6_Out1437096939|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1437096939, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1437096939, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1437096939, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1437096939} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1437096939|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1437096939, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1437096939, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1437096939, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1437096939} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:28:34,937 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1979958401 256))) (.cse0 (= ~z$r_buff0_thd1~0_In1979958401 ~z$r_buff0_thd1~0_Out1979958401)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In1979958401 256) 0))) (or (and .cse0 .cse1) (and (= 0 ~z$r_buff0_thd1~0_Out1979958401) (not .cse2) (not .cse1)) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1979958401, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1979958401} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1979958401, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1979958401|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1979958401} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:28:34,937 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In265075884 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In265075884 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd1~0_In265075884 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In265075884 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite8_Out265075884| ~z$r_buff1_thd1~0_In265075884)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out265075884| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In265075884, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In265075884, ~z$w_buff1_used~0=~z$w_buff1_used~0_In265075884, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In265075884} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In265075884, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out265075884|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In265075884, ~z$w_buff1_used~0=~z$w_buff1_used~0_In265075884, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In265075884} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:28:34,937 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:28:34,938 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-37073091 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-37073091 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite9_Out-37073091| ~z~0_In-37073091) (or .cse0 .cse1)) (and (= ~z$w_buff1~0_In-37073091 |P1Thread1of1ForFork1_#t~ite9_Out-37073091|) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-37073091, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-37073091, ~z$w_buff1~0=~z$w_buff1~0_In-37073091, ~z~0=~z~0_In-37073091} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-37073091|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-37073091, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-37073091, ~z$w_buff1~0=~z$w_buff1~0_In-37073091, ~z~0=~z~0_In-37073091} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:28:34,938 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:28:34,938 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd2~0_In1100538828 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1100538828 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out1100538828| 0)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out1100538828| ~z$w_buff0_used~0_In1100538828)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1100538828} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1100538828|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1100538828} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:28:34,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In835114967 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In835114967 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out835114967| ~z~0_In835114967)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out835114967| ~z$w_buff1~0_In835114967) (not .cse0) (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In835114967, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835114967, ~z$w_buff1~0=~z$w_buff1~0_In835114967, ~z~0=~z~0_In835114967} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out835114967|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In835114967, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835114967, ~z$w_buff1~0=~z$w_buff1~0_In835114967, ~z~0=~z~0_In835114967} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:28:34,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In-182628863 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd2~0_In-182628863 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd2~0_In-182628863 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-182628863 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-182628863 |P1Thread1of1ForFork1_#t~ite12_Out-182628863|)) (and (= |P1Thread1of1ForFork1_#t~ite12_Out-182628863| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-182628863, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-182628863, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-182628863, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-182628863} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-182628863, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-182628863, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-182628863, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-182628863|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-182628863} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:28:34,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-103677559 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd2~0_In-103677559 256) 0))) (or (and (= ~z$r_buff0_thd2~0_In-103677559 |P1Thread1of1ForFork1_#t~ite13_Out-103677559|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-103677559|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-103677559, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-103677559} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-103677559, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-103677559|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-103677559} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:28:34,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:28:34,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In87378247 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In87378247 256) 0))) (or (and (= ~z$w_buff0_used~0_In87378247 |P2Thread1of1ForFork2_#t~ite17_Out87378247|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out87378247| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out87378247|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:28:34,940 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd3~0_In-1266046541 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1266046541 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1266046541 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1266046541 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1266046541 |P2Thread1of1ForFork2_#t~ite18_Out-1266046541|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork2_#t~ite18_Out-1266046541| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1266046541} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1266046541, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1266046541|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:28:34,940 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1831161158 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1831161158 256)))) (or (and (= ~z$r_buff0_thd3~0_In-1831161158 |P2Thread1of1ForFork2_#t~ite19_Out-1831161158|) (or .cse0 .cse1)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-1831161158| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1831161158, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1831161158} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1831161158, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1831161158, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1831161158|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:28:34,940 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1129599191 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1129599191 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1129599191 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-1129599191 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out-1129599191| ~z$r_buff1_thd3~0_In-1129599191)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1129599191| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1129599191, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1129599191, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1129599191, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1129599191} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1129599191, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1129599191|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1129599191, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1129599191, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1129599191} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-70352383 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-70352383 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-70352383 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd2~0_In-70352383 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out-70352383| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite14_Out-70352383| ~z$r_buff1_thd2~0_In-70352383) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-70352383, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-70352383, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-70352383, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-70352383} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-70352383, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-70352383, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-70352383, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-70352383|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-70352383} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In1732436677 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1732436677 256)))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out1732436677| ~z~0_In1732436677) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out1732436677| ~z$w_buff1~0_In1732436677)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1732436677, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1732436677, ~z$w_buff1~0=~z$w_buff1~0_In1732436677, ~z~0=~z~0_In1732436677} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1732436677, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1732436677|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1732436677, ~z$w_buff1~0=~z$w_buff1~0_In1732436677, ~z~0=~z~0_In1732436677} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:28:34,941 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-311688709 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In-311688709 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite26_Out-311688709| ~z$w_buff0_used~0_In-311688709) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out-311688709| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-311688709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-311688709} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-311688709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-311688709, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-311688709|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:28:34,942 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-996875936 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-996875936 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-996875936 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-996875936 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite27_Out-996875936| 0)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-996875936 |ULTIMATE.start_main_#t~ite27_Out-996875936|) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-996875936, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-996875936, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-996875936, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-996875936} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-996875936, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-996875936, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-996875936, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-996875936, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-996875936|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:28:34,942 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In453638749 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In453638749 256) 0))) (or (and (= ~z$r_buff0_thd0~0_In453638749 |ULTIMATE.start_main_#t~ite28_Out453638749|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out453638749|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In453638749, ~z$w_buff0_used~0=~z$w_buff0_used~0_In453638749} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In453638749, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out453638749|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In453638749} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:28:34,942 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In1567520197 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In1567520197 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In1567520197 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1567520197 256)))) (or (and (= ~z$r_buff1_thd0~0_In1567520197 |ULTIMATE.start_main_#t~ite29_Out1567520197|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out1567520197| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1567520197, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1567520197, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1567520197, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1567520197} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1567520197, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1567520197|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1567520197, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1567520197, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1567520197} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:28:34,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:28:34,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:28:34,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:28:34,998 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:28:34 BasicIcfg [2019-12-07 16:28:34,998 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:28:34,999 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:28:34,999 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:28:34,999 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:28:34,999 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:26:20" (3/4) ... [2019-12-07 16:28:35,001 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:28:35,001 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23|) |v_ULTIMATE.start_main_~#t1970~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1970~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1970~0.base_23|) (= 0 v_~z$flush_delayed~0_41) (= 0 |v_ULTIMATE.start_main_~#t1970~0.offset_17|) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23|) 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23| 1) |v_#valid_64|) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_~#t1970~0.base=|v_ULTIMATE.start_main_~#t1970~0.base_23|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_~#t1970~0.offset=|v_ULTIMATE.start_main_~#t1970~0.offset_17|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_20|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1970~0.base, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_~#t1970~0.offset, ULTIMATE.start_main_~#t1971~0.base, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1972~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:28:35,001 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11|) |v_ULTIMATE.start_main_~#t1971~0.offset_10| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1971~0.offset_10|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1971~0.base_11|) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1971~0.base_11| 4) |v_#length_17|) (not (= 0 |v_ULTIMATE.start_main_~#t1971~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1971~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:28:35,001 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:28:35,002 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1972~0.base_12|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12|) |v_ULTIMATE.start_main_~#t1972~0.offset_10| 2))) (not (= |v_ULTIMATE.start_main_~#t1972~0.base_12| 0)) (= 0 |v_ULTIMATE.start_main_~#t1972~0.offset_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1972~0.base_12| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1972~0.base] because there is no mapped edge [2019-12-07 16:28:35,002 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In2113920738 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In2113920738 256)))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out2113920738| ~z$w_buff0_used~0_In2113920738)) (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out2113920738| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2113920738, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2113920738} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out2113920738|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2113920738, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2113920738} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:28:35,003 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd1~0_In1437096939 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1437096939 256))) (.cse3 (= (mod ~z$r_buff0_thd1~0_In1437096939 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1437096939 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1437096939|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In1437096939 |P0Thread1of1ForFork0_#t~ite6_Out1437096939|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1437096939, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1437096939, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1437096939, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1437096939} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1437096939|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1437096939, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1437096939, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1437096939, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1437096939} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:28:35,003 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1979958401 256))) (.cse0 (= ~z$r_buff0_thd1~0_In1979958401 ~z$r_buff0_thd1~0_Out1979958401)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In1979958401 256) 0))) (or (and .cse0 .cse1) (and (= 0 ~z$r_buff0_thd1~0_Out1979958401) (not .cse2) (not .cse1)) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1979958401, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1979958401} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1979958401, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1979958401|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1979958401} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:28:35,003 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In265075884 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In265075884 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd1~0_In265075884 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In265075884 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite8_Out265075884| ~z$r_buff1_thd1~0_In265075884)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out265075884| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In265075884, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In265075884, ~z$w_buff1_used~0=~z$w_buff1_used~0_In265075884, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In265075884} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In265075884, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out265075884|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In265075884, ~z$w_buff1_used~0=~z$w_buff1_used~0_In265075884, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In265075884} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:28:35,003 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:28:35,004 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-37073091 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-37073091 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite9_Out-37073091| ~z~0_In-37073091) (or .cse0 .cse1)) (and (= ~z$w_buff1~0_In-37073091 |P1Thread1of1ForFork1_#t~ite9_Out-37073091|) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-37073091, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-37073091, ~z$w_buff1~0=~z$w_buff1~0_In-37073091, ~z~0=~z~0_In-37073091} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-37073091|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-37073091, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-37073091, ~z$w_buff1~0=~z$w_buff1~0_In-37073091, ~z~0=~z~0_In-37073091} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:28:35,004 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:28:35,004 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd2~0_In1100538828 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1100538828 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out1100538828| 0)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out1100538828| ~z$w_buff0_used~0_In1100538828)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1100538828} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1100538828, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1100538828|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1100538828} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:28:35,005 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In835114967 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In835114967 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out835114967| ~z~0_In835114967)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out835114967| ~z$w_buff1~0_In835114967) (not .cse0) (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In835114967, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835114967, ~z$w_buff1~0=~z$w_buff1~0_In835114967, ~z~0=~z~0_In835114967} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out835114967|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In835114967, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835114967, ~z$w_buff1~0=~z$w_buff1~0_In835114967, ~z~0=~z~0_In835114967} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:28:35,005 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In-182628863 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd2~0_In-182628863 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd2~0_In-182628863 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-182628863 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-182628863 |P1Thread1of1ForFork1_#t~ite12_Out-182628863|)) (and (= |P1Thread1of1ForFork1_#t~ite12_Out-182628863| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-182628863, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-182628863, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-182628863, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-182628863} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-182628863, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-182628863, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-182628863, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-182628863|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-182628863} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:28:35,005 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-103677559 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd2~0_In-103677559 256) 0))) (or (and (= ~z$r_buff0_thd2~0_In-103677559 |P1Thread1of1ForFork1_#t~ite13_Out-103677559|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-103677559|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-103677559, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-103677559} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-103677559, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-103677559|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-103677559} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:28:35,005 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:28:35,005 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In87378247 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In87378247 256) 0))) (or (and (= ~z$w_buff0_used~0_In87378247 |P2Thread1of1ForFork2_#t~ite17_Out87378247|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out87378247| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In87378247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In87378247, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out87378247|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd3~0_In-1266046541 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1266046541 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1266046541 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1266046541 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1266046541 |P2Thread1of1ForFork2_#t~ite18_Out-1266046541|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork2_#t~ite18_Out-1266046541| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1266046541} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1266046541, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1266046541, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1266046541, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1266046541, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1266046541|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1831161158 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1831161158 256)))) (or (and (= ~z$r_buff0_thd3~0_In-1831161158 |P2Thread1of1ForFork2_#t~ite19_Out-1831161158|) (or .cse0 .cse1)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-1831161158| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1831161158, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1831161158} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1831161158, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1831161158, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1831161158|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1129599191 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1129599191 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1129599191 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-1129599191 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out-1129599191| ~z$r_buff1_thd3~0_In-1129599191)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1129599191| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1129599191, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1129599191, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1129599191, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1129599191} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1129599191, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1129599191|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1129599191, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1129599191, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1129599191} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-70352383 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-70352383 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-70352383 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd2~0_In-70352383 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out-70352383| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite14_Out-70352383| ~z$r_buff1_thd2~0_In-70352383) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-70352383, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-70352383, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-70352383, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-70352383} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-70352383, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-70352383, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-70352383, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-70352383|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-70352383} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:28:35,006 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:28:35,007 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:28:35,007 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In1732436677 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1732436677 256)))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out1732436677| ~z~0_In1732436677) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out1732436677| ~z$w_buff1~0_In1732436677)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1732436677, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1732436677, ~z$w_buff1~0=~z$w_buff1~0_In1732436677, ~z~0=~z~0_In1732436677} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1732436677, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1732436677|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1732436677, ~z$w_buff1~0=~z$w_buff1~0_In1732436677, ~z~0=~z~0_In1732436677} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:28:35,007 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:28:35,007 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-311688709 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In-311688709 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite26_Out-311688709| ~z$w_buff0_used~0_In-311688709) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out-311688709| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-311688709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-311688709} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-311688709, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-311688709, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-311688709|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:28:35,007 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-996875936 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-996875936 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-996875936 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-996875936 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite27_Out-996875936| 0)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-996875936 |ULTIMATE.start_main_#t~ite27_Out-996875936|) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-996875936, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-996875936, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-996875936, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-996875936} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-996875936, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-996875936, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-996875936, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-996875936, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-996875936|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:28:35,008 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In453638749 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In453638749 256) 0))) (or (and (= ~z$r_buff0_thd0~0_In453638749 |ULTIMATE.start_main_#t~ite28_Out453638749|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out453638749|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In453638749, ~z$w_buff0_used~0=~z$w_buff0_used~0_In453638749} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In453638749, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out453638749|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In453638749} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:28:35,008 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In1567520197 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In1567520197 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In1567520197 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1567520197 256)))) (or (and (= ~z$r_buff1_thd0~0_In1567520197 |ULTIMATE.start_main_#t~ite29_Out1567520197|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out1567520197| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1567520197, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1567520197, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1567520197, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1567520197} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1567520197, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1567520197|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1567520197, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1567520197, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1567520197} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:28:35,010 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:28:35,011 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:28:35,011 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:28:35,072 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_45a7b5a9-789a-4933-960c-a83396574887/bin/utaipan/witness.graphml [2019-12-07 16:28:35,072 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:28:35,074 INFO L168 Benchmark]: Toolchain (without parser) took 135446.17 ms. Allocated memory was 1.0 GB in the beginning and 8.6 GB in the end (delta: 7.6 GB). Free memory was 937.1 MB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,074 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:28:35,075 INFO L168 Benchmark]: CACSL2BoogieTranslator took 387.43 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -135.6 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,075 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.88 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,075 INFO L168 Benchmark]: Boogie Preprocessor took 26.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:28:35,075 INFO L168 Benchmark]: RCFGBuilder took 412.98 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,076 INFO L168 Benchmark]: TraceAbstraction took 134500.23 ms. Allocated memory was 1.1 GB in the beginning and 8.6 GB in the end (delta: 7.5 GB). Free memory was 1.0 GB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,076 INFO L168 Benchmark]: Witness Printer took 74.02 ms. Allocated memory is still 8.6 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 11.5 GB. [2019-12-07 16:28:35,078 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 387.43 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -135.6 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.88 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 412.98 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 134500.23 ms. Allocated memory was 1.1 GB in the beginning and 8.6 GB in the end (delta: 7.5 GB). Free memory was 1.0 GB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. * Witness Printer took 74.02 ms. Allocated memory is still 8.6 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1970, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1971, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1972, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 134.3s, OverallIterations: 28, TraceHistogramMax: 1, AutomataDifference: 27.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4890 SDtfs, 7011 SDslu, 17244 SDs, 0 SdLazy, 12363 SolverSat, 542 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 466 GetRequests, 47 SyntacticMatches, 30 SemanticMatches, 389 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2847 ImplicationChecksByTransitivity, 4.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=245714occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 85.7s AutomataMinimizationTime, 27 MinimizatonAttempts, 498585 StatesRemovedByMinimization, 25 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.3s InterpolantComputationTime, 1376 NumberOfCodeBlocks, 1376 NumberOfCodeBlocksAsserted, 28 NumberOfCheckSat, 1281 ConstructedInterpolants, 0 QuantifiedInterpolants, 464725 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 27 InterpolantComputations, 27 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...