./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1cab4ceea0126be7a5379a9e32896660842c307a ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 15:07:02,240 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 15:07:02,242 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 15:07:02,249 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 15:07:02,249 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 15:07:02,250 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 15:07:02,251 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 15:07:02,252 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 15:07:02,253 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 15:07:02,254 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 15:07:02,255 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 15:07:02,255 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 15:07:02,256 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 15:07:02,256 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 15:07:02,257 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 15:07:02,258 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 15:07:02,258 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 15:07:02,259 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 15:07:02,260 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 15:07:02,262 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 15:07:02,263 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 15:07:02,264 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 15:07:02,264 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 15:07:02,265 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 15:07:02,267 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 15:07:02,267 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 15:07:02,267 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 15:07:02,267 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 15:07:02,268 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 15:07:02,268 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 15:07:02,268 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 15:07:02,269 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 15:07:02,269 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 15:07:02,270 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 15:07:02,270 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 15:07:02,270 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 15:07:02,271 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 15:07:02,271 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 15:07:02,271 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 15:07:02,271 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 15:07:02,272 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 15:07:02,272 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 15:07:02,282 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 15:07:02,282 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 15:07:02,283 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 15:07:02,283 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 15:07:02,283 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 15:07:02,284 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 15:07:02,284 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 15:07:02,284 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 15:07:02,284 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 15:07:02,284 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 15:07:02,284 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 15:07:02,285 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 15:07:02,286 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 15:07:02,286 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:07:02,286 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 15:07:02,287 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1cab4ceea0126be7a5379a9e32896660842c307a [2019-12-07 15:07:02,390 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 15:07:02,397 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 15:07:02,399 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 15:07:02,400 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 15:07:02,400 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 15:07:02,401 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i [2019-12-07 15:07:02,437 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/data/48a77d186/8245f4eec7834358b0a2480558de22d0/FLAGeb6e2cab2 [2019-12-07 15:07:02,954 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 15:07:02,954 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i [2019-12-07 15:07:02,967 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/data/48a77d186/8245f4eec7834358b0a2480558de22d0/FLAGeb6e2cab2 [2019-12-07 15:07:03,470 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/data/48a77d186/8245f4eec7834358b0a2480558de22d0 [2019-12-07 15:07:03,472 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 15:07:03,473 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 15:07:03,474 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 15:07:03,474 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 15:07:03,477 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 15:07:03,478 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,480 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27a7eda1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03, skipping insertion in model container [2019-12-07 15:07:03,480 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,485 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 15:07:03,516 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 15:07:03,764 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:07:03,772 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 15:07:03,815 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:07:03,863 INFO L208 MainTranslator]: Completed translation [2019-12-07 15:07:03,864 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03 WrapperNode [2019-12-07 15:07:03,864 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 15:07:03,864 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 15:07:03,864 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 15:07:03,865 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 15:07:03,870 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,885 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,909 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 15:07:03,909 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 15:07:03,909 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 15:07:03,909 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 15:07:03,916 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,917 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,920 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,920 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,928 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,931 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,933 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... [2019-12-07 15:07:03,937 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 15:07:03,937 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 15:07:03,937 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 15:07:03,937 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 15:07:03,938 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:07:03,978 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 15:07:03,979 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 15:07:03,979 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 15:07:03,979 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 15:07:03,979 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 15:07:03,979 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 15:07:03,981 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 15:07:04,340 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 15:07:04,340 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 15:07:04,341 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:04 BoogieIcfgContainer [2019-12-07 15:07:04,341 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 15:07:04,342 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 15:07:04,342 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 15:07:04,344 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 15:07:04,344 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 03:07:03" (1/3) ... [2019-12-07 15:07:04,345 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1fe87ad3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:07:04, skipping insertion in model container [2019-12-07 15:07:04,345 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:03" (2/3) ... [2019-12-07 15:07:04,345 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1fe87ad3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:07:04, skipping insertion in model container [2019-12-07 15:07:04,345 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:04" (3/3) ... [2019-12-07 15:07:04,346 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_rmo.opt.i [2019-12-07 15:07:04,353 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 15:07:04,353 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 15:07:04,358 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 15:07:04,359 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,383 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,384 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,384 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,384 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,384 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,384 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,385 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,386 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,387 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,388 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,389 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,390 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,391 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,392 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,393 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,394 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,395 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,396 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,396 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,396 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,396 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:04,407 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 15:07:04,419 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 15:07:04,420 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 15:07:04,420 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 15:07:04,420 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 15:07:04,420 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 15:07:04,420 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 15:07:04,420 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 15:07:04,420 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 15:07:04,431 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 15:07:04,432 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 15:07:04,486 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 15:07:04,486 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:07:04,496 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:07:04,511 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 15:07:04,547 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 15:07:04,547 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:07:04,553 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:07:04,568 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 15:07:04,569 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 15:07:07,373 WARN L192 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 15:07:07,461 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 15:07:07,461 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 15:07:07,463 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 15:07:22,907 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 15:07:22,908 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 15:07:22,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 15:07:22,913 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:22,913 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 15:07:22,914 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:22,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:22,917 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 15:07:22,923 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:07:22,923 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255888635] [2019-12-07 15:07:22,923 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:23,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:23,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:23,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255888635] [2019-12-07 15:07:23,069 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:23,069 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 15:07:23,069 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243740428] [2019-12-07 15:07:23,072 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:07:23,072 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:07:23,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:07:23,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:07:23,083 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 15:07:23,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:23,793 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 15:07:23,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:07:23,794 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 15:07:23,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:24,555 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 15:07:24,556 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 15:07:24,557 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:07:29,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 15:07:30,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 15:07:30,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 15:07:31,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 15:07:31,371 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 15:07:31,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:31,372 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 15:07:31,372 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:07:31,372 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 15:07:31,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 15:07:31,376 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:31,376 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:31,376 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:31,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:31,377 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 15:07:31,377 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:07:31,377 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996077502] [2019-12-07 15:07:31,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:31,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:31,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:31,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996077502] [2019-12-07 15:07:31,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:31,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:07:31,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390705548] [2019-12-07 15:07:31,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:07:31,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:07:31,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:07:31,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:07:31,449 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 15:07:32,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:32,371 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 15:07:32,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:07:32,371 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 15:07:32,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:33,208 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 15:07:33,209 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 15:07:33,209 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:07:39,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 15:07:41,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 15:07:41,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 15:07:42,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 15:07:42,181 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 15:07:42,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:42,181 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 15:07:42,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:07:42,181 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 15:07:42,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:07:42,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:42,185 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:42,185 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:42,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:42,186 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 15:07:42,186 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:07:42,186 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203504406] [2019-12-07 15:07:42,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:42,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:42,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:42,232 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203504406] [2019-12-07 15:07:42,232 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:42,232 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:07:42,233 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469335544] [2019-12-07 15:07:42,233 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:07:42,233 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:07:42,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:07:42,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:07:42,234 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 15:07:43,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:43,400 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 15:07:43,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:07:43,400 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:07:43,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:44,536 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 15:07:44,536 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 15:07:44,536 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:07:51,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 15:07:54,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 15:07:54,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 15:07:55,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 15:07:55,431 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 15:07:55,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:55,432 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 15:07:55,432 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:07:55,432 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 15:07:55,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:07:55,434 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:55,434 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:55,434 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:55,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:55,434 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 15:07:55,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:07:55,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007668609] [2019-12-07 15:07:55,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:55,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:55,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:55,476 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007668609] [2019-12-07 15:07:55,476 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:55,476 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:07:55,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955969290] [2019-12-07 15:07:55,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:07:55,477 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:07:55,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:07:55,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:07:55,477 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 15:07:56,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:56,655 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 15:07:56,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:07:56,656 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:07:56,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:57,276 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 15:07:57,277 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 15:07:57,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:08:02,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 15:08:08,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 15:08:08,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 15:08:09,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 15:08:09,382 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 15:08:09,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:09,382 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 15:08:09,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:08:09,382 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 15:08:09,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:08:09,408 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:09,408 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:09,409 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:09,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:09,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 15:08:09,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:08:09,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264024325] [2019-12-07 15:08:09,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:09,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:09,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:09,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264024325] [2019-12-07 15:08:09,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:08:09,456 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:08:09,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893501070] [2019-12-07 15:08:09,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:08:09,456 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:08:09,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:08:09,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:08:09,456 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 15:08:11,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:11,025 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 15:08:11,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:08:11,026 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:08:11,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:12,339 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 15:08:12,339 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 15:08:12,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:08:18,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 15:08:22,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 15:08:22,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 15:08:23,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 15:08:23,089 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 15:08:23,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:23,089 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 15:08:23,089 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:08:23,089 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 15:08:23,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:08:23,103 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:23,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:23,104 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:23,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:23,104 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 15:08:23,104 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:08:23,104 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615364358] [2019-12-07 15:08:23,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:23,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:23,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:23,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615364358] [2019-12-07 15:08:23,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:08:23,151 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:08:23,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154466053] [2019-12-07 15:08:23,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:08:23,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:08:23,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:08:23,152 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:08:23,152 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 5 states. [2019-12-07 15:08:27,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:27,799 INFO L93 Difference]: Finished difference Result 326371 states and 1320375 transitions. [2019-12-07 15:08:27,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:08:27,800 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:08:27,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:28,583 INFO L225 Difference]: With dead ends: 326371 [2019-12-07 15:08:28,583 INFO L226 Difference]: Without dead ends: 326224 [2019-12-07 15:08:28,583 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:08:34,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326224 states. [2019-12-07 15:08:38,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326224 to 227768. [2019-12-07 15:08:38,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227768 states. [2019-12-07 15:08:39,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227768 states to 227768 states and 938858 transitions. [2019-12-07 15:08:39,232 INFO L78 Accepts]: Start accepts. Automaton has 227768 states and 938858 transitions. Word has length 19 [2019-12-07 15:08:39,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:39,232 INFO L462 AbstractCegarLoop]: Abstraction has 227768 states and 938858 transitions. [2019-12-07 15:08:39,232 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:08:39,232 INFO L276 IsEmpty]: Start isEmpty. Operand 227768 states and 938858 transitions. [2019-12-07 15:08:39,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:08:39,247 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:39,247 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:39,248 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:39,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:39,248 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 15:08:39,248 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:08:39,248 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148847131] [2019-12-07 15:08:39,248 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:39,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:39,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:39,287 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148847131] [2019-12-07 15:08:39,287 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:08:39,287 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:08:39,287 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049875365] [2019-12-07 15:08:39,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:08:39,287 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:08:39,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:08:39,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:08:39,288 INFO L87 Difference]: Start difference. First operand 227768 states and 938858 transitions. Second operand 5 states. [2019-12-07 15:08:41,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:41,317 INFO L93 Difference]: Finished difference Result 330156 states and 1338658 transitions. [2019-12-07 15:08:41,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:08:41,318 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:08:41,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:42,750 INFO L225 Difference]: With dead ends: 330156 [2019-12-07 15:08:42,750 INFO L226 Difference]: Without dead ends: 330093 [2019-12-07 15:08:42,750 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:08:49,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330093 states. [2019-12-07 15:08:52,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330093 to 245714. [2019-12-07 15:08:52,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245714 states. [2019-12-07 15:08:53,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245714 states to 245714 states and 1011495 transitions. [2019-12-07 15:08:53,648 INFO L78 Accepts]: Start accepts. Automaton has 245714 states and 1011495 transitions. Word has length 19 [2019-12-07 15:08:53,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:53,648 INFO L462 AbstractCegarLoop]: Abstraction has 245714 states and 1011495 transitions. [2019-12-07 15:08:53,648 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:08:53,648 INFO L276 IsEmpty]: Start isEmpty. Operand 245714 states and 1011495 transitions. [2019-12-07 15:08:53,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:08:53,714 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:53,714 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:53,714 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:53,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:53,714 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 15:08:53,714 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:08:53,714 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431528867] [2019-12-07 15:08:53,714 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:53,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:53,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:53,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431528867] [2019-12-07 15:08:53,770 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:08:53,770 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:08:53,770 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152817331] [2019-12-07 15:08:53,770 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:08:53,770 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:08:53,771 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:08:53,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:08:53,771 INFO L87 Difference]: Start difference. First operand 245714 states and 1011495 transitions. Second operand 6 states. [2019-12-07 15:08:56,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:56,082 INFO L93 Difference]: Finished difference Result 293437 states and 1194200 transitions. [2019-12-07 15:08:56,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 15:08:56,083 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 15:08:56,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:56,862 INFO L225 Difference]: With dead ends: 293437 [2019-12-07 15:08:56,862 INFO L226 Difference]: Without dead ends: 293290 [2019-12-07 15:08:56,863 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:09:05,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293290 states. [2019-12-07 15:09:08,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293290 to 203000. [2019-12-07 15:09:08,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203000 states. [2019-12-07 15:09:09,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203000 states to 203000 states and 839373 transitions. [2019-12-07 15:09:09,684 INFO L78 Accepts]: Start accepts. Automaton has 203000 states and 839373 transitions. Word has length 25 [2019-12-07 15:09:09,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:09,685 INFO L462 AbstractCegarLoop]: Abstraction has 203000 states and 839373 transitions. [2019-12-07 15:09:09,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:09:09,685 INFO L276 IsEmpty]: Start isEmpty. Operand 203000 states and 839373 transitions. [2019-12-07 15:09:09,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:09:09,760 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:09,760 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:09,760 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:09,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:09,760 INFO L82 PathProgramCache]: Analyzing trace with hash -826573092, now seen corresponding path program 1 times [2019-12-07 15:09:09,760 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:09,760 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180837844] [2019-12-07 15:09:09,760 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:09,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:09,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:09,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180837844] [2019-12-07 15:09:09,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:09,793 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:09:09,793 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430360750] [2019-12-07 15:09:09,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:09:09,793 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:09,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:09:09,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:09,794 INFO L87 Difference]: Start difference. First operand 203000 states and 839373 transitions. Second operand 3 states. [2019-12-07 15:09:09,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:09,912 INFO L93 Difference]: Finished difference Result 41735 states and 134919 transitions. [2019-12-07 15:09:09,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:09:09,912 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:09:09,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:09,969 INFO L225 Difference]: With dead ends: 41735 [2019-12-07 15:09:09,970 INFO L226 Difference]: Without dead ends: 41735 [2019-12-07 15:09:09,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:10,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41735 states. [2019-12-07 15:09:10,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41735 to 41735. [2019-12-07 15:09:10,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41735 states. [2019-12-07 15:09:10,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41735 states to 41735 states and 134919 transitions. [2019-12-07 15:09:10,643 INFO L78 Accepts]: Start accepts. Automaton has 41735 states and 134919 transitions. Word has length 27 [2019-12-07 15:09:10,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:10,643 INFO L462 AbstractCegarLoop]: Abstraction has 41735 states and 134919 transitions. [2019-12-07 15:09:10,643 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:09:10,643 INFO L276 IsEmpty]: Start isEmpty. Operand 41735 states and 134919 transitions. [2019-12-07 15:09:10,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 15:09:10,662 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:10,662 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:10,662 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:10,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:10,663 INFO L82 PathProgramCache]: Analyzing trace with hash -181038669, now seen corresponding path program 1 times [2019-12-07 15:09:10,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:10,663 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151445797] [2019-12-07 15:09:10,663 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:10,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:10,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:10,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151445797] [2019-12-07 15:09:10,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:10,698 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:09:10,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679271405] [2019-12-07 15:09:10,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:09:10,699 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:10,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:09:10,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:09:10,699 INFO L87 Difference]: Start difference. First operand 41735 states and 134919 transitions. Second operand 4 states. [2019-12-07 15:09:10,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:10,735 INFO L93 Difference]: Finished difference Result 7949 states and 21432 transitions. [2019-12-07 15:09:10,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 15:09:10,735 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 15:09:10,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:10,744 INFO L225 Difference]: With dead ends: 7949 [2019-12-07 15:09:10,745 INFO L226 Difference]: Without dead ends: 7949 [2019-12-07 15:09:10,745 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:09:10,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7949 states. [2019-12-07 15:09:10,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7949 to 7837. [2019-12-07 15:09:10,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7837 states. [2019-12-07 15:09:10,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7837 states to 7837 states and 21112 transitions. [2019-12-07 15:09:10,835 INFO L78 Accepts]: Start accepts. Automaton has 7837 states and 21112 transitions. Word has length 39 [2019-12-07 15:09:10,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:10,835 INFO L462 AbstractCegarLoop]: Abstraction has 7837 states and 21112 transitions. [2019-12-07 15:09:10,835 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:09:10,835 INFO L276 IsEmpty]: Start isEmpty. Operand 7837 states and 21112 transitions. [2019-12-07 15:09:10,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 15:09:10,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:10,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:10,842 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:10,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:10,842 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 15:09:10,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:10,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032634216] [2019-12-07 15:09:10,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:10,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:10,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:10,889 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032634216] [2019-12-07 15:09:10,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:10,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:09:10,890 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512615098] [2019-12-07 15:09:10,890 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:09:10,890 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:10,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:09:10,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:09:10,890 INFO L87 Difference]: Start difference. First operand 7837 states and 21112 transitions. Second operand 5 states. [2019-12-07 15:09:10,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:10,913 INFO L93 Difference]: Finished difference Result 5331 states and 15289 transitions. [2019-12-07 15:09:10,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:09:10,914 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 15:09:10,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:10,918 INFO L225 Difference]: With dead ends: 5331 [2019-12-07 15:09:10,918 INFO L226 Difference]: Without dead ends: 5331 [2019-12-07 15:09:10,919 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:09:10,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2019-12-07 15:09:10,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 4967. [2019-12-07 15:09:10,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4967 states. [2019-12-07 15:09:10,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4967 states to 4967 states and 14305 transitions. [2019-12-07 15:09:10,979 INFO L78 Accepts]: Start accepts. Automaton has 4967 states and 14305 transitions. Word has length 51 [2019-12-07 15:09:10,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:10,979 INFO L462 AbstractCegarLoop]: Abstraction has 4967 states and 14305 transitions. [2019-12-07 15:09:10,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:09:10,979 INFO L276 IsEmpty]: Start isEmpty. Operand 4967 states and 14305 transitions. [2019-12-07 15:09:10,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:09:10,982 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:10,983 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:10,983 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:10,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:10,983 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 15:09:10,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:10,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879687901] [2019-12-07 15:09:10,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:10,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:11,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:11,042 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879687901] [2019-12-07 15:09:11,042 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:11,042 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:09:11,042 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061437525] [2019-12-07 15:09:11,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:09:11,042 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:11,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:09:11,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:09:11,043 INFO L87 Difference]: Start difference. First operand 4967 states and 14305 transitions. Second operand 5 states. [2019-12-07 15:09:11,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:11,228 INFO L93 Difference]: Finished difference Result 7558 states and 21570 transitions. [2019-12-07 15:09:11,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:09:11,228 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 15:09:11,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:11,235 INFO L225 Difference]: With dead ends: 7558 [2019-12-07 15:09:11,235 INFO L226 Difference]: Without dead ends: 7558 [2019-12-07 15:09:11,235 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:09:11,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7558 states. [2019-12-07 15:09:11,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7558 to 6659. [2019-12-07 15:09:11,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6659 states. [2019-12-07 15:09:11,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6659 states to 6659 states and 19091 transitions. [2019-12-07 15:09:11,317 INFO L78 Accepts]: Start accepts. Automaton has 6659 states and 19091 transitions. Word has length 65 [2019-12-07 15:09:11,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:11,317 INFO L462 AbstractCegarLoop]: Abstraction has 6659 states and 19091 transitions. [2019-12-07 15:09:11,318 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:09:11,318 INFO L276 IsEmpty]: Start isEmpty. Operand 6659 states and 19091 transitions. [2019-12-07 15:09:11,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:09:11,322 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:11,322 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:11,323 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:11,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:11,323 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 15:09:11,323 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:11,323 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651405555] [2019-12-07 15:09:11,323 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:11,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:11,690 WARN L192 SmtUtils]: Spent 318.00 ms on a formula simplification. DAG size of input: 15 DAG size of output: 10 [2019-12-07 15:09:11,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:11,699 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651405555] [2019-12-07 15:09:11,699 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:11,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:09:11,700 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576236375] [2019-12-07 15:09:11,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:09:11,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:11,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:09:11,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:11,700 INFO L87 Difference]: Start difference. First operand 6659 states and 19091 transitions. Second operand 3 states. [2019-12-07 15:09:11,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:11,721 INFO L93 Difference]: Finished difference Result 6289 states and 17750 transitions. [2019-12-07 15:09:11,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:09:11,721 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 15:09:11,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:11,726 INFO L225 Difference]: With dead ends: 6289 [2019-12-07 15:09:11,726 INFO L226 Difference]: Without dead ends: 6289 [2019-12-07 15:09:11,727 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:11,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6289 states. [2019-12-07 15:09:11,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6289 to 6133. [2019-12-07 15:09:11,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6133 states. [2019-12-07 15:09:11,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6133 states to 6133 states and 17320 transitions. [2019-12-07 15:09:11,795 INFO L78 Accepts]: Start accepts. Automaton has 6133 states and 17320 transitions. Word has length 65 [2019-12-07 15:09:11,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:11,795 INFO L462 AbstractCegarLoop]: Abstraction has 6133 states and 17320 transitions. [2019-12-07 15:09:11,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:09:11,796 INFO L276 IsEmpty]: Start isEmpty. Operand 6133 states and 17320 transitions. [2019-12-07 15:09:11,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:11,800 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:11,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:11,800 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:11,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:11,800 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 15:09:11,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:11,800 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064382985] [2019-12-07 15:09:11,800 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:11,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:11,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:11,869 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064382985] [2019-12-07 15:09:11,869 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:11,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:09:11,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463891619] [2019-12-07 15:09:11,870 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:09:11,870 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:11,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:09:11,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:09:11,871 INFO L87 Difference]: Start difference. First operand 6133 states and 17320 transitions. Second operand 5 states. [2019-12-07 15:09:12,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:12,079 INFO L93 Difference]: Finished difference Result 8712 states and 24399 transitions. [2019-12-07 15:09:12,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:09:12,079 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 15:09:12,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:12,086 INFO L225 Difference]: With dead ends: 8712 [2019-12-07 15:09:12,086 INFO L226 Difference]: Without dead ends: 8712 [2019-12-07 15:09:12,086 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:09:12,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8712 states. [2019-12-07 15:09:12,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8712 to 6784. [2019-12-07 15:09:12,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6784 states. [2019-12-07 15:09:12,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6784 states to 6784 states and 19209 transitions. [2019-12-07 15:09:12,173 INFO L78 Accepts]: Start accepts. Automaton has 6784 states and 19209 transitions. Word has length 66 [2019-12-07 15:09:12,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:12,173 INFO L462 AbstractCegarLoop]: Abstraction has 6784 states and 19209 transitions. [2019-12-07 15:09:12,173 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:09:12,173 INFO L276 IsEmpty]: Start isEmpty. Operand 6784 states and 19209 transitions. [2019-12-07 15:09:12,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:12,178 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:12,178 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:12,178 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:12,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:12,178 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 15:09:12,179 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:12,179 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293269784] [2019-12-07 15:09:12,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:12,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:12,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:12,251 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293269784] [2019-12-07 15:09:12,252 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:12,252 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:09:12,252 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005025484] [2019-12-07 15:09:12,252 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:09:12,252 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:12,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:09:12,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:09:12,252 INFO L87 Difference]: Start difference. First operand 6784 states and 19209 transitions. Second operand 6 states. [2019-12-07 15:09:12,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:12,304 INFO L93 Difference]: Finished difference Result 11958 states and 33833 transitions. [2019-12-07 15:09:12,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:09:12,304 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 15:09:12,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:12,310 INFO L225 Difference]: With dead ends: 11958 [2019-12-07 15:09:12,310 INFO L226 Difference]: Without dead ends: 6415 [2019-12-07 15:09:12,310 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:09:12,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6415 states. [2019-12-07 15:09:12,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6415 to 6415. [2019-12-07 15:09:12,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6415 states. [2019-12-07 15:09:12,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6415 states to 6415 states and 18105 transitions. [2019-12-07 15:09:12,389 INFO L78 Accepts]: Start accepts. Automaton has 6415 states and 18105 transitions. Word has length 66 [2019-12-07 15:09:12,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:12,389 INFO L462 AbstractCegarLoop]: Abstraction has 6415 states and 18105 transitions. [2019-12-07 15:09:12,390 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:09:12,390 INFO L276 IsEmpty]: Start isEmpty. Operand 6415 states and 18105 transitions. [2019-12-07 15:09:12,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:12,394 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:12,394 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:12,394 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:12,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:12,394 INFO L82 PathProgramCache]: Analyzing trace with hash -806353662, now seen corresponding path program 3 times [2019-12-07 15:09:12,394 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:12,395 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053550329] [2019-12-07 15:09:12,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:12,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:12,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:12,460 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053550329] [2019-12-07 15:09:12,460 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:12,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 15:09:12,460 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592609965] [2019-12-07 15:09:12,461 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:09:12,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:12,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:09:12,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:09:12,461 INFO L87 Difference]: Start difference. First operand 6415 states and 18105 transitions. Second operand 7 states. [2019-12-07 15:09:12,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:12,820 INFO L93 Difference]: Finished difference Result 9213 states and 25620 transitions. [2019-12-07 15:09:12,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:09:12,820 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 15:09:12,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:12,827 INFO L225 Difference]: With dead ends: 9213 [2019-12-07 15:09:12,827 INFO L226 Difference]: Without dead ends: 9213 [2019-12-07 15:09:12,828 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:09:12,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9213 states. [2019-12-07 15:09:12,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9213 to 6830. [2019-12-07 15:09:12,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6830 states. [2019-12-07 15:09:12,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6830 states to 6830 states and 19261 transitions. [2019-12-07 15:09:12,920 INFO L78 Accepts]: Start accepts. Automaton has 6830 states and 19261 transitions. Word has length 66 [2019-12-07 15:09:12,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:12,921 INFO L462 AbstractCegarLoop]: Abstraction has 6830 states and 19261 transitions. [2019-12-07 15:09:12,921 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:09:12,921 INFO L276 IsEmpty]: Start isEmpty. Operand 6830 states and 19261 transitions. [2019-12-07 15:09:12,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:12,926 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:12,926 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:12,926 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:12,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:12,926 INFO L82 PathProgramCache]: Analyzing trace with hash 1549059410, now seen corresponding path program 4 times [2019-12-07 15:09:12,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:12,926 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596893487] [2019-12-07 15:09:12,926 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:12,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:13,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:13,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596893487] [2019-12-07 15:09:13,022 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:13,022 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 15:09:13,022 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146280117] [2019-12-07 15:09:13,022 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 15:09:13,022 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:13,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 15:09:13,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:09:13,023 INFO L87 Difference]: Start difference. First operand 6830 states and 19261 transitions. Second operand 9 states. [2019-12-07 15:09:13,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:13,546 INFO L93 Difference]: Finished difference Result 11724 states and 32586 transitions. [2019-12-07 15:09:13,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:09:13,546 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 15:09:13,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:13,556 INFO L225 Difference]: With dead ends: 11724 [2019-12-07 15:09:13,556 INFO L226 Difference]: Without dead ends: 11724 [2019-12-07 15:09:13,556 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=160, Unknown=0, NotChecked=0, Total=210 [2019-12-07 15:09:13,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11724 states. [2019-12-07 15:09:13,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11724 to 7479. [2019-12-07 15:09:13,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7479 states. [2019-12-07 15:09:13,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7479 states to 7479 states and 21056 transitions. [2019-12-07 15:09:13,671 INFO L78 Accepts]: Start accepts. Automaton has 7479 states and 21056 transitions. Word has length 66 [2019-12-07 15:09:13,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:13,671 INFO L462 AbstractCegarLoop]: Abstraction has 7479 states and 21056 transitions. [2019-12-07 15:09:13,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 15:09:13,671 INFO L276 IsEmpty]: Start isEmpty. Operand 7479 states and 21056 transitions. [2019-12-07 15:09:13,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:13,677 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:13,677 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:13,677 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:13,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:13,677 INFO L82 PathProgramCache]: Analyzing trace with hash 479477378, now seen corresponding path program 5 times [2019-12-07 15:09:13,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:13,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725918979] [2019-12-07 15:09:13,678 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:13,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:13,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:13,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725918979] [2019-12-07 15:09:13,781 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:13,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 15:09:13,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257948220] [2019-12-07 15:09:13,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 15:09:13,781 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:13,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 15:09:13,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:09:13,781 INFO L87 Difference]: Start difference. First operand 7479 states and 21056 transitions. Second operand 10 states. [2019-12-07 15:09:14,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:14,672 INFO L93 Difference]: Finished difference Result 12163 states and 33776 transitions. [2019-12-07 15:09:14,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 15:09:14,672 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 15:09:14,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:14,685 INFO L225 Difference]: With dead ends: 12163 [2019-12-07 15:09:14,686 INFO L226 Difference]: Without dead ends: 12163 [2019-12-07 15:09:14,686 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2019-12-07 15:09:14,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12163 states. [2019-12-07 15:09:14,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12163 to 8091. [2019-12-07 15:09:14,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8091 states. [2019-12-07 15:09:14,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8091 states to 8091 states and 22798 transitions. [2019-12-07 15:09:14,811 INFO L78 Accepts]: Start accepts. Automaton has 8091 states and 22798 transitions. Word has length 66 [2019-12-07 15:09:14,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:14,811 INFO L462 AbstractCegarLoop]: Abstraction has 8091 states and 22798 transitions. [2019-12-07 15:09:14,811 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 15:09:14,811 INFO L276 IsEmpty]: Start isEmpty. Operand 8091 states and 22798 transitions. [2019-12-07 15:09:14,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:14,817 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:14,817 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:14,817 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:14,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:14,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1795321204, now seen corresponding path program 6 times [2019-12-07 15:09:14,818 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:14,818 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455552990] [2019-12-07 15:09:14,818 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:14,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:14,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:14,919 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455552990] [2019-12-07 15:09:14,919 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:14,919 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 15:09:14,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259179168] [2019-12-07 15:09:14,919 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 15:09:14,919 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:14,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 15:09:14,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:09:14,920 INFO L87 Difference]: Start difference. First operand 8091 states and 22798 transitions. Second operand 10 states. [2019-12-07 15:09:16,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:16,020 INFO L93 Difference]: Finished difference Result 12207 states and 33965 transitions. [2019-12-07 15:09:16,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 15:09:16,021 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 15:09:16,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:16,041 INFO L225 Difference]: With dead ends: 12207 [2019-12-07 15:09:16,041 INFO L226 Difference]: Without dead ends: 12207 [2019-12-07 15:09:16,042 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=148, Invalid=664, Unknown=0, NotChecked=0, Total=812 [2019-12-07 15:09:16,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12207 states. [2019-12-07 15:09:16,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12207 to 7521. [2019-12-07 15:09:16,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7521 states. [2019-12-07 15:09:16,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7521 states to 7521 states and 21207 transitions. [2019-12-07 15:09:16,453 INFO L78 Accepts]: Start accepts. Automaton has 7521 states and 21207 transitions. Word has length 66 [2019-12-07 15:09:16,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:16,453 INFO L462 AbstractCegarLoop]: Abstraction has 7521 states and 21207 transitions. [2019-12-07 15:09:16,453 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 15:09:16,453 INFO L276 IsEmpty]: Start isEmpty. Operand 7521 states and 21207 transitions. [2019-12-07 15:09:16,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:16,458 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:16,458 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:16,458 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:16,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:16,459 INFO L82 PathProgramCache]: Analyzing trace with hash 2091502336, now seen corresponding path program 7 times [2019-12-07 15:09:16,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:16,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940524464] [2019-12-07 15:09:16,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:16,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:16,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:16,557 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940524464] [2019-12-07 15:09:16,557 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:16,557 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 15:09:16,557 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [828864441] [2019-12-07 15:09:16,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 15:09:16,558 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:16,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 15:09:16,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:09:16,558 INFO L87 Difference]: Start difference. First operand 7521 states and 21207 transitions. Second operand 9 states. [2019-12-07 15:09:17,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:17,227 INFO L93 Difference]: Finished difference Result 12432 states and 34845 transitions. [2019-12-07 15:09:17,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 15:09:17,227 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 15:09:17,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:17,238 INFO L225 Difference]: With dead ends: 12432 [2019-12-07 15:09:17,238 INFO L226 Difference]: Without dead ends: 12432 [2019-12-07 15:09:17,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 10 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=284, Unknown=0, NotChecked=0, Total=380 [2019-12-07 15:09:17,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12432 states. [2019-12-07 15:09:17,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12432 to 7731. [2019-12-07 15:09:17,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7731 states. [2019-12-07 15:09:17,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7731 states to 7731 states and 21807 transitions. [2019-12-07 15:09:17,358 INFO L78 Accepts]: Start accepts. Automaton has 7731 states and 21807 transitions. Word has length 66 [2019-12-07 15:09:17,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:17,359 INFO L462 AbstractCegarLoop]: Abstraction has 7731 states and 21807 transitions. [2019-12-07 15:09:17,359 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 15:09:17,359 INFO L276 IsEmpty]: Start isEmpty. Operand 7731 states and 21807 transitions. [2019-12-07 15:09:17,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:09:17,364 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:17,365 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:17,365 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:17,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:17,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1951217226, now seen corresponding path program 8 times [2019-12-07 15:09:17,365 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:17,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407889703] [2019-12-07 15:09:17,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:17,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:17,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:17,396 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407889703] [2019-12-07 15:09:17,397 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:17,397 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:09:17,397 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286135433] [2019-12-07 15:09:17,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:09:17,397 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:17,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:09:17,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:17,397 INFO L87 Difference]: Start difference. First operand 7731 states and 21807 transitions. Second operand 3 states. [2019-12-07 15:09:17,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:17,441 INFO L93 Difference]: Finished difference Result 7730 states and 21805 transitions. [2019-12-07 15:09:17,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:09:17,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 15:09:17,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:17,450 INFO L225 Difference]: With dead ends: 7730 [2019-12-07 15:09:17,450 INFO L226 Difference]: Without dead ends: 7730 [2019-12-07 15:09:17,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:17,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7730 states. [2019-12-07 15:09:17,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7730 to 5129. [2019-12-07 15:09:17,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5129 states. [2019-12-07 15:09:17,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5129 states to 5129 states and 14540 transitions. [2019-12-07 15:09:17,534 INFO L78 Accepts]: Start accepts. Automaton has 5129 states and 14540 transitions. Word has length 66 [2019-12-07 15:09:17,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:17,534 INFO L462 AbstractCegarLoop]: Abstraction has 5129 states and 14540 transitions. [2019-12-07 15:09:17,534 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:09:17,534 INFO L276 IsEmpty]: Start isEmpty. Operand 5129 states and 14540 transitions. [2019-12-07 15:09:17,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:09:17,538 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:17,538 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:17,538 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:17,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:17,538 INFO L82 PathProgramCache]: Analyzing trace with hash 1374418208, now seen corresponding path program 1 times [2019-12-07 15:09:17,538 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:17,538 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304293822] [2019-12-07 15:09:17,538 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:17,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:17,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:17,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304293822] [2019-12-07 15:09:17,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:17,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:09:17,571 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204154841] [2019-12-07 15:09:17,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:09:17,572 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:17,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:09:17,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:17,572 INFO L87 Difference]: Start difference. First operand 5129 states and 14540 transitions. Second operand 3 states. [2019-12-07 15:09:17,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:17,593 INFO L93 Difference]: Finished difference Result 4739 states and 13191 transitions. [2019-12-07 15:09:17,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:09:17,594 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 15:09:17,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:17,599 INFO L225 Difference]: With dead ends: 4739 [2019-12-07 15:09:17,599 INFO L226 Difference]: Without dead ends: 4739 [2019-12-07 15:09:17,599 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:09:17,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4739 states. [2019-12-07 15:09:17,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4739 to 4174. [2019-12-07 15:09:17,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 15:09:17,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 15:09:17,652 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 67 [2019-12-07 15:09:17,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:17,652 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 15:09:17,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:09:17,652 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 15:09:17,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:09:17,655 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:17,655 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:17,655 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:17,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:17,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 1 times [2019-12-07 15:09:17,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:17,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885917683] [2019-12-07 15:09:17,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:17,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:17,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:17,807 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885917683] [2019-12-07 15:09:17,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:17,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 15:09:17,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82183625] [2019-12-07 15:09:17,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 15:09:17,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:17,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 15:09:17,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:09:17,808 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 12 states. [2019-12-07 15:09:18,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:18,065 INFO L93 Difference]: Finished difference Result 7786 states and 21631 transitions. [2019-12-07 15:09:18,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 15:09:18,065 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 68 [2019-12-07 15:09:18,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:18,071 INFO L225 Difference]: With dead ends: 7786 [2019-12-07 15:09:18,072 INFO L226 Difference]: Without dead ends: 7027 [2019-12-07 15:09:18,072 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=308, Unknown=0, NotChecked=0, Total=380 [2019-12-07 15:09:18,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7027 states. [2019-12-07 15:09:18,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7027 to 5351. [2019-12-07 15:09:18,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5351 states. [2019-12-07 15:09:18,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 14810 transitions. [2019-12-07 15:09:18,141 INFO L78 Accepts]: Start accepts. Automaton has 5351 states and 14810 transitions. Word has length 68 [2019-12-07 15:09:18,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:18,142 INFO L462 AbstractCegarLoop]: Abstraction has 5351 states and 14810 transitions. [2019-12-07 15:09:18,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 15:09:18,142 INFO L276 IsEmpty]: Start isEmpty. Operand 5351 states and 14810 transitions. [2019-12-07 15:09:18,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:09:18,145 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:18,145 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:18,145 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:18,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:18,145 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 2 times [2019-12-07 15:09:18,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:18,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883461218] [2019-12-07 15:09:18,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:18,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:18,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:18,289 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883461218] [2019-12-07 15:09:18,289 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:18,289 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 15:09:18,289 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624119661] [2019-12-07 15:09:18,289 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 15:09:18,289 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:18,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 15:09:18,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:09:18,290 INFO L87 Difference]: Start difference. First operand 5351 states and 14810 transitions. Second operand 13 states. [2019-12-07 15:09:18,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:18,728 INFO L93 Difference]: Finished difference Result 8219 states and 22676 transitions. [2019-12-07 15:09:18,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:09:18,729 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 15:09:18,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:18,735 INFO L225 Difference]: With dead ends: 8219 [2019-12-07 15:09:18,735 INFO L226 Difference]: Without dead ends: 7712 [2019-12-07 15:09:18,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2019-12-07 15:09:18,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7712 states. [2019-12-07 15:09:18,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7712 to 5640. [2019-12-07 15:09:18,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5640 states. [2019-12-07 15:09:18,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 15625 transitions. [2019-12-07 15:09:18,806 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 15625 transitions. Word has length 68 [2019-12-07 15:09:18,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:18,807 INFO L462 AbstractCegarLoop]: Abstraction has 5640 states and 15625 transitions. [2019-12-07 15:09:18,807 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 15:09:18,807 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 15625 transitions. [2019-12-07 15:09:18,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:09:18,810 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:18,810 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:18,810 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:18,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:18,811 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 3 times [2019-12-07 15:09:18,811 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:18,811 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720431837] [2019-12-07 15:09:18,811 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:18,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:09:18,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:09:18,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720431837] [2019-12-07 15:09:18,953 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:09:18,953 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 15:09:18,953 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280510054] [2019-12-07 15:09:18,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 15:09:18,954 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 15:09:18,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 15:09:18,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2019-12-07 15:09:18,954 INFO L87 Difference]: Start difference. First operand 5640 states and 15625 transitions. Second operand 14 states. [2019-12-07 15:09:19,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:09:19,351 INFO L93 Difference]: Finished difference Result 8292 states and 22743 transitions. [2019-12-07 15:09:19,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 15:09:19,352 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 15:09:19,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:09:19,358 INFO L225 Difference]: With dead ends: 8292 [2019-12-07 15:09:19,358 INFO L226 Difference]: Without dead ends: 7701 [2019-12-07 15:09:19,358 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=195, Invalid=735, Unknown=0, NotChecked=0, Total=930 [2019-12-07 15:09:19,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7701 states. [2019-12-07 15:09:19,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7701 to 5476. [2019-12-07 15:09:19,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5476 states. [2019-12-07 15:09:19,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5476 states to 5476 states and 15095 transitions. [2019-12-07 15:09:19,427 INFO L78 Accepts]: Start accepts. Automaton has 5476 states and 15095 transitions. Word has length 68 [2019-12-07 15:09:19,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:09:19,427 INFO L462 AbstractCegarLoop]: Abstraction has 5476 states and 15095 transitions. [2019-12-07 15:09:19,427 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 15:09:19,427 INFO L276 IsEmpty]: Start isEmpty. Operand 5476 states and 15095 transitions. [2019-12-07 15:09:19,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:09:19,430 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:09:19,430 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:09:19,431 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:09:19,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:09:19,431 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 4 times [2019-12-07 15:09:19,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 15:09:19,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039224112] [2019-12-07 15:09:19,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:09:19,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:09:19,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:09:19,497 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 15:09:19,497 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 15:09:19,500 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23|) |v_ULTIMATE.start_main_~#t1976~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23|)) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1976~0.offset_17|) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1976~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1976~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_16|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_~#t1976~0.base=|v_ULTIMATE.start_main_~#t1976~0.base_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1976~0.offset=|v_ULTIMATE.start_main_~#t1976~0.offset_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_21|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_20|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1977~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1976~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1976~0.offset, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1977~0.base, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 15:09:19,500 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1977~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11|) |v_ULTIMATE.start_main_~#t1977~0.offset_10| 1)) |v_#memory_int_15|) (= |v_ULTIMATE.start_main_~#t1977~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1977~0.base_11|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1977~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_11|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1977~0.base, ULTIMATE.start_main_~#t1977~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:09:19,500 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 15:09:19,501 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1978~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1978~0.base_12| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1978~0.base_12|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12|) |v_ULTIMATE.start_main_~#t1978~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12| 1)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12|) 0) (= |v_ULTIMATE.start_main_~#t1978~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 15:09:19,501 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1527255017 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1527255017 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1527255017|)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out1527255017| ~z$w_buff0_used~0_In1527255017)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1527255017|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:09:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In993815377 256))) (.cse0 (= (mod ~z$r_buff1_thd1~0_In993815377 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In993815377 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In993815377 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out993815377| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out993815377| ~z$w_buff1_used~0_In993815377) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In993815377, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In993815377, ~z$w_buff1_used~0=~z$w_buff1_used~0_In993815377, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In993815377} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out993815377|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In993815377, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In993815377, ~z$w_buff1_used~0=~z$w_buff1_used~0_In993815377, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In993815377} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:09:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd1~0_In-1688631616 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_In-1688631616 ~z$r_buff0_thd1~0_Out-1688631616)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1688631616 256)))) (or (and (= ~z$r_buff0_thd1~0_Out-1688631616 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1688631616, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1688631616} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1688631616, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1688631616|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-1688631616} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 15:09:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In-915845322 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd1~0_In-915845322 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-915845322 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-915845322| 0)) (and (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In-915845322 |P0Thread1of1ForFork0_#t~ite8_Out-915845322|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-915845322|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:09:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 15:09:19,503 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-812263784 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-812263784 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out-812263784| ~z$w_buff1~0_In-812263784) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite9_Out-812263784| ~z~0_In-812263784) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$w_buff1~0=~z$w_buff1~0_In-812263784, ~z~0=~z~0_In-812263784} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-812263784|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$w_buff1~0=~z$w_buff1~0_In-812263784, ~z~0=~z~0_In-812263784} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 15:09:19,503 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 15:09:19,503 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1921554792 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1921554792| ~z$w_buff0_used~0_In-1921554792)) (and (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1921554792| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1921554792|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1921554792} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:09:19,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In694862629 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In694862629 256) 0))) (or (and (= ~z~0_In694862629 |P2Thread1of1ForFork2_#t~ite15_Out694862629|) (or .cse0 .cse1)) (and (not .cse1) (= ~z$w_buff1~0_In694862629 |P2Thread1of1ForFork2_#t~ite15_Out694862629|) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In694862629, ~z$w_buff1_used~0=~z$w_buff1_used~0_In694862629, ~z$w_buff1~0=~z$w_buff1~0_In694862629, ~z~0=~z~0_In694862629} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out694862629|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In694862629, ~z$w_buff1_used~0=~z$w_buff1_used~0_In694862629, ~z$w_buff1~0=~z$w_buff1~0_In694862629, ~z~0=~z~0_In694862629} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:09:19,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1583702253 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In-1583702253 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd2~0_In-1583702253 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1583702253 256)))) (or (and (= ~z$w_buff1_used~0_In-1583702253 |P1Thread1of1ForFork1_#t~ite12_Out-1583702253|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-1583702253|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1583702253, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1583702253, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1583702253, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1583702253} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1583702253, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1583702253, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1583702253, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1583702253|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1583702253} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:09:19,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-802701951 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-802701951 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-802701951|)) (and (= ~z$r_buff0_thd2~0_In-802701951 |P1Thread1of1ForFork1_#t~ite13_Out-802701951|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-802701951, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-802701951} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-802701951, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-802701951|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-802701951} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 15:09:19,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 15:09:19,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In875920522 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In875920522 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out875920522| ~z$w_buff0_used~0_In875920522) (or .cse0 .cse1)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out875920522| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out875920522|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:09:19,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-928969378 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-928969378 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite18_Out-928969378| 0)) (and (= |P2Thread1of1ForFork2_#t~ite18_Out-928969378| ~z$w_buff1_used~0_In-928969378) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-928969378} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-928969378, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-928969378|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:09:19,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-1683167558 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-1683167558 |P2Thread1of1ForFork2_#t~ite19_Out-1683167558|)) (and (not .cse1) (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1683167558|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1683167558} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1683167558, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1683167558|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:09:19,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In46320247 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In46320247 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In46320247 256))) (.cse2 (= (mod ~z$w_buff1_used~0_In46320247 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out46320247| ~z$r_buff1_thd3~0_In46320247) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out46320247|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In46320247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out46320247|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In46320247} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:09:19,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-1867632557 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out-1867632557| 0)) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In-1867632557 |P1Thread1of1ForFork1_#t~ite14_Out-1867632557|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1867632557} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1867632557|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1867632557} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256)))) (or (and (= ~z~0_In-516925516 |ULTIMATE.start_main_#t~ite24_Out-516925516|) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out-516925516| ~z$w_buff1~0_In-516925516) (not .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$w_buff1~0=~z$w_buff1~0_In-516925516, ~z~0=~z~0_In-516925516} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-516925516|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$w_buff1~0=~z$w_buff1~0_In-516925516, ~z~0=~z~0_In-516925516} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 15:09:19,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In67406370 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In67406370 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out67406370| ~z$w_buff0_used~0_In67406370)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out67406370| 0) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out67406370|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:09:19,507 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1809829356 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1809829356 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd0~0_In1809829356 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1809829356 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out1809829356| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1809829356 |ULTIMATE.start_main_#t~ite27_Out1809829356|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1809829356, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1809829356, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1809829356|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:09:19,507 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In36371985 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In36371985 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite28_Out36371985| ~z$r_buff0_thd0~0_In36371985)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out36371985|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out36371985|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:09:19,507 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1957311214| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite29_Out-1957311214| ~z$r_buff1_thd0~0_In-1957311214) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1957311214|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:09:19,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:09:19,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:09:19,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:09:19,572 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 03:09:19 BasicIcfg [2019-12-07 15:09:19,572 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 15:09:19,572 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 15:09:19,572 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 15:09:19,573 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 15:09:19,573 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:04" (3/4) ... [2019-12-07 15:09:19,575 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 15:09:19,576 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23|) |v_ULTIMATE.start_main_~#t1976~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23|)) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1976~0.offset_17|) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1976~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1976~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_16|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_~#t1976~0.base=|v_ULTIMATE.start_main_~#t1976~0.base_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1976~0.offset=|v_ULTIMATE.start_main_~#t1976~0.offset_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_21|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_20|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1977~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1976~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1976~0.offset, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1977~0.base, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 15:09:19,576 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1977~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11|) |v_ULTIMATE.start_main_~#t1977~0.offset_10| 1)) |v_#memory_int_15|) (= |v_ULTIMATE.start_main_~#t1977~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1977~0.base_11|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1977~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_11|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1977~0.base, ULTIMATE.start_main_~#t1977~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:09:19,576 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 15:09:19,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1978~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1978~0.base_12| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1978~0.base_12|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12|) |v_ULTIMATE.start_main_~#t1978~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12| 1)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12|) 0) (= |v_ULTIMATE.start_main_~#t1978~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 15:09:19,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1527255017 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1527255017 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1527255017|)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out1527255017| ~z$w_buff0_used~0_In1527255017)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1527255017|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:09:19,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In993815377 256))) (.cse0 (= (mod ~z$r_buff1_thd1~0_In993815377 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In993815377 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In993815377 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out993815377| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out993815377| ~z$w_buff1_used~0_In993815377) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In993815377, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In993815377, ~z$w_buff1_used~0=~z$w_buff1_used~0_In993815377, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In993815377} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out993815377|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In993815377, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In993815377, ~z$w_buff1_used~0=~z$w_buff1_used~0_In993815377, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In993815377} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:09:19,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd1~0_In-1688631616 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_In-1688631616 ~z$r_buff0_thd1~0_Out-1688631616)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1688631616 256)))) (or (and (= ~z$r_buff0_thd1~0_Out-1688631616 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1688631616, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1688631616} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1688631616, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1688631616|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-1688631616} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 15:09:19,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In-915845322 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd1~0_In-915845322 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-915845322 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-915845322| 0)) (and (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In-915845322 |P0Thread1of1ForFork0_#t~ite8_Out-915845322|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-915845322|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:09:19,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 15:09:19,580 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-812263784 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-812263784 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out-812263784| ~z$w_buff1~0_In-812263784) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite9_Out-812263784| ~z~0_In-812263784) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$w_buff1~0=~z$w_buff1~0_In-812263784, ~z~0=~z~0_In-812263784} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-812263784|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$w_buff1~0=~z$w_buff1~0_In-812263784, ~z~0=~z~0_In-812263784} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 15:09:19,580 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 15:09:19,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1921554792 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1921554792| ~z$w_buff0_used~0_In-1921554792)) (and (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1921554792| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1921554792|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1921554792} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:09:19,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In694862629 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In694862629 256) 0))) (or (and (= ~z~0_In694862629 |P2Thread1of1ForFork2_#t~ite15_Out694862629|) (or .cse0 .cse1)) (and (not .cse1) (= ~z$w_buff1~0_In694862629 |P2Thread1of1ForFork2_#t~ite15_Out694862629|) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In694862629, ~z$w_buff1_used~0=~z$w_buff1_used~0_In694862629, ~z$w_buff1~0=~z$w_buff1~0_In694862629, ~z~0=~z~0_In694862629} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out694862629|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In694862629, ~z$w_buff1_used~0=~z$w_buff1_used~0_In694862629, ~z$w_buff1~0=~z$w_buff1~0_In694862629, ~z~0=~z~0_In694862629} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:09:19,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1583702253 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In-1583702253 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd2~0_In-1583702253 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1583702253 256)))) (or (and (= ~z$w_buff1_used~0_In-1583702253 |P1Thread1of1ForFork1_#t~ite12_Out-1583702253|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-1583702253|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1583702253, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1583702253, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1583702253, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1583702253} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1583702253, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1583702253, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1583702253, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1583702253|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1583702253} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:09:19,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-802701951 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-802701951 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-802701951|)) (and (= ~z$r_buff0_thd2~0_In-802701951 |P1Thread1of1ForFork1_#t~ite13_Out-802701951|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-802701951, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-802701951} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-802701951, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-802701951|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-802701951} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 15:09:19,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 15:09:19,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In875920522 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In875920522 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out875920522| ~z$w_buff0_used~0_In875920522) (or .cse0 .cse1)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out875920522| 0) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In875920522, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out875920522|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:09:19,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-928969378 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-928969378 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite18_Out-928969378| 0)) (and (= |P2Thread1of1ForFork2_#t~ite18_Out-928969378| ~z$w_buff1_used~0_In-928969378) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-928969378} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-928969378, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-928969378|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:09:19,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-1683167558 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-1683167558 |P2Thread1of1ForFork2_#t~ite19_Out-1683167558|)) (and (not .cse1) (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1683167558|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1683167558} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1683167558, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1683167558|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In46320247 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In46320247 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In46320247 256))) (.cse2 (= (mod ~z$w_buff1_used~0_In46320247 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out46320247| ~z$r_buff1_thd3~0_In46320247) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out46320247|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In46320247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out46320247|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In46320247} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-1867632557 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out-1867632557| 0)) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In-1867632557 |P1Thread1of1ForFork1_#t~ite14_Out-1867632557|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1867632557} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1867632557|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1867632557} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256)))) (or (and (= ~z~0_In-516925516 |ULTIMATE.start_main_#t~ite24_Out-516925516|) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out-516925516| ~z$w_buff1~0_In-516925516) (not .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$w_buff1~0=~z$w_buff1~0_In-516925516, ~z~0=~z~0_In-516925516} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-516925516|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$w_buff1~0=~z$w_buff1~0_In-516925516, ~z~0=~z~0_In-516925516} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 15:09:19,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 15:09:19,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In67406370 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In67406370 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out67406370| ~z$w_buff0_used~0_In67406370)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out67406370| 0) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out67406370|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:09:19,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1809829356 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1809829356 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd0~0_In1809829356 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1809829356 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out1809829356| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1809829356 |ULTIMATE.start_main_#t~ite27_Out1809829356|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1809829356, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1809829356, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1809829356|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:09:19,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In36371985 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In36371985 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite28_Out36371985| ~z$r_buff0_thd0~0_In36371985)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out36371985|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out36371985|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:09:19,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1957311214| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite29_Out-1957311214| ~z$r_buff1_thd0~0_In-1957311214) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1957311214|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:09:19,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:09:19,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:09:19,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:09:19,665 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_8bafa232-aebf-407c-bde1-4e4cb769598d/bin/utaipan/witness.graphml [2019-12-07 15:09:19,665 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 15:09:19,667 INFO L168 Benchmark]: Toolchain (without parser) took 136193.43 ms. Allocated memory was 1.0 GB in the beginning and 8.7 GB in the end (delta: 7.7 GB). Free memory was 938.0 MB in the beginning and 4.4 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,667 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:09:19,668 INFO L168 Benchmark]: CACSL2BoogieTranslator took 389.92 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.8 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -120.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,668 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,668 INFO L168 Benchmark]: Boogie Preprocessor took 27.71 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:09:19,668 INFO L168 Benchmark]: RCFGBuilder took 404.38 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,669 INFO L168 Benchmark]: TraceAbstraction took 135230.17 ms. Allocated memory was 1.1 GB in the beginning and 8.7 GB in the end (delta: 7.6 GB). Free memory was 992.7 MB in the beginning and 4.5 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,669 INFO L168 Benchmark]: Witness Printer took 93.15 ms. Allocated memory is still 8.7 GB. Free memory was 4.5 GB in the beginning and 4.4 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 15:09:19,671 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 389.92 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.8 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -120.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.71 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 404.38 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 135230.17 ms. Allocated memory was 1.1 GB in the beginning and 8.7 GB in the end (delta: 7.6 GB). Free memory was 992.7 MB in the beginning and 4.5 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. * Witness Printer took 93.15 ms. Allocated memory is still 8.7 GB. Free memory was 4.5 GB in the beginning and 4.4 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1976, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1977, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1978, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 135.0s, OverallIterations: 26, TraceHistogramMax: 1, AutomataDifference: 27.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4633 SDtfs, 4422 SDslu, 12964 SDs, 0 SdLazy, 8700 SolverSat, 282 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 320 GetRequests, 57 SyntacticMatches, 23 SemanticMatches, 240 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 836 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=245714occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 86.2s AutomataMinimizationTime, 25 MinimizatonAttempts, 479782 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 1236 NumberOfCodeBlocks, 1236 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1143 ConstructedInterpolants, 0 QuantifiedInterpolants, 296896 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 25 InterpolantComputations, 25 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...