./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f876662a86f1aceded2e700e24741bef1c5d97c0 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:24:47,060 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:24:47,062 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:24:47,069 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:24:47,069 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:24:47,070 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:24:47,071 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:24:47,072 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:24:47,073 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:24:47,074 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:24:47,074 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:24:47,075 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:24:47,075 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:24:47,076 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:24:47,077 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:24:47,078 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:24:47,078 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:24:47,079 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:24:47,080 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:24:47,081 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:24:47,082 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:24:47,083 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:24:47,084 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:24:47,084 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:24:47,086 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:24:47,086 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:24:47,086 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:24:47,087 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:24:47,087 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:24:47,087 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:24:47,088 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:24:47,088 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:24:47,088 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:24:47,089 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:24:47,089 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:24:47,089 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:24:47,090 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:24:47,090 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:24:47,090 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:24:47,091 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:24:47,091 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:24:47,092 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-12-07 14:24:47,101 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:24:47,101 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:24:47,102 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * User list type=DISABLED [2019-12-07 14:24:47,102 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Explicit value domain=true [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Octagon Domain=false [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-12-07 14:24:47,102 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-12-07 14:24:47,103 INFO L138 SettingsManager]: * Interval Domain=false [2019-12-07 14:24:47,103 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-12-07 14:24:47,103 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-12-07 14:24:47,103 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-12-07 14:24:47,103 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:24:47,103 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:24:47,104 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:24:47,105 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:24:47,105 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:24:47,105 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-07 14:24:47,106 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f876662a86f1aceded2e700e24741bef1c5d97c0 [2019-12-07 14:24:47,205 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:24:47,213 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:24:47,215 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:24:47,216 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:24:47,216 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:24:47,217 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i [2019-12-07 14:24:47,253 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/data/8a4663271/faa0bac0c15642c792586e27ace5b085/FLAGd033625f3 [2019-12-07 14:24:47,632 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:24:47,633 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/sv-benchmarks/c/pthread-wmm/safe030_power.opt.i [2019-12-07 14:24:47,643 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/data/8a4663271/faa0bac0c15642c792586e27ace5b085/FLAGd033625f3 [2019-12-07 14:24:47,652 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/data/8a4663271/faa0bac0c15642c792586e27ace5b085 [2019-12-07 14:24:47,654 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:24:47,655 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:24:47,656 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:24:47,656 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:24:47,658 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:24:47,658 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:24:47" (1/1) ... [2019-12-07 14:24:47,660 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:47, skipping insertion in model container [2019-12-07 14:24:47,660 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:24:47" (1/1) ... [2019-12-07 14:24:47,665 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:24:47,695 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:24:47,946 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:24:47,954 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:24:47,996 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:24:48,041 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:24:48,042 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48 WrapperNode [2019-12-07 14:24:48,042 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:24:48,042 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:24:48,042 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:24:48,043 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:24:48,048 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,060 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,082 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:24:48,082 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:24:48,083 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:24:48,083 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:24:48,089 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,089 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,092 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,093 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,099 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,102 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,104 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... [2019-12-07 14:24:48,107 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:24:48,108 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:24:48,108 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:24:48,108 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:24:48,109 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:24:48,149 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 14:24:48,149 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 14:24:48,149 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 14:24:48,149 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 14:24:48,149 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 14:24:48,149 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 14:24:48,150 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 14:24:48,150 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 14:24:48,150 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 14:24:48,150 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 14:24:48,150 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 14:24:48,150 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:24:48,150 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:24:48,152 WARN L205 CfgBuilder]: User set CodeBlockSize to LoopFreeBlock but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 14:24:48,503 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:24:48,503 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 14:24:48,504 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:24:48 BoogieIcfgContainer [2019-12-07 14:24:48,504 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:24:48,505 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:24:48,505 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:24:48,507 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:24:48,507 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:24:47" (1/3) ... [2019-12-07 14:24:48,507 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@458fa38e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:24:48, skipping insertion in model container [2019-12-07 14:24:48,507 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:24:48" (2/3) ... [2019-12-07 14:24:48,508 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@458fa38e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:24:48, skipping insertion in model container [2019-12-07 14:24:48,508 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:24:48" (3/3) ... [2019-12-07 14:24:48,509 INFO L109 eAbstractionObserver]: Analyzing ICFG safe030_power.opt.i [2019-12-07 14:24:48,515 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 14:24:48,515 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:24:48,519 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 14:24:48,520 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 14:24:48,543 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,543 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,543 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,543 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,544 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,544 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,545 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,545 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,545 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,546 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,547 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,547 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,547 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,547 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,547 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,548 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,549 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,549 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,549 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,549 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,549 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,550 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,550 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,551 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:24:48,571 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 14:24:48,587 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:24:48,587 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:24:48,587 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:24:48,587 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:24:48,588 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:24:48,588 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:24:48,588 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:24:48,588 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:24:48,598 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 161 places, 192 transitions [2019-12-07 14:24:48,600 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 14:24:48,658 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 14:24:48,658 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:24:48,669 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 14:24:48,680 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 14:24:48,704 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 14:24:48,704 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:24:48,709 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 14:24:48,719 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 14:24:48,720 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 14:24:51,523 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-12-07 14:24:51,602 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46210 [2019-12-07 14:24:51,603 INFO L214 etLargeBlockEncoding]: Total number of compositions: 110 [2019-12-07 14:24:51,605 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 81 places, 86 transitions [2019-12-07 14:24:52,260 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15658 states. [2019-12-07 14:24:52,262 INFO L276 IsEmpty]: Start isEmpty. Operand 15658 states. [2019-12-07 14:24:52,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 14:24:52,266 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:52,266 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:52,267 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:52,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:52,270 INFO L82 PathProgramCache]: Analyzing trace with hash 430910871, now seen corresponding path program 1 times [2019-12-07 14:24:52,276 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:52,276 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943625313] [2019-12-07 14:24:52,277 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:52,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:52,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:52,424 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943625313] [2019-12-07 14:24:52,424 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:52,424 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 14:24:52,425 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603312291] [2019-12-07 14:24:52,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:24:52,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:52,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:24:52,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:52,439 INFO L87 Difference]: Start difference. First operand 15658 states. Second operand 3 states. [2019-12-07 14:24:52,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:52,649 INFO L93 Difference]: Finished difference Result 15586 states and 57554 transitions. [2019-12-07 14:24:52,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:24:52,650 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 14:24:52,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:52,762 INFO L225 Difference]: With dead ends: 15586 [2019-12-07 14:24:52,762 INFO L226 Difference]: Without dead ends: 15248 [2019-12-07 14:24:52,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:52,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15248 states. [2019-12-07 14:24:53,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15248 to 15248. [2019-12-07 14:24:53,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15248 states. [2019-12-07 14:24:53,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15248 states to 15248 states and 56345 transitions. [2019-12-07 14:24:53,312 INFO L78 Accepts]: Start accepts. Automaton has 15248 states and 56345 transitions. Word has length 7 [2019-12-07 14:24:53,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:53,313 INFO L462 AbstractCegarLoop]: Abstraction has 15248 states and 56345 transitions. [2019-12-07 14:24:53,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:24:53,313 INFO L276 IsEmpty]: Start isEmpty. Operand 15248 states and 56345 transitions. [2019-12-07 14:24:53,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:24:53,317 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:53,317 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:53,317 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:53,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:53,317 INFO L82 PathProgramCache]: Analyzing trace with hash 1550259791, now seen corresponding path program 1 times [2019-12-07 14:24:53,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:53,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826936576] [2019-12-07 14:24:53,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:53,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:53,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:53,378 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826936576] [2019-12-07 14:24:53,378 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:53,378 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:24:53,378 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063107239] [2019-12-07 14:24:53,379 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:24:53,379 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:53,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:24:53,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:24:53,380 INFO L87 Difference]: Start difference. First operand 15248 states and 56345 transitions. Second operand 4 states. [2019-12-07 14:24:53,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:53,777 INFO L93 Difference]: Finished difference Result 24364 states and 86703 transitions. [2019-12-07 14:24:53,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:24:53,778 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:24:53,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:53,900 INFO L225 Difference]: With dead ends: 24364 [2019-12-07 14:24:53,901 INFO L226 Difference]: Without dead ends: 24350 [2019-12-07 14:24:53,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:24:54,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24350 states. [2019-12-07 14:24:54,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24350 to 21678. [2019-12-07 14:24:54,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21678 states. [2019-12-07 14:24:54,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21678 states to 21678 states and 78082 transitions. [2019-12-07 14:24:54,409 INFO L78 Accepts]: Start accepts. Automaton has 21678 states and 78082 transitions. Word has length 13 [2019-12-07 14:24:54,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:54,410 INFO L462 AbstractCegarLoop]: Abstraction has 21678 states and 78082 transitions. [2019-12-07 14:24:54,410 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:24:54,410 INFO L276 IsEmpty]: Start isEmpty. Operand 21678 states and 78082 transitions. [2019-12-07 14:24:54,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:24:54,412 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:54,412 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:54,412 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:54,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:54,412 INFO L82 PathProgramCache]: Analyzing trace with hash -1785022215, now seen corresponding path program 1 times [2019-12-07 14:24:54,413 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:54,413 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892516837] [2019-12-07 14:24:54,413 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:54,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:54,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:54,458 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892516837] [2019-12-07 14:24:54,459 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:54,459 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:24:54,459 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899618316] [2019-12-07 14:24:54,459 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:24:54,459 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:54,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:24:54,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:24:54,460 INFO L87 Difference]: Start difference. First operand 21678 states and 78082 transitions. Second operand 4 states. [2019-12-07 14:24:54,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:54,704 INFO L93 Difference]: Finished difference Result 26634 states and 94744 transitions. [2019-12-07 14:24:54,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:24:54,704 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:24:54,705 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:54,755 INFO L225 Difference]: With dead ends: 26634 [2019-12-07 14:24:54,756 INFO L226 Difference]: Without dead ends: 26634 [2019-12-07 14:24:54,756 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:24:54,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26634 states. [2019-12-07 14:24:55,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26634 to 23780. [2019-12-07 14:24:55,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23780 states. [2019-12-07 14:24:55,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23780 states to 23780 states and 85353 transitions. [2019-12-07 14:24:55,181 INFO L78 Accepts]: Start accepts. Automaton has 23780 states and 85353 transitions. Word has length 13 [2019-12-07 14:24:55,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:55,181 INFO L462 AbstractCegarLoop]: Abstraction has 23780 states and 85353 transitions. [2019-12-07 14:24:55,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:24:55,182 INFO L276 IsEmpty]: Start isEmpty. Operand 23780 states and 85353 transitions. [2019-12-07 14:24:55,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 14:24:55,186 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:55,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:55,187 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:55,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:55,187 INFO L82 PathProgramCache]: Analyzing trace with hash -1491137103, now seen corresponding path program 1 times [2019-12-07 14:24:55,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:55,188 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584320313] [2019-12-07 14:24:55,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:55,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:55,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:55,258 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584320313] [2019-12-07 14:24:55,258 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:55,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:24:55,259 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205885808] [2019-12-07 14:24:55,259 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:24:55,259 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:55,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:24:55,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:24:55,259 INFO L87 Difference]: Start difference. First operand 23780 states and 85353 transitions. Second operand 5 states. [2019-12-07 14:24:55,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:55,691 INFO L93 Difference]: Finished difference Result 32276 states and 113793 transitions. [2019-12-07 14:24:55,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:24:55,691 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 14:24:55,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:55,746 INFO L225 Difference]: With dead ends: 32276 [2019-12-07 14:24:55,746 INFO L226 Difference]: Without dead ends: 32262 [2019-12-07 14:24:55,746 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:24:55,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32262 states. [2019-12-07 14:24:56,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32262 to 23678. [2019-12-07 14:24:56,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23678 states. [2019-12-07 14:24:56,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23678 states to 23678 states and 84856 transitions. [2019-12-07 14:24:56,196 INFO L78 Accepts]: Start accepts. Automaton has 23678 states and 84856 transitions. Word has length 19 [2019-12-07 14:24:56,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:56,196 INFO L462 AbstractCegarLoop]: Abstraction has 23678 states and 84856 transitions. [2019-12-07 14:24:56,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:24:56,197 INFO L276 IsEmpty]: Start isEmpty. Operand 23678 states and 84856 transitions. [2019-12-07 14:24:56,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 14:24:56,215 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:56,215 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:56,215 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:56,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:56,215 INFO L82 PathProgramCache]: Analyzing trace with hash -1614044955, now seen corresponding path program 1 times [2019-12-07 14:24:56,215 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:56,216 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306667395] [2019-12-07 14:24:56,216 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:56,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:56,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:56,269 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306667395] [2019-12-07 14:24:56,269 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:56,269 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:24:56,270 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194189862] [2019-12-07 14:24:56,270 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:24:56,270 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:56,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:24:56,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:24:56,271 INFO L87 Difference]: Start difference. First operand 23678 states and 84856 transitions. Second operand 5 states. [2019-12-07 14:24:56,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:56,574 INFO L93 Difference]: Finished difference Result 30866 states and 109434 transitions. [2019-12-07 14:24:56,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:24:56,575 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2019-12-07 14:24:56,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:56,626 INFO L225 Difference]: With dead ends: 30866 [2019-12-07 14:24:56,626 INFO L226 Difference]: Without dead ends: 30850 [2019-12-07 14:24:56,626 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:24:56,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30850 states. [2019-12-07 14:24:57,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30850 to 27838. [2019-12-07 14:24:57,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27838 states. [2019-12-07 14:24:57,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27838 states to 27838 states and 99028 transitions. [2019-12-07 14:24:57,109 INFO L78 Accepts]: Start accepts. Automaton has 27838 states and 99028 transitions. Word has length 27 [2019-12-07 14:24:57,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:57,109 INFO L462 AbstractCegarLoop]: Abstraction has 27838 states and 99028 transitions. [2019-12-07 14:24:57,109 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:24:57,109 INFO L276 IsEmpty]: Start isEmpty. Operand 27838 states and 99028 transitions. [2019-12-07 14:24:57,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 14:24:57,134 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:57,135 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:57,135 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:57,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:57,135 INFO L82 PathProgramCache]: Analyzing trace with hash -633448160, now seen corresponding path program 1 times [2019-12-07 14:24:57,135 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:57,135 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891551657] [2019-12-07 14:24:57,135 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:57,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:57,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:57,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891551657] [2019-12-07 14:24:57,165 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:57,165 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:24:57,165 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714949641] [2019-12-07 14:24:57,166 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:24:57,166 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:57,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:24:57,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:57,166 INFO L87 Difference]: Start difference. First operand 27838 states and 99028 transitions. Second operand 3 states. [2019-12-07 14:24:57,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:57,301 INFO L93 Difference]: Finished difference Result 33728 states and 120449 transitions. [2019-12-07 14:24:57,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:24:57,302 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 14:24:57,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:57,361 INFO L225 Difference]: With dead ends: 33728 [2019-12-07 14:24:57,361 INFO L226 Difference]: Without dead ends: 33728 [2019-12-07 14:24:57,361 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:57,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33728 states. [2019-12-07 14:24:57,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33728 to 31198. [2019-12-07 14:24:57,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31198 states. [2019-12-07 14:24:57,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31198 states to 31198 states and 111684 transitions. [2019-12-07 14:24:57,951 INFO L78 Accepts]: Start accepts. Automaton has 31198 states and 111684 transitions. Word has length 32 [2019-12-07 14:24:57,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:57,952 INFO L462 AbstractCegarLoop]: Abstraction has 31198 states and 111684 transitions. [2019-12-07 14:24:57,952 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:24:57,952 INFO L276 IsEmpty]: Start isEmpty. Operand 31198 states and 111684 transitions. [2019-12-07 14:24:57,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 14:24:57,978 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:57,978 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:57,978 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:57,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:57,979 INFO L82 PathProgramCache]: Analyzing trace with hash 775187136, now seen corresponding path program 1 times [2019-12-07 14:24:57,979 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:57,979 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384494726] [2019-12-07 14:24:57,979 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:57,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:58,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:58,006 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384494726] [2019-12-07 14:24:58,006 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:58,006 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:24:58,006 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348638491] [2019-12-07 14:24:58,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:24:58,007 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:58,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:24:58,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:58,007 INFO L87 Difference]: Start difference. First operand 31198 states and 111684 transitions. Second operand 3 states. [2019-12-07 14:24:58,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:58,051 INFO L93 Difference]: Finished difference Result 17541 states and 54208 transitions. [2019-12-07 14:24:58,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:24:58,052 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 14:24:58,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:58,073 INFO L225 Difference]: With dead ends: 17541 [2019-12-07 14:24:58,073 INFO L226 Difference]: Without dead ends: 17541 [2019-12-07 14:24:58,074 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:58,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17541 states. [2019-12-07 14:24:58,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17541 to 17541. [2019-12-07 14:24:58,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17541 states. [2019-12-07 14:24:58,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17541 states to 17541 states and 54208 transitions. [2019-12-07 14:24:58,315 INFO L78 Accepts]: Start accepts. Automaton has 17541 states and 54208 transitions. Word has length 32 [2019-12-07 14:24:58,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:58,316 INFO L462 AbstractCegarLoop]: Abstraction has 17541 states and 54208 transitions. [2019-12-07 14:24:58,316 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:24:58,316 INFO L276 IsEmpty]: Start isEmpty. Operand 17541 states and 54208 transitions. [2019-12-07 14:24:58,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 14:24:58,328 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:58,328 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:58,328 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:58,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:58,328 INFO L82 PathProgramCache]: Analyzing trace with hash 1291274326, now seen corresponding path program 1 times [2019-12-07 14:24:58,329 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:58,329 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981469317] [2019-12-07 14:24:58,329 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:58,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:58,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:58,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981469317] [2019-12-07 14:24:58,401 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:58,401 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:24:58,401 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451694863] [2019-12-07 14:24:58,401 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:24:58,401 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:58,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:24:58,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:24:58,402 INFO L87 Difference]: Start difference. First operand 17541 states and 54208 transitions. Second operand 6 states. [2019-12-07 14:24:58,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:58,652 INFO L93 Difference]: Finished difference Result 39110 states and 121673 transitions. [2019-12-07 14:24:58,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:24:58,652 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2019-12-07 14:24:58,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:58,682 INFO L225 Difference]: With dead ends: 39110 [2019-12-07 14:24:58,682 INFO L226 Difference]: Without dead ends: 24298 [2019-12-07 14:24:58,682 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:24:58,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24298 states. [2019-12-07 14:24:58,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24298 to 21545. [2019-12-07 14:24:58,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21545 states. [2019-12-07 14:24:59,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21545 states to 21545 states and 65180 transitions. [2019-12-07 14:24:59,001 INFO L78 Accepts]: Start accepts. Automaton has 21545 states and 65180 transitions. Word has length 33 [2019-12-07 14:24:59,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:59,002 INFO L462 AbstractCegarLoop]: Abstraction has 21545 states and 65180 transitions. [2019-12-07 14:24:59,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:24:59,002 INFO L276 IsEmpty]: Start isEmpty. Operand 21545 states and 65180 transitions. [2019-12-07 14:24:59,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:24:59,018 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:59,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:59,019 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:59,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:59,019 INFO L82 PathProgramCache]: Analyzing trace with hash -1378487753, now seen corresponding path program 1 times [2019-12-07 14:24:59,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:59,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803386596] [2019-12-07 14:24:59,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:59,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:59,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:59,049 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803386596] [2019-12-07 14:24:59,050 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:59,050 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:24:59,050 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669214151] [2019-12-07 14:24:59,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:24:59,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:59,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:24:59,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:59,051 INFO L87 Difference]: Start difference. First operand 21545 states and 65180 transitions. Second operand 3 states. [2019-12-07 14:24:59,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:59,138 INFO L93 Difference]: Finished difference Result 21545 states and 64972 transitions. [2019-12-07 14:24:59,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:24:59,139 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2019-12-07 14:24:59,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:59,164 INFO L225 Difference]: With dead ends: 21545 [2019-12-07 14:24:59,164 INFO L226 Difference]: Without dead ends: 21545 [2019-12-07 14:24:59,164 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:24:59,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21545 states. [2019-12-07 14:24:59,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21545 to 21545. [2019-12-07 14:24:59,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21545 states. [2019-12-07 14:24:59,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21545 states to 21545 states and 64972 transitions. [2019-12-07 14:24:59,451 INFO L78 Accepts]: Start accepts. Automaton has 21545 states and 64972 transitions. Word has length 34 [2019-12-07 14:24:59,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:24:59,451 INFO L462 AbstractCegarLoop]: Abstraction has 21545 states and 64972 transitions. [2019-12-07 14:24:59,451 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:24:59,451 INFO L276 IsEmpty]: Start isEmpty. Operand 21545 states and 64972 transitions. [2019-12-07 14:24:59,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:24:59,461 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:24:59,461 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:24:59,461 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:24:59,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:24:59,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1833353799, now seen corresponding path program 1 times [2019-12-07 14:24:59,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:24:59,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116016551] [2019-12-07 14:24:59,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:24:59,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:24:59,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:24:59,510 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116016551] [2019-12-07 14:24:59,510 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:24:59,510 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:24:59,510 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763018648] [2019-12-07 14:24:59,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:24:59,511 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:24:59,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:24:59,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:24:59,511 INFO L87 Difference]: Start difference. First operand 21545 states and 64972 transitions. Second operand 6 states. [2019-12-07 14:24:59,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:24:59,868 INFO L93 Difference]: Finished difference Result 25124 states and 75040 transitions. [2019-12-07 14:24:59,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 14:24:59,869 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 14:24:59,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:24:59,901 INFO L225 Difference]: With dead ends: 25124 [2019-12-07 14:24:59,901 INFO L226 Difference]: Without dead ends: 24712 [2019-12-07 14:24:59,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:24:59,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24712 states. [2019-12-07 14:25:00,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24712 to 19573. [2019-12-07 14:25:00,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19573 states. [2019-12-07 14:25:00,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19573 states to 19573 states and 59529 transitions. [2019-12-07 14:25:00,262 INFO L78 Accepts]: Start accepts. Automaton has 19573 states and 59529 transitions. Word has length 34 [2019-12-07 14:25:00,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:00,263 INFO L462 AbstractCegarLoop]: Abstraction has 19573 states and 59529 transitions. [2019-12-07 14:25:00,263 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:25:00,263 INFO L276 IsEmpty]: Start isEmpty. Operand 19573 states and 59529 transitions. [2019-12-07 14:25:00,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:25:00,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:00,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:00,272 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:00,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:00,272 INFO L82 PathProgramCache]: Analyzing trace with hash 638623931, now seen corresponding path program 1 times [2019-12-07 14:25:00,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:00,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531908639] [2019-12-07 14:25:00,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:00,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:00,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:00,368 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531908639] [2019-12-07 14:25:00,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:00,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 14:25:00,369 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217791247] [2019-12-07 14:25:00,369 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 14:25:00,369 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:00,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 14:25:00,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:25:00,370 INFO L87 Difference]: Start difference. First operand 19573 states and 59529 transitions. Second operand 9 states. [2019-12-07 14:25:00,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:00,714 INFO L93 Difference]: Finished difference Result 33190 states and 102659 transitions. [2019-12-07 14:25:00,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:25:00,714 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2019-12-07 14:25:00,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:00,748 INFO L225 Difference]: With dead ends: 33190 [2019-12-07 14:25:00,748 INFO L226 Difference]: Without dead ends: 28366 [2019-12-07 14:25:00,749 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:00,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28366 states. [2019-12-07 14:25:01,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28366 to 22134. [2019-12-07 14:25:01,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22134 states. [2019-12-07 14:25:01,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22134 states to 22134 states and 67372 transitions. [2019-12-07 14:25:01,099 INFO L78 Accepts]: Start accepts. Automaton has 22134 states and 67372 transitions. Word has length 34 [2019-12-07 14:25:01,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:01,099 INFO L462 AbstractCegarLoop]: Abstraction has 22134 states and 67372 transitions. [2019-12-07 14:25:01,099 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 14:25:01,099 INFO L276 IsEmpty]: Start isEmpty. Operand 22134 states and 67372 transitions. [2019-12-07 14:25:01,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:25:01,111 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:01,112 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:01,112 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:01,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:01,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1676958407, now seen corresponding path program 2 times [2019-12-07 14:25:01,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:01,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085269524] [2019-12-07 14:25:01,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:01,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:01,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:01,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085269524] [2019-12-07 14:25:01,189 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:01,189 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:25:01,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605298040] [2019-12-07 14:25:01,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 14:25:01,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:01,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 14:25:01,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:25:01,190 INFO L87 Difference]: Start difference. First operand 22134 states and 67372 transitions. Second operand 8 states. [2019-12-07 14:25:01,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:01,406 INFO L93 Difference]: Finished difference Result 36819 states and 113734 transitions. [2019-12-07 14:25:01,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 14:25:01,407 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2019-12-07 14:25:01,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:01,447 INFO L225 Difference]: With dead ends: 36819 [2019-12-07 14:25:01,447 INFO L226 Difference]: Without dead ends: 31814 [2019-12-07 14:25:01,448 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:25:01,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31814 states. [2019-12-07 14:25:01,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31814 to 22902. [2019-12-07 14:25:01,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22902 states. [2019-12-07 14:25:01,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22902 states to 22902 states and 69381 transitions. [2019-12-07 14:25:01,820 INFO L78 Accepts]: Start accepts. Automaton has 22902 states and 69381 transitions. Word has length 34 [2019-12-07 14:25:01,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:01,821 INFO L462 AbstractCegarLoop]: Abstraction has 22902 states and 69381 transitions. [2019-12-07 14:25:01,821 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 14:25:01,821 INFO L276 IsEmpty]: Start isEmpty. Operand 22902 states and 69381 transitions. [2019-12-07 14:25:01,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 14:25:01,835 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:01,836 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:01,836 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:01,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:01,836 INFO L82 PathProgramCache]: Analyzing trace with hash 80593671, now seen corresponding path program 1 times [2019-12-07 14:25:01,836 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:01,836 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808490844] [2019-12-07 14:25:01,836 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:01,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:01,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:01,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808490844] [2019-12-07 14:25:01,980 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:01,980 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 14:25:01,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519460903] [2019-12-07 14:25:01,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 14:25:01,980 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:01,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 14:25:01,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:25:01,981 INFO L87 Difference]: Start difference. First operand 22902 states and 69381 transitions. Second operand 9 states. [2019-12-07 14:25:02,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:02,258 INFO L93 Difference]: Finished difference Result 37585 states and 116302 transitions. [2019-12-07 14:25:02,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:25:02,258 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 35 [2019-12-07 14:25:02,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:02,298 INFO L225 Difference]: With dead ends: 37585 [2019-12-07 14:25:02,298 INFO L226 Difference]: Without dead ends: 33468 [2019-12-07 14:25:02,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:02,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33468 states. [2019-12-07 14:25:02,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33468 to 22927. [2019-12-07 14:25:02,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22927 states. [2019-12-07 14:25:02,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22927 states to 22927 states and 69454 transitions. [2019-12-07 14:25:02,678 INFO L78 Accepts]: Start accepts. Automaton has 22927 states and 69454 transitions. Word has length 35 [2019-12-07 14:25:02,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:02,678 INFO L462 AbstractCegarLoop]: Abstraction has 22927 states and 69454 transitions. [2019-12-07 14:25:02,678 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 14:25:02,678 INFO L276 IsEmpty]: Start isEmpty. Operand 22927 states and 69454 transitions. [2019-12-07 14:25:02,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 14:25:02,693 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:02,693 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:02,694 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:02,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:02,694 INFO L82 PathProgramCache]: Analyzing trace with hash 1945525913, now seen corresponding path program 2 times [2019-12-07 14:25:02,694 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:02,694 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743924667] [2019-12-07 14:25:02,694 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:02,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:02,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:02,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743924667] [2019-12-07 14:25:02,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:02,799 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 14:25:02,799 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166925818] [2019-12-07 14:25:02,799 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 14:25:02,799 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:02,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 14:25:02,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2019-12-07 14:25:02,800 INFO L87 Difference]: Start difference. First operand 22927 states and 69454 transitions. Second operand 10 states. [2019-12-07 14:25:03,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:03,275 INFO L93 Difference]: Finished difference Result 43886 states and 136661 transitions. [2019-12-07 14:25:03,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 14:25:03,276 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 35 [2019-12-07 14:25:03,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:03,330 INFO L225 Difference]: With dead ends: 43886 [2019-12-07 14:25:03,330 INFO L226 Difference]: Without dead ends: 41000 [2019-12-07 14:25:03,330 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=300, Unknown=0, NotChecked=0, Total=380 [2019-12-07 14:25:03,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41000 states. [2019-12-07 14:25:03,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41000 to 22919. [2019-12-07 14:25:03,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22919 states. [2019-12-07 14:25:03,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22919 states to 22919 states and 69419 transitions. [2019-12-07 14:25:03,756 INFO L78 Accepts]: Start accepts. Automaton has 22919 states and 69419 transitions. Word has length 35 [2019-12-07 14:25:03,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:03,757 INFO L462 AbstractCegarLoop]: Abstraction has 22919 states and 69419 transitions. [2019-12-07 14:25:03,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 14:25:03,757 INFO L276 IsEmpty]: Start isEmpty. Operand 22919 states and 69419 transitions. [2019-12-07 14:25:03,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:03,770 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:03,770 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:03,771 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:03,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:03,771 INFO L82 PathProgramCache]: Analyzing trace with hash 338185064, now seen corresponding path program 1 times [2019-12-07 14:25:03,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:03,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698207975] [2019-12-07 14:25:03,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:03,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:03,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:03,916 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698207975] [2019-12-07 14:25:03,916 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:03,916 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:03,916 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574011003] [2019-12-07 14:25:03,916 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:03,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:03,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:03,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:03,917 INFO L87 Difference]: Start difference. First operand 22919 states and 69419 transitions. Second operand 11 states. [2019-12-07 14:25:04,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:04,803 INFO L93 Difference]: Finished difference Result 39749 states and 123797 transitions. [2019-12-07 14:25:04,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:25:04,804 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 36 [2019-12-07 14:25:04,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:04,862 INFO L225 Difference]: With dead ends: 39749 [2019-12-07 14:25:04,862 INFO L226 Difference]: Without dead ends: 37037 [2019-12-07 14:25:04,862 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-12-07 14:25:04,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37037 states. [2019-12-07 14:25:05,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37037 to 22971. [2019-12-07 14:25:05,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22971 states. [2019-12-07 14:25:05,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22971 states to 22971 states and 69600 transitions. [2019-12-07 14:25:05,318 INFO L78 Accepts]: Start accepts. Automaton has 22971 states and 69600 transitions. Word has length 36 [2019-12-07 14:25:05,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:05,319 INFO L462 AbstractCegarLoop]: Abstraction has 22971 states and 69600 transitions. [2019-12-07 14:25:05,319 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:05,319 INFO L276 IsEmpty]: Start isEmpty. Operand 22971 states and 69600 transitions. [2019-12-07 14:25:05,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:05,334 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:05,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:05,334 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:05,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:05,334 INFO L82 PathProgramCache]: Analyzing trace with hash 1810599033, now seen corresponding path program 1 times [2019-12-07 14:25:05,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:05,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414111060] [2019-12-07 14:25:05,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:05,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:05,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:05,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414111060] [2019-12-07 14:25:05,435 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:05,435 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:25:05,435 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386697214] [2019-12-07 14:25:05,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:25:05,436 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:05,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:25:05,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:25:05,436 INFO L87 Difference]: Start difference. First operand 22971 states and 69600 transitions. Second operand 7 states. [2019-12-07 14:25:05,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:05,897 INFO L93 Difference]: Finished difference Result 33200 states and 100368 transitions. [2019-12-07 14:25:05,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 14:25:05,898 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2019-12-07 14:25:05,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:05,941 INFO L225 Difference]: With dead ends: 33200 [2019-12-07 14:25:05,941 INFO L226 Difference]: Without dead ends: 33056 [2019-12-07 14:25:05,942 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 7 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:06,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33056 states. [2019-12-07 14:25:06,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33056 to 27815. [2019-12-07 14:25:06,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27815 states. [2019-12-07 14:25:06,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27815 states to 27815 states and 84006 transitions. [2019-12-07 14:25:06,378 INFO L78 Accepts]: Start accepts. Automaton has 27815 states and 84006 transitions. Word has length 36 [2019-12-07 14:25:06,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:06,378 INFO L462 AbstractCegarLoop]: Abstraction has 27815 states and 84006 transitions. [2019-12-07 14:25:06,378 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:25:06,378 INFO L276 IsEmpty]: Start isEmpty. Operand 27815 states and 84006 transitions. [2019-12-07 14:25:06,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:06,397 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:06,397 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:06,397 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:06,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:06,397 INFO L82 PathProgramCache]: Analyzing trace with hash 774289006, now seen corresponding path program 2 times [2019-12-07 14:25:06,397 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:06,398 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619354764] [2019-12-07 14:25:06,398 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:06,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:06,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:06,450 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619354764] [2019-12-07 14:25:06,451 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:06,451 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:25:06,451 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419816158] [2019-12-07 14:25:06,451 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:25:06,451 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:06,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:25:06,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:25:06,451 INFO L87 Difference]: Start difference. First operand 27815 states and 84006 transitions. Second operand 5 states. [2019-12-07 14:25:06,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:06,584 INFO L93 Difference]: Finished difference Result 39250 states and 119598 transitions. [2019-12-07 14:25:06,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:25:06,584 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2019-12-07 14:25:06,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:06,599 INFO L225 Difference]: With dead ends: 39250 [2019-12-07 14:25:06,599 INFO L226 Difference]: Without dead ends: 14020 [2019-12-07 14:25:06,600 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:25:06,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14020 states. [2019-12-07 14:25:06,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14020 to 13242. [2019-12-07 14:25:06,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13242 states. [2019-12-07 14:25:06,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13242 states to 13242 states and 39452 transitions. [2019-12-07 14:25:06,786 INFO L78 Accepts]: Start accepts. Automaton has 13242 states and 39452 transitions. Word has length 36 [2019-12-07 14:25:06,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:06,786 INFO L462 AbstractCegarLoop]: Abstraction has 13242 states and 39452 transitions. [2019-12-07 14:25:06,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:25:06,786 INFO L276 IsEmpty]: Start isEmpty. Operand 13242 states and 39452 transitions. [2019-12-07 14:25:06,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:06,794 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:06,794 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:06,794 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:06,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:06,794 INFO L82 PathProgramCache]: Analyzing trace with hash -2016154181, now seen corresponding path program 2 times [2019-12-07 14:25:06,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:06,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648213330] [2019-12-07 14:25:06,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:06,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:06,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:06,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648213330] [2019-12-07 14:25:06,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:06,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:25:06,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456535466] [2019-12-07 14:25:06,900 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:25:06,900 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:06,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:25:06,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:25:06,900 INFO L87 Difference]: Start difference. First operand 13242 states and 39452 transitions. Second operand 7 states. [2019-12-07 14:25:07,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:07,143 INFO L93 Difference]: Finished difference Result 19115 states and 56677 transitions. [2019-12-07 14:25:07,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:25:07,143 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2019-12-07 14:25:07,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:07,163 INFO L225 Difference]: With dead ends: 19115 [2019-12-07 14:25:07,163 INFO L226 Difference]: Without dead ends: 18529 [2019-12-07 14:25:07,163 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:25:07,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18529 states. [2019-12-07 14:25:07,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18529 to 16802. [2019-12-07 14:25:07,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16802 states. [2019-12-07 14:25:07,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16802 states to 16802 states and 50517 transitions. [2019-12-07 14:25:07,436 INFO L78 Accepts]: Start accepts. Automaton has 16802 states and 50517 transitions. Word has length 36 [2019-12-07 14:25:07,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:07,436 INFO L462 AbstractCegarLoop]: Abstraction has 16802 states and 50517 transitions. [2019-12-07 14:25:07,436 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:25:07,437 INFO L276 IsEmpty]: Start isEmpty. Operand 16802 states and 50517 transitions. [2019-12-07 14:25:07,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:07,445 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:07,445 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:07,446 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:07,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:07,446 INFO L82 PathProgramCache]: Analyzing trace with hash -801911607, now seen corresponding path program 3 times [2019-12-07 14:25:07,446 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:07,446 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905147413] [2019-12-07 14:25:07,446 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:07,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:07,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:07,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905147413] [2019-12-07 14:25:07,499 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:07,500 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:25:07,500 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319269502] [2019-12-07 14:25:07,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:25:07,500 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:07,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:25:07,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:25:07,500 INFO L87 Difference]: Start difference. First operand 16802 states and 50517 transitions. Second operand 5 states. [2019-12-07 14:25:07,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:07,595 INFO L93 Difference]: Finished difference Result 15024 states and 44149 transitions. [2019-12-07 14:25:07,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:25:07,595 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2019-12-07 14:25:07,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:07,609 INFO L225 Difference]: With dead ends: 15024 [2019-12-07 14:25:07,610 INFO L226 Difference]: Without dead ends: 14325 [2019-12-07 14:25:07,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:25:07,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14325 states. [2019-12-07 14:25:07,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14325 to 8374. [2019-12-07 14:25:07,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8374 states. [2019-12-07 14:25:07,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8374 states to 8374 states and 24818 transitions. [2019-12-07 14:25:07,744 INFO L78 Accepts]: Start accepts. Automaton has 8374 states and 24818 transitions. Word has length 36 [2019-12-07 14:25:07,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:07,744 INFO L462 AbstractCegarLoop]: Abstraction has 8374 states and 24818 transitions. [2019-12-07 14:25:07,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:25:07,744 INFO L276 IsEmpty]: Start isEmpty. Operand 8374 states and 24818 transitions. [2019-12-07 14:25:07,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 14:25:07,748 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:07,748 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:07,749 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:07,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:07,749 INFO L82 PathProgramCache]: Analyzing trace with hash 1686572430, now seen corresponding path program 3 times [2019-12-07 14:25:07,749 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:07,749 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230459780] [2019-12-07 14:25:07,749 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:07,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:07,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:07,841 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230459780] [2019-12-07 14:25:07,841 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:07,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:07,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891621667] [2019-12-07 14:25:07,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:07,842 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:07,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:07,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:07,842 INFO L87 Difference]: Start difference. First operand 8374 states and 24818 transitions. Second operand 11 states. [2019-12-07 14:25:08,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:08,255 INFO L93 Difference]: Finished difference Result 13953 states and 41540 transitions. [2019-12-07 14:25:08,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 14:25:08,256 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 36 [2019-12-07 14:25:08,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:08,266 INFO L225 Difference]: With dead ends: 13953 [2019-12-07 14:25:08,267 INFO L226 Difference]: Without dead ends: 11205 [2019-12-07 14:25:08,267 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 157 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=182, Invalid=630, Unknown=0, NotChecked=0, Total=812 [2019-12-07 14:25:08,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11205 states. [2019-12-07 14:25:08,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11205 to 8110. [2019-12-07 14:25:08,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8110 states. [2019-12-07 14:25:08,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8110 states to 8110 states and 23816 transitions. [2019-12-07 14:25:08,384 INFO L78 Accepts]: Start accepts. Automaton has 8110 states and 23816 transitions. Word has length 36 [2019-12-07 14:25:08,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:08,384 INFO L462 AbstractCegarLoop]: Abstraction has 8110 states and 23816 transitions. [2019-12-07 14:25:08,384 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:08,384 INFO L276 IsEmpty]: Start isEmpty. Operand 8110 states and 23816 transitions. [2019-12-07 14:25:08,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:08,389 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:08,389 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:08,389 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:08,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:08,389 INFO L82 PathProgramCache]: Analyzing trace with hash 1164744073, now seen corresponding path program 1 times [2019-12-07 14:25:08,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:08,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790118427] [2019-12-07 14:25:08,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:08,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:08,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:08,410 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790118427] [2019-12-07 14:25:08,411 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:08,411 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:25:08,411 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388321075] [2019-12-07 14:25:08,411 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:25:08,411 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:08,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:25:08,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:25:08,412 INFO L87 Difference]: Start difference. First operand 8110 states and 23816 transitions. Second operand 3 states. [2019-12-07 14:25:08,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:08,436 INFO L93 Difference]: Finished difference Result 8110 states and 23193 transitions. [2019-12-07 14:25:08,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:25:08,436 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 37 [2019-12-07 14:25:08,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:08,443 INFO L225 Difference]: With dead ends: 8110 [2019-12-07 14:25:08,443 INFO L226 Difference]: Without dead ends: 8110 [2019-12-07 14:25:08,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:25:08,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8110 states. [2019-12-07 14:25:08,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8110 to 8110. [2019-12-07 14:25:08,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8110 states. [2019-12-07 14:25:08,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8110 states to 8110 states and 23193 transitions. [2019-12-07 14:25:08,542 INFO L78 Accepts]: Start accepts. Automaton has 8110 states and 23193 transitions. Word has length 37 [2019-12-07 14:25:08,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:08,542 INFO L462 AbstractCegarLoop]: Abstraction has 8110 states and 23193 transitions. [2019-12-07 14:25:08,542 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:25:08,542 INFO L276 IsEmpty]: Start isEmpty. Operand 8110 states and 23193 transitions. [2019-12-07 14:25:08,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:08,546 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:08,546 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:08,547 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:08,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:08,547 INFO L82 PathProgramCache]: Analyzing trace with hash 871404576, now seen corresponding path program 1 times [2019-12-07 14:25:08,547 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:08,547 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911098470] [2019-12-07 14:25:08,547 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:08,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:08,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:08,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911098470] [2019-12-07 14:25:08,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:08,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:08,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000927007] [2019-12-07 14:25:08,638 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:08,638 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:08,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:08,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:08,639 INFO L87 Difference]: Start difference. First operand 8110 states and 23193 transitions. Second operand 11 states. [2019-12-07 14:25:08,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:08,956 INFO L93 Difference]: Finished difference Result 10959 states and 31025 transitions. [2019-12-07 14:25:08,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 14:25:08,956 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 14:25:08,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:08,964 INFO L225 Difference]: With dead ends: 10959 [2019-12-07 14:25:08,965 INFO L226 Difference]: Without dead ends: 9674 [2019-12-07 14:25:08,965 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=428, Unknown=0, NotChecked=0, Total=552 [2019-12-07 14:25:08,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9674 states. [2019-12-07 14:25:09,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9674 to 7945. [2019-12-07 14:25:09,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7945 states. [2019-12-07 14:25:09,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7945 states to 7945 states and 22714 transitions. [2019-12-07 14:25:09,069 INFO L78 Accepts]: Start accepts. Automaton has 7945 states and 22714 transitions. Word has length 37 [2019-12-07 14:25:09,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:09,069 INFO L462 AbstractCegarLoop]: Abstraction has 7945 states and 22714 transitions. [2019-12-07 14:25:09,069 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:09,070 INFO L276 IsEmpty]: Start isEmpty. Operand 7945 states and 22714 transitions. [2019-12-07 14:25:09,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:09,073 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:09,073 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:09,074 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:09,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:09,074 INFO L82 PathProgramCache]: Analyzing trace with hash -1236357120, now seen corresponding path program 2 times [2019-12-07 14:25:09,074 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:09,074 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997778914] [2019-12-07 14:25:09,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:09,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:09,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:09,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997778914] [2019-12-07 14:25:09,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:09,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:25:09,142 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462452641] [2019-12-07 14:25:09,142 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 14:25:09,142 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:09,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 14:25:09,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:25:09,142 INFO L87 Difference]: Start difference. First operand 7945 states and 22714 transitions. Second operand 8 states. [2019-12-07 14:25:09,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:09,298 INFO L93 Difference]: Finished difference Result 10259 states and 28848 transitions. [2019-12-07 14:25:09,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 14:25:09,298 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2019-12-07 14:25:09,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:09,309 INFO L225 Difference]: With dead ends: 10259 [2019-12-07 14:25:09,309 INFO L226 Difference]: Without dead ends: 9367 [2019-12-07 14:25:09,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:25:09,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9367 states. [2019-12-07 14:25:09,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9367 to 8003. [2019-12-07 14:25:09,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8003 states. [2019-12-07 14:25:09,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8003 states to 8003 states and 22849 transitions. [2019-12-07 14:25:09,414 INFO L78 Accepts]: Start accepts. Automaton has 8003 states and 22849 transitions. Word has length 37 [2019-12-07 14:25:09,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:09,414 INFO L462 AbstractCegarLoop]: Abstraction has 8003 states and 22849 transitions. [2019-12-07 14:25:09,414 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 14:25:09,414 INFO L276 IsEmpty]: Start isEmpty. Operand 8003 states and 22849 transitions. [2019-12-07 14:25:09,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:09,418 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:09,418 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:09,418 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:09,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:09,418 INFO L82 PathProgramCache]: Analyzing trace with hash 393927768, now seen corresponding path program 3 times [2019-12-07 14:25:09,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:09,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136190268] [2019-12-07 14:25:09,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:09,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:09,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:09,521 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136190268] [2019-12-07 14:25:09,521 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:09,521 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 14:25:09,521 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916880642] [2019-12-07 14:25:09,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 14:25:09,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:09,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 14:25:09,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2019-12-07 14:25:09,522 INFO L87 Difference]: Start difference. First operand 8003 states and 22849 transitions. Second operand 10 states. [2019-12-07 14:25:09,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:09,924 INFO L93 Difference]: Finished difference Result 11000 states and 30786 transitions. [2019-12-07 14:25:09,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 14:25:09,925 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2019-12-07 14:25:09,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:09,933 INFO L225 Difference]: With dead ends: 11000 [2019-12-07 14:25:09,933 INFO L226 Difference]: Without dead ends: 9652 [2019-12-07 14:25:09,934 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 97 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=125, Invalid=427, Unknown=0, NotChecked=0, Total=552 [2019-12-07 14:25:09,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9652 states. [2019-12-07 14:25:10,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9652 to 7985. [2019-12-07 14:25:10,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7985 states. [2019-12-07 14:25:10,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7985 states to 7985 states and 22785 transitions. [2019-12-07 14:25:10,040 INFO L78 Accepts]: Start accepts. Automaton has 7985 states and 22785 transitions. Word has length 37 [2019-12-07 14:25:10,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:10,040 INFO L462 AbstractCegarLoop]: Abstraction has 7985 states and 22785 transitions. [2019-12-07 14:25:10,040 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 14:25:10,040 INFO L276 IsEmpty]: Start isEmpty. Operand 7985 states and 22785 transitions. [2019-12-07 14:25:10,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:10,044 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:10,044 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:10,044 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:10,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:10,045 INFO L82 PathProgramCache]: Analyzing trace with hash 616825358, now seen corresponding path program 4 times [2019-12-07 14:25:10,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:10,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6291870] [2019-12-07 14:25:10,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:10,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:10,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:10,140 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6291870] [2019-12-07 14:25:10,140 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:10,140 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:10,140 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565146964] [2019-12-07 14:25:10,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:10,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:10,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:10,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:10,141 INFO L87 Difference]: Start difference. First operand 7985 states and 22785 transitions. Second operand 11 states. [2019-12-07 14:25:10,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:10,460 INFO L93 Difference]: Finished difference Result 10597 states and 29530 transitions. [2019-12-07 14:25:10,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:25:10,460 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 14:25:10,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:10,469 INFO L225 Difference]: With dead ends: 10597 [2019-12-07 14:25:10,469 INFO L226 Difference]: Without dead ends: 9651 [2019-12-07 14:25:10,469 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=300, Unknown=0, NotChecked=0, Total=380 [2019-12-07 14:25:10,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9651 states. [2019-12-07 14:25:10,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9651 to 8218. [2019-12-07 14:25:10,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8218 states. [2019-12-07 14:25:10,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8218 states to 8218 states and 23246 transitions. [2019-12-07 14:25:10,591 INFO L78 Accepts]: Start accepts. Automaton has 8218 states and 23246 transitions. Word has length 37 [2019-12-07 14:25:10,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:10,591 INFO L462 AbstractCegarLoop]: Abstraction has 8218 states and 23246 transitions. [2019-12-07 14:25:10,591 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:10,591 INFO L276 IsEmpty]: Start isEmpty. Operand 8218 states and 23246 transitions. [2019-12-07 14:25:10,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:10,596 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:10,596 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:10,597 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:10,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:10,597 INFO L82 PathProgramCache]: Analyzing trace with hash -605493120, now seen corresponding path program 5 times [2019-12-07 14:25:10,597 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:10,597 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834084596] [2019-12-07 14:25:10,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:10,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:10,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:10,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834084596] [2019-12-07 14:25:10,673 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:10,673 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 14:25:10,673 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765325534] [2019-12-07 14:25:10,673 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 14:25:10,673 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:10,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 14:25:10,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:25:10,674 INFO L87 Difference]: Start difference. First operand 8218 states and 23246 transitions. Second operand 9 states. [2019-12-07 14:25:10,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:10,828 INFO L93 Difference]: Finished difference Result 9440 states and 26250 transitions. [2019-12-07 14:25:10,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 14:25:10,829 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2019-12-07 14:25:10,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:10,836 INFO L225 Difference]: With dead ends: 9440 [2019-12-07 14:25:10,836 INFO L226 Difference]: Without dead ends: 8636 [2019-12-07 14:25:10,836 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=166, Unknown=0, NotChecked=0, Total=210 [2019-12-07 14:25:10,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8636 states. [2019-12-07 14:25:10,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8636 to 8238. [2019-12-07 14:25:10,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8238 states. [2019-12-07 14:25:10,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8238 states to 8238 states and 23301 transitions. [2019-12-07 14:25:10,937 INFO L78 Accepts]: Start accepts. Automaton has 8238 states and 23301 transitions. Word has length 37 [2019-12-07 14:25:10,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:10,937 INFO L462 AbstractCegarLoop]: Abstraction has 8238 states and 23301 transitions. [2019-12-07 14:25:10,938 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 14:25:10,938 INFO L276 IsEmpty]: Start isEmpty. Operand 8238 states and 23301 transitions. [2019-12-07 14:25:10,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:10,943 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:10,943 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:10,943 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:10,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:10,944 INFO L82 PathProgramCache]: Analyzing trace with hash 1656695050, now seen corresponding path program 6 times [2019-12-07 14:25:10,944 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:10,944 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101500845] [2019-12-07 14:25:10,944 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:10,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:11,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:11,063 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101500845] [2019-12-07 14:25:11,063 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:11,063 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:11,063 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392239354] [2019-12-07 14:25:11,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:11,063 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:11,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:11,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:11,064 INFO L87 Difference]: Start difference. First operand 8238 states and 23301 transitions. Second operand 12 states. [2019-12-07 14:25:11,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:11,651 INFO L93 Difference]: Finished difference Result 13848 states and 38769 transitions. [2019-12-07 14:25:11,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 14:25:11,652 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 37 [2019-12-07 14:25:11,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:11,663 INFO L225 Difference]: With dead ends: 13848 [2019-12-07 14:25:11,663 INFO L226 Difference]: Without dead ends: 12613 [2019-12-07 14:25:11,664 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=175, Invalid=637, Unknown=0, NotChecked=0, Total=812 [2019-12-07 14:25:11,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12613 states. [2019-12-07 14:25:11,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12613 to 8386. [2019-12-07 14:25:11,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8386 states. [2019-12-07 14:25:11,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8386 states to 8386 states and 23650 transitions. [2019-12-07 14:25:11,785 INFO L78 Accepts]: Start accepts. Automaton has 8386 states and 23650 transitions. Word has length 37 [2019-12-07 14:25:11,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:11,786 INFO L462 AbstractCegarLoop]: Abstraction has 8386 states and 23650 transitions. [2019-12-07 14:25:11,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:11,786 INFO L276 IsEmpty]: Start isEmpty. Operand 8386 states and 23650 transitions. [2019-12-07 14:25:11,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:11,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:11,790 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:11,790 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:11,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:11,790 INFO L82 PathProgramCache]: Analyzing trace with hash -2022133604, now seen corresponding path program 7 times [2019-12-07 14:25:11,791 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:11,791 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438195802] [2019-12-07 14:25:11,791 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:11,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:11,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:11,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438195802] [2019-12-07 14:25:11,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:11,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:11,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360240024] [2019-12-07 14:25:11,932 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:11,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:11,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:11,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:11,933 INFO L87 Difference]: Start difference. First operand 8386 states and 23650 transitions. Second operand 13 states. [2019-12-07 14:25:13,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:13,857 INFO L93 Difference]: Finished difference Result 15680 states and 43677 transitions. [2019-12-07 14:25:13,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 14:25:13,858 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 37 [2019-12-07 14:25:13,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:13,871 INFO L225 Difference]: With dead ends: 15680 [2019-12-07 14:25:13,871 INFO L226 Difference]: Without dead ends: 14069 [2019-12-07 14:25:13,872 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 766 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=461, Invalid=2295, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 14:25:13,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14069 states. [2019-12-07 14:25:13,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14069 to 8390. [2019-12-07 14:25:13,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8390 states. [2019-12-07 14:25:14,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8390 states to 8390 states and 23639 transitions. [2019-12-07 14:25:14,008 INFO L78 Accepts]: Start accepts. Automaton has 8390 states and 23639 transitions. Word has length 37 [2019-12-07 14:25:14,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:14,008 INFO L462 AbstractCegarLoop]: Abstraction has 8390 states and 23639 transitions. [2019-12-07 14:25:14,008 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:14,008 INFO L276 IsEmpty]: Start isEmpty. Operand 8390 states and 23639 transitions. [2019-12-07 14:25:14,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:14,013 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:14,013 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:14,013 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:14,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:14,013 INFO L82 PathProgramCache]: Analyzing trace with hash -821771730, now seen corresponding path program 8 times [2019-12-07 14:25:14,013 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:14,013 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618626312] [2019-12-07 14:25:14,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:14,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:14,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:14,090 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618626312] [2019-12-07 14:25:14,090 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:14,090 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 14:25:14,090 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043589282] [2019-12-07 14:25:14,091 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 14:25:14,091 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:14,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 14:25:14,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:25:14,091 INFO L87 Difference]: Start difference. First operand 8390 states and 23639 transitions. Second operand 9 states. [2019-12-07 14:25:14,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:14,279 INFO L93 Difference]: Finished difference Result 10856 states and 30004 transitions. [2019-12-07 14:25:14,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 14:25:14,279 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2019-12-07 14:25:14,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:14,287 INFO L225 Difference]: With dead ends: 10856 [2019-12-07 14:25:14,287 INFO L226 Difference]: Without dead ends: 10052 [2019-12-07 14:25:14,288 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=185, Unknown=0, NotChecked=0, Total=240 [2019-12-07 14:25:14,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10052 states. [2019-12-07 14:25:14,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10052 to 8386. [2019-12-07 14:25:14,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8386 states. [2019-12-07 14:25:14,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8386 states to 8386 states and 23627 transitions. [2019-12-07 14:25:14,395 INFO L78 Accepts]: Start accepts. Automaton has 8386 states and 23627 transitions. Word has length 37 [2019-12-07 14:25:14,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:14,396 INFO L462 AbstractCegarLoop]: Abstraction has 8386 states and 23627 transitions. [2019-12-07 14:25:14,396 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 14:25:14,396 INFO L276 IsEmpty]: Start isEmpty. Operand 8386 states and 23627 transitions. [2019-12-07 14:25:14,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:14,400 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:14,400 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:14,400 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:14,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:14,401 INFO L82 PathProgramCache]: Analyzing trace with hash 1440416440, now seen corresponding path program 9 times [2019-12-07 14:25:14,401 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:14,401 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266426469] [2019-12-07 14:25:14,401 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:14,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:14,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:14,501 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266426469] [2019-12-07 14:25:14,501 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:14,501 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:14,501 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282698474] [2019-12-07 14:25:14,502 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:14,502 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:14,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:14,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:14,502 INFO L87 Difference]: Start difference. First operand 8386 states and 23627 transitions. Second operand 12 states. [2019-12-07 14:25:15,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:15,147 INFO L93 Difference]: Finished difference Result 16629 states and 46451 transitions. [2019-12-07 14:25:15,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 14:25:15,147 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 37 [2019-12-07 14:25:15,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:15,164 INFO L225 Difference]: With dead ends: 16629 [2019-12-07 14:25:15,164 INFO L226 Difference]: Without dead ends: 15171 [2019-12-07 14:25:15,165 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=212, Invalid=910, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 14:25:15,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15171 states. [2019-12-07 14:25:15,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15171 to 8450. [2019-12-07 14:25:15,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8450 states. [2019-12-07 14:25:15,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8450 states to 8450 states and 23790 transitions. [2019-12-07 14:25:15,312 INFO L78 Accepts]: Start accepts. Automaton has 8450 states and 23790 transitions. Word has length 37 [2019-12-07 14:25:15,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:15,312 INFO L462 AbstractCegarLoop]: Abstraction has 8450 states and 23790 transitions. [2019-12-07 14:25:15,312 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:15,312 INFO L276 IsEmpty]: Start isEmpty. Operand 8450 states and 23790 transitions. [2019-12-07 14:25:15,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:15,317 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:15,317 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:15,317 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:15,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:15,317 INFO L82 PathProgramCache]: Analyzing trace with hash 2056555082, now seen corresponding path program 10 times [2019-12-07 14:25:15,318 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:15,318 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449920771] [2019-12-07 14:25:15,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:15,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:15,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:15,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449920771] [2019-12-07 14:25:15,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:15,421 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:15,421 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514562090] [2019-12-07 14:25:15,421 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:15,421 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:15,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:15,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:15,422 INFO L87 Difference]: Start difference. First operand 8450 states and 23790 transitions. Second operand 11 states. [2019-12-07 14:25:15,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:15,996 INFO L93 Difference]: Finished difference Result 11953 states and 32314 transitions. [2019-12-07 14:25:15,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 14:25:15,996 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 14:25:15,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:16,005 INFO L225 Difference]: With dead ends: 11953 [2019-12-07 14:25:16,005 INFO L226 Difference]: Without dead ends: 10621 [2019-12-07 14:25:16,005 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=140, Invalid=616, Unknown=0, NotChecked=0, Total=756 [2019-12-07 14:25:16,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10621 states. [2019-12-07 14:25:16,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10621 to 8498. [2019-12-07 14:25:16,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8498 states. [2019-12-07 14:25:16,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8498 states to 8498 states and 23799 transitions. [2019-12-07 14:25:16,118 INFO L78 Accepts]: Start accepts. Automaton has 8498 states and 23799 transitions. Word has length 37 [2019-12-07 14:25:16,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:16,118 INFO L462 AbstractCegarLoop]: Abstraction has 8498 states and 23799 transitions. [2019-12-07 14:25:16,118 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:16,118 INFO L276 IsEmpty]: Start isEmpty. Operand 8498 states and 23799 transitions. [2019-12-07 14:25:16,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:16,122 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:16,123 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:16,123 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:16,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:16,123 INFO L82 PathProgramCache]: Analyzing trace with hash 582587128, now seen corresponding path program 11 times [2019-12-07 14:25:16,123 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:16,123 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796488322] [2019-12-07 14:25:16,123 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:16,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:16,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:16,236 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796488322] [2019-12-07 14:25:16,237 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:16,237 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:16,237 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210705778] [2019-12-07 14:25:16,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:16,237 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:16,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:16,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:16,237 INFO L87 Difference]: Start difference. First operand 8498 states and 23799 transitions. Second operand 11 states. [2019-12-07 14:25:16,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:16,923 INFO L93 Difference]: Finished difference Result 13316 states and 36957 transitions. [2019-12-07 14:25:16,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 14:25:16,923 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 14:25:16,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:16,931 INFO L225 Difference]: With dead ends: 13316 [2019-12-07 14:25:16,931 INFO L226 Difference]: Without dead ends: 11851 [2019-12-07 14:25:16,932 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=204, Invalid=852, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 14:25:16,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11851 states. [2019-12-07 14:25:17,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11851 to 8490. [2019-12-07 14:25:17,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8490 states. [2019-12-07 14:25:17,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8490 states to 8490 states and 23773 transitions. [2019-12-07 14:25:17,043 INFO L78 Accepts]: Start accepts. Automaton has 8490 states and 23773 transitions. Word has length 37 [2019-12-07 14:25:17,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:17,043 INFO L462 AbstractCegarLoop]: Abstraction has 8490 states and 23773 transitions. [2019-12-07 14:25:17,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:17,044 INFO L276 IsEmpty]: Start isEmpty. Operand 8490 states and 23773 transitions. [2019-12-07 14:25:17,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 14:25:17,048 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:17,048 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:17,048 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:17,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:17,048 INFO L82 PathProgramCache]: Analyzing trace with hash 619776820, now seen corresponding path program 12 times [2019-12-07 14:25:17,048 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:17,048 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591730469] [2019-12-07 14:25:17,049 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:17,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:17,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:17,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591730469] [2019-12-07 14:25:17,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:17,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:17,140 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047607696] [2019-12-07 14:25:17,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:17,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:17,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:17,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:17,140 INFO L87 Difference]: Start difference. First operand 8490 states and 23773 transitions. Second operand 11 states. [2019-12-07 14:25:18,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:18,696 INFO L93 Difference]: Finished difference Result 16759 states and 46578 transitions. [2019-12-07 14:25:18,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 14:25:18,696 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 14:25:18,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:18,712 INFO L225 Difference]: With dead ends: 16759 [2019-12-07 14:25:18,712 INFO L226 Difference]: Without dead ends: 14227 [2019-12-07 14:25:18,713 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 778 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=454, Invalid=1996, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 14:25:18,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14227 states. [2019-12-07 14:25:18,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14227 to 8485. [2019-12-07 14:25:18,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8485 states. [2019-12-07 14:25:18,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8485 states to 8485 states and 23734 transitions. [2019-12-07 14:25:18,849 INFO L78 Accepts]: Start accepts. Automaton has 8485 states and 23734 transitions. Word has length 37 [2019-12-07 14:25:18,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:18,850 INFO L462 AbstractCegarLoop]: Abstraction has 8485 states and 23734 transitions. [2019-12-07 14:25:18,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:18,850 INFO L276 IsEmpty]: Start isEmpty. Operand 8485 states and 23734 transitions. [2019-12-07 14:25:18,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:18,855 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:18,855 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:18,855 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:18,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:18,855 INFO L82 PathProgramCache]: Analyzing trace with hash -1884635564, now seen corresponding path program 1 times [2019-12-07 14:25:18,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:18,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292108050] [2019-12-07 14:25:18,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:18,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:18,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:18,973 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292108050] [2019-12-07 14:25:18,973 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:18,973 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:18,973 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094301561] [2019-12-07 14:25:18,973 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:18,973 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:18,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:18,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:18,973 INFO L87 Difference]: Start difference. First operand 8485 states and 23734 transitions. Second operand 12 states. [2019-12-07 14:25:19,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:19,411 INFO L93 Difference]: Finished difference Result 11448 states and 31739 transitions. [2019-12-07 14:25:19,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 14:25:19,411 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:19,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:19,420 INFO L225 Difference]: With dead ends: 11448 [2019-12-07 14:25:19,420 INFO L226 Difference]: Without dead ends: 10663 [2019-12-07 14:25:19,420 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=307, Unknown=0, NotChecked=0, Total=380 [2019-12-07 14:25:19,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10663 states. [2019-12-07 14:25:19,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10663 to 8552. [2019-12-07 14:25:19,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8552 states. [2019-12-07 14:25:19,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8552 states to 8552 states and 23848 transitions. [2019-12-07 14:25:19,532 INFO L78 Accepts]: Start accepts. Automaton has 8552 states and 23848 transitions. Word has length 38 [2019-12-07 14:25:19,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:19,532 INFO L462 AbstractCegarLoop]: Abstraction has 8552 states and 23848 transitions. [2019-12-07 14:25:19,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:19,532 INFO L276 IsEmpty]: Start isEmpty. Operand 8552 states and 23848 transitions. [2019-12-07 14:25:19,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:19,537 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:19,537 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:19,537 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:19,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:19,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1994366254, now seen corresponding path program 2 times [2019-12-07 14:25:19,537 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:19,537 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125723919] [2019-12-07 14:25:19,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:19,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:19,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:19,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125723919] [2019-12-07 14:25:19,633 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:19,633 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:19,633 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566031766] [2019-12-07 14:25:19,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:19,633 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:19,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:19,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:19,633 INFO L87 Difference]: Start difference. First operand 8552 states and 23848 transitions. Second operand 12 states. [2019-12-07 14:25:20,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:20,050 INFO L93 Difference]: Finished difference Result 11358 states and 31546 transitions. [2019-12-07 14:25:20,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 14:25:20,051 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:20,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:20,060 INFO L225 Difference]: With dead ends: 11358 [2019-12-07 14:25:20,060 INFO L226 Difference]: Without dead ends: 10641 [2019-12-07 14:25:20,060 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=276, Unknown=0, NotChecked=0, Total=342 [2019-12-07 14:25:20,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10641 states. [2019-12-07 14:25:20,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10641 to 8540. [2019-12-07 14:25:20,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8540 states. [2019-12-07 14:25:20,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8540 states to 8540 states and 23826 transitions. [2019-12-07 14:25:20,172 INFO L78 Accepts]: Start accepts. Automaton has 8540 states and 23826 transitions. Word has length 38 [2019-12-07 14:25:20,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:20,172 INFO L462 AbstractCegarLoop]: Abstraction has 8540 states and 23826 transitions. [2019-12-07 14:25:20,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:20,172 INFO L276 IsEmpty]: Start isEmpty. Operand 8540 states and 23826 transitions. [2019-12-07 14:25:20,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:20,177 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:20,177 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:20,177 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:20,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:20,177 INFO L82 PathProgramCache]: Analyzing trace with hash -364081366, now seen corresponding path program 3 times [2019-12-07 14:25:20,177 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:20,177 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069891354] [2019-12-07 14:25:20,177 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:20,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:20,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:20,285 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069891354] [2019-12-07 14:25:20,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:20,285 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:20,285 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387098209] [2019-12-07 14:25:20,285 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:20,285 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:20,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:20,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:20,285 INFO L87 Difference]: Start difference. First operand 8540 states and 23826 transitions. Second operand 12 states. [2019-12-07 14:25:20,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:20,666 INFO L93 Difference]: Finished difference Result 10925 states and 30507 transitions. [2019-12-07 14:25:20,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 14:25:20,666 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:20,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:20,675 INFO L225 Difference]: With dead ends: 10925 [2019-12-07 14:25:20,675 INFO L226 Difference]: Without dead ends: 10370 [2019-12-07 14:25:20,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2019-12-07 14:25:20,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10370 states. [2019-12-07 14:25:20,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10370 to 8536. [2019-12-07 14:25:20,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8536 states. [2019-12-07 14:25:20,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8536 states to 8536 states and 23818 transitions. [2019-12-07 14:25:20,783 INFO L78 Accepts]: Start accepts. Automaton has 8536 states and 23818 transitions. Word has length 38 [2019-12-07 14:25:20,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:20,784 INFO L462 AbstractCegarLoop]: Abstraction has 8536 states and 23818 transitions. [2019-12-07 14:25:20,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:20,784 INFO L276 IsEmpty]: Start isEmpty. Operand 8536 states and 23818 transitions. [2019-12-07 14:25:20,788 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:20,789 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:20,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:20,789 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:20,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:20,789 INFO L82 PathProgramCache]: Analyzing trace with hash 1266913812, now seen corresponding path program 4 times [2019-12-07 14:25:20,789 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:20,789 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088569841] [2019-12-07 14:25:20,789 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:20,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:20,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:20,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088569841] [2019-12-07 14:25:20,895 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:20,895 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:20,895 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951269339] [2019-12-07 14:25:20,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:20,895 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:20,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:20,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:20,896 INFO L87 Difference]: Start difference. First operand 8536 states and 23818 transitions. Second operand 12 states. [2019-12-07 14:25:21,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:21,424 INFO L93 Difference]: Finished difference Result 12123 states and 32992 transitions. [2019-12-07 14:25:21,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 14:25:21,425 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:21,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:21,433 INFO L225 Difference]: With dead ends: 12123 [2019-12-07 14:25:21,433 INFO L226 Difference]: Without dead ends: 10295 [2019-12-07 14:25:21,434 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=101, Invalid=451, Unknown=0, NotChecked=0, Total=552 [2019-12-07 14:25:21,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10295 states. [2019-12-07 14:25:21,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10295 to 8474. [2019-12-07 14:25:21,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8474 states. [2019-12-07 14:25:21,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8474 states to 8474 states and 23691 transitions. [2019-12-07 14:25:21,541 INFO L78 Accepts]: Start accepts. Automaton has 8474 states and 23691 transitions. Word has length 38 [2019-12-07 14:25:21,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:21,541 INFO L462 AbstractCegarLoop]: Abstraction has 8474 states and 23691 transitions. [2019-12-07 14:25:21,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:21,541 INFO L276 IsEmpty]: Start isEmpty. Operand 8474 states and 23691 transitions. [2019-12-07 14:25:21,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:21,546 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:21,546 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:21,546 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:21,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:21,547 INFO L82 PathProgramCache]: Analyzing trace with hash 1454071890, now seen corresponding path program 5 times [2019-12-07 14:25:21,547 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:21,547 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578485341] [2019-12-07 14:25:21,547 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:21,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:21,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:21,668 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578485341] [2019-12-07 14:25:21,668 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:21,668 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:21,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243946213] [2019-12-07 14:25:21,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:21,669 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:21,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:21,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:21,669 INFO L87 Difference]: Start difference. First operand 8474 states and 23691 transitions. Second operand 12 states. [2019-12-07 14:25:22,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:22,154 INFO L93 Difference]: Finished difference Result 11015 states and 30744 transitions. [2019-12-07 14:25:22,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 14:25:22,155 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:22,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:22,163 INFO L225 Difference]: With dead ends: 11015 [2019-12-07 14:25:22,163 INFO L226 Difference]: Without dead ends: 9816 [2019-12-07 14:25:22,163 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 121 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=133, Invalid=569, Unknown=0, NotChecked=0, Total=702 [2019-12-07 14:25:22,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9816 states. [2019-12-07 14:25:22,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9816 to 8131. [2019-12-07 14:25:22,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8131 states. [2019-12-07 14:25:22,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8131 states to 8131 states and 22972 transitions. [2019-12-07 14:25:22,288 INFO L78 Accepts]: Start accepts. Automaton has 8131 states and 22972 transitions. Word has length 38 [2019-12-07 14:25:22,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:22,289 INFO L462 AbstractCegarLoop]: Abstraction has 8131 states and 22972 transitions. [2019-12-07 14:25:22,289 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:22,289 INFO L276 IsEmpty]: Start isEmpty. Operand 8131 states and 22972 transitions. [2019-12-07 14:25:22,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:22,294 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:22,294 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:22,295 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:22,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:22,295 INFO L82 PathProgramCache]: Analyzing trace with hash -321061526, now seen corresponding path program 6 times [2019-12-07 14:25:22,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:22,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23962064] [2019-12-07 14:25:22,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:22,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:22,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:22,394 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23962064] [2019-12-07 14:25:22,394 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:22,395 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:22,395 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603249282] [2019-12-07 14:25:22,395 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:22,395 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:22,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:22,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:22,395 INFO L87 Difference]: Start difference. First operand 8131 states and 22972 transitions. Second operand 11 states. [2019-12-07 14:25:22,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:22,732 INFO L93 Difference]: Finished difference Result 9753 states and 27485 transitions. [2019-12-07 14:25:22,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 14:25:22,732 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 14:25:22,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:22,741 INFO L225 Difference]: With dead ends: 9753 [2019-12-07 14:25:22,741 INFO L226 Difference]: Without dead ends: 8466 [2019-12-07 14:25:22,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=103, Invalid=403, Unknown=0, NotChecked=0, Total=506 [2019-12-07 14:25:22,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8466 states. [2019-12-07 14:25:22,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8466 to 7458. [2019-12-07 14:25:22,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7458 states. [2019-12-07 14:25:22,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7458 states to 7458 states and 21439 transitions. [2019-12-07 14:25:22,842 INFO L78 Accepts]: Start accepts. Automaton has 7458 states and 21439 transitions. Word has length 38 [2019-12-07 14:25:22,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:22,842 INFO L462 AbstractCegarLoop]: Abstraction has 7458 states and 21439 transitions. [2019-12-07 14:25:22,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:22,860 INFO L276 IsEmpty]: Start isEmpty. Operand 7458 states and 21439 transitions. [2019-12-07 14:25:22,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:22,864 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:22,864 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:22,864 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:22,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:22,864 INFO L82 PathProgramCache]: Analyzing trace with hash -642742930, now seen corresponding path program 7 times [2019-12-07 14:25:22,864 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:22,865 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103432949] [2019-12-07 14:25:22,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:22,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:22,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:22,973 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103432949] [2019-12-07 14:25:22,973 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:22,973 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:22,974 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [383419188] [2019-12-07 14:25:22,974 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:22,974 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:22,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:22,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:22,974 INFO L87 Difference]: Start difference. First operand 7458 states and 21439 transitions. Second operand 12 states. [2019-12-07 14:25:23,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:23,494 INFO L93 Difference]: Finished difference Result 13580 states and 39340 transitions. [2019-12-07 14:25:23,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 14:25:23,494 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:23,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:23,504 INFO L225 Difference]: With dead ends: 13580 [2019-12-07 14:25:23,505 INFO L226 Difference]: Without dead ends: 11033 [2019-12-07 14:25:23,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2019-12-07 14:25:23,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11033 states. [2019-12-07 14:25:23,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11033 to 7697. [2019-12-07 14:25:23,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7697 states. [2019-12-07 14:25:23,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7697 states to 7697 states and 22111 transitions. [2019-12-07 14:25:23,615 INFO L78 Accepts]: Start accepts. Automaton has 7697 states and 22111 transitions. Word has length 38 [2019-12-07 14:25:23,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:23,616 INFO L462 AbstractCegarLoop]: Abstraction has 7697 states and 22111 transitions. [2019-12-07 14:25:23,616 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:23,616 INFO L276 IsEmpty]: Start isEmpty. Operand 7697 states and 22111 transitions. [2019-12-07 14:25:23,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:23,620 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:23,620 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:23,620 INFO L410 AbstractCegarLoop]: === Iteration 41 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:23,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:23,621 INFO L82 PathProgramCache]: Analyzing trace with hash 877811268, now seen corresponding path program 8 times [2019-12-07 14:25:23,621 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:23,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402399539] [2019-12-07 14:25:23,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:23,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:23,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:23,735 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402399539] [2019-12-07 14:25:23,735 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:23,735 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:23,735 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082607205] [2019-12-07 14:25:23,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:23,736 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:23,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:23,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:23,736 INFO L87 Difference]: Start difference. First operand 7697 states and 22111 transitions. Second operand 13 states. [2019-12-07 14:25:24,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:24,395 INFO L93 Difference]: Finished difference Result 14421 states and 41678 transitions. [2019-12-07 14:25:24,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 14:25:24,395 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 14:25:24,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:24,406 INFO L225 Difference]: With dead ends: 14421 [2019-12-07 14:25:24,406 INFO L226 Difference]: Without dead ends: 11614 [2019-12-07 14:25:24,407 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=140, Invalid=616, Unknown=0, NotChecked=0, Total=756 [2019-12-07 14:25:24,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11614 states. [2019-12-07 14:25:24,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11614 to 7957. [2019-12-07 14:25:24,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7957 states. [2019-12-07 14:25:24,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7957 states to 7957 states and 22720 transitions. [2019-12-07 14:25:24,525 INFO L78 Accepts]: Start accepts. Automaton has 7957 states and 22720 transitions. Word has length 38 [2019-12-07 14:25:24,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:24,526 INFO L462 AbstractCegarLoop]: Abstraction has 7957 states and 22720 transitions. [2019-12-07 14:25:24,526 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:24,526 INFO L276 IsEmpty]: Start isEmpty. Operand 7957 states and 22720 transitions. [2019-12-07 14:25:24,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:24,530 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:24,530 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:24,530 INFO L410 AbstractCegarLoop]: === Iteration 42 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:24,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:24,530 INFO L82 PathProgramCache]: Analyzing trace with hash -1786160850, now seen corresponding path program 9 times [2019-12-07 14:25:24,530 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:24,530 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856101199] [2019-12-07 14:25:24,531 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:24,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:24,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:24,671 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [856101199] [2019-12-07 14:25:24,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:24,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:24,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231643098] [2019-12-07 14:25:24,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:24,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:24,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:24,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:24,672 INFO L87 Difference]: Start difference. First operand 7957 states and 22720 transitions. Second operand 13 states. [2019-12-07 14:25:25,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:25,375 INFO L93 Difference]: Finished difference Result 15209 states and 43887 transitions. [2019-12-07 14:25:25,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 14:25:25,376 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 14:25:25,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:25,387 INFO L225 Difference]: With dead ends: 15209 [2019-12-07 14:25:25,387 INFO L226 Difference]: Without dead ends: 12538 [2019-12-07 14:25:25,388 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=187, Invalid=805, Unknown=0, NotChecked=0, Total=992 [2019-12-07 14:25:25,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12538 states. [2019-12-07 14:25:25,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12538 to 8185. [2019-12-07 14:25:25,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8185 states. [2019-12-07 14:25:25,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8185 states to 8185 states and 23300 transitions. [2019-12-07 14:25:25,508 INFO L78 Accepts]: Start accepts. Automaton has 8185 states and 23300 transitions. Word has length 38 [2019-12-07 14:25:25,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:25,508 INFO L462 AbstractCegarLoop]: Abstraction has 8185 states and 23300 transitions. [2019-12-07 14:25:25,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:25,508 INFO L276 IsEmpty]: Start isEmpty. Operand 8185 states and 23300 transitions. [2019-12-07 14:25:25,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:25,513 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:25,513 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:25,513 INFO L410 AbstractCegarLoop]: === Iteration 43 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:25,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:25,513 INFO L82 PathProgramCache]: Analyzing trace with hash -897322148, now seen corresponding path program 10 times [2019-12-07 14:25:25,513 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:25,513 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230484828] [2019-12-07 14:25:25,514 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:25,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:25,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:25,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230484828] [2019-12-07 14:25:25,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:25,621 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:25,621 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734515914] [2019-12-07 14:25:25,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:25,621 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:25,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:25,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:25,622 INFO L87 Difference]: Start difference. First operand 8185 states and 23300 transitions. Second operand 12 states. [2019-12-07 14:25:25,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:25,952 INFO L93 Difference]: Finished difference Result 9878 states and 28039 transitions. [2019-12-07 14:25:25,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:25:25,952 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:25,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:25,961 INFO L225 Difference]: With dead ends: 9878 [2019-12-07 14:25:25,961 INFO L226 Difference]: Without dead ends: 9337 [2019-12-07 14:25:25,961 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 70 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=373, Unknown=0, NotChecked=0, Total=462 [2019-12-07 14:25:25,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9337 states. [2019-12-07 14:25:26,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9337 to 8157. [2019-12-07 14:25:26,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8157 states. [2019-12-07 14:25:26,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8157 states to 8157 states and 23251 transitions. [2019-12-07 14:25:26,065 INFO L78 Accepts]: Start accepts. Automaton has 8157 states and 23251 transitions. Word has length 38 [2019-12-07 14:25:26,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:26,065 INFO L462 AbstractCegarLoop]: Abstraction has 8157 states and 23251 transitions. [2019-12-07 14:25:26,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:26,065 INFO L276 IsEmpty]: Start isEmpty. Operand 8157 states and 23251 transitions. [2019-12-07 14:25:26,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:26,069 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:26,069 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:26,070 INFO L410 AbstractCegarLoop]: === Iteration 44 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:26,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:26,070 INFO L82 PathProgramCache]: Analyzing trace with hash -2123833024, now seen corresponding path program 11 times [2019-12-07 14:25:26,070 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:26,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63596710] [2019-12-07 14:25:26,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:26,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:26,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:26,163 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63596710] [2019-12-07 14:25:26,164 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:26,164 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:26,164 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988423748] [2019-12-07 14:25:26,164 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:26,164 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:26,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:26,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:26,164 INFO L87 Difference]: Start difference. First operand 8157 states and 23251 transitions. Second operand 11 states. [2019-12-07 14:25:26,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:26,849 INFO L93 Difference]: Finished difference Result 8821 states and 24889 transitions. [2019-12-07 14:25:26,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 14:25:26,851 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 14:25:26,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:26,863 INFO L225 Difference]: With dead ends: 8821 [2019-12-07 14:25:26,864 INFO L226 Difference]: Without dead ends: 8180 [2019-12-07 14:25:26,864 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=81, Invalid=339, Unknown=0, NotChecked=0, Total=420 [2019-12-07 14:25:26,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8180 states. [2019-12-07 14:25:26,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8180 to 8135. [2019-12-07 14:25:26,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8135 states. [2019-12-07 14:25:26,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8135 states to 8135 states and 23207 transitions. [2019-12-07 14:25:26,968 INFO L78 Accepts]: Start accepts. Automaton has 8135 states and 23207 transitions. Word has length 38 [2019-12-07 14:25:26,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:26,969 INFO L462 AbstractCegarLoop]: Abstraction has 8135 states and 23207 transitions. [2019-12-07 14:25:26,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:26,969 INFO L276 IsEmpty]: Start isEmpty. Operand 8135 states and 23207 transitions. [2019-12-07 14:25:26,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:26,973 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:26,973 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:26,973 INFO L410 AbstractCegarLoop]: === Iteration 45 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:26,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:26,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1954855662, now seen corresponding path program 12 times [2019-12-07 14:25:26,974 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:26,974 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477636028] [2019-12-07 14:25:26,974 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:26,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:27,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:27,040 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477636028] [2019-12-07 14:25:27,040 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:27,040 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 14:25:27,040 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393627142] [2019-12-07 14:25:27,040 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 14:25:27,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:27,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 14:25:27,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 14:25:27,041 INFO L87 Difference]: Start difference. First operand 8135 states and 23207 transitions. Second operand 10 states. [2019-12-07 14:25:27,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:27,371 INFO L93 Difference]: Finished difference Result 15003 states and 43170 transitions. [2019-12-07 14:25:27,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 14:25:27,372 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 38 [2019-12-07 14:25:27,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:27,382 INFO L225 Difference]: With dead ends: 15003 [2019-12-07 14:25:27,382 INFO L226 Difference]: Without dead ends: 12249 [2019-12-07 14:25:27,383 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=129, Invalid=471, Unknown=0, NotChecked=0, Total=600 [2019-12-07 14:25:27,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12249 states. [2019-12-07 14:25:27,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12249 to 8459. [2019-12-07 14:25:27,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8459 states. [2019-12-07 14:25:27,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8459 states to 8459 states and 24070 transitions. [2019-12-07 14:25:27,503 INFO L78 Accepts]: Start accepts. Automaton has 8459 states and 24070 transitions. Word has length 38 [2019-12-07 14:25:27,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:27,503 INFO L462 AbstractCegarLoop]: Abstraction has 8459 states and 24070 transitions. [2019-12-07 14:25:27,504 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 14:25:27,504 INFO L276 IsEmpty]: Start isEmpty. Operand 8459 states and 24070 transitions. [2019-12-07 14:25:27,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:27,508 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:27,508 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:27,509 INFO L410 AbstractCegarLoop]: === Iteration 46 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:27,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:27,509 INFO L82 PathProgramCache]: Analyzing trace with hash 810915238, now seen corresponding path program 13 times [2019-12-07 14:25:27,509 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:27,509 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983702154] [2019-12-07 14:25:27,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:27,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:27,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:27,635 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983702154] [2019-12-07 14:25:27,635 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:27,635 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:27,635 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098324876] [2019-12-07 14:25:27,636 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:27,636 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:27,636 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:27,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:27,636 INFO L87 Difference]: Start difference. First operand 8459 states and 24070 transitions. Second operand 13 states. [2019-12-07 14:25:28,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:28,770 INFO L93 Difference]: Finished difference Result 22477 states and 65049 transitions. [2019-12-07 14:25:28,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 14:25:28,771 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 14:25:28,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:28,791 INFO L225 Difference]: With dead ends: 22477 [2019-12-07 14:25:28,791 INFO L226 Difference]: Without dead ends: 20317 [2019-12-07 14:25:28,792 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 509 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=351, Invalid=1541, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 14:25:28,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20317 states. [2019-12-07 14:25:28,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20317 to 9224. [2019-12-07 14:25:28,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9224 states. [2019-12-07 14:25:28,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9224 states to 9224 states and 26417 transitions. [2019-12-07 14:25:28,976 INFO L78 Accepts]: Start accepts. Automaton has 9224 states and 26417 transitions. Word has length 38 [2019-12-07 14:25:28,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:28,976 INFO L462 AbstractCegarLoop]: Abstraction has 9224 states and 26417 transitions. [2019-12-07 14:25:28,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:28,977 INFO L276 IsEmpty]: Start isEmpty. Operand 9224 states and 26417 transitions. [2019-12-07 14:25:28,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:28,981 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:28,982 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:28,982 INFO L410 AbstractCegarLoop]: === Iteration 47 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:28,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:28,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1427053880, now seen corresponding path program 14 times [2019-12-07 14:25:28,982 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:28,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370083421] [2019-12-07 14:25:28,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:28,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:29,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:29,102 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370083421] [2019-12-07 14:25:29,102 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:29,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:29,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644506436] [2019-12-07 14:25:29,103 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:29,103 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:29,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:29,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:29,103 INFO L87 Difference]: Start difference. First operand 9224 states and 26417 transitions. Second operand 13 states. [2019-12-07 14:25:30,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:30,411 INFO L93 Difference]: Finished difference Result 20579 states and 58989 transitions. [2019-12-07 14:25:30,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 14:25:30,411 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 14:25:30,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:30,428 INFO L225 Difference]: With dead ends: 20579 [2019-12-07 14:25:30,428 INFO L226 Difference]: Without dead ends: 17771 [2019-12-07 14:25:30,429 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 730 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=436, Invalid=2014, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 14:25:30,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17771 states. [2019-12-07 14:25:30,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17771 to 9017. [2019-12-07 14:25:30,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9017 states. [2019-12-07 14:25:30,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9017 states to 9017 states and 25721 transitions. [2019-12-07 14:25:30,588 INFO L78 Accepts]: Start accepts. Automaton has 9017 states and 25721 transitions. Word has length 38 [2019-12-07 14:25:30,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:30,588 INFO L462 AbstractCegarLoop]: Abstraction has 9017 states and 25721 transitions. [2019-12-07 14:25:30,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:30,588 INFO L276 IsEmpty]: Start isEmpty. Operand 9017 states and 25721 transitions. [2019-12-07 14:25:30,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:30,593 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:30,594 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:30,594 INFO L410 AbstractCegarLoop]: === Iteration 48 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:30,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:30,594 INFO L82 PathProgramCache]: Analyzing trace with hash 323181576, now seen corresponding path program 15 times [2019-12-07 14:25:30,594 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:30,594 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325638993] [2019-12-07 14:25:30,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:30,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:30,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:30,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325638993] [2019-12-07 14:25:30,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:30,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 14:25:30,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428500569] [2019-12-07 14:25:30,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 14:25:30,692 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:30,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 14:25:30,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:25:30,692 INFO L87 Difference]: Start difference. First operand 9017 states and 25721 transitions. Second operand 11 states. [2019-12-07 14:25:30,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:30,926 INFO L93 Difference]: Finished difference Result 9516 states and 27038 transitions. [2019-12-07 14:25:30,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 14:25:30,926 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 14:25:30,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:30,934 INFO L225 Difference]: With dead ends: 9516 [2019-12-07 14:25:30,934 INFO L226 Difference]: Without dead ends: 8995 [2019-12-07 14:25:30,934 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-12-07 14:25:30,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8995 states. [2019-12-07 14:25:31,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8995 to 8995. [2019-12-07 14:25:31,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8995 states. [2019-12-07 14:25:31,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8995 states to 8995 states and 25677 transitions. [2019-12-07 14:25:31,040 INFO L78 Accepts]: Start accepts. Automaton has 8995 states and 25677 transitions. Word has length 38 [2019-12-07 14:25:31,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:31,040 INFO L462 AbstractCegarLoop]: Abstraction has 8995 states and 25677 transitions. [2019-12-07 14:25:31,040 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 14:25:31,040 INFO L276 IsEmpty]: Start isEmpty. Operand 8995 states and 25677 transitions. [2019-12-07 14:25:31,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:31,045 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:31,045 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:31,045 INFO L410 AbstractCegarLoop]: === Iteration 49 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:31,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:31,046 INFO L82 PathProgramCache]: Analyzing trace with hash -1833354344, now seen corresponding path program 16 times [2019-12-07 14:25:31,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:31,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015415824] [2019-12-07 14:25:31,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:31,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:31,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:31,145 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015415824] [2019-12-07 14:25:31,145 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:31,145 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:31,145 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288234480] [2019-12-07 14:25:31,145 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:31,145 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:31,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:31,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:31,145 INFO L87 Difference]: Start difference. First operand 8995 states and 25677 transitions. Second operand 12 states. [2019-12-07 14:25:32,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:32,215 INFO L93 Difference]: Finished difference Result 23927 states and 68951 transitions. [2019-12-07 14:25:32,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 14:25:32,215 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:32,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:32,236 INFO L225 Difference]: With dead ends: 23927 [2019-12-07 14:25:32,237 INFO L226 Difference]: Without dead ends: 21875 [2019-12-07 14:25:32,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 449 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=318, Invalid=1404, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 14:25:32,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21875 states. [2019-12-07 14:25:32,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21875 to 9383. [2019-12-07 14:25:32,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9383 states. [2019-12-07 14:25:32,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9383 states to 9383 states and 26934 transitions. [2019-12-07 14:25:32,425 INFO L78 Accepts]: Start accepts. Automaton has 9383 states and 26934 transitions. Word has length 38 [2019-12-07 14:25:32,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:32,426 INFO L462 AbstractCegarLoop]: Abstraction has 9383 states and 26934 transitions. [2019-12-07 14:25:32,426 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:32,426 INFO L276 IsEmpty]: Start isEmpty. Operand 9383 states and 26934 transitions. [2019-12-07 14:25:32,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:32,431 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:32,431 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:32,431 INFO L410 AbstractCegarLoop]: === Iteration 50 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:32,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:32,432 INFO L82 PathProgramCache]: Analyzing trace with hash -1217215702, now seen corresponding path program 17 times [2019-12-07 14:25:32,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:32,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095835782] [2019-12-07 14:25:32,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:32,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:32,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:32,533 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095835782] [2019-12-07 14:25:32,533 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:32,533 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:25:32,533 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624349827] [2019-12-07 14:25:32,533 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:25:32,533 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:32,533 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:25:32,533 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:25:32,534 INFO L87 Difference]: Start difference. First operand 9383 states and 26934 transitions. Second operand 12 states. [2019-12-07 14:25:33,997 WARN L192 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 26 [2019-12-07 14:25:34,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:34,473 INFO L93 Difference]: Finished difference Result 23138 states and 66096 transitions. [2019-12-07 14:25:34,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 14:25:34,474 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 14:25:34,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:34,493 INFO L225 Difference]: With dead ends: 23138 [2019-12-07 14:25:34,493 INFO L226 Difference]: Without dead ends: 19466 [2019-12-07 14:25:34,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 973 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=524, Invalid=2556, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 14:25:34,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19466 states. [2019-12-07 14:25:34,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19466 to 8969. [2019-12-07 14:25:34,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8969 states. [2019-12-07 14:25:34,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8969 states to 8969 states and 25610 transitions. [2019-12-07 14:25:34,666 INFO L78 Accepts]: Start accepts. Automaton has 8969 states and 25610 transitions. Word has length 38 [2019-12-07 14:25:34,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:34,666 INFO L462 AbstractCegarLoop]: Abstraction has 8969 states and 25610 transitions. [2019-12-07 14:25:34,666 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:25:34,666 INFO L276 IsEmpty]: Start isEmpty. Operand 8969 states and 25610 transitions. [2019-12-07 14:25:34,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:34,672 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:34,672 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:34,672 INFO L410 AbstractCegarLoop]: === Iteration 51 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:34,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:34,672 INFO L82 PathProgramCache]: Analyzing trace with hash 848104930, now seen corresponding path program 18 times [2019-12-07 14:25:34,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:34,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14488009] [2019-12-07 14:25:34,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:34,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:34,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:34,731 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14488009] [2019-12-07 14:25:34,731 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:34,731 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:25:34,731 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001298773] [2019-12-07 14:25:34,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 14:25:34,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:34,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 14:25:34,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:25:34,732 INFO L87 Difference]: Start difference. First operand 8969 states and 25610 transitions. Second operand 8 states. [2019-12-07 14:25:34,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:34,924 INFO L93 Difference]: Finished difference Result 10495 states and 29954 transitions. [2019-12-07 14:25:34,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 14:25:34,924 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2019-12-07 14:25:34,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:34,933 INFO L225 Difference]: With dead ends: 10495 [2019-12-07 14:25:34,933 INFO L226 Difference]: Without dead ends: 9929 [2019-12-07 14:25:34,933 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2019-12-07 14:25:34,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9929 states. [2019-12-07 14:25:35,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9929 to 8929. [2019-12-07 14:25:35,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8929 states. [2019-12-07 14:25:35,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8929 states to 8929 states and 25519 transitions. [2019-12-07 14:25:35,045 INFO L78 Accepts]: Start accepts. Automaton has 8929 states and 25519 transitions. Word has length 38 [2019-12-07 14:25:35,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:35,046 INFO L462 AbstractCegarLoop]: Abstraction has 8929 states and 25519 transitions. [2019-12-07 14:25:35,046 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 14:25:35,046 INFO L276 IsEmpty]: Start isEmpty. Operand 8929 states and 25519 transitions. [2019-12-07 14:25:35,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 14:25:35,051 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:35,051 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:35,051 INFO L410 AbstractCegarLoop]: === Iteration 52 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:35,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:35,051 INFO L82 PathProgramCache]: Analyzing trace with hash 2089288892, now seen corresponding path program 1 times [2019-12-07 14:25:35,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:35,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445399777] [2019-12-07 14:25:35,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:35,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:35,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:35,078 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445399777] [2019-12-07 14:25:35,079 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:35,079 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:25:35,079 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385278469] [2019-12-07 14:25:35,079 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:25:35,079 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:35,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:25:35,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:25:35,079 INFO L87 Difference]: Start difference. First operand 8929 states and 25519 transitions. Second operand 4 states. [2019-12-07 14:25:35,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:35,090 INFO L93 Difference]: Finished difference Result 1327 states and 2574 transitions. [2019-12-07 14:25:35,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:25:35,090 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2019-12-07 14:25:35,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:35,091 INFO L225 Difference]: With dead ends: 1327 [2019-12-07 14:25:35,091 INFO L226 Difference]: Without dead ends: 1271 [2019-12-07 14:25:35,091 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:25:35,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1271 states. [2019-12-07 14:25:35,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1271 to 1253. [2019-12-07 14:25:35,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1253 states. [2019-12-07 14:25:35,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 2449 transitions. [2019-12-07 14:25:35,101 INFO L78 Accepts]: Start accepts. Automaton has 1253 states and 2449 transitions. Word has length 38 [2019-12-07 14:25:35,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:35,101 INFO L462 AbstractCegarLoop]: Abstraction has 1253 states and 2449 transitions. [2019-12-07 14:25:35,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:25:35,101 INFO L276 IsEmpty]: Start isEmpty. Operand 1253 states and 2449 transitions. [2019-12-07 14:25:35,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 14:25:35,102 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:35,102 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:35,102 INFO L410 AbstractCegarLoop]: === Iteration 53 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:35,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:35,102 INFO L82 PathProgramCache]: Analyzing trace with hash 2121919124, now seen corresponding path program 1 times [2019-12-07 14:25:35,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:35,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596629366] [2019-12-07 14:25:35,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:35,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:35,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:35,131 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596629366] [2019-12-07 14:25:35,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:35,131 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:25:35,132 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490858207] [2019-12-07 14:25:35,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:25:35,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:35,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:25:35,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:25:35,132 INFO L87 Difference]: Start difference. First operand 1253 states and 2449 transitions. Second operand 5 states. [2019-12-07 14:25:35,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:35,146 INFO L93 Difference]: Finished difference Result 301 states and 528 transitions. [2019-12-07 14:25:35,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:25:35,146 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 14:25:35,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:35,146 INFO L225 Difference]: With dead ends: 301 [2019-12-07 14:25:35,146 INFO L226 Difference]: Without dead ends: 239 [2019-12-07 14:25:35,147 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:25:35,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2019-12-07 14:25:35,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 207. [2019-12-07 14:25:35,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-12-07 14:25:35,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 366 transitions. [2019-12-07 14:25:35,149 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 366 transitions. Word has length 45 [2019-12-07 14:25:35,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:35,150 INFO L462 AbstractCegarLoop]: Abstraction has 207 states and 366 transitions. [2019-12-07 14:25:35,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:25:35,150 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 366 transitions. [2019-12-07 14:25:35,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 14:25:35,150 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:35,150 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:35,150 INFO L410 AbstractCegarLoop]: === Iteration 54 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:35,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:35,151 INFO L82 PathProgramCache]: Analyzing trace with hash -1590264344, now seen corresponding path program 1 times [2019-12-07 14:25:35,151 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:35,151 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436657852] [2019-12-07 14:25:35,151 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:35,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:35,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:35,325 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436657852] [2019-12-07 14:25:35,325 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:35,325 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:35,325 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934347568] [2019-12-07 14:25:35,325 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:35,325 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:35,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:35,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:35,326 INFO L87 Difference]: Start difference. First operand 207 states and 366 transitions. Second operand 13 states. [2019-12-07 14:25:35,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:35,643 INFO L93 Difference]: Finished difference Result 357 states and 614 transitions. [2019-12-07 14:25:35,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 14:25:35,643 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2019-12-07 14:25:35,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:35,644 INFO L225 Difference]: With dead ends: 357 [2019-12-07 14:25:35,644 INFO L226 Difference]: Without dead ends: 239 [2019-12-07 14:25:35,644 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=85, Invalid=421, Unknown=0, NotChecked=0, Total=506 [2019-12-07 14:25:35,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2019-12-07 14:25:35,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 215. [2019-12-07 14:25:35,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2019-12-07 14:25:35,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 376 transitions. [2019-12-07 14:25:35,647 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 376 transitions. Word has length 56 [2019-12-07 14:25:35,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:35,647 INFO L462 AbstractCegarLoop]: Abstraction has 215 states and 376 transitions. [2019-12-07 14:25:35,647 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:35,647 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 376 transitions. [2019-12-07 14:25:35,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 14:25:35,647 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:35,647 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:35,648 INFO L410 AbstractCegarLoop]: === Iteration 55 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:35,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:35,648 INFO L82 PathProgramCache]: Analyzing trace with hash 1710889504, now seen corresponding path program 2 times [2019-12-07 14:25:35,648 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:35,648 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913172723] [2019-12-07 14:25:35,648 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:35,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:35,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:35,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913172723] [2019-12-07 14:25:35,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:35,799 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:25:35,799 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638485466] [2019-12-07 14:25:35,799 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:25:35,799 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-12-07 14:25:35,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:25:35,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:25:35,800 INFO L87 Difference]: Start difference. First operand 215 states and 376 transitions. Second operand 13 states. [2019-12-07 14:25:36,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:36,003 INFO L93 Difference]: Finished difference Result 301 states and 504 transitions. [2019-12-07 14:25:36,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 14:25:36,003 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2019-12-07 14:25:36,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:36,003 INFO L225 Difference]: With dead ends: 301 [2019-12-07 14:25:36,003 INFO L226 Difference]: Without dead ends: 191 [2019-12-07 14:25:36,004 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=337, Unknown=0, NotChecked=0, Total=420 [2019-12-07 14:25:36,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2019-12-07 14:25:36,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 191. [2019-12-07 14:25:36,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2019-12-07 14:25:36,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 330 transitions. [2019-12-07 14:25:36,005 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 330 transitions. Word has length 56 [2019-12-07 14:25:36,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:36,005 INFO L462 AbstractCegarLoop]: Abstraction has 191 states and 330 transitions. [2019-12-07 14:25:36,005 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:25:36,005 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 330 transitions. [2019-12-07 14:25:36,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 14:25:36,006 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:36,006 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:36,006 INFO L410 AbstractCegarLoop]: === Iteration 56 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:36,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:36,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1475134232, now seen corresponding path program 3 times [2019-12-07 14:25:36,006 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-12-07 14:25:36,006 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530992503] [2019-12-07 14:25:36,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:36,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:25:36,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:25:36,064 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-12-07 14:25:36,065 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:25:36,067 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2492~0.base_27|) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= 0 v_~y$r_buff0_thd2~0_108) (= (store .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27| 1) |v_#valid_59|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27|)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2492~0.base_27| 4) |v_#length_25|) (= 0 |v_ULTIMATE.start_main_~#t2492~0.offset_20|) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27|) |v_ULTIMATE.start_main_~#t2492~0.offset_20| 0))) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_20|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_16|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_17|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_~#t2492~0.offset=|v_ULTIMATE.start_main_~#t2492~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_20|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2492~0.base=|v_ULTIMATE.start_main_~#t2492~0.base_27|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t2494~0.base, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_~#t2494~0.offset, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2492~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2493~0.base, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2492~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:25:36,067 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2493~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t2493~0.offset_9| 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9| 1)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9|) |v_ULTIMATE.start_main_~#t2493~0.offset_9| 1))) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2493~0.base_9| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2493~0.base] because there is no mapped edge [2019-12-07 14:25:36,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10|) |v_ULTIMATE.start_main_~#t2494~0.offset_9| 2)) |v_#memory_int_11|) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10| 1) |v_#valid_31|) (not (= 0 |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2494~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2494~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2494~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2494~0.offset] because there is no mapped edge [2019-12-07 14:25:36,068 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0_#in~arg.offset_In1995149116| P2Thread1of1ForFork0_~arg.offset_Out1995149116) (= P2Thread1of1ForFork0_~arg.base_Out1995149116 |P2Thread1of1ForFork0_#in~arg.base_In1995149116|) (= 1 ~y$w_buff0_used~0_Out1995149116) (= ~y$w_buff0~0_Out1995149116 2) (= (ite (not (and (not (= 0 (mod ~y$w_buff0_used~0_Out1995149116 256))) (not (= 0 (mod ~y$w_buff1_used~0_Out1995149116 256))))) 1 0) |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|) (= ~y$w_buff0~0_In1995149116 ~y$w_buff1~0_Out1995149116) (= ~y$w_buff1_used~0_Out1995149116 ~y$w_buff0_used~0_In1995149116) (not (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116 0)) (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116 |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In1995149116|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, ~y$w_buff0~0=~y$w_buff0~0_In1995149116, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In1995149116|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out1995149116, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In1995149116|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out1995149116, ~y$w_buff1~0=~y$w_buff1~0_Out1995149116, ~y$w_buff0~0=~y$w_buff0~0_Out1995149116, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out1995149116, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In1995149116|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out1995149116} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:25:36,069 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 14:25:36,069 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In2115763753 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2115763753 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out2115763753|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In2115763753 |P2Thread1of1ForFork0_#t~ite11_Out2115763753|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2115763753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2115763753} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2115763753, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out2115763753|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2115763753} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 14:25:36,069 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| |P1Thread1of1ForFork2_#t~ite4_Out1064713212|)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1064713212 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1064713212 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| ~y$w_buff1~0_In1064713212) (not .cse0) .cse1 (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| ~y~0_In1064713212)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1064713212, ~y$w_buff1~0=~y$w_buff1~0_In1064713212, ~y~0=~y~0_In1064713212, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1064713212} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1064713212, ~y$w_buff1~0=~y$w_buff1~0_In1064713212, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out1064713212|, ~y~0=~y~0_In1064713212, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1064713212|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1064713212} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:25:36,070 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-332330525 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In-332330525 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-332330525 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-332330525 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-332330525 |P2Thread1of1ForFork0_#t~ite12_Out-332330525|)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-332330525|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-332330525, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-332330525, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-332330525, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-332330525} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-332330525, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-332330525, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-332330525|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-332330525, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-332330525} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 14:25:36,070 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-211971094 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-211971094 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-211971094|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-211971094 |P1Thread1of1ForFork2_#t~ite5_Out-211971094|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-211971094, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-211971094} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-211971094, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-211971094, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-211971094|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1444390538 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1444390538 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1444390538 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd2~0_In-1444390538 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-1444390538 |P1Thread1of1ForFork2_#t~ite6_Out-1444390538|) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-1444390538|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1444390538, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1444390538, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1444390538, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1444390538} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1444390538, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1444390538, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1444390538, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-1444390538|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1444390538} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In659112573 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In659112573 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite7_Out659112573| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite7_Out659112573| ~y$r_buff0_thd2~0_In659112573) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In659112573} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In659112573, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out659112573|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In734023225 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In734023225 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In734023225 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In734023225 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out734023225|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In734023225 |P1Thread1of1ForFork2_#t~ite8_Out734023225|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In734023225, ~y$w_buff0_used~0=~y$w_buff0_used~0_In734023225, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In734023225, ~y$w_buff1_used~0=~y$w_buff1_used~0_In734023225} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In734023225, ~y$w_buff0_used~0=~y$w_buff0_used~0_In734023225, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out734023225|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In734023225, ~y$w_buff1_used~0=~y$w_buff1_used~0_In734023225} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In730952048 256))) (.cse2 (= ~y$r_buff0_thd3~0_In730952048 ~y$r_buff0_thd3~0_Out730952048)) (.cse0 (= (mod ~y$w_buff0_used~0_In730952048 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out730952048 0) (not .cse0) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In730952048, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In730952048} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In730952048, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out730952048, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out730952048|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd3~0_In48365534 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In48365534 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In48365534 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In48365534 256)))) (or (and (= ~y$r_buff1_thd3~0_In48365534 |P2Thread1of1ForFork0_#t~ite14_Out48365534|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out48365534|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In48365534, ~y$w_buff0_used~0=~y$w_buff0_used~0_In48365534, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In48365534, ~y$w_buff1_used~0=~y$w_buff1_used~0_In48365534} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out48365534|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In48365534, ~y$w_buff0_used~0=~y$w_buff0_used~0_In48365534, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In48365534, ~y$w_buff1_used~0=~y$w_buff1_used~0_In48365534} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 14:25:36,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 14:25:36,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 14:25:36,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-1112150713| |ULTIMATE.start_main_#t~ite18_Out-1112150713|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1112150713 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-1112150713 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out-1112150713| ~y$w_buff1~0_In-1112150713) .cse0 (not .cse1) (not .cse2)) (and .cse0 (or .cse2 .cse1) (= ~y~0_In-1112150713 |ULTIMATE.start_main_#t~ite18_Out-1112150713|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1112150713, ~y~0=~y~0_In-1112150713, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1112150713, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1112150713} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1112150713, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1112150713|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1112150713|, ~y~0=~y~0_In-1112150713, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1112150713, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1112150713} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:25:36,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1915576892 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1915576892 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1915576892| ~y$w_buff0_used~0_In-1915576892)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1915576892| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1915576892, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1915576892} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1915576892, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1915576892, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1915576892|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:25:36,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In2146070796 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In2146070796 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In2146070796 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In2146070796 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out2146070796| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$w_buff1_used~0_In2146070796 |ULTIMATE.start_main_#t~ite21_Out2146070796|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2146070796, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2146070796, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2146070796, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2146070796} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2146070796, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2146070796, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out2146070796|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2146070796, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2146070796} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:25:36,073 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1350341585 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1350341585 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-1350341585| 0)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd0~0_In-1350341585 |ULTIMATE.start_main_#t~ite22_Out-1350341585|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1350341585|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:25:36,073 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-1792641108 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-1792641108 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1792641108 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1792641108 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite23_Out-1792641108| ~y$r_buff1_thd0~0_In-1792641108)) (and (= |ULTIMATE.start_main_#t~ite23_Out-1792641108| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1792641108, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1792641108, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1792641108, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1792641108, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1792641108, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1792641108, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1792641108|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:25:36,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In444173124 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite29_In444173124| |ULTIMATE.start_main_#t~ite29_Out444173124|) (= |ULTIMATE.start_main_#t~ite30_Out444173124| ~y$w_buff0~0_In444173124)) (and (= |ULTIMATE.start_main_#t~ite30_Out444173124| |ULTIMATE.start_main_#t~ite29_Out444173124|) .cse0 (= ~y$w_buff0~0_In444173124 |ULTIMATE.start_main_#t~ite29_Out444173124|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In444173124 256)))) (or (and (= (mod ~y$r_buff1_thd0~0_In444173124 256) 0) .cse1) (= (mod ~y$w_buff0_used~0_In444173124 256) 0) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In444173124 256)))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In444173124, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In444173124|, ~y$w_buff0~0=~y$w_buff0~0_In444173124, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In444173124, ~weak$$choice2~0=~weak$$choice2~0_In444173124, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In444173124, ~y$w_buff1_used~0=~y$w_buff1_used~0_In444173124} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out444173124|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In444173124, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out444173124|, ~y$w_buff0~0=~y$w_buff0~0_In444173124, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In444173124, ~weak$$choice2~0=~weak$$choice2~0_In444173124, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In444173124, ~y$w_buff1_used~0=~y$w_buff1_used~0_In444173124} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 14:25:36,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1237046549 256)))) (or (and (= |ULTIMATE.start_main_#t~ite33_Out-1237046549| |ULTIMATE.start_main_#t~ite32_Out-1237046549|) (= ~y$w_buff1~0_In-1237046549 |ULTIMATE.start_main_#t~ite32_Out-1237046549|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1237046549 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-1237046549 256) 0)) (= 0 (mod ~y$w_buff0_used~0_In-1237046549 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-1237046549 256)) .cse1)))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1237046549| |ULTIMATE.start_main_#t~ite32_Out-1237046549|) (= ~y$w_buff1~0_In-1237046549 |ULTIMATE.start_main_#t~ite33_Out-1237046549|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1237046549, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1237046549, ~weak$$choice2~0=~weak$$choice2~0_In-1237046549, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1237046549, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1237046549|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1237046549} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1237046549, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1237046549, ~weak$$choice2~0=~weak$$choice2~0_In-1237046549, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1237046549|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1237046549, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1237046549|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1237046549} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 14:25:36,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1987365611 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite35_In-1987365611| |ULTIMATE.start_main_#t~ite35_Out-1987365611|) (not .cse0) (= |ULTIMATE.start_main_#t~ite36_Out-1987365611| ~y$w_buff0_used~0_In-1987365611)) (and (= |ULTIMATE.start_main_#t~ite35_Out-1987365611| ~y$w_buff0_used~0_In-1987365611) (= |ULTIMATE.start_main_#t~ite36_Out-1987365611| |ULTIMATE.start_main_#t~ite35_Out-1987365611|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1987365611 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-1987365611 256) 0)) (= (mod ~y$w_buff0_used~0_In-1987365611 256) 0) (and (= (mod ~y$r_buff1_thd0~0_In-1987365611 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1987365611, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-1987365611|, ~weak$$choice2~0=~weak$$choice2~0_In-1987365611, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1987365611, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-1987365611|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-1987365611|, ~weak$$choice2~0=~weak$$choice2~0_In-1987365611, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 14:25:36,075 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 14:25:36,075 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:25:36,075 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:25:36,124 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:25:36 BasicIcfg [2019-12-07 14:25:36,125 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:25:36,125 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:25:36,125 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:25:36,125 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:25:36,125 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:24:48" (3/4) ... [2019-12-07 14:25:36,127 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:25:36,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2492~0.base_27|) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= 0 v_~y$r_buff0_thd2~0_108) (= (store .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27| 1) |v_#valid_59|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27|)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2492~0.base_27| 4) |v_#length_25|) (= 0 |v_ULTIMATE.start_main_~#t2492~0.offset_20|) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27|) |v_ULTIMATE.start_main_~#t2492~0.offset_20| 0))) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_20|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_16|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_17|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_~#t2492~0.offset=|v_ULTIMATE.start_main_~#t2492~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_20|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2492~0.base=|v_ULTIMATE.start_main_~#t2492~0.base_27|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t2494~0.base, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_~#t2494~0.offset, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2492~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2493~0.base, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2492~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:25:36,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2493~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t2493~0.offset_9| 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9| 1)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9|) |v_ULTIMATE.start_main_~#t2493~0.offset_9| 1))) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2493~0.base_9| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2493~0.base] because there is no mapped edge [2019-12-07 14:25:36,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10|) |v_ULTIMATE.start_main_~#t2494~0.offset_9| 2)) |v_#memory_int_11|) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10| 1) |v_#valid_31|) (not (= 0 |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2494~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2494~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2494~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2494~0.offset] because there is no mapped edge [2019-12-07 14:25:36,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0_#in~arg.offset_In1995149116| P2Thread1of1ForFork0_~arg.offset_Out1995149116) (= P2Thread1of1ForFork0_~arg.base_Out1995149116 |P2Thread1of1ForFork0_#in~arg.base_In1995149116|) (= 1 ~y$w_buff0_used~0_Out1995149116) (= ~y$w_buff0~0_Out1995149116 2) (= (ite (not (and (not (= 0 (mod ~y$w_buff0_used~0_Out1995149116 256))) (not (= 0 (mod ~y$w_buff1_used~0_Out1995149116 256))))) 1 0) |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|) (= ~y$w_buff0~0_In1995149116 ~y$w_buff1~0_Out1995149116) (= ~y$w_buff1_used~0_Out1995149116 ~y$w_buff0_used~0_In1995149116) (not (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116 0)) (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116 |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In1995149116|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, ~y$w_buff0~0=~y$w_buff0~0_In1995149116, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In1995149116|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out1995149116, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out1995149116|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In1995149116|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out1995149116, ~y$w_buff1~0=~y$w_buff1~0_Out1995149116, ~y$w_buff0~0=~y$w_buff0~0_Out1995149116, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out1995149116, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In1995149116|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out1995149116, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out1995149116} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:25:36,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 14:25:36,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In2115763753 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2115763753 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out2115763753|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In2115763753 |P2Thread1of1ForFork0_#t~ite11_Out2115763753|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2115763753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2115763753} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2115763753, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out2115763753|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2115763753} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 14:25:36,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| |P1Thread1of1ForFork2_#t~ite4_Out1064713212|)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1064713212 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1064713212 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| ~y$w_buff1~0_In1064713212) (not .cse0) .cse1 (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out1064713212| ~y~0_In1064713212)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1064713212, ~y$w_buff1~0=~y$w_buff1~0_In1064713212, ~y~0=~y~0_In1064713212, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1064713212} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1064713212, ~y$w_buff1~0=~y$w_buff1~0_In1064713212, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out1064713212|, ~y~0=~y~0_In1064713212, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1064713212|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1064713212} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:25:36,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-332330525 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In-332330525 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-332330525 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-332330525 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-332330525 |P2Thread1of1ForFork0_#t~ite12_Out-332330525|)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-332330525|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-332330525, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-332330525, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-332330525, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-332330525} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-332330525, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-332330525, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-332330525|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-332330525, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-332330525} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 14:25:36,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-211971094 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-211971094 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-211971094|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-211971094 |P1Thread1of1ForFork2_#t~ite5_Out-211971094|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-211971094, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-211971094} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-211971094, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-211971094, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-211971094|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:25:36,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1444390538 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1444390538 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1444390538 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd2~0_In-1444390538 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-1444390538 |P1Thread1of1ForFork2_#t~ite6_Out-1444390538|) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-1444390538|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1444390538, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1444390538, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1444390538, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1444390538} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1444390538, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1444390538, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1444390538, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-1444390538|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1444390538} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In659112573 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In659112573 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite7_Out659112573| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite7_Out659112573| ~y$r_buff0_thd2~0_In659112573) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In659112573} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In659112573, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out659112573|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In734023225 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In734023225 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In734023225 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In734023225 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out734023225|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In734023225 |P1Thread1of1ForFork2_#t~ite8_Out734023225|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In734023225, ~y$w_buff0_used~0=~y$w_buff0_used~0_In734023225, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In734023225, ~y$w_buff1_used~0=~y$w_buff1_used~0_In734023225} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In734023225, ~y$w_buff0_used~0=~y$w_buff0_used~0_In734023225, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out734023225|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In734023225, ~y$w_buff1_used~0=~y$w_buff1_used~0_In734023225} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In730952048 256))) (.cse2 (= ~y$r_buff0_thd3~0_In730952048 ~y$r_buff0_thd3~0_Out730952048)) (.cse0 (= (mod ~y$w_buff0_used~0_In730952048 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out730952048 0) (not .cse0) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In730952048, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In730952048} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In730952048, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out730952048, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out730952048|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd3~0_In48365534 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In48365534 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In48365534 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In48365534 256)))) (or (and (= ~y$r_buff1_thd3~0_In48365534 |P2Thread1of1ForFork0_#t~ite14_Out48365534|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out48365534|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In48365534, ~y$w_buff0_used~0=~y$w_buff0_used~0_In48365534, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In48365534, ~y$w_buff1_used~0=~y$w_buff1_used~0_In48365534} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out48365534|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In48365534, ~y$w_buff0_used~0=~y$w_buff0_used~0_In48365534, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In48365534, ~y$w_buff1_used~0=~y$w_buff1_used~0_In48365534} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 14:25:36,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 14:25:36,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-1112150713| |ULTIMATE.start_main_#t~ite18_Out-1112150713|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1112150713 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-1112150713 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out-1112150713| ~y$w_buff1~0_In-1112150713) .cse0 (not .cse1) (not .cse2)) (and .cse0 (or .cse2 .cse1) (= ~y~0_In-1112150713 |ULTIMATE.start_main_#t~ite18_Out-1112150713|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1112150713, ~y~0=~y~0_In-1112150713, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1112150713, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1112150713} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1112150713, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1112150713|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1112150713|, ~y~0=~y~0_In-1112150713, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1112150713, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1112150713} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:25:36,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1915576892 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1915576892 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1915576892| ~y$w_buff0_used~0_In-1915576892)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1915576892| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1915576892, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1915576892} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1915576892, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1915576892, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1915576892|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:25:36,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In2146070796 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In2146070796 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In2146070796 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In2146070796 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out2146070796| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$w_buff1_used~0_In2146070796 |ULTIMATE.start_main_#t~ite21_Out2146070796|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2146070796, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2146070796, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2146070796, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2146070796} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2146070796, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2146070796, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out2146070796|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2146070796, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2146070796} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:25:36,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1350341585 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1350341585 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-1350341585| 0)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd0~0_In-1350341585 |ULTIMATE.start_main_#t~ite22_Out-1350341585|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1350341585|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:25:36,133 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-1792641108 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-1792641108 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1792641108 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1792641108 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite23_Out-1792641108| ~y$r_buff1_thd0~0_In-1792641108)) (and (= |ULTIMATE.start_main_#t~ite23_Out-1792641108| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1792641108, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1792641108, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1792641108, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1792641108, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1792641108, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1792641108, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1792641108|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:25:36,133 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In444173124 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite29_In444173124| |ULTIMATE.start_main_#t~ite29_Out444173124|) (= |ULTIMATE.start_main_#t~ite30_Out444173124| ~y$w_buff0~0_In444173124)) (and (= |ULTIMATE.start_main_#t~ite30_Out444173124| |ULTIMATE.start_main_#t~ite29_Out444173124|) .cse0 (= ~y$w_buff0~0_In444173124 |ULTIMATE.start_main_#t~ite29_Out444173124|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In444173124 256)))) (or (and (= (mod ~y$r_buff1_thd0~0_In444173124 256) 0) .cse1) (= (mod ~y$w_buff0_used~0_In444173124 256) 0) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In444173124 256)))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In444173124, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In444173124|, ~y$w_buff0~0=~y$w_buff0~0_In444173124, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In444173124, ~weak$$choice2~0=~weak$$choice2~0_In444173124, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In444173124, ~y$w_buff1_used~0=~y$w_buff1_used~0_In444173124} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out444173124|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In444173124, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out444173124|, ~y$w_buff0~0=~y$w_buff0~0_In444173124, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In444173124, ~weak$$choice2~0=~weak$$choice2~0_In444173124, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In444173124, ~y$w_buff1_used~0=~y$w_buff1_used~0_In444173124} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 14:25:36,134 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1237046549 256)))) (or (and (= |ULTIMATE.start_main_#t~ite33_Out-1237046549| |ULTIMATE.start_main_#t~ite32_Out-1237046549|) (= ~y$w_buff1~0_In-1237046549 |ULTIMATE.start_main_#t~ite32_Out-1237046549|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1237046549 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-1237046549 256) 0)) (= 0 (mod ~y$w_buff0_used~0_In-1237046549 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-1237046549 256)) .cse1)))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1237046549| |ULTIMATE.start_main_#t~ite32_Out-1237046549|) (= ~y$w_buff1~0_In-1237046549 |ULTIMATE.start_main_#t~ite33_Out-1237046549|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1237046549, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1237046549, ~weak$$choice2~0=~weak$$choice2~0_In-1237046549, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1237046549, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1237046549|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1237046549} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1237046549, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1237046549, ~weak$$choice2~0=~weak$$choice2~0_In-1237046549, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1237046549|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1237046549, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1237046549|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1237046549} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 14:25:36,134 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1987365611 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite35_In-1987365611| |ULTIMATE.start_main_#t~ite35_Out-1987365611|) (not .cse0) (= |ULTIMATE.start_main_#t~ite36_Out-1987365611| ~y$w_buff0_used~0_In-1987365611)) (and (= |ULTIMATE.start_main_#t~ite35_Out-1987365611| ~y$w_buff0_used~0_In-1987365611) (= |ULTIMATE.start_main_#t~ite36_Out-1987365611| |ULTIMATE.start_main_#t~ite35_Out-1987365611|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1987365611 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-1987365611 256) 0)) (= (mod ~y$w_buff0_used~0_In-1987365611 256) 0) (and (= (mod ~y$r_buff1_thd0~0_In-1987365611 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1987365611, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-1987365611|, ~weak$$choice2~0=~weak$$choice2~0_In-1987365611, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1987365611, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-1987365611|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-1987365611|, ~weak$$choice2~0=~weak$$choice2~0_In-1987365611, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 14:25:36,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 14:25:36,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:25:36,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:25:36,184 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c61f4251-1baa-42aa-b718-cb150159b667/bin/utaipan/witness.graphml [2019-12-07 14:25:36,184 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:25:36,185 INFO L168 Benchmark]: Toolchain (without parser) took 48530.68 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 937.1 MB in the beginning and 3.0 GB in the end (delta: -2.1 GB). Peak memory consumption was 146.0 MB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,186 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:25:36,186 INFO L168 Benchmark]: CACSL2BoogieTranslator took 386.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 125.3 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -158.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,186 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,186 INFO L168 Benchmark]: Boogie Preprocessor took 25.16 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:25:36,187 INFO L168 Benchmark]: RCFGBuilder took 396.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,187 INFO L168 Benchmark]: TraceAbstraction took 47619.83 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 3.0 GB in the end (delta: -2.0 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,187 INFO L168 Benchmark]: Witness Printer took 59.53 ms. Allocated memory is still 3.2 GB. Free memory was 3.0 GB in the beginning and 3.0 GB in the end (delta: 14.4 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:25:36,188 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 386.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 125.3 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -158.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.16 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 396.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 47619.83 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 3.0 GB in the end (delta: -2.0 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 59.53 ms. Allocated memory is still 3.2 GB. Free memory was 3.0 GB in the beginning and 3.0 GB in the end (delta: 14.4 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 161 ProgramPointsBefore, 81 ProgramPointsAfterwards, 192 TransitionsBefore, 86 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 30 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 4050 VarBasedMoverChecksPositive, 194 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 46210 CheckedPairsTotal, 110 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L798] FCALL, FORK 0 pthread_create(&t2492, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L800] FCALL, FORK 0 pthread_create(&t2493, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t2494, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L765] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L766] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L767] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L768] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L769] 3 y$r_buff0_thd3 = (_Bool)1 [L772] 3 z = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L775] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L740] 2 x = 2 [L743] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L775] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L746] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L776] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L746] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L777] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L747] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L748] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L749] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L808] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L808] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L809] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L810] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L811] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L812] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L815] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L816] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L817] 0 y$flush_delayed = weak$$choice2 [L818] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L820] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L821] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L822] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L825] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L826] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 152 locations, 2 error locations. Result: UNSAFE, OverallTime: 47.4s, OverallIterations: 56, TraceHistogramMax: 1, AutomataDifference: 27.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10019 SDtfs, 17182 SDslu, 49232 SDs, 0 SdLazy, 20556 SolverSat, 1306 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1091 GetRequests, 60 SyntacticMatches, 30 SemanticMatches, 1001 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6980 ImplicationChecksByTransitivity, 11.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=31198occurred in iteration=6, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.1s AutomataMinimizationTime, 55 MinimizatonAttempts, 209109 StatesRemovedByMinimization, 49 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 4.2s InterpolantComputationTime, 2014 NumberOfCodeBlocks, 2014 NumberOfCodeBlocksAsserted, 56 NumberOfCheckSat, 1903 ConstructedInterpolants, 0 QuantifiedInterpolants, 407030 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 55 InterpolantComputations, 55 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...