./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4b4145914802a18ceef375a77d9a4f2f13e6c70b ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 02:57:12,727 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 02:57:12,729 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 02:57:12,793 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 02:57:12,794 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 02:57:12,798 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 02:57:12,801 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 02:57:12,805 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 02:57:12,808 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 02:57:12,814 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 02:57:12,815 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 02:57:12,817 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 02:57:12,818 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 02:57:12,822 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 02:57:12,823 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 02:57:12,825 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 02:57:12,826 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 02:57:12,830 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 02:57:12,833 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 02:57:12,841 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 02:57:12,843 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 02:57:12,844 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 02:57:12,846 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 02:57:12,847 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 02:57:12,856 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 02:57:12,857 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 02:57:12,857 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 02:57:12,859 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 02:57:12,860 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 02:57:12,861 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 02:57:12,861 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 02:57:12,863 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 02:57:12,865 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 02:57:12,866 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 02:57:12,868 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 02:57:12,868 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 02:57:12,869 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 02:57:12,869 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 02:57:12,870 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 02:57:12,870 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 02:57:12,871 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 02:57:12,873 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 02:57:12,914 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 02:57:12,915 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 02:57:12,917 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 02:57:12,917 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 02:57:12,917 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 02:57:12,917 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 02:57:12,918 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 02:57:12,918 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 02:57:12,918 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 02:57:12,918 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 02:57:12,919 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 02:57:12,920 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 02:57:12,920 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 02:57:12,920 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 02:57:12,920 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 02:57:12,921 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 02:57:12,921 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 02:57:12,921 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 02:57:12,921 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 02:57:12,921 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 02:57:12,922 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 02:57:12,922 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 02:57:12,922 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 02:57:12,922 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 02:57:12,923 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 02:57:12,923 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 02:57:12,923 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 02:57:12,923 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 02:57:12,924 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 02:57:12,925 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 02:57:12,926 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 02:57:12,926 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 02:57:12,927 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 02:57:12,927 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4b4145914802a18ceef375a77d9a4f2f13e6c70b [2020-11-28 02:57:13,220 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 02:57:13,256 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 02:57:13,261 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 02:57:13,262 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 02:57:13,263 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 02:57:13,264 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2020-11-28 02:57:13,357 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/data/6ae59795e/3fd02428256640d28363e6b9c3cc938d/FLAG7af29f42a [2020-11-28 02:57:13,963 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 02:57:13,964 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2020-11-28 02:57:13,974 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/data/6ae59795e/3fd02428256640d28363e6b9c3cc938d/FLAG7af29f42a [2020-11-28 02:57:14,296 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/data/6ae59795e/3fd02428256640d28363e6b9c3cc938d [2020-11-28 02:57:14,299 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 02:57:14,301 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 02:57:14,317 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 02:57:14,317 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 02:57:14,321 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 02:57:14,322 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,324 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a1cb470 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14, skipping insertion in model container [2020-11-28 02:57:14,324 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,332 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 02:57:14,366 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 02:57:14,639 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 02:57:14,666 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 02:57:14,719 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 02:57:14,741 INFO L208 MainTranslator]: Completed translation [2020-11-28 02:57:14,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14 WrapperNode [2020-11-28 02:57:14,742 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 02:57:14,744 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 02:57:14,744 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 02:57:14,744 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 02:57:14,751 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,761 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,806 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 02:57:14,807 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 02:57:14,807 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 02:57:14,807 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 02:57:14,819 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,820 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,825 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,825 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,836 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,848 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,852 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... [2020-11-28 02:57:14,859 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 02:57:14,887 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 02:57:14,887 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 02:57:14,887 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 02:57:14,888 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 02:57:14,973 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 02:57:14,974 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 02:57:14,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 02:57:14,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 02:57:15,937 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 02:57:15,938 INFO L298 CfgBuilder]: Removed 105 assume(true) statements. [2020-11-28 02:57:15,944 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:15 BoogieIcfgContainer [2020-11-28 02:57:15,944 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 02:57:15,946 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 02:57:15,946 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 02:57:15,950 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 02:57:15,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:15,951 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 02:57:14" (1/3) ... [2020-11-28 02:57:15,952 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7aa1f3a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 02:57:15, skipping insertion in model container [2020-11-28 02:57:15,952 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:15,953 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:14" (2/3) ... [2020-11-28 02:57:15,954 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7aa1f3a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 02:57:15, skipping insertion in model container [2020-11-28 02:57:15,954 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:15,954 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:15" (3/3) ... [2020-11-28 02:57:15,959 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2020-11-28 02:57:16,010 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 02:57:16,011 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 02:57:16,011 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 02:57:16,011 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 02:57:16,011 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 02:57:16,011 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 02:57:16,011 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 02:57:16,012 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 02:57:16,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states. [2020-11-28 02:57:16,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 175 [2020-11-28 02:57:16,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:16,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:16,071 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,071 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,071 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 02:57:16,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states. [2020-11-28 02:57:16,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 175 [2020-11-28 02:57:16,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:16,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:16,086 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,086 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,094 INFO L794 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 19#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 142#L508true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 161#L216true assume !(1 == ~m_i~0);~m_st~0 := 2; 186#L223-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 201#L228-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 213#L233-1true assume !(0 == ~M_E~0); 105#L336-1true assume !(0 == ~T1_E~0); 112#L341-1true assume !(0 == ~T2_E~0); 129#L346-1true assume !(0 == ~E_M~0); 20#L351-1true assume !(0 == ~E_1~0); 67#L356-1true assume !(0 == ~E_2~0); 91#L361-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50#L158true assume 1 == ~m_pc~0; 132#L159true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 51#L169true is_master_triggered_#res := is_master_triggered_~__retres1~0; 133#L170true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 45#L417true assume !(0 != activate_threads_~tmp~1); 52#L417-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 167#L177true assume 1 == ~t1_pc~0; 211#L178true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 169#L188true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 212#L189true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 154#L425true assume !(0 != activate_threads_~tmp___0~0); 156#L425-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 101#L196true assume !(1 == ~t2_pc~0); 97#L196-2true is_transmit2_triggered_~__retres1~2 := 0; 84#L207true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8#L208true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 79#L433true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 83#L433-2true assume !(1 == ~M_E~0); 124#L374-1true assume !(1 == ~T1_E~0); 137#L379-1true assume !(1 == ~T2_E~0); 53#L384-1true assume !(1 == ~E_M~0); 65#L389-1true assume 1 == ~E_1~0;~E_1~0 := 2; 87#L394-1true assume !(1 == ~E_2~0); 109#L545-1true [2020-11-28 02:57:16,096 INFO L796 eck$LassoCheckResult]: Loop: 109#L545-1true assume !false; 168#L546true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 190#L311true assume false; 159#L326true start_simulation_~kernel_st~0 := 2; 157#L216-1true start_simulation_~kernel_st~0 := 3; 102#L336-2true assume 0 == ~M_E~0;~M_E~0 := 1; 103#L336-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 115#L341-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 131#L346-3true assume 0 == ~E_M~0;~E_M~0 := 1; 28#L351-3true assume 0 == ~E_1~0;~E_1~0 := 1; 72#L356-3true assume 0 == ~E_2~0;~E_2~0 := 1; 98#L361-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14#L158-12true assume 1 == ~m_pc~0; 118#L159-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 38#L169-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 119#L170-4true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18#L417-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 134#L417-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 147#L177-12true assume !(1 == ~t1_pc~0); 162#L177-14true is_transmit1_triggered_~__retres1~1 := 0; 178#L188-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 220#L189-4true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 140#L425-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 143#L425-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81#L196-12true assume 1 == ~t2_pc~0; 26#L197-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 92#L207-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27#L208-4true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 61#L433-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39#L433-14true assume 1 == ~M_E~0;~M_E~0 := 2; 114#L374-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 130#L379-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 25#L384-3true assume 1 == ~E_M~0;~E_M~0 := 2; 69#L389-3true assume 1 == ~E_1~0;~E_1~0 := 2; 96#L394-3true assume !(1 == ~E_2~0); 191#L399-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 75#L246-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11#L263-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 107#L264-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 192#L564true assume !(0 == start_simulation_~tmp~3); 194#L564-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 54#L246-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7#L263-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 106#L264-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 141#L519true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 184#L526true stop_simulation_#res := stop_simulation_~__retres2~0; 64#L527true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15#L577true assume !(0 != start_simulation_~tmp___0~1); 109#L545-1true [2020-11-28 02:57:16,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,103 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2020-11-28 02:57:16,112 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,113 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297234910] [2020-11-28 02:57:16,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,288 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297234910] [2020-11-28 02:57:16,289 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,289 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:16,290 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432603583] [2020-11-28 02:57:16,295 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:16,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,297 INFO L82 PathProgramCache]: Analyzing trace with hash -751338332, now seen corresponding path program 1 times [2020-11-28 02:57:16,297 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,297 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114002508] [2020-11-28 02:57:16,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,378 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114002508] [2020-11-28 02:57:16,380 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,381 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:16,381 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992532791] [2020-11-28 02:57:16,389 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:16,390 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:16,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:16,409 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:16,411 INFO L87 Difference]: Start difference. First operand 218 states. Second operand 3 states. [2020-11-28 02:57:16,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:16,464 INFO L93 Difference]: Finished difference Result 217 states and 327 transitions. [2020-11-28 02:57:16,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:16,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 327 transitions. [2020-11-28 02:57:16,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-11-28 02:57:16,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 212 states and 322 transitions. [2020-11-28 02:57:16,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2020-11-28 02:57:16,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2020-11-28 02:57:16,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 322 transitions. [2020-11-28 02:57:16,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:16,494 INFO L691 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-11-28 02:57:16,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 322 transitions. [2020-11-28 02:57:16,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2020-11-28 02:57:16,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2020-11-28 02:57:16,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 322 transitions. [2020-11-28 02:57:16,537 INFO L714 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-11-28 02:57:16,537 INFO L594 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2020-11-28 02:57:16,537 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 02:57:16,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 322 transitions. [2020-11-28 02:57:16,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-11-28 02:57:16,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:16,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:16,546 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,547 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,547 INFO L794 eck$LassoCheckResult]: Stem: 592#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 477#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 478#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 605#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 628#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 650#L228-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 655#L233-1 assume !(0 == ~M_E~0); 584#L336-1 assume !(0 == ~T1_E~0); 585#L341-1 assume !(0 == ~T2_E~0); 591#L346-1 assume !(0 == ~E_M~0); 479#L351-1 assume !(0 == ~E_1~0); 480#L356-1 assume !(0 == ~E_2~0); 556#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 536#L158 assume 1 == ~m_pc~0; 537#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 525#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 538#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 528#L417 assume !(0 != activate_threads_~tmp~1); 529#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 539#L177 assume 1 == ~t1_pc~0; 635#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 631#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 636#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 620#L425 assume !(0 != activate_threads_~tmp___0~0); 621#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 577#L196 assume !(1 == ~t2_pc~0); 453#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 452#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 456#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 457#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 566#L433-2 assume !(1 == ~M_E~0); 569#L374-1 assume !(1 == ~T1_E~0); 596#L379-1 assume !(1 == ~T2_E~0); 540#L384-1 assume !(1 == ~E_M~0); 541#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 554#L394-1 assume !(1 == ~E_2~0); 471#L545-1 [2020-11-28 02:57:16,548 INFO L796 eck$LassoCheckResult]: Loop: 471#L545-1 assume !false; 589#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 583#L311 assume !false; 466#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 467#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 464#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 465#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 588#L278 assume !(0 != eval_~tmp~0); 626#L326 start_simulation_~kernel_st~0 := 2; 624#L216-1 start_simulation_~kernel_st~0 := 3; 578#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 579#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 580#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 594#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 497#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 498#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 560#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 468#L158-12 assume 1 == ~m_pc~0; 469#L159-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 459#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 517#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 475#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 476#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 597#L177-12 assume 1 == ~t1_pc~0; 610#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 629#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 644#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 602#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 603#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 568#L196-12 assume 1 == ~t2_pc~0; 492#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 493#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 495#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 496#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 518#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 519#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 593#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 490#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 491#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 558#L394-3 assume !(1 == ~E_2~0); 576#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 562#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 462#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 463#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 587#L564 assume !(0 == start_simulation_~tmp~3); 607#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 542#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 454#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 455#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 586#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 604#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 553#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 470#L577 assume !(0 != start_simulation_~tmp___0~1); 471#L545-1 [2020-11-28 02:57:16,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,549 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2020-11-28 02:57:16,549 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,550 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456833614] [2020-11-28 02:57:16,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,612 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456833614] [2020-11-28 02:57:16,612 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,612 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:16,612 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218328648] [2020-11-28 02:57:16,613 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:16,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,613 INFO L82 PathProgramCache]: Analyzing trace with hash 355282980, now seen corresponding path program 1 times [2020-11-28 02:57:16,614 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,614 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387173224] [2020-11-28 02:57:16,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,728 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387173224] [2020-11-28 02:57:16,728 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,729 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:16,730 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703012553] [2020-11-28 02:57:16,731 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:16,733 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:16,735 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:16,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:16,736 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. cyclomatic complexity: 111 Second operand 3 states. [2020-11-28 02:57:16,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:16,759 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2020-11-28 02:57:16,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:16,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 321 transitions. [2020-11-28 02:57:16,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-11-28 02:57:16,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 321 transitions. [2020-11-28 02:57:16,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2020-11-28 02:57:16,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2020-11-28 02:57:16,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 321 transitions. [2020-11-28 02:57:16,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:16,786 INFO L691 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-11-28 02:57:16,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 321 transitions. [2020-11-28 02:57:16,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2020-11-28 02:57:16,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2020-11-28 02:57:16,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 321 transitions. [2020-11-28 02:57:16,804 INFO L714 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-11-28 02:57:16,804 INFO L594 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2020-11-28 02:57:16,804 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 02:57:16,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 321 transitions. [2020-11-28 02:57:16,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2020-11-28 02:57:16,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:16,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:16,815 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,815 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:16,816 INFO L794 eck$LassoCheckResult]: Stem: 1023#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 908#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 909#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1036#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1059#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1081#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1086#L233-1 assume !(0 == ~M_E~0); 1015#L336-1 assume !(0 == ~T1_E~0); 1016#L341-1 assume !(0 == ~T2_E~0); 1022#L346-1 assume !(0 == ~E_M~0); 910#L351-1 assume !(0 == ~E_1~0); 911#L356-1 assume !(0 == ~E_2~0); 987#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 967#L158 assume 1 == ~m_pc~0; 968#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 956#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 969#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 959#L417 assume !(0 != activate_threads_~tmp~1); 960#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 970#L177 assume 1 == ~t1_pc~0; 1066#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1062#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1067#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1051#L425 assume !(0 != activate_threads_~tmp___0~0); 1052#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1008#L196 assume !(1 == ~t2_pc~0); 884#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 883#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 887#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 888#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 997#L433-2 assume !(1 == ~M_E~0); 1000#L374-1 assume !(1 == ~T1_E~0); 1027#L379-1 assume !(1 == ~T2_E~0); 971#L384-1 assume !(1 == ~E_M~0); 972#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 985#L394-1 assume !(1 == ~E_2~0); 902#L545-1 [2020-11-28 02:57:16,817 INFO L796 eck$LassoCheckResult]: Loop: 902#L545-1 assume !false; 1020#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1014#L311 assume !false; 897#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 898#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 895#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 896#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1019#L278 assume !(0 != eval_~tmp~0); 1057#L326 start_simulation_~kernel_st~0 := 2; 1055#L216-1 start_simulation_~kernel_st~0 := 3; 1009#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1010#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1011#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1025#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 928#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 929#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 991#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 899#L158-12 assume 1 == ~m_pc~0; 900#L159-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 890#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 948#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 906#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 907#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1028#L177-12 assume 1 == ~t1_pc~0; 1041#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1060#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1075#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1033#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1034#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 999#L196-12 assume 1 == ~t2_pc~0; 923#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 924#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 926#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 927#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 949#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 950#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1024#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 921#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 922#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 989#L394-3 assume !(1 == ~E_2~0); 1007#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 993#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 893#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 894#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1018#L564 assume !(0 == start_simulation_~tmp~3); 1038#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 973#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 885#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 886#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1017#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1035#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 984#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 901#L577 assume !(0 != start_simulation_~tmp___0~1); 902#L545-1 [2020-11-28 02:57:16,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,817 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2020-11-28 02:57:16,818 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,819 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987362701] [2020-11-28 02:57:16,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,915 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987362701] [2020-11-28 02:57:16,915 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,915 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:16,915 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847145131] [2020-11-28 02:57:16,916 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:16,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:16,916 INFO L82 PathProgramCache]: Analyzing trace with hash 355282980, now seen corresponding path program 2 times [2020-11-28 02:57:16,917 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:16,917 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931435532] [2020-11-28 02:57:16,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:16,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:16,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:16,996 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931435532] [2020-11-28 02:57:16,997 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:16,997 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:16,997 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179750010] [2020-11-28 02:57:16,998 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:17,000 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:17,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:17,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:17,002 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. cyclomatic complexity: 110 Second operand 3 states. [2020-11-28 02:57:17,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:17,111 INFO L93 Difference]: Finished difference Result 377 states and 559 transitions. [2020-11-28 02:57:17,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:17,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 559 transitions. [2020-11-28 02:57:17,117 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 338 [2020-11-28 02:57:17,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 559 transitions. [2020-11-28 02:57:17,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2020-11-28 02:57:17,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2020-11-28 02:57:17,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 377 states and 559 transitions. [2020-11-28 02:57:17,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:17,131 INFO L691 BuchiCegarLoop]: Abstraction has 377 states and 559 transitions. [2020-11-28 02:57:17,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states and 559 transitions. [2020-11-28 02:57:17,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 358. [2020-11-28 02:57:17,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 358 states. [2020-11-28 02:57:17,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 533 transitions. [2020-11-28 02:57:17,171 INFO L714 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2020-11-28 02:57:17,171 INFO L594 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2020-11-28 02:57:17,172 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 02:57:17,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 358 states and 533 transitions. [2020-11-28 02:57:17,177 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2020-11-28 02:57:17,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:17,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:17,181 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,184 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,185 INFO L794 eck$LassoCheckResult]: Stem: 1614#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1503#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1504#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1638#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1663#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1687#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1692#L233-1 assume !(0 == ~M_E~0); 1605#L336-1 assume !(0 == ~T1_E~0); 1606#L341-1 assume !(0 == ~T2_E~0); 1613#L346-1 assume !(0 == ~E_M~0); 1505#L351-1 assume !(0 == ~E_1~0); 1506#L356-1 assume !(0 == ~E_2~0); 1578#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1561#L158 assume !(1 == ~m_pc~0); 1549#L158-2 is_master_triggered_~__retres1~0 := 0; 1550#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1562#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1553#L417 assume !(0 != activate_threads_~tmp~1); 1554#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1563#L177 assume 1 == ~t1_pc~0; 1670#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1666#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1671#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1654#L425 assume !(0 != activate_threads_~tmp___0~0); 1655#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1598#L196 assume !(1 == ~t2_pc~0); 1480#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 1479#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1483#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1484#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1588#L433-2 assume !(1 == ~M_E~0); 1591#L374-1 assume !(1 == ~T1_E~0); 1627#L379-1 assume !(1 == ~T2_E~0); 1564#L384-1 assume !(1 == ~E_M~0); 1565#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1576#L394-1 assume !(1 == ~E_2~0); 1497#L545-1 [2020-11-28 02:57:17,185 INFO L796 eck$LassoCheckResult]: Loop: 1497#L545-1 assume !false; 1610#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1604#L311 assume !false; 1493#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1494#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1491#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1492#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1609#L278 assume !(0 != eval_~tmp~0); 1661#L326 start_simulation_~kernel_st~0 := 2; 1658#L216-1 start_simulation_~kernel_st~0 := 3; 1599#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1600#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1601#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1616#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1523#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1524#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1582#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1495#L158-12 assume !(1 == ~m_pc~0); 1485#L158-14 is_master_triggered_~__retres1~0 := 0; 1486#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1543#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1501#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1502#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1643#L177-12 assume 1 == ~t1_pc~0; 1644#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1664#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1681#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1635#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1636#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1590#L196-12 assume !(1 == ~t2_pc~0); 1520#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 1519#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1521#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1522#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1544#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1545#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1615#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1516#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1517#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1580#L394-3 assume !(1 == ~E_2~0); 1597#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1584#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1489#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1490#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1608#L564 assume !(0 == start_simulation_~tmp~3); 1640#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1566#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1481#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1482#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1607#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1637#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 1575#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1496#L577 assume !(0 != start_simulation_~tmp___0~1); 1497#L545-1 [2020-11-28 02:57:17,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,190 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2020-11-28 02:57:17,190 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,190 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709042788] [2020-11-28 02:57:17,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,243 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709042788] [2020-11-28 02:57:17,243 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,243 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:17,243 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703626483] [2020-11-28 02:57:17,244 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:17,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1295038690, now seen corresponding path program 1 times [2020-11-28 02:57:17,244 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,245 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021149422] [2020-11-28 02:57:17,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,282 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021149422] [2020-11-28 02:57:17,283 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,283 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:17,283 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116755416] [2020-11-28 02:57:17,284 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:17,284 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:17,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 02:57:17,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 02:57:17,285 INFO L87 Difference]: Start difference. First operand 358 states and 533 transitions. cyclomatic complexity: 177 Second operand 4 states. [2020-11-28 02:57:17,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:17,441 INFO L93 Difference]: Finished difference Result 792 states and 1155 transitions. [2020-11-28 02:57:17,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 02:57:17,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1155 transitions. [2020-11-28 02:57:17,450 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 727 [2020-11-28 02:57:17,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1155 transitions. [2020-11-28 02:57:17,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2020-11-28 02:57:17,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2020-11-28 02:57:17,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1155 transitions. [2020-11-28 02:57:17,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:17,462 INFO L691 BuchiCegarLoop]: Abstraction has 792 states and 1155 transitions. [2020-11-28 02:57:17,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1155 transitions. [2020-11-28 02:57:17,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 623. [2020-11-28 02:57:17,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 623 states. [2020-11-28 02:57:17,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 919 transitions. [2020-11-28 02:57:17,491 INFO L714 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2020-11-28 02:57:17,491 INFO L594 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2020-11-28 02:57:17,491 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 02:57:17,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 623 states and 919 transitions. [2020-11-28 02:57:17,496 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 584 [2020-11-28 02:57:17,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:17,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:17,498 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,498 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,499 INFO L794 eck$LassoCheckResult]: Stem: 2777#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2662#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2663#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2802#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 2822#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2844#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2849#L233-1 assume !(0 == ~M_E~0); 2766#L336-1 assume !(0 == ~T1_E~0); 2767#L341-1 assume !(0 == ~T2_E~0); 2775#L346-1 assume !(0 == ~E_M~0); 2666#L351-1 assume !(0 == ~E_1~0); 2667#L356-1 assume !(0 == ~E_2~0); 2739#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2721#L158 assume !(1 == ~m_pc~0); 2709#L158-2 is_master_triggered_~__retres1~0 := 0; 2710#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2722#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2713#L417 assume !(0 != activate_threads_~tmp~1); 2714#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2725#L177 assume !(1 == ~t1_pc~0); 2824#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 2825#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2830#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2815#L425 assume !(0 != activate_threads_~tmp___0~0); 2816#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2759#L196 assume !(1 == ~t2_pc~0); 2641#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 2640#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2644#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2645#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2750#L433-2 assume !(1 == ~M_E~0); 2752#L374-1 assume !(1 == ~T1_E~0); 2793#L379-1 assume !(1 == ~T2_E~0); 2726#L384-1 assume !(1 == ~E_M~0); 2727#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2737#L394-1 assume !(1 == ~E_2~0); 2656#L545-1 [2020-11-28 02:57:17,499 INFO L796 eck$LassoCheckResult]: Loop: 2656#L545-1 assume !false; 2771#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2765#L311 assume !false; 2652#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2653#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2650#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2651#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2770#L278 assume !(0 != eval_~tmp~0); 2821#L326 start_simulation_~kernel_st~0 := 2; 2819#L216-1 start_simulation_~kernel_st~0 := 3; 2760#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2761#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2762#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2778#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2682#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2683#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2743#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2654#L158-12 assume !(1 == ~m_pc~0); 2642#L158-14 is_master_triggered_~__retres1~0 := 0; 2643#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2703#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2660#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2661#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2794#L177-12 assume !(1 == ~t1_pc~0); 2807#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 2823#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2840#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2799#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2800#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2751#L196-12 assume 1 == ~t2_pc~0; 2677#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2678#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2680#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2681#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2704#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 2705#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2776#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2673#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2674#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2741#L394-3 assume !(1 == ~E_2~0); 2758#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2745#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2648#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2649#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2769#L564 assume !(0 == start_simulation_~tmp~3); 2804#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2723#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2637#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2638#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2768#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2801#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 2736#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2655#L577 assume !(0 != start_simulation_~tmp___0~1); 2656#L545-1 [2020-11-28 02:57:17,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,500 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2020-11-28 02:57:17,500 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,500 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852718481] [2020-11-28 02:57:17,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,558 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852718481] [2020-11-28 02:57:17,558 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,558 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:17,559 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729712646] [2020-11-28 02:57:17,559 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:17,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1466677854, now seen corresponding path program 1 times [2020-11-28 02:57:17,568 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,568 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194742728] [2020-11-28 02:57:17,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,602 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194742728] [2020-11-28 02:57:17,602 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,603 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:17,603 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777720668] [2020-11-28 02:57:17,603 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:17,603 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:17,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:17,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:17,608 INFO L87 Difference]: Start difference. First operand 623 states and 919 transitions. cyclomatic complexity: 298 Second operand 5 states. [2020-11-28 02:57:17,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:17,776 INFO L93 Difference]: Finished difference Result 1454 states and 2154 transitions. [2020-11-28 02:57:17,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 02:57:17,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1454 states and 2154 transitions. [2020-11-28 02:57:17,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2020-11-28 02:57:17,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1454 states to 1454 states and 2154 transitions. [2020-11-28 02:57:17,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1454 [2020-11-28 02:57:17,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1454 [2020-11-28 02:57:17,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1454 states and 2154 transitions. [2020-11-28 02:57:17,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:17,814 INFO L691 BuchiCegarLoop]: Abstraction has 1454 states and 2154 transitions. [2020-11-28 02:57:17,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1454 states and 2154 transitions. [2020-11-28 02:57:17,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1454 to 674. [2020-11-28 02:57:17,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 674 states. [2020-11-28 02:57:17,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 970 transitions. [2020-11-28 02:57:17,839 INFO L714 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2020-11-28 02:57:17,839 INFO L594 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2020-11-28 02:57:17,839 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 02:57:17,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 970 transitions. [2020-11-28 02:57:17,845 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2020-11-28 02:57:17,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:17,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:17,848 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,848 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:17,848 INFO L794 eck$LassoCheckResult]: Stem: 4890#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4752#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4753#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4920#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 4944#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4967#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4974#L233-1 assume !(0 == ~M_E~0); 4879#L336-1 assume !(0 == ~T1_E~0); 4880#L341-1 assume !(0 == ~T2_E~0); 4888#L346-1 assume !(0 == ~E_M~0); 4754#L351-1 assume !(0 == ~E_1~0); 4755#L356-1 assume !(0 == ~E_2~0); 4831#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4811#L158 assume !(1 == ~m_pc~0); 4798#L158-2 is_master_triggered_~__retres1~0 := 0; 4799#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4812#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4802#L417 assume !(0 != activate_threads_~tmp~1); 4803#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4815#L177 assume !(1 == ~t1_pc~0); 4946#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 4947#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4952#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4936#L425 assume !(0 != activate_threads_~tmp___0~0); 4937#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4872#L196 assume !(1 == ~t2_pc~0); 4731#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 4857#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4858#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4850#L433 assume !(0 != activate_threads_~tmp___1~0); 4851#L433-2 assume !(1 == ~M_E~0); 4856#L374-1 assume !(1 == ~T1_E~0); 4907#L379-1 assume !(1 == ~T2_E~0); 4816#L384-1 assume !(1 == ~E_M~0); 4817#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4828#L394-1 assume !(1 == ~E_2~0); 4744#L545-1 [2020-11-28 02:57:17,849 INFO L796 eck$LassoCheckResult]: Loop: 4744#L545-1 assume !false; 4884#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4878#L311 assume !false; 4745#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4746#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4740#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4741#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4883#L278 assume !(0 != eval_~tmp~0); 4971#L326 start_simulation_~kernel_st~0 := 2; 5394#L216-1 start_simulation_~kernel_st~0 := 3; 5393#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5392#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5391#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5390#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4772#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4773#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4870#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4742#L158-12 assume !(1 == ~m_pc~0); 4732#L158-14 is_master_triggered_~__retres1~0 := 0; 4733#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4792#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4750#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4751#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4909#L177-12 assume !(1 == ~t1_pc~0); 4927#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 4945#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4961#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4987#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5383#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5349#L196-12 assume !(1 == ~t2_pc~0); 5350#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 5382#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5380#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5378#L433-12 assume !(0 != activate_threads_~tmp___1~0); 5376#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 5373#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5372#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5371#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5370#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5369#L394-3 assume !(1 == ~E_2~0); 4968#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4842#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4738#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4739#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4882#L564 assume !(0 == start_simulation_~tmp~3); 4923#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4813#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4727#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4728#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 4881#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4919#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 4827#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4743#L577 assume !(0 != start_simulation_~tmp___0~1); 4744#L545-1 [2020-11-28 02:57:17,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330394, now seen corresponding path program 1 times [2020-11-28 02:57:17,850 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,850 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548356198] [2020-11-28 02:57:17,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,921 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548356198] [2020-11-28 02:57:17,921 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,921 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:17,921 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91169034] [2020-11-28 02:57:17,922 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:17,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:17,922 INFO L82 PathProgramCache]: Analyzing trace with hash 420246015, now seen corresponding path program 1 times [2020-11-28 02:57:17,922 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:17,923 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800551439] [2020-11-28 02:57:17,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:17,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:17,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:17,980 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800551439] [2020-11-28 02:57:17,980 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:17,980 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:17,991 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928317923] [2020-11-28 02:57:17,992 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:17,992 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:17,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 02:57:17,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 02:57:17,993 INFO L87 Difference]: Start difference. First operand 674 states and 970 transitions. cyclomatic complexity: 298 Second operand 4 states. [2020-11-28 02:57:18,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:18,126 INFO L93 Difference]: Finished difference Result 1093 states and 1544 transitions. [2020-11-28 02:57:18,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 02:57:18,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1093 states and 1544 transitions. [2020-11-28 02:57:18,137 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 984 [2020-11-28 02:57:18,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1093 states to 1093 states and 1544 transitions. [2020-11-28 02:57:18,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1093 [2020-11-28 02:57:18,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1093 [2020-11-28 02:57:18,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1093 states and 1544 transitions. [2020-11-28 02:57:18,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:18,154 INFO L691 BuchiCegarLoop]: Abstraction has 1093 states and 1544 transitions. [2020-11-28 02:57:18,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1093 states and 1544 transitions. [2020-11-28 02:57:18,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1093 to 1073. [2020-11-28 02:57:18,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1073 states. [2020-11-28 02:57:18,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1073 states to 1073 states and 1520 transitions. [2020-11-28 02:57:18,181 INFO L714 BuchiCegarLoop]: Abstraction has 1073 states and 1520 transitions. [2020-11-28 02:57:18,181 INFO L594 BuchiCegarLoop]: Abstraction has 1073 states and 1520 transitions. [2020-11-28 02:57:18,182 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 02:57:18,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1073 states and 1520 transitions. [2020-11-28 02:57:18,190 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 970 [2020-11-28 02:57:18,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:18,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:18,193 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,193 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,194 INFO L794 eck$LassoCheckResult]: Stem: 6670#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6530#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6531#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6702#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 6725#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6752#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6767#L233-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6775#L336-1 assume !(0 == ~T1_E~0); 7560#L341-1 assume !(0 == ~T2_E~0); 7559#L346-1 assume !(0 == ~E_M~0); 7558#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6533#L356-1 assume !(0 == ~E_2~0); 7133#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7132#L158 assume !(1 == ~m_pc~0); 7131#L158-2 is_master_triggered_~__retres1~0 := 0; 7130#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7129#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7128#L417 assume !(0 != activate_threads_~tmp~1); 7127#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7126#L177 assume !(1 == ~t1_pc~0); 7125#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 7124#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7123#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7122#L425 assume !(0 != activate_threads_~tmp___0~0); 7121#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7120#L196 assume !(1 == ~t2_pc~0); 7119#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 6637#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6512#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6513#L433 assume !(0 != activate_threads_~tmp___1~0); 7114#L433-2 assume !(1 == ~M_E~0); 7113#L374-1 assume !(1 == ~T1_E~0); 7112#L379-1 assume !(1 == ~T2_E~0); 7111#L384-1 assume !(1 == ~E_M~0); 7109#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7110#L394-1 assume !(1 == ~E_2~0); 7526#L545-1 [2020-11-28 02:57:18,194 INFO L796 eck$LassoCheckResult]: Loop: 7526#L545-1 assume !false; 7416#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7415#L311 assume !false; 7171#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6627#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6518#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6519#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6662#L278 assume !(0 != eval_~tmp~0); 6723#L326 start_simulation_~kernel_st~0 := 2; 6720#L216-1 start_simulation_~kernel_st~0 := 3; 6652#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6653#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6654#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6688#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6689#L351-3 assume !(0 == ~E_1~0); 7397#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7391#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7392#L158-12 assume !(1 == ~m_pc~0); 7396#L158-14 is_master_triggered_~__retres1~0 := 0; 7393#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7384#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7385#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7386#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7362#L177-12 assume !(1 == ~t1_pc~0); 7360#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 7358#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7357#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7353#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7351#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7349#L196-12 assume 1 == ~t2_pc~0; 7341#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7336#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7335#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7333#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7330#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 7331#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7563#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7562#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7561#L389-3 assume !(1 == ~E_1~0); 6647#L394-3 assume !(1 == ~E_2~0); 6648#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6620#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6621#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7172#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7173#L564 assume !(0 == start_simulation_~tmp~3); 6704#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6759#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7532#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7531#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7530#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 7529#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 7528#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7527#L577 assume !(0 != start_simulation_~tmp___0~1); 7526#L545-1 [2020-11-28 02:57:18,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,195 INFO L82 PathProgramCache]: Analyzing trace with hash -2059002262, now seen corresponding path program 1 times [2020-11-28 02:57:18,195 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,200 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620248175] [2020-11-28 02:57:18,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:18,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:18,243 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620248175] [2020-11-28 02:57:18,243 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:18,243 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:18,244 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852565154] [2020-11-28 02:57:18,244 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:18,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,244 INFO L82 PathProgramCache]: Analyzing trace with hash -296941402, now seen corresponding path program 1 times [2020-11-28 02:57:18,245 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,245 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021763743] [2020-11-28 02:57:18,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:18,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:18,268 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021763743] [2020-11-28 02:57:18,268 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:18,268 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:18,268 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504993611] [2020-11-28 02:57:18,268 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:18,269 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:18,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:18,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:18,269 INFO L87 Difference]: Start difference. First operand 1073 states and 1520 transitions. cyclomatic complexity: 450 Second operand 3 states. [2020-11-28 02:57:18,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:18,302 INFO L93 Difference]: Finished difference Result 1693 states and 2394 transitions. [2020-11-28 02:57:18,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:18,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1693 states and 2394 transitions. [2020-11-28 02:57:18,318 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1620 [2020-11-28 02:57:18,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1693 states to 1693 states and 2394 transitions. [2020-11-28 02:57:18,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1693 [2020-11-28 02:57:18,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1693 [2020-11-28 02:57:18,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1693 states and 2394 transitions. [2020-11-28 02:57:18,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:18,363 INFO L691 BuchiCegarLoop]: Abstraction has 1693 states and 2394 transitions. [2020-11-28 02:57:18,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states and 2394 transitions. [2020-11-28 02:57:18,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 1468. [2020-11-28 02:57:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1468 states. [2020-11-28 02:57:18,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1468 states to 1468 states and 2079 transitions. [2020-11-28 02:57:18,402 INFO L714 BuchiCegarLoop]: Abstraction has 1468 states and 2079 transitions. [2020-11-28 02:57:18,402 INFO L594 BuchiCegarLoop]: Abstraction has 1468 states and 2079 transitions. [2020-11-28 02:57:18,402 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 02:57:18,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1468 states and 2079 transitions. [2020-11-28 02:57:18,412 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2020-11-28 02:57:18,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:18,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:18,416 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,416 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,416 INFO L794 eck$LassoCheckResult]: Stem: 9434#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9302#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9303#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9465#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 9489#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9513#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9521#L233-1 assume !(0 == ~M_E~0); 9422#L336-1 assume !(0 == ~T1_E~0); 9423#L341-1 assume !(0 == ~T2_E~0); 9432#L346-1 assume !(0 == ~E_M~0); 9306#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9307#L356-1 assume !(0 == ~E_2~0); 9408#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9364#L158 assume !(1 == ~m_pc~0); 9365#L158-2 is_master_triggered_~__retres1~0 := 0; 9366#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9367#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9453#L417 assume !(0 != activate_threads_~tmp~1); 9553#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9552#L177 assume !(1 == ~t1_pc~0); 9551#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 9550#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9549#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9548#L425 assume !(0 != activate_threads_~tmp___0~0); 9483#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9415#L196 assume !(1 == ~t2_pc~0); 9281#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 9545#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9543#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9540#L433 assume !(0 != activate_threads_~tmp___1~0); 9401#L433-2 assume !(1 == ~M_E~0); 9402#L374-1 assume !(1 == ~T1_E~0); 9450#L379-1 assume !(1 == ~T2_E~0); 9537#L384-1 assume !(1 == ~E_M~0); 9536#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9381#L394-1 assume !(1 == ~E_2~0); 9294#L545-1 [2020-11-28 02:57:18,417 INFO L796 eck$LassoCheckResult]: Loop: 9294#L545-1 assume !false; 9427#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9421#L311 assume !false; 9295#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9296#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9290#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9291#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9426#L278 assume !(0 != eval_~tmp~0); 9486#L326 start_simulation_~kernel_st~0 := 2; 9484#L216-1 start_simulation_~kernel_st~0 := 3; 9416#L336-2 assume !(0 == ~M_E~0); 9417#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9418#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9435#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9323#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9324#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10682#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10680#L158-12 assume !(1 == ~m_pc~0); 10678#L158-14 is_master_triggered_~__retres1~0 := 0; 10670#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10671#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10551#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10552#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10548#L177-12 assume !(1 == ~t1_pc~0); 10547#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 10546#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10545#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10544#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10543#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10542#L196-12 assume 1 == ~t2_pc~0; 10540#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10538#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10536#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10534#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10533#L433-14 assume !(1 == ~M_E~0); 10098#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10532#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10531#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10529#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10502#L394-3 assume !(1 == ~E_2~0); 10501#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10499#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10471#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10324#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9574#L564 assume !(0 == start_simulation_~tmp~3); 9467#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9368#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9277#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9278#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9424#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9464#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 9380#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9293#L577 assume !(0 != start_simulation_~tmp___0~1); 9294#L545-1 [2020-11-28 02:57:18,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,417 INFO L82 PathProgramCache]: Analyzing trace with hash -2036370008, now seen corresponding path program 1 times [2020-11-28 02:57:18,418 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,418 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754318254] [2020-11-28 02:57:18,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:18,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:18,470 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754318254] [2020-11-28 02:57:18,470 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:18,471 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:18,471 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848768414] [2020-11-28 02:57:18,471 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:18,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,472 INFO L82 PathProgramCache]: Analyzing trace with hash 241952422, now seen corresponding path program 1 times [2020-11-28 02:57:18,472 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,472 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672450668] [2020-11-28 02:57:18,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:18,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:18,507 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672450668] [2020-11-28 02:57:18,508 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:18,508 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:18,508 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192025140] [2020-11-28 02:57:18,508 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:18,508 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:18,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 02:57:18,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 02:57:18,509 INFO L87 Difference]: Start difference. First operand 1468 states and 2079 transitions. cyclomatic complexity: 613 Second operand 4 states. [2020-11-28 02:57:18,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:18,604 INFO L93 Difference]: Finished difference Result 1442 states and 2021 transitions. [2020-11-28 02:57:18,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 02:57:18,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1442 states and 2021 transitions. [2020-11-28 02:57:18,616 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1392 [2020-11-28 02:57:18,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1442 states to 1442 states and 2021 transitions. [2020-11-28 02:57:18,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1442 [2020-11-28 02:57:18,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1442 [2020-11-28 02:57:18,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1442 states and 2021 transitions. [2020-11-28 02:57:18,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:18,632 INFO L691 BuchiCegarLoop]: Abstraction has 1442 states and 2021 transitions. [2020-11-28 02:57:18,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1442 states and 2021 transitions. [2020-11-28 02:57:18,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1442 to 1212. [2020-11-28 02:57:18,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1212 states. [2020-11-28 02:57:18,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1212 states to 1212 states and 1704 transitions. [2020-11-28 02:57:18,661 INFO L714 BuchiCegarLoop]: Abstraction has 1212 states and 1704 transitions. [2020-11-28 02:57:18,661 INFO L594 BuchiCegarLoop]: Abstraction has 1212 states and 1704 transitions. [2020-11-28 02:57:18,661 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 02:57:18,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1212 states and 1704 transitions. [2020-11-28 02:57:18,669 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1168 [2020-11-28 02:57:18,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:18,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:18,670 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,670 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,671 INFO L794 eck$LassoCheckResult]: Stem: 12353#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12223#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12224#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12382#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 12405#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12431#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12441#L233-1 assume !(0 == ~M_E~0); 12343#L336-1 assume !(0 == ~T1_E~0); 12344#L341-1 assume !(0 == ~T2_E~0); 12352#L346-1 assume !(0 == ~E_M~0); 12225#L351-1 assume !(0 == ~E_1~0); 12226#L356-1 assume !(0 == ~E_2~0); 12305#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12285#L158 assume !(1 == ~m_pc~0); 12271#L158-2 is_master_triggered_~__retres1~0 := 0; 12272#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12286#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12275#L417 assume !(0 != activate_threads_~tmp~1); 12276#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12287#L177 assume !(1 == ~t1_pc~0); 12407#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 12408#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12413#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12397#L425 assume !(0 != activate_threads_~tmp___0~0); 12398#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12336#L196 assume !(1 == ~t2_pc~0); 12199#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 12325#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12202#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12203#L433 assume !(0 != activate_threads_~tmp___1~0); 12319#L433-2 assume !(1 == ~M_E~0); 12324#L374-1 assume !(1 == ~T1_E~0); 12369#L379-1 assume !(1 == ~T2_E~0); 12288#L384-1 assume !(1 == ~E_M~0); 12289#L389-1 assume !(1 == ~E_1~0); 12303#L394-1 assume !(1 == ~E_2~0); 12216#L545-1 [2020-11-28 02:57:18,671 INFO L796 eck$LassoCheckResult]: Loop: 12216#L545-1 assume !false; 13258#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13251#L311 assume !false; 13236#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13186#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13183#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13180#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 13177#L278 assume !(0 != eval_~tmp~0); 12403#L326 start_simulation_~kernel_st~0 := 2; 12401#L216-1 start_simulation_~kernel_st~0 := 3; 12337#L336-2 assume !(0 == ~M_E~0); 12338#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12339#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12355#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13383#L351-3 assume !(0 == ~E_1~0); 13382#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13381#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13380#L158-12 assume !(1 == ~m_pc~0); 13379#L158-14 is_master_triggered_~__retres1~0 := 0; 13378#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13377#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13376#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13375#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12388#L177-12 assume !(1 == ~t1_pc~0); 12389#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 12406#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12424#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12379#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12380#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12322#L196-12 assume !(1 == ~t2_pc~0); 12240#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 12318#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12241#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12242#L433-12 assume !(0 != activate_threads_~tmp___1~0); 12264#L433-14 assume !(1 == ~M_E~0); 12265#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12354#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12236#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12237#L389-3 assume !(1 == ~E_1~0); 12307#L394-3 assume !(1 == ~E_2~0); 12335#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12313#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12208#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12209#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 12346#L564 assume !(0 == start_simulation_~tmp~3); 12432#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13398#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13395#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13394#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 13393#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 13392#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 13391#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12215#L577 assume !(0 != start_simulation_~tmp___0~1); 12216#L545-1 [2020-11-28 02:57:18,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2020-11-28 02:57:18,672 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,672 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431891205] [2020-11-28 02:57:18,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:18,687 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:18,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:18,698 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:18,738 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:18,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,739 INFO L82 PathProgramCache]: Analyzing trace with hash -996354553, now seen corresponding path program 1 times [2020-11-28 02:57:18,740 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:18,740 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892942379] [2020-11-28 02:57:18,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:18,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:18,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:18,816 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892942379] [2020-11-28 02:57:18,816 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:18,817 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:18,817 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100958775] [2020-11-28 02:57:18,817 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:18,817 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:18,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:18,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:18,818 INFO L87 Difference]: Start difference. First operand 1212 states and 1704 transitions. cyclomatic complexity: 494 Second operand 3 states. [2020-11-28 02:57:18,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:18,895 INFO L93 Difference]: Finished difference Result 2011 states and 2801 transitions. [2020-11-28 02:57:18,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:18,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2011 states and 2801 transitions. [2020-11-28 02:57:18,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2020-11-28 02:57:18,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2011 states to 2011 states and 2801 transitions. [2020-11-28 02:57:18,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2011 [2020-11-28 02:57:18,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2011 [2020-11-28 02:57:18,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2011 states and 2801 transitions. [2020-11-28 02:57:18,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:18,933 INFO L691 BuchiCegarLoop]: Abstraction has 2011 states and 2801 transitions. [2020-11-28 02:57:18,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2011 states and 2801 transitions. [2020-11-28 02:57:18,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2011 to 2007. [2020-11-28 02:57:18,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2007 states. [2020-11-28 02:57:18,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2007 states to 2007 states and 2797 transitions. [2020-11-28 02:57:18,978 INFO L714 BuchiCegarLoop]: Abstraction has 2007 states and 2797 transitions. [2020-11-28 02:57:18,978 INFO L594 BuchiCegarLoop]: Abstraction has 2007 states and 2797 transitions. [2020-11-28 02:57:18,978 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 02:57:18,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2007 states and 2797 transitions. [2020-11-28 02:57:18,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1934 [2020-11-28 02:57:18,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:18,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:18,998 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,998 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:18,998 INFO L794 eck$LassoCheckResult]: Stem: 15594#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 15450#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15451#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15621#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 15644#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15673#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15681#L233-1 assume !(0 == ~M_E~0); 15583#L336-1 assume !(0 == ~T1_E~0); 15584#L341-1 assume !(0 == ~T2_E~0); 15593#L346-1 assume !(0 == ~E_M~0); 15452#L351-1 assume !(0 == ~E_1~0); 15453#L356-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15534#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15696#L158 assume !(1 == ~m_pc~0); 15495#L158-2 is_master_triggered_~__retres1~0 := 0; 15496#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15511#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15499#L417 assume !(0 != activate_threads_~tmp~1); 15500#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15512#L177 assume !(1 == ~t1_pc~0); 15647#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 15648#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15693#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15635#L425 assume !(0 != activate_threads_~tmp___0~0); 15636#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15692#L196 assume !(1 == ~t2_pc~0); 15573#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 15559#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15430#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15431#L433 assume !(0 != activate_threads_~tmp___1~0); 15553#L433-2 assume !(1 == ~M_E~0); 15558#L374-1 assume !(1 == ~T1_E~0); 15607#L379-1 assume !(1 == ~T2_E~0); 15615#L384-1 assume !(1 == ~E_M~0); 17054#L389-1 assume !(1 == ~E_1~0); 15562#L394-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15563#L545-1 [2020-11-28 02:57:18,999 INFO L796 eck$LassoCheckResult]: Loop: 15563#L545-1 assume !false; 16404#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16390#L311 assume !false; 16403#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16400#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16399#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16398#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16396#L278 assume !(0 != eval_~tmp~0); 16397#L326 start_simulation_~kernel_st~0 := 2; 17141#L216-1 start_simulation_~kernel_st~0 := 3; 17138#L336-2 assume !(0 == ~M_E~0); 17133#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17132#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17130#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17128#L351-3 assume !(0 == ~E_1~0); 17125#L356-3 assume !(0 == ~E_2~0); 17123#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17121#L158-12 assume !(1 == ~m_pc~0); 17119#L158-14 is_master_triggered_~__retres1~0 := 0; 17117#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17114#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17112#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17110#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17108#L177-12 assume !(1 == ~t1_pc~0); 15891#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 17104#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17102#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17100#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17098#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17093#L196-12 assume !(1 == ~t2_pc~0); 17090#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 17088#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17086#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17084#L433-12 assume !(0 != activate_threads_~tmp___1~0); 17081#L433-14 assume !(1 == ~M_E~0); 17076#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17074#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17072#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17070#L389-3 assume !(1 == ~E_1~0); 17067#L394-3 assume !(1 == ~E_2~0); 17066#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17061#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16430#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16426#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 16424#L564 assume !(0 == start_simulation_~tmp~3); 16419#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16418#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16415#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16414#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 16412#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16410#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 16408#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 16406#L577 assume !(0 != start_simulation_~tmp___0~1); 15563#L545-1 [2020-11-28 02:57:18,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:18,999 INFO L82 PathProgramCache]: Analyzing trace with hash -2114878944, now seen corresponding path program 1 times [2020-11-28 02:57:18,999 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,000 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261515417] [2020-11-28 02:57:19,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:19,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:19,028 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261515417] [2020-11-28 02:57:19,028 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:19,028 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:19,028 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280193359] [2020-11-28 02:57:19,028 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:19,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,029 INFO L82 PathProgramCache]: Analyzing trace with hash -2025713851, now seen corresponding path program 1 times [2020-11-28 02:57:19,029 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,029 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876982772] [2020-11-28 02:57:19,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:19,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:19,066 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876982772] [2020-11-28 02:57:19,066 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:19,066 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:19,067 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374927079] [2020-11-28 02:57:19,067 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:19,067 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:19,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:19,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:19,068 INFO L87 Difference]: Start difference. First operand 2007 states and 2797 transitions. cyclomatic complexity: 792 Second operand 3 states. [2020-11-28 02:57:19,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:19,110 INFO L93 Difference]: Finished difference Result 1137 states and 1549 transitions. [2020-11-28 02:57:19,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:19,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1137 states and 1549 transitions. [2020-11-28 02:57:19,121 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1096 [2020-11-28 02:57:19,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1137 states to 1137 states and 1549 transitions. [2020-11-28 02:57:19,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1137 [2020-11-28 02:57:19,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1137 [2020-11-28 02:57:19,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1137 states and 1549 transitions. [2020-11-28 02:57:19,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:19,134 INFO L691 BuchiCegarLoop]: Abstraction has 1137 states and 1549 transitions. [2020-11-28 02:57:19,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1137 states and 1549 transitions. [2020-11-28 02:57:19,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1137 to 1137. [2020-11-28 02:57:19,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1137 states. [2020-11-28 02:57:19,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1137 states to 1137 states and 1549 transitions. [2020-11-28 02:57:19,158 INFO L714 BuchiCegarLoop]: Abstraction has 1137 states and 1549 transitions. [2020-11-28 02:57:19,159 INFO L594 BuchiCegarLoop]: Abstraction has 1137 states and 1549 transitions. [2020-11-28 02:57:19,159 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 02:57:19,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1137 states and 1549 transitions. [2020-11-28 02:57:19,164 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1096 [2020-11-28 02:57:19,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:19,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:19,165 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,165 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,165 INFO L794 eck$LassoCheckResult]: Stem: 18728#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18603#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18604#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18757#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 18780#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18804#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18813#L233-1 assume !(0 == ~M_E~0); 18715#L336-1 assume !(0 == ~T1_E~0); 18716#L341-1 assume !(0 == ~T2_E~0); 18725#L346-1 assume !(0 == ~E_M~0); 18605#L351-1 assume !(0 == ~E_1~0); 18606#L356-1 assume !(0 == ~E_2~0); 18676#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18658#L158 assume !(1 == ~m_pc~0); 18644#L158-2 is_master_triggered_~__retres1~0 := 0; 18645#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18659#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18648#L417 assume !(0 != activate_threads_~tmp~1); 18649#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18660#L177 assume !(1 == ~t1_pc~0); 18782#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 18783#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18787#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18773#L425 assume !(0 != activate_threads_~tmp___0~0); 18774#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18708#L196 assume !(1 == ~t2_pc~0); 18580#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 18698#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18585#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18586#L433 assume !(0 != activate_threads_~tmp___1~0); 18691#L433-2 assume !(1 == ~M_E~0); 18697#L374-1 assume !(1 == ~T1_E~0); 18745#L379-1 assume !(1 == ~T2_E~0); 18661#L384-1 assume !(1 == ~E_M~0); 18662#L389-1 assume !(1 == ~E_1~0); 18674#L394-1 assume !(1 == ~E_2~0); 18700#L545-1 [2020-11-28 02:57:19,166 INFO L796 eck$LassoCheckResult]: Loop: 18700#L545-1 assume !false; 19459#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19457#L311 assume !false; 19455#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19449#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19447#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 19445#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 19443#L278 assume !(0 != eval_~tmp~0); 18778#L326 start_simulation_~kernel_st~0 := 2; 18777#L216-1 start_simulation_~kernel_st~0 := 3; 18709#L336-2 assume !(0 == ~M_E~0); 18710#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18711#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18729#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19705#L351-3 assume !(0 == ~E_1~0); 19704#L356-3 assume !(0 == ~E_2~0); 19703#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19702#L158-12 assume !(1 == ~m_pc~0); 19701#L158-14 is_master_triggered_~__retres1~0 := 0; 19700#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19699#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18601#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18602#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18749#L177-12 assume !(1 == ~t1_pc~0); 19663#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 19661#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19659#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19658#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19657#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19655#L196-12 assume !(1 == ~t2_pc~0); 19654#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 19653#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19652#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19651#L433-12 assume !(0 != activate_threads_~tmp___1~0); 18639#L433-14 assume !(1 == ~M_E~0); 18640#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19604#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19602#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18908#L389-3 assume !(1 == ~E_1~0); 18902#L394-3 assume !(1 == ~E_2~0); 18897#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18898#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18871#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18872#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 19582#L564 assume !(0 == start_simulation_~tmp~3); 19580#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19572#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19565#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 19560#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 19559#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19558#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 19557#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 19492#L577 assume !(0 != start_simulation_~tmp___0~1); 18700#L545-1 [2020-11-28 02:57:19,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,166 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2020-11-28 02:57:19,166 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,167 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32345740] [2020-11-28 02:57:19,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,184 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,194 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,211 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:19,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,211 INFO L82 PathProgramCache]: Analyzing trace with hash -2025713851, now seen corresponding path program 2 times [2020-11-28 02:57:19,211 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,212 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231968705] [2020-11-28 02:57:19,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:19,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:19,246 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231968705] [2020-11-28 02:57:19,246 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:19,246 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:19,246 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061753788] [2020-11-28 02:57:19,247 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:19,247 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:19,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:19,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:19,248 INFO L87 Difference]: Start difference. First operand 1137 states and 1549 transitions. cyclomatic complexity: 414 Second operand 5 states. [2020-11-28 02:57:19,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:19,375 INFO L93 Difference]: Finished difference Result 1957 states and 2623 transitions. [2020-11-28 02:57:19,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 02:57:19,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1957 states and 2623 transitions. [2020-11-28 02:57:19,387 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1912 [2020-11-28 02:57:19,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1957 states to 1957 states and 2623 transitions. [2020-11-28 02:57:19,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1957 [2020-11-28 02:57:19,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1957 [2020-11-28 02:57:19,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1957 states and 2623 transitions. [2020-11-28 02:57:19,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:19,408 INFO L691 BuchiCegarLoop]: Abstraction has 1957 states and 2623 transitions. [2020-11-28 02:57:19,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1957 states and 2623 transitions. [2020-11-28 02:57:19,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1957 to 1161. [2020-11-28 02:57:19,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1161 states. [2020-11-28 02:57:19,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1161 states to 1161 states and 1573 transitions. [2020-11-28 02:57:19,437 INFO L714 BuchiCegarLoop]: Abstraction has 1161 states and 1573 transitions. [2020-11-28 02:57:19,437 INFO L594 BuchiCegarLoop]: Abstraction has 1161 states and 1573 transitions. [2020-11-28 02:57:19,437 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 02:57:19,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1161 states and 1573 transitions. [2020-11-28 02:57:19,442 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1120 [2020-11-28 02:57:19,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:19,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:19,443 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,443 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,443 INFO L794 eck$LassoCheckResult]: Stem: 21839#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21714#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21715#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21867#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 21888#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21913#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21927#L233-1 assume !(0 == ~M_E~0); 21826#L336-1 assume !(0 == ~T1_E~0); 21827#L341-1 assume !(0 == ~T2_E~0); 21837#L346-1 assume !(0 == ~E_M~0); 21718#L351-1 assume !(0 == ~E_1~0); 21719#L356-1 assume !(0 == ~E_2~0); 21786#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21769#L158 assume !(1 == ~m_pc~0); 21755#L158-2 is_master_triggered_~__retres1~0 := 0; 21756#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21770#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21759#L417 assume !(0 != activate_threads_~tmp~1); 21760#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21773#L177 assume !(1 == ~t1_pc~0); 21890#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 21891#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21896#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21880#L425 assume !(0 != activate_threads_~tmp___0~0); 21881#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21819#L196 assume !(1 == ~t2_pc~0); 21692#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 21807#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21695#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21696#L433 assume !(0 != activate_threads_~tmp___1~0); 21803#L433-2 assume !(1 == ~M_E~0); 21806#L374-1 assume !(1 == ~T1_E~0); 21855#L379-1 assume !(1 == ~T2_E~0); 21774#L384-1 assume !(1 == ~E_M~0); 21775#L389-1 assume !(1 == ~E_1~0); 21784#L394-1 assume !(1 == ~E_2~0); 21811#L545-1 [2020-11-28 02:57:19,444 INFO L796 eck$LassoCheckResult]: Loop: 21811#L545-1 assume !false; 22724#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22714#L311 assume !false; 22682#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22680#L246 assume !(0 == ~m_st~0); 22678#L250 assume !(0 == ~t1_st~0); 22668#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 22662#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22656#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 22654#L278 assume !(0 != eval_~tmp~0); 22653#L326 start_simulation_~kernel_st~0 := 2; 22652#L216-1 start_simulation_~kernel_st~0 := 3; 21820#L336-2 assume !(0 == ~M_E~0); 21821#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21822#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21840#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21858#L351-3 assume !(0 == ~E_1~0); 22648#L356-3 assume !(0 == ~E_2~0); 21817#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21818#L158-12 assume !(1 == ~m_pc~0); 21693#L158-14 is_master_triggered_~__retres1~0 := 0; 21694#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21749#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21712#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21713#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21859#L177-12 assume !(1 == ~t1_pc~0); 21872#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 21889#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21936#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21864#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21865#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21804#L196-12 assume !(1 == ~t2_pc~0); 21729#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 21799#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21730#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21731#L433-12 assume !(0 != activate_threads_~tmp___1~0); 21750#L433-14 assume !(1 == ~M_E~0); 21751#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21838#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21724#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21725#L389-3 assume !(1 == ~E_1~0); 21815#L394-3 assume !(1 == ~E_2~0); 21816#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21796#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 21797#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22771#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 22767#L564 assume !(0 == start_simulation_~tmp~3); 22763#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22762#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22756#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22751#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 22748#L519 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 22745#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 22740#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22733#L577 assume !(0 != start_simulation_~tmp___0~1); 21811#L545-1 [2020-11-28 02:57:19,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,444 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2020-11-28 02:57:19,444 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,445 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458111612] [2020-11-28 02:57:19,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,456 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,468 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,485 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:19,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1868880180, now seen corresponding path program 1 times [2020-11-28 02:57:19,486 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,486 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353009457] [2020-11-28 02:57:19,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:19,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:19,525 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353009457] [2020-11-28 02:57:19,526 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:19,526 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:19,526 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318975556] [2020-11-28 02:57:19,526 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:19,526 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:19,527 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:19,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:19,527 INFO L87 Difference]: Start difference. First operand 1161 states and 1573 transitions. cyclomatic complexity: 414 Second operand 5 states. [2020-11-28 02:57:19,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:19,676 INFO L93 Difference]: Finished difference Result 3581 states and 4807 transitions. [2020-11-28 02:57:19,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 02:57:19,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3581 states and 4807 transitions. [2020-11-28 02:57:19,699 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3528 [2020-11-28 02:57:19,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3581 states to 3581 states and 4807 transitions. [2020-11-28 02:57:19,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3581 [2020-11-28 02:57:19,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3581 [2020-11-28 02:57:19,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3581 states and 4807 transitions. [2020-11-28 02:57:19,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:19,737 INFO L691 BuchiCegarLoop]: Abstraction has 3581 states and 4807 transitions. [2020-11-28 02:57:19,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3581 states and 4807 transitions. [2020-11-28 02:57:19,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3581 to 1185. [2020-11-28 02:57:19,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1185 states. [2020-11-28 02:57:19,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1597 transitions. [2020-11-28 02:57:19,809 INFO L714 BuchiCegarLoop]: Abstraction has 1185 states and 1597 transitions. [2020-11-28 02:57:19,809 INFO L594 BuchiCegarLoop]: Abstraction has 1185 states and 1597 transitions. [2020-11-28 02:57:19,809 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 02:57:19,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1597 transitions. [2020-11-28 02:57:19,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1144 [2020-11-28 02:57:19,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:19,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:19,816 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,816 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:19,816 INFO L794 eck$LassoCheckResult]: Stem: 26598#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 26473#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26474#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26626#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 26647#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26673#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26683#L233-1 assume !(0 == ~M_E~0); 26584#L336-1 assume !(0 == ~T1_E~0); 26585#L341-1 assume !(0 == ~T2_E~0); 26595#L346-1 assume !(0 == ~E_M~0); 26477#L351-1 assume !(0 == ~E_1~0); 26478#L356-1 assume !(0 == ~E_2~0); 26547#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26529#L158 assume !(1 == ~m_pc~0); 26515#L158-2 is_master_triggered_~__retres1~0 := 0; 26516#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26530#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26519#L417 assume !(0 != activate_threads_~tmp~1); 26520#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26533#L177 assume !(1 == ~t1_pc~0); 26650#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 26651#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26657#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26639#L425 assume !(0 != activate_threads_~tmp___0~0); 26640#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26577#L196 assume !(1 == ~t2_pc~0); 26451#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 26566#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26454#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26455#L433 assume !(0 != activate_threads_~tmp___1~0); 26562#L433-2 assume !(1 == ~M_E~0); 26565#L374-1 assume !(1 == ~T1_E~0); 26616#L379-1 assume !(1 == ~T2_E~0); 26534#L384-1 assume !(1 == ~E_M~0); 26535#L389-1 assume !(1 == ~E_1~0); 26545#L394-1 assume !(1 == ~E_2~0); 26571#L545-1 [2020-11-28 02:57:19,816 INFO L796 eck$LassoCheckResult]: Loop: 26571#L545-1 assume !false; 27509#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 27507#L311 assume !false; 27501#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 27500#L246 assume !(0 == ~m_st~0); 26680#L250 assume !(0 == ~t1_st~0); 26682#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 27497#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 27496#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 27494#L278 assume !(0 != eval_~tmp~0); 27493#L326 start_simulation_~kernel_st~0 := 2; 27492#L216-1 start_simulation_~kernel_st~0 := 3; 26578#L336-2 assume !(0 == ~M_E~0); 26579#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26580#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26599#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26492#L351-3 assume !(0 == ~E_1~0); 26493#L356-3 assume !(0 == ~E_2~0); 26553#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27586#L158-12 assume !(1 == ~m_pc~0); 26452#L158-14 is_master_triggered_~__retres1~0 := 0; 26453#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26508#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26607#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27583#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27582#L177-12 assume !(1 == ~t1_pc~0); 26648#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 26649#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26667#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26622#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26623#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26563#L196-12 assume !(1 == ~t2_pc~0); 26488#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 26558#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26489#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26490#L433-12 assume !(0 != activate_threads_~tmp___1~0); 26509#L433-14 assume !(1 == ~M_E~0); 26510#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27564#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27562#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27561#L389-3 assume !(1 == ~E_1~0); 27559#L394-3 assume !(1 == ~E_2~0); 27557#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 27554#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 27551#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 27527#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 27526#L564 assume !(0 == start_simulation_~tmp~3); 27524#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 26531#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 26448#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 26449#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 26624#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26625#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 26543#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 26544#L577 assume !(0 != start_simulation_~tmp___0~1); 26571#L545-1 [2020-11-28 02:57:19,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,817 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2020-11-28 02:57:19,817 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,817 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277123818] [2020-11-28 02:57:19,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,829 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:19,839 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:19,856 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:19,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:19,858 INFO L82 PathProgramCache]: Analyzing trace with hash -1868939762, now seen corresponding path program 1 times [2020-11-28 02:57:19,858 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:19,858 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870019168] [2020-11-28 02:57:19,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:19,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:19,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:19,939 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870019168] [2020-11-28 02:57:19,939 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:19,940 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:19,940 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948848558] [2020-11-28 02:57:19,940 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:19,940 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:19,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:19,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:19,941 INFO L87 Difference]: Start difference. First operand 1185 states and 1597 transitions. cyclomatic complexity: 414 Second operand 5 states. [2020-11-28 02:57:20,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:20,126 INFO L93 Difference]: Finished difference Result 2303 states and 3064 transitions. [2020-11-28 02:57:20,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 02:57:20,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2303 states and 3064 transitions. [2020-11-28 02:57:20,138 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2262 [2020-11-28 02:57:20,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2303 states to 2303 states and 3064 transitions. [2020-11-28 02:57:20,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2303 [2020-11-28 02:57:20,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2303 [2020-11-28 02:57:20,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2303 states and 3064 transitions. [2020-11-28 02:57:20,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:20,172 INFO L691 BuchiCegarLoop]: Abstraction has 2303 states and 3064 transitions. [2020-11-28 02:57:20,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2303 states and 3064 transitions. [2020-11-28 02:57:20,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2303 to 1233. [2020-11-28 02:57:20,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1233 states. [2020-11-28 02:57:20,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1233 states to 1233 states and 1632 transitions. [2020-11-28 02:57:20,204 INFO L714 BuchiCegarLoop]: Abstraction has 1233 states and 1632 transitions. [2020-11-28 02:57:20,204 INFO L594 BuchiCegarLoop]: Abstraction has 1233 states and 1632 transitions. [2020-11-28 02:57:20,204 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 02:57:20,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1233 states and 1632 transitions. [2020-11-28 02:57:20,209 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1192 [2020-11-28 02:57:20,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:20,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:20,210 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,210 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,210 INFO L794 eck$LassoCheckResult]: Stem: 30109#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 29975#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 29976#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30142#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 30167#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30193#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30202#L233-1 assume !(0 == ~M_E~0); 30098#L336-1 assume !(0 == ~T1_E~0); 30099#L341-1 assume !(0 == ~T2_E~0); 30106#L346-1 assume !(0 == ~E_M~0); 29979#L351-1 assume !(0 == ~E_1~0); 29980#L356-1 assume !(0 == ~E_2~0); 30058#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30033#L158 assume !(1 == ~m_pc~0); 30019#L158-2 is_master_triggered_~__retres1~0 := 0; 30020#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30034#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30023#L417 assume !(0 != activate_threads_~tmp~1); 30024#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30037#L177 assume !(1 == ~t1_pc~0); 30170#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 30171#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30178#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30159#L425 assume !(0 != activate_threads_~tmp___0~0); 30160#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30091#L196 assume !(1 == ~t2_pc~0); 29952#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 30078#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29955#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29956#L433 assume !(0 != activate_threads_~tmp___1~0); 30074#L433-2 assume !(1 == ~M_E~0); 30077#L374-1 assume !(1 == ~T1_E~0); 30128#L379-1 assume !(1 == ~T2_E~0); 30038#L384-1 assume !(1 == ~E_M~0); 30039#L389-1 assume !(1 == ~E_1~0); 30055#L394-1 assume !(1 == ~E_2~0); 30083#L545-1 [2020-11-28 02:57:20,216 INFO L796 eck$LassoCheckResult]: Loop: 30083#L545-1 assume !false; 30427#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 30415#L311 assume !false; 30411#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 30407#L246 assume !(0 == ~m_st~0); 30403#L250 assume !(0 == ~t1_st~0); 30397#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 30391#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 30387#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 30381#L278 assume !(0 != eval_~tmp~0); 30375#L326 start_simulation_~kernel_st~0 := 2; 30371#L216-1 start_simulation_~kernel_st~0 := 3; 30367#L336-2 assume !(0 == ~M_E~0); 30363#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30359#L341-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30355#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30351#L351-3 assume !(0 == ~E_1~0); 30347#L356-3 assume !(0 == ~E_2~0); 30343#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30339#L158-12 assume !(1 == ~m_pc~0); 30335#L158-14 is_master_triggered_~__retres1~0 := 0; 30331#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30327#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30323#L417-12 assume !(0 != activate_threads_~tmp~1); 30319#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30287#L177-12 assume !(1 == ~t1_pc~0); 30285#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 30283#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30281#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30279#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30277#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30274#L196-12 assume !(1 == ~t2_pc~0); 30271#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 30269#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30267#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30265#L433-12 assume !(0 != activate_threads_~tmp___1~0); 30263#L433-14 assume !(1 == ~M_E~0); 30259#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30257#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30255#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30252#L389-3 assume !(1 == ~E_1~0); 30249#L394-3 assume !(1 == ~E_2~0); 30247#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 30235#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 30234#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 30224#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 30225#L564 assume !(0 == start_simulation_~tmp~3); 30243#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 30666#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 30662#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 30660#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 30659#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30657#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 30655#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 30653#L577 assume !(0 != start_simulation_~tmp___0~1); 30083#L545-1 [2020-11-28 02:57:20,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 5 times [2020-11-28 02:57:20,218 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,218 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499254838] [2020-11-28 02:57:20,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,226 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,233 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,241 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:20,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,245 INFO L82 PathProgramCache]: Analyzing trace with hash -1594180148, now seen corresponding path program 1 times [2020-11-28 02:57:20,245 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,245 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636598886] [2020-11-28 02:57:20,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:20,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:20,282 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636598886] [2020-11-28 02:57:20,282 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:20,306 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:20,307 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905248108] [2020-11-28 02:57:20,307 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:20,307 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:20,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:20,308 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:20,308 INFO L87 Difference]: Start difference. First operand 1233 states and 1632 transitions. cyclomatic complexity: 401 Second operand 3 states. [2020-11-28 02:57:20,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:20,362 INFO L93 Difference]: Finished difference Result 1823 states and 2363 transitions. [2020-11-28 02:57:20,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:20,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1823 states and 2363 transitions. [2020-11-28 02:57:20,373 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1782 [2020-11-28 02:57:20,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1823 states to 1823 states and 2363 transitions. [2020-11-28 02:57:20,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1823 [2020-11-28 02:57:20,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1823 [2020-11-28 02:57:20,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1823 states and 2363 transitions. [2020-11-28 02:57:20,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:20,390 INFO L691 BuchiCegarLoop]: Abstraction has 1823 states and 2363 transitions. [2020-11-28 02:57:20,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1823 states and 2363 transitions. [2020-11-28 02:57:20,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1823 to 1765. [2020-11-28 02:57:20,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1765 states. [2020-11-28 02:57:20,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2293 transitions. [2020-11-28 02:57:20,430 INFO L714 BuchiCegarLoop]: Abstraction has 1765 states and 2293 transitions. [2020-11-28 02:57:20,430 INFO L594 BuchiCegarLoop]: Abstraction has 1765 states and 2293 transitions. [2020-11-28 02:57:20,431 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 02:57:20,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1765 states and 2293 transitions. [2020-11-28 02:57:20,438 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1724 [2020-11-28 02:57:20,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:20,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:20,439 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,439 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,439 INFO L794 eck$LassoCheckResult]: Stem: 33168#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 33037#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 33038#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33192#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 33215#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33244#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33251#L233-1 assume !(0 == ~M_E~0); 33155#L336-1 assume !(0 == ~T1_E~0); 33156#L341-1 assume !(0 == ~T2_E~0); 33166#L346-1 assume !(0 == ~E_M~0); 33039#L351-1 assume !(0 == ~E_1~0); 33040#L356-1 assume !(0 == ~E_2~0); 33116#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33094#L158 assume !(1 == ~m_pc~0); 33080#L158-2 is_master_triggered_~__retres1~0 := 0; 33081#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33095#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33084#L417 assume !(0 != activate_threads_~tmp~1); 33085#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33096#L177 assume !(1 == ~t1_pc~0); 33217#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 33218#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33222#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33206#L425 assume !(0 != activate_threads_~tmp___0~0); 33207#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33148#L196 assume !(1 == ~t2_pc~0); 33013#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 33138#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33018#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33019#L433 assume !(0 != activate_threads_~tmp___1~0); 33132#L433-2 assume !(1 == ~M_E~0); 33137#L374-1 assume !(1 == ~T1_E~0); 33178#L379-1 assume !(1 == ~T2_E~0); 33097#L384-1 assume !(1 == ~E_M~0); 33098#L389-1 assume !(1 == ~E_1~0); 33114#L394-1 assume !(1 == ~E_2~0); 33140#L545-1 assume !false; 33310#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 33311#L311 [2020-11-28 02:57:20,439 INFO L796 eck$LassoCheckResult]: Loop: 33311#L311 assume !false; 33306#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 33307#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 33301#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 33302#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 33297#L278 assume 0 != eval_~tmp~0; 33298#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 33292#L286 assume !(0 != eval_~tmp_ndt_1~0); 33293#L283 assume !(0 == ~t1_st~0); 33315#L297 assume !(0 == ~t2_st~0); 33311#L311 [2020-11-28 02:57:20,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,440 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2020-11-28 02:57:20,440 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,442 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589139764] [2020-11-28 02:57:20,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,455 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,463 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,470 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:20,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,471 INFO L82 PathProgramCache]: Analyzing trace with hash -1924963853, now seen corresponding path program 1 times [2020-11-28 02:57:20,471 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,471 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119781542] [2020-11-28 02:57:20,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,482 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,484 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,486 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:20,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,487 INFO L82 PathProgramCache]: Analyzing trace with hash -460322568, now seen corresponding path program 1 times [2020-11-28 02:57:20,487 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,487 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132457110] [2020-11-28 02:57:20,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:20,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:20,517 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132457110] [2020-11-28 02:57:20,517 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:20,518 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:20,518 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167685762] [2020-11-28 02:57:20,615 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:20,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:20,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:20,616 INFO L87 Difference]: Start difference. First operand 1765 states and 2293 transitions. cyclomatic complexity: 531 Second operand 3 states. [2020-11-28 02:57:20,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:20,752 INFO L93 Difference]: Finished difference Result 3098 states and 3956 transitions. [2020-11-28 02:57:20,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:20,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3098 states and 3956 transitions. [2020-11-28 02:57:20,768 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3021 [2020-11-28 02:57:20,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3098 states to 3098 states and 3956 transitions. [2020-11-28 02:57:20,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3098 [2020-11-28 02:57:20,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3098 [2020-11-28 02:57:20,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3098 states and 3956 transitions. [2020-11-28 02:57:20,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:20,793 INFO L691 BuchiCegarLoop]: Abstraction has 3098 states and 3956 transitions. [2020-11-28 02:57:20,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3098 states and 3956 transitions. [2020-11-28 02:57:20,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3098 to 3007. [2020-11-28 02:57:20,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3007 states. [2020-11-28 02:57:20,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3007 states to 3007 states and 3851 transitions. [2020-11-28 02:57:20,849 INFO L714 BuchiCegarLoop]: Abstraction has 3007 states and 3851 transitions. [2020-11-28 02:57:20,849 INFO L594 BuchiCegarLoop]: Abstraction has 3007 states and 3851 transitions. [2020-11-28 02:57:20,849 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 02:57:20,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3007 states and 3851 transitions. [2020-11-28 02:57:20,860 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2930 [2020-11-28 02:57:20,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:20,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:20,861 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,861 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:20,861 INFO L794 eck$LassoCheckResult]: Stem: 38046#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 37906#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 37907#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 38087#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 38115#L223-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 38147#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38155#L233-1 assume !(0 == ~M_E~0); 38034#L336-1 assume !(0 == ~T1_E~0); 38035#L341-1 assume !(0 == ~T2_E~0); 38067#L346-1 assume !(0 == ~E_M~0); 38068#L351-1 assume !(0 == ~E_1~0); 37986#L356-1 assume !(0 == ~E_2~0); 37987#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37962#L158 assume !(1 == ~m_pc~0); 37963#L158-2 is_master_triggered_~__retres1~0 := 0; 37964#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37965#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 37952#L417 assume !(0 != activate_threads_~tmp~1); 37953#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38122#L177 assume !(1 == ~t1_pc~0); 38123#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 38125#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38126#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38104#L425 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38105#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38109#L196 assume !(1 == ~t2_pc~0); 38021#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 38022#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39668#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 39667#L433 assume !(0 != activate_threads_~tmp___1~0); 39666#L433-2 assume !(1 == ~M_E~0); 38063#L374-1 assume !(1 == ~T1_E~0); 38064#L379-1 assume !(1 == ~T2_E~0); 37968#L384-1 assume !(1 == ~E_M~0); 37969#L389-1 assume !(1 == ~E_1~0); 38011#L394-1 assume !(1 == ~E_2~0); 38012#L545-1 assume !false; 40046#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 40044#L311 [2020-11-28 02:57:20,862 INFO L796 eck$LassoCheckResult]: Loop: 40044#L311 assume !false; 40043#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 40040#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 40038#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 40036#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 40034#L278 assume 0 != eval_~tmp~0; 40031#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 38040#L286 assume !(0 != eval_~tmp_ndt_1~0); 38041#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 39643#L300 assume !(0 != eval_~tmp_ndt_2~0); 39707#L297 assume !(0 == ~t2_st~0); 40044#L311 [2020-11-28 02:57:20,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,862 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2020-11-28 02:57:20,863 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,863 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537711493] [2020-11-28 02:57:20,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:20,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:20,886 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537711493] [2020-11-28 02:57:20,887 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:20,887 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:20,887 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093056248] [2020-11-28 02:57:20,887 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:20,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:20,888 INFO L82 PathProgramCache]: Analyzing trace with hash 455557886, now seen corresponding path program 1 times [2020-11-28 02:57:20,888 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:20,888 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619594668] [2020-11-28 02:57:20,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:20,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,891 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:20,893 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:20,895 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:21,036 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:21,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:21,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:21,037 INFO L87 Difference]: Start difference. First operand 3007 states and 3851 transitions. cyclomatic complexity: 847 Second operand 3 states. [2020-11-28 02:57:21,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:21,056 INFO L93 Difference]: Finished difference Result 2973 states and 3808 transitions. [2020-11-28 02:57:21,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:21,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2973 states and 3808 transitions. [2020-11-28 02:57:21,070 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2930 [2020-11-28 02:57:21,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2973 states to 2973 states and 3808 transitions. [2020-11-28 02:57:21,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2973 [2020-11-28 02:57:21,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2973 [2020-11-28 02:57:21,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2973 states and 3808 transitions. [2020-11-28 02:57:21,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:21,105 INFO L691 BuchiCegarLoop]: Abstraction has 2973 states and 3808 transitions. [2020-11-28 02:57:21,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2973 states and 3808 transitions. [2020-11-28 02:57:21,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2973 to 2973. [2020-11-28 02:57:21,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2973 states. [2020-11-28 02:57:21,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2973 states to 2973 states and 3808 transitions. [2020-11-28 02:57:21,160 INFO L714 BuchiCegarLoop]: Abstraction has 2973 states and 3808 transitions. [2020-11-28 02:57:21,160 INFO L594 BuchiCegarLoop]: Abstraction has 2973 states and 3808 transitions. [2020-11-28 02:57:21,160 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 02:57:21,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2973 states and 3808 transitions. [2020-11-28 02:57:21,171 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2930 [2020-11-28 02:57:21,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:21,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:21,171 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:21,172 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:21,172 INFO L794 eck$LassoCheckResult]: Stem: 44017#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 43892#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 43893#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44047#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 44069#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44096#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44106#L233-1 assume !(0 == ~M_E~0); 44005#L336-1 assume !(0 == ~T1_E~0); 44006#L341-1 assume !(0 == ~T2_E~0); 44014#L346-1 assume !(0 == ~E_M~0); 43896#L351-1 assume !(0 == ~E_1~0); 43897#L356-1 assume !(0 == ~E_2~0); 43966#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43947#L158 assume !(1 == ~m_pc~0); 43933#L158-2 is_master_triggered_~__retres1~0 := 0; 43934#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43948#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43937#L417 assume !(0 != activate_threads_~tmp~1); 43938#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43951#L177 assume !(1 == ~t1_pc~0); 44072#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 44073#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44080#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44061#L425 assume !(0 != activate_threads_~tmp___0~0); 44062#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43998#L196 assume !(1 == ~t2_pc~0); 43871#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 43985#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43874#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43875#L433 assume !(0 != activate_threads_~tmp___1~0); 43981#L433-2 assume !(1 == ~M_E~0); 43984#L374-1 assume !(1 == ~T1_E~0); 44035#L379-1 assume !(1 == ~T2_E~0); 43952#L384-1 assume !(1 == ~E_M~0); 43953#L389-1 assume !(1 == ~E_1~0); 43964#L394-1 assume !(1 == ~E_2~0); 43989#L545-1 assume !false; 46224#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 46221#L311 [2020-11-28 02:57:21,172 INFO L796 eck$LassoCheckResult]: Loop: 46221#L311 assume !false; 46218#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 46214#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 46210#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 46206#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 46203#L278 assume 0 != eval_~tmp~0; 46180#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 44011#L286 assume !(0 != eval_~tmp_ndt_1~0); 44012#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 45877#L300 assume !(0 != eval_~tmp_ndt_2~0); 45878#L297 assume !(0 == ~t2_st~0); 46221#L311 [2020-11-28 02:57:21,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2020-11-28 02:57:21,172 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,173 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453861489] [2020-11-28 02:57:21,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,181 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,189 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,202 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:21,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,203 INFO L82 PathProgramCache]: Analyzing trace with hash 455557886, now seen corresponding path program 2 times [2020-11-28 02:57:21,203 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,203 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256584552] [2020-11-28 02:57:21,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,211 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,216 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,218 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:21,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1385202535, now seen corresponding path program 1 times [2020-11-28 02:57:21,219 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,219 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798478630] [2020-11-28 02:57:21,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:21,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:21,275 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798478630] [2020-11-28 02:57:21,275 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:21,276 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:21,276 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709182070] [2020-11-28 02:57:21,358 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:21,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:21,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:21,359 INFO L87 Difference]: Start difference. First operand 2973 states and 3808 transitions. cyclomatic complexity: 838 Second operand 3 states. [2020-11-28 02:57:21,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:21,404 INFO L93 Difference]: Finished difference Result 4284 states and 5451 transitions. [2020-11-28 02:57:21,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:21,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4284 states and 5451 transitions. [2020-11-28 02:57:21,424 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4237 [2020-11-28 02:57:21,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4284 states to 4284 states and 5451 transitions. [2020-11-28 02:57:21,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4284 [2020-11-28 02:57:21,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4284 [2020-11-28 02:57:21,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4284 states and 5451 transitions. [2020-11-28 02:57:21,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:21,453 INFO L691 BuchiCegarLoop]: Abstraction has 4284 states and 5451 transitions. [2020-11-28 02:57:21,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4284 states and 5451 transitions. [2020-11-28 02:57:21,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4284 to 4284. [2020-11-28 02:57:21,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4284 states. [2020-11-28 02:57:21,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4284 states to 4284 states and 5451 transitions. [2020-11-28 02:57:21,585 INFO L714 BuchiCegarLoop]: Abstraction has 4284 states and 5451 transitions. [2020-11-28 02:57:21,585 INFO L594 BuchiCegarLoop]: Abstraction has 4284 states and 5451 transitions. [2020-11-28 02:57:21,586 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-28 02:57:21,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4284 states and 5451 transitions. [2020-11-28 02:57:21,601 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4237 [2020-11-28 02:57:21,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:21,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:21,602 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:21,602 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:21,602 INFO L794 eck$LassoCheckResult]: Stem: 51291#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 51157#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 51158#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 51322#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 51347#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51372#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51385#L233-1 assume !(0 == ~M_E~0); 51278#L336-1 assume !(0 == ~T1_E~0); 51279#L341-1 assume !(0 == ~T2_E~0); 51288#L346-1 assume !(0 == ~E_M~0); 51161#L351-1 assume !(0 == ~E_1~0); 51162#L356-1 assume !(0 == ~E_2~0); 51235#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51214#L158 assume !(1 == ~m_pc~0); 51200#L158-2 is_master_triggered_~__retres1~0 := 0; 51201#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51215#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51204#L417 assume !(0 != activate_threads_~tmp~1); 51205#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51218#L177 assume !(1 == ~t1_pc~0); 51349#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 51350#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51356#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51337#L425 assume !(0 != activate_threads_~tmp___0~0); 51338#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51270#L196 assume !(1 == ~t2_pc~0); 51136#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 51260#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51139#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51140#L433 assume !(0 != activate_threads_~tmp___1~0); 51255#L433-2 assume !(1 == ~M_E~0); 51259#L374-1 assume !(1 == ~T1_E~0); 51310#L379-1 assume !(1 == ~T2_E~0); 51219#L384-1 assume !(1 == ~E_M~0); 51220#L389-1 assume !(1 == ~E_1~0); 51233#L394-1 assume !(1 == ~E_2~0); 51265#L545-1 assume !false; 53695#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 53459#L311 [2020-11-28 02:57:21,603 INFO L796 eck$LassoCheckResult]: Loop: 53459#L311 assume !false; 53694#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 53691#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 53690#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 53689#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 53687#L278 assume 0 != eval_~tmp~0; 53684#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 53541#L286 assume !(0 != eval_~tmp_ndt_1~0); 53096#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 53091#L300 assume !(0 != eval_~tmp_ndt_2~0); 53092#L297 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 53441#L314 assume !(0 != eval_~tmp_ndt_3~0); 53459#L311 [2020-11-28 02:57:21,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2020-11-28 02:57:21,603 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,604 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670220047] [2020-11-28 02:57:21,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,615 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,627 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,634 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:21,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1237389843, now seen corresponding path program 1 times [2020-11-28 02:57:21,637 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,637 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58080828] [2020-11-28 02:57:21,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,641 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,643 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,644 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:21,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:21,646 INFO L82 PathProgramCache]: Analyzing trace with hash 8391640, now seen corresponding path program 1 times [2020-11-28 02:57:21,646 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:21,647 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492961303] [2020-11-28 02:57:21,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:21,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,656 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:21,669 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:21,682 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:22,546 WARN L193 SmtUtils]: Spent 734.00 ms on a formula simplification. DAG size of input: 158 DAG size of output: 119 [2020-11-28 02:57:22,831 WARN L193 SmtUtils]: Spent 258.00 ms on a formula simplification that was a NOOP. DAG size: 105 [2020-11-28 02:57:22,874 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 02:57:22 BoogieIcfgContainer [2020-11-28 02:57:22,875 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 02:57:22,875 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 02:57:22,875 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 02:57:22,875 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 02:57:22,876 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:15" (3/4) ... [2020-11-28 02:57:22,878 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 02:57:22,924 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_dd9f3d3c-8d63-4d95-be53-b9ae081aa207/bin/uautomizer/witness.graphml [2020-11-28 02:57:22,925 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 02:57:22,926 INFO L168 Benchmark]: Toolchain (without parser) took 8625.06 ms. Allocated memory was 102.8 MB in the beginning and 331.4 MB in the end (delta: 228.6 MB). Free memory was 66.1 MB in the beginning and 252.5 MB in the end (delta: -186.4 MB). Peak memory consumption was 42.4 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,926 INFO L168 Benchmark]: CDTParser took 0.81 ms. Allocated memory is still 102.8 MB. Free memory is still 82.7 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 02:57:22,927 INFO L168 Benchmark]: CACSL2BoogieTranslator took 426.17 ms. Allocated memory is still 102.8 MB. Free memory was 65.9 MB in the beginning and 76.0 MB in the end (delta: -10.1 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,927 INFO L168 Benchmark]: Boogie Procedure Inliner took 62.54 ms. Allocated memory is still 102.8 MB. Free memory was 76.0 MB in the beginning and 73.0 MB in the end (delta: 2.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,928 INFO L168 Benchmark]: Boogie Preprocessor took 79.11 ms. Allocated memory is still 102.8 MB. Free memory was 73.0 MB in the beginning and 70.6 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,928 INFO L168 Benchmark]: RCFGBuilder took 1058.00 ms. Allocated memory is still 102.8 MB. Free memory was 70.6 MB in the beginning and 55.3 MB in the end (delta: 15.3 MB). Peak memory consumption was 34.6 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,929 INFO L168 Benchmark]: BuchiAutomizer took 6928.67 ms. Allocated memory was 102.8 MB in the beginning and 331.4 MB in the end (delta: 228.6 MB). Free memory was 55.3 MB in the beginning and 255.6 MB in the end (delta: -200.3 MB). Peak memory consumption was 111.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,929 INFO L168 Benchmark]: Witness Printer took 49.81 ms. Allocated memory is still 331.4 MB. Free memory was 255.6 MB in the beginning and 252.5 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:57:22,931 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.81 ms. Allocated memory is still 102.8 MB. Free memory is still 82.7 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 426.17 ms. Allocated memory is still 102.8 MB. Free memory was 65.9 MB in the beginning and 76.0 MB in the end (delta: -10.1 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 62.54 ms. Allocated memory is still 102.8 MB. Free memory was 76.0 MB in the beginning and 73.0 MB in the end (delta: 2.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 79.11 ms. Allocated memory is still 102.8 MB. Free memory was 73.0 MB in the beginning and 70.6 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1058.00 ms. Allocated memory is still 102.8 MB. Free memory was 70.6 MB in the beginning and 55.3 MB in the end (delta: 15.3 MB). Peak memory consumption was 34.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 6928.67 ms. Allocated memory was 102.8 MB in the beginning and 331.4 MB in the end (delta: 228.6 MB). Free memory was 55.3 MB in the beginning and 255.6 MB in the end (delta: -200.3 MB). Peak memory consumption was 111.1 MB. Max. memory is 16.1 GB. * Witness Printer took 49.81 ms. Allocated memory is still 331.4 MB. Free memory was 255.6 MB in the beginning and 252.5 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4284 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.8s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 3.5s. Construction of modules took 0.9s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 17 MinimizatonAttempts, 5858 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 4284 states and ocurred in iteration 17. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5790 SDtfs, 7065 SDslu, 6932 SDs, 0 SdLazy, 531 SolverSat, 183 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 273]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=2061} State at position 1 is {NULL=0, token=0, NULL=2061, tmp=1, __retres1=0, kernel_st=1, t2_st=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b596091=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@48d9bd68=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@202b096d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ffd668b=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7789f84=0, NULL=2062, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=2063, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=2064, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@269ff437=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f1ced6c=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@350a68d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50e2a0cf=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 273]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int M_E = 2; [L26] int T1_E = 2; [L27] int T2_E = 2; [L28] int E_M = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L35] int token ; [L37] int local ; [L590] int __retres1 ; [L504] m_i = 1 [L505] t1_i = 1 [L506] t2_i = 1 [L531] int kernel_st ; [L532] int tmp ; [L533] int tmp___0 ; [L537] kernel_st = 0 [L223] COND TRUE m_i == 1 [L224] m_st = 0 [L228] COND TRUE t1_i == 1 [L229] t1_st = 0 [L233] COND TRUE t2_i == 1 [L234] t2_st = 0 [L336] COND FALSE !(M_E == 0) [L341] COND FALSE !(T1_E == 0) [L346] COND FALSE !(T2_E == 0) [L351] COND FALSE !(E_M == 0) [L356] COND FALSE !(E_1 == 0) [L361] COND FALSE !(E_2 == 0) [L409] int tmp ; [L410] int tmp___0 ; [L411] int tmp___1 ; [L155] int __retres1 ; [L158] COND FALSE !(m_pc == 1) [L168] __retres1 = 0 [L170] return (__retres1); [L415] tmp = is_master_triggered() [L417] COND FALSE !(\read(tmp)) [L174] int __retres1 ; [L177] COND FALSE !(t1_pc == 1) [L187] __retres1 = 0 [L189] return (__retres1); [L423] tmp___0 = is_transmit1_triggered() [L425] COND FALSE !(\read(tmp___0)) [L193] int __retres1 ; [L196] COND FALSE !(t2_pc == 1) [L206] __retres1 = 0 [L208] return (__retres1); [L431] tmp___1 = is_transmit2_triggered() [L433] COND FALSE !(\read(tmp___1)) [L374] COND FALSE !(M_E == 1) [L379] COND FALSE !(T1_E == 1) [L384] COND FALSE !(T2_E == 1) [L389] COND FALSE !(E_M == 1) [L394] COND FALSE !(E_1 == 1) [L399] COND FALSE !(E_2 == 1) [L545] COND TRUE 1 [L548] kernel_st = 1 [L269] int tmp ; Loop: [L273] COND TRUE 1 [L243] int __retres1 ; [L246] COND TRUE m_st == 0 [L247] __retres1 = 1 [L264] return (__retres1); [L276] tmp = exists_runnable_thread() [L278] COND TRUE \read(tmp) [L283] COND TRUE m_st == 0 [L284] int tmp_ndt_1; [L285] tmp_ndt_1 = __VERIFIER_nondet_int() [L286] COND FALSE !(\read(tmp_ndt_1)) [L297] COND TRUE t1_st == 0 [L298] int tmp_ndt_2; [L299] tmp_ndt_2 = __VERIFIER_nondet_int() [L300] COND FALSE !(\read(tmp_ndt_2)) [L311] COND TRUE t2_st == 0 [L312] int tmp_ndt_3; [L313] tmp_ndt_3 = __VERIFIER_nondet_int() [L314] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...