./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ba5ca2b9b2a5f86416453e0608f62cc01593f29e .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 03:04:36,444 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 03:04:36,447 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 03:04:36,527 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 03:04:36,528 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 03:04:36,533 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 03:04:36,535 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 03:04:36,542 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 03:04:36,545 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 03:04:36,551 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 03:04:36,552 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 03:04:36,554 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 03:04:36,555 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 03:04:36,558 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 03:04:36,559 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 03:04:36,562 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 03:04:36,563 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 03:04:36,567 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 03:04:36,570 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 03:04:36,577 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 03:04:36,580 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 03:04:36,581 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 03:04:36,583 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 03:04:36,584 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 03:04:36,593 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 03:04:36,594 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 03:04:36,594 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 03:04:36,596 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 03:04:36,597 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 03:04:36,598 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 03:04:36,599 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 03:04:36,600 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 03:04:36,602 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 03:04:36,603 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 03:04:36,605 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 03:04:36,605 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 03:04:36,606 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 03:04:36,606 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 03:04:36,606 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 03:04:36,607 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 03:04:36,609 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 03:04:36,612 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 03:04:36,638 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 03:04:36,639 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 03:04:36,642 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 03:04:36,643 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 03:04:36,643 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 03:04:36,643 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 03:04:36,643 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 03:04:36,644 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 03:04:36,644 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 03:04:36,644 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 03:04:36,645 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 03:04:36,646 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 03:04:36,646 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 03:04:36,646 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 03:04:36,646 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 03:04:36,647 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 03:04:36,647 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 03:04:36,647 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 03:04:36,647 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 03:04:36,647 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 03:04:36,648 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 03:04:36,648 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 03:04:36,648 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 03:04:36,648 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 03:04:36,649 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 03:04:36,649 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 03:04:36,649 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 03:04:36,649 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 03:04:36,650 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 03:04:36,651 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 03:04:36,651 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 03:04:36,652 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 03:04:36,653 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 03:04:36,653 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ba5ca2b9b2a5f86416453e0608f62cc01593f29e [2020-11-28 03:04:36,987 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 03:04:37,019 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 03:04:37,022 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 03:04:37,023 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 03:04:37,026 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 03:04:37,027 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2020-11-28 03:04:37,101 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/data/628aad3a4/dc2b33fbccc644859ef137c3c8e4124d/FLAG229d3d224 [2020-11-28 03:04:37,656 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 03:04:37,662 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2020-11-28 03:04:37,681 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/data/628aad3a4/dc2b33fbccc644859ef137c3c8e4124d/FLAG229d3d224 [2020-11-28 03:04:37,977 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/data/628aad3a4/dc2b33fbccc644859ef137c3c8e4124d [2020-11-28 03:04:37,979 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 03:04:37,981 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 03:04:37,983 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 03:04:37,983 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 03:04:37,986 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 03:04:37,987 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:04:37" (1/1) ... [2020-11-28 03:04:37,990 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@192a8098 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:37, skipping insertion in model container [2020-11-28 03:04:37,990 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:04:37" (1/1) ... [2020-11-28 03:04:37,997 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 03:04:38,054 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 03:04:38,353 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:04:38,362 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 03:04:38,409 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:04:38,433 INFO L208 MainTranslator]: Completed translation [2020-11-28 03:04:38,434 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38 WrapperNode [2020-11-28 03:04:38,436 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 03:04:38,437 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 03:04:38,437 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 03:04:38,437 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 03:04:38,445 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,468 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,542 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 03:04:38,544 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 03:04:38,545 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 03:04:38,545 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 03:04:38,553 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,553 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,565 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,566 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,577 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,606 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,623 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... [2020-11-28 03:04:38,629 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 03:04:38,630 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 03:04:38,630 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 03:04:38,639 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 03:04:38,640 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 03:04:38,712 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 03:04:38,713 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 03:04:38,713 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 03:04:38,713 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 03:04:39,895 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 03:04:39,895 INFO L298 CfgBuilder]: Removed 136 assume(true) statements. [2020-11-28 03:04:39,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:04:39 BoogieIcfgContainer [2020-11-28 03:04:39,900 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 03:04:39,906 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 03:04:39,906 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 03:04:39,912 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 03:04:39,913 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:04:39,913 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:04:37" (1/3) ... [2020-11-28 03:04:39,915 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bba4f9e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:04:39, skipping insertion in model container [2020-11-28 03:04:39,915 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:04:39,916 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:04:38" (2/3) ... [2020-11-28 03:04:39,916 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bba4f9e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:04:39, skipping insertion in model container [2020-11-28 03:04:39,916 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:04:39,916 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:04:39" (3/3) ... [2020-11-28 03:04:39,922 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2020-11-28 03:04:39,963 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 03:04:39,964 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 03:04:39,964 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 03:04:39,964 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 03:04:39,964 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 03:04:39,964 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 03:04:39,964 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 03:04:39,964 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 03:04:40,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 316 states. [2020-11-28 03:04:40,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 261 [2020-11-28 03:04:40,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:40,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:40,058 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,058 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,058 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 03:04:40,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 316 states. [2020-11-28 03:04:40,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 261 [2020-11-28 03:04:40,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:40,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:40,073 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,073 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,080 INFO L794 eck$LassoCheckResult]: Stem: 129#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 226#L645true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 291#L289true assume !(1 == ~m_i~0);~m_st~0 := 2; 3#L296-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 38#L301-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 74#L306-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 283#L311-1true assume !(0 == ~M_E~0); 42#L433-1true assume !(0 == ~T1_E~0); 261#L438-1true assume !(0 == ~T2_E~0); 294#L443-1true assume !(0 == ~T3_E~0); 316#L448-1true assume !(0 == ~E_M~0); 170#L453-1true assume 0 == ~E_1~0;~E_1~0 := 1; 190#L458-1true assume !(0 == ~E_2~0); 231#L463-1true assume !(0 == ~E_3~0); 95#L468-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 266#L212true assume 1 == ~m_pc~0; 33#L213true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 287#L223true is_master_triggered_#res := is_master_triggered_~__retres1~0; 35#L224true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 206#L535true assume !(0 != activate_threads_~tmp~1); 213#L535-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 125#L231true assume !(1 == ~t1_pc~0); 118#L231-2true is_transmit1_triggered_~__retres1~1 := 0; 126#L242true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 212#L243true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58#L543true assume !(0 != activate_threads_~tmp___0~0); 36#L543-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 295#L250true assume 1 == ~t2_pc~0; 50#L251true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 296#L261true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52#L262true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 246#L551true assume !(0 != activate_threads_~tmp___1~0); 247#L551-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166#L269true assume 1 == ~t3_pc~0; 110#L270true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 167#L280true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 111#L281true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 276#L559true assume !(0 != activate_threads_~tmp___2~0); 252#L559-2true assume 1 == ~M_E~0;~M_E~0 := 2; 315#L481-1true assume !(1 == ~T1_E~0); 184#L486-1true assume !(1 == ~T2_E~0); 215#L491-1true assume !(1 == ~T3_E~0); 248#L496-1true assume !(1 == ~E_M~0); 91#L501-1true assume !(1 == ~E_1~0); 137#L506-1true assume !(1 == ~E_2~0); 159#L511-1true assume !(1 == ~E_3~0); 149#L682-1true [2020-11-28 03:04:40,082 INFO L796 eck$LassoCheckResult]: Loop: 149#L682-1true assume !false; 89#L683true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 232#L408true assume !true; 163#L423true start_simulation_~kernel_st~0 := 2; 289#L289-1true start_simulation_~kernel_st~0 := 3; 44#L433-2true assume 0 == ~M_E~0;~M_E~0 := 1; 28#L433-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 62#L438-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 280#L443-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 304#L448-3true assume 0 == ~E_M~0;~E_M~0 := 1; 173#L453-3true assume 0 == ~E_1~0;~E_1~0 := 1; 194#L458-3true assume !(0 == ~E_2~0); 236#L463-3true assume 0 == ~E_3~0;~E_3~0 := 1; 104#L468-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47#L212-15true assume !(1 == ~m_pc~0); 81#L212-17true is_master_triggered_~__retres1~0 := 0; 250#L223-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 11#L224-5true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 182#L535-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 183#L535-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107#L231-15true assume 1 == ~t1_pc~0; 224#L232-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 133#L242-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 228#L243-5true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26#L543-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8#L543-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 290#L250-15true assume 1 == ~t2_pc~0; 68#L251-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 302#L261-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69#L262-5true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 203#L551-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 210#L551-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127#L269-15true assume 1 == ~t3_pc~0; 241#L270-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 146#L280-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 244#L281-5true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 56#L559-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 34#L559-17true assume 1 == ~M_E~0;~M_E~0 := 2; 301#L481-3true assume !(1 == ~T1_E~0); 171#L486-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 192#L491-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 234#L496-3true assume 1 == ~E_M~0;~E_M~0 := 2; 99#L501-3true assume 1 == ~E_1~0;~E_1~0 := 2; 140#L506-3true assume 1 == ~E_2~0;~E_2~0 := 2; 165#L511-3true assume 1 == ~E_3~0;~E_3~0 := 2; 16#L516-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 155#L324-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 154#L346-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 113#L347-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 317#L701true assume !(0 == start_simulation_~tmp~3); 318#L701-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 157#L324-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 156#L346-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 85#L347-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 225#L656true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 297#L663true stop_simulation_#res := stop_simulation_~__retres2~0; 51#L664true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 31#L714true assume !(0 != start_simulation_~tmp___0~1); 149#L682-1true [2020-11-28 03:04:40,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,087 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2020-11-28 03:04:40,096 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,096 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378548562] [2020-11-28 03:04:40,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,290 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [378548562] [2020-11-28 03:04:40,290 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,291 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:40,291 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069038802] [2020-11-28 03:04:40,295 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:40,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,297 INFO L82 PathProgramCache]: Analyzing trace with hash 1086411250, now seen corresponding path program 1 times [2020-11-28 03:04:40,297 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,297 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213039066] [2020-11-28 03:04:40,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,324 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213039066] [2020-11-28 03:04:40,325 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,325 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:04:40,325 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12685402] [2020-11-28 03:04:40,330 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:40,331 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:40,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:40,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:40,347 INFO L87 Difference]: Start difference. First operand 316 states. Second operand 3 states. [2020-11-28 03:04:40,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:40,410 INFO L93 Difference]: Finished difference Result 314 states and 476 transitions. [2020-11-28 03:04:40,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:40,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 476 transitions. [2020-11-28 03:04:40,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 308 states and 470 transitions. [2020-11-28 03:04:40,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2020-11-28 03:04:40,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2020-11-28 03:04:40,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 470 transitions. [2020-11-28 03:04:40,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:40,456 INFO L691 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2020-11-28 03:04:40,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 470 transitions. [2020-11-28 03:04:40,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2020-11-28 03:04:40,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2020-11-28 03:04:40,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 470 transitions. [2020-11-28 03:04:40,520 INFO L714 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2020-11-28 03:04:40,520 INFO L594 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2020-11-28 03:04:40,520 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 03:04:40,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 470 transitions. [2020-11-28 03:04:40,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:40,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:40,532 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,532 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,533 INFO L794 eck$LassoCheckResult]: Stem: 870#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 641#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 642#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 931#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 639#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 640#L301-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 710#L306-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 774#L311-1 assume !(0 == ~M_E~0); 717#L433-1 assume !(0 == ~T1_E~0); 718#L438-1 assume !(0 == ~T2_E~0); 941#L443-1 assume !(0 == ~T3_E~0); 946#L448-1 assume !(0 == ~E_M~0); 899#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 900#L458-1 assume !(0 == ~E_2~0); 916#L463-1 assume !(0 == ~E_3~0); 811#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812#L212 assume 1 == ~m_pc~0; 701#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 702#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 704#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 705#L535 assume !(0 != activate_threads_~tmp~1); 925#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 864#L231 assume !(1 == ~t1_pc~0); 850#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 851#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 866#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 739#L543 assume !(0 != activate_threads_~tmp___0~0); 708#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 709#L250 assume 1 == ~t2_pc~0; 732#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 733#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 735#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 736#L551 assume !(0 != activate_threads_~tmp___1~0); 937#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 897#L269 assume 1 == ~t3_pc~0; 837#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 838#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 842#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 843#L559 assume !(0 != activate_threads_~tmp___2~0); 938#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 939#L481-1 assume !(1 == ~T1_E~0); 912#L486-1 assume !(1 == ~T2_E~0); 913#L491-1 assume !(1 == ~T3_E~0); 926#L496-1 assume !(1 == ~E_M~0); 802#L501-1 assume !(1 == ~E_1~0); 803#L506-1 assume !(1 == ~E_2~0); 881#L511-1 assume !(1 == ~E_3~0); 696#L682-1 [2020-11-28 03:04:40,533 INFO L796 eck$LassoCheckResult]: Loop: 696#L682-1 assume !false; 799#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 716#L408 assume !false; 898#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 893#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 752#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 833#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 742#L361 assume !(0 != eval_~tmp~0); 743#L423 start_simulation_~kernel_st~0 := 2; 896#L289-1 start_simulation_~kernel_st~0 := 3; 720#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 691#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 692#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 750#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 944#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 904#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 905#L458-3 assume !(0 == ~E_2~0); 919#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 827#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 728#L212-15 assume 1 == ~m_pc~0; 653#L213-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 654#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 656#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 657#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 911#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 834#L231-15 assume !(1 == ~t1_pc~0); 817#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 818#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 876#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 688#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 648#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 649#L250-15 assume 1 == ~t2_pc~0; 756#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 758#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 760#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 761#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 924#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 867#L269-15 assume 1 == ~t3_pc~0; 868#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 863#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 890#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 738#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 699#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 700#L481-3 assume !(1 == ~T1_E~0); 901#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 902#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 918#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 819#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 820#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 882#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 665#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 666#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 764#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 840#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 841#L701 assume !(0 == start_simulation_~tmp~3); 859#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 894#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 778#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 791#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 792#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 930#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 731#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 695#L714 assume !(0 != start_simulation_~tmp___0~1); 696#L682-1 [2020-11-28 03:04:40,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,535 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2020-11-28 03:04:40,536 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,536 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769889333] [2020-11-28 03:04:40,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,635 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769889333] [2020-11-28 03:04:40,636 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,636 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:40,636 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093382790] [2020-11-28 03:04:40,637 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:40,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1006052069, now seen corresponding path program 1 times [2020-11-28 03:04:40,638 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,638 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287748635] [2020-11-28 03:04:40,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,747 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287748635] [2020-11-28 03:04:40,748 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,748 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:40,748 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507639740] [2020-11-28 03:04:40,749 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:40,749 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:40,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:40,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:40,750 INFO L87 Difference]: Start difference. First operand 308 states and 470 transitions. cyclomatic complexity: 163 Second operand 3 states. [2020-11-28 03:04:40,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:40,775 INFO L93 Difference]: Finished difference Result 308 states and 469 transitions. [2020-11-28 03:04:40,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:40,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 469 transitions. [2020-11-28 03:04:40,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 469 transitions. [2020-11-28 03:04:40,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2020-11-28 03:04:40,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2020-11-28 03:04:40,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 469 transitions. [2020-11-28 03:04:40,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:40,794 INFO L691 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2020-11-28 03:04:40,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 469 transitions. [2020-11-28 03:04:40,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2020-11-28 03:04:40,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2020-11-28 03:04:40,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 469 transitions. [2020-11-28 03:04:40,807 INFO L714 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2020-11-28 03:04:40,807 INFO L594 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2020-11-28 03:04:40,808 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 03:04:40,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 469 transitions. [2020-11-28 03:04:40,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:40,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:40,813 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,813 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,814 INFO L794 eck$LassoCheckResult]: Stem: 1493#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1264#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1265#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1556#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 1262#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1263#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1333#L306-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1397#L311-1 assume !(0 == ~M_E~0); 1340#L433-1 assume !(0 == ~T1_E~0); 1341#L438-1 assume !(0 == ~T2_E~0); 1564#L443-1 assume !(0 == ~T3_E~0); 1569#L448-1 assume !(0 == ~E_M~0); 1522#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1523#L458-1 assume !(0 == ~E_2~0); 1539#L463-1 assume !(0 == ~E_3~0); 1434#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1435#L212 assume 1 == ~m_pc~0; 1324#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1325#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1327#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1328#L535 assume !(0 != activate_threads_~tmp~1); 1548#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1487#L231 assume !(1 == ~t1_pc~0); 1473#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 1474#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1489#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1362#L543 assume !(0 != activate_threads_~tmp___0~0); 1331#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1332#L250 assume 1 == ~t2_pc~0; 1355#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1356#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1358#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1359#L551 assume !(0 != activate_threads_~tmp___1~0); 1560#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1520#L269 assume 1 == ~t3_pc~0; 1460#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1461#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1466#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1467#L559 assume !(0 != activate_threads_~tmp___2~0); 1561#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1562#L481-1 assume !(1 == ~T1_E~0); 1535#L486-1 assume !(1 == ~T2_E~0); 1536#L491-1 assume !(1 == ~T3_E~0); 1549#L496-1 assume !(1 == ~E_M~0); 1425#L501-1 assume !(1 == ~E_1~0); 1426#L506-1 assume !(1 == ~E_2~0); 1504#L511-1 assume !(1 == ~E_3~0); 1319#L682-1 [2020-11-28 03:04:40,815 INFO L796 eck$LassoCheckResult]: Loop: 1319#L682-1 assume !false; 1422#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1338#L408 assume !false; 1521#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1516#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1375#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1458#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1365#L361 assume !(0 != eval_~tmp~0); 1366#L423 start_simulation_~kernel_st~0 := 2; 1519#L289-1 start_simulation_~kernel_st~0 := 3; 1343#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1314#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1315#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1371#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1567#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1527#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1528#L458-3 assume !(0 == ~E_2~0); 1542#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1450#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1349#L212-15 assume 1 == ~m_pc~0; 1276#L213-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1277#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1279#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1280#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1534#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1454#L231-15 assume 1 == ~t1_pc~0; 1455#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1440#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1499#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1311#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1271#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1272#L250-15 assume 1 == ~t2_pc~0; 1380#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1382#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1383#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1384#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1547#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1490#L269-15 assume 1 == ~t3_pc~0; 1491#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1486#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1513#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1361#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1322#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1323#L481-3 assume !(1 == ~T1_E~0); 1524#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1525#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1541#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1442#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1443#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1507#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1291#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1292#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1389#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1464#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1465#L701 assume !(0 == start_simulation_~tmp~3); 1482#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1517#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1401#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1414#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1415#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1553#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 1354#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1318#L714 assume !(0 != start_simulation_~tmp___0~1); 1319#L682-1 [2020-11-28 03:04:40,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,815 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2020-11-28 03:04:40,816 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,816 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803531492] [2020-11-28 03:04:40,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,880 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803531492] [2020-11-28 03:04:40,880 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,880 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:40,881 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891261787] [2020-11-28 03:04:40,881 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:40,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,881 INFO L82 PathProgramCache]: Analyzing trace with hash 482731398, now seen corresponding path program 1 times [2020-11-28 03:04:40,882 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,882 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936553590] [2020-11-28 03:04:40,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:40,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:40,937 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936553590] [2020-11-28 03:04:40,938 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:40,938 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:40,938 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966871185] [2020-11-28 03:04:40,938 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:40,939 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:40,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:40,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:40,940 INFO L87 Difference]: Start difference. First operand 308 states and 469 transitions. cyclomatic complexity: 162 Second operand 3 states. [2020-11-28 03:04:40,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:40,951 INFO L93 Difference]: Finished difference Result 308 states and 468 transitions. [2020-11-28 03:04:40,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:40,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 468 transitions. [2020-11-28 03:04:40,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 468 transitions. [2020-11-28 03:04:40,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2020-11-28 03:04:40,958 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2020-11-28 03:04:40,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 468 transitions. [2020-11-28 03:04:40,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:40,959 INFO L691 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2020-11-28 03:04:40,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 468 transitions. [2020-11-28 03:04:40,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2020-11-28 03:04:40,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2020-11-28 03:04:40,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 468 transitions. [2020-11-28 03:04:40,969 INFO L714 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2020-11-28 03:04:40,969 INFO L594 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2020-11-28 03:04:40,969 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 03:04:40,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 468 transitions. [2020-11-28 03:04:40,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2020-11-28 03:04:40,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:40,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:40,973 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,973 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:40,973 INFO L794 eck$LassoCheckResult]: Stem: 2116#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1887#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1888#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2177#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 1885#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1886#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1956#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2017#L311-1 assume !(0 == ~M_E~0); 1963#L433-1 assume !(0 == ~T1_E~0); 1964#L438-1 assume !(0 == ~T2_E~0); 2187#L443-1 assume !(0 == ~T3_E~0); 2192#L448-1 assume !(0 == ~E_M~0); 2145#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2146#L458-1 assume !(0 == ~E_2~0); 2162#L463-1 assume !(0 == ~E_3~0); 2057#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2058#L212 assume 1 == ~m_pc~0; 1945#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1946#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1950#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1951#L535 assume !(0 != activate_threads_~tmp~1); 2171#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2110#L231 assume !(1 == ~t1_pc~0); 2096#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 2097#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2112#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1985#L543 assume !(0 != activate_threads_~tmp___0~0); 1952#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1953#L250 assume 1 == ~t2_pc~0; 1977#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1978#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1981#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1982#L551 assume !(0 != activate_threads_~tmp___1~0); 2183#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2143#L269 assume 1 == ~t3_pc~0; 2083#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2084#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2086#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2087#L559 assume !(0 != activate_threads_~tmp___2~0); 2184#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2185#L481-1 assume !(1 == ~T1_E~0); 2158#L486-1 assume !(1 == ~T2_E~0); 2159#L491-1 assume !(1 == ~T3_E~0); 2172#L496-1 assume !(1 == ~E_M~0); 2048#L501-1 assume !(1 == ~E_1~0); 2049#L506-1 assume !(1 == ~E_2~0); 2127#L511-1 assume !(1 == ~E_3~0); 1942#L682-1 [2020-11-28 03:04:40,973 INFO L796 eck$LassoCheckResult]: Loop: 1942#L682-1 assume !false; 2045#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1961#L408 assume !false; 2144#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2139#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1998#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2077#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1986#L361 assume !(0 != eval_~tmp~0); 1987#L423 start_simulation_~kernel_st~0 := 2; 2142#L289-1 start_simulation_~kernel_st~0 := 3; 1966#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1937#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1938#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1994#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2190#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2150#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2151#L458-3 assume !(0 == ~E_2~0); 2165#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2073#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1972#L212-15 assume 1 == ~m_pc~0; 1899#L213-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1900#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1902#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1903#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2157#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2078#L231-15 assume !(1 == ~t1_pc~0); 2062#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 2063#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2122#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1934#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1894#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1895#L250-15 assume 1 == ~t2_pc~0; 2003#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2005#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2006#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2007#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2170#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2113#L269-15 assume 1 == ~t3_pc~0; 2114#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2109#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2136#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1984#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1948#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1949#L481-3 assume !(1 == ~T1_E~0); 2147#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2148#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2164#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2065#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2066#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2130#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1914#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1915#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2012#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2089#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2090#L701 assume !(0 == start_simulation_~tmp~3); 2105#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2140#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2024#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2037#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 2038#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2176#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 1980#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1941#L714 assume !(0 != start_simulation_~tmp___0~1); 1942#L682-1 [2020-11-28 03:04:40,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:40,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2020-11-28 03:04:40,974 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:40,974 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034008284] [2020-11-28 03:04:40,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:40,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,013 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034008284] [2020-11-28 03:04:41,013 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,014 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,014 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177480975] [2020-11-28 03:04:41,014 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:41,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,015 INFO L82 PathProgramCache]: Analyzing trace with hash 1006052069, now seen corresponding path program 2 times [2020-11-28 03:04:41,015 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,015 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481756912] [2020-11-28 03:04:41,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,070 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481756912] [2020-11-28 03:04:41,071 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,071 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,071 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454164052] [2020-11-28 03:04:41,071 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:41,072 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:41,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:41,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:41,072 INFO L87 Difference]: Start difference. First operand 308 states and 468 transitions. cyclomatic complexity: 161 Second operand 4 states. [2020-11-28 03:04:41,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:41,247 INFO L93 Difference]: Finished difference Result 508 states and 769 transitions. [2020-11-28 03:04:41,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:41,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 508 states and 769 transitions. [2020-11-28 03:04:41,253 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 440 [2020-11-28 03:04:41,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 508 states to 508 states and 769 transitions. [2020-11-28 03:04:41,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 508 [2020-11-28 03:04:41,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 508 [2020-11-28 03:04:41,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 508 states and 769 transitions. [2020-11-28 03:04:41,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:41,260 INFO L691 BuchiCegarLoop]: Abstraction has 508 states and 769 transitions. [2020-11-28 03:04:41,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states and 769 transitions. [2020-11-28 03:04:41,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 498. [2020-11-28 03:04:41,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 498 states. [2020-11-28 03:04:41,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 753 transitions. [2020-11-28 03:04:41,275 INFO L714 BuchiCegarLoop]: Abstraction has 498 states and 753 transitions. [2020-11-28 03:04:41,278 INFO L594 BuchiCegarLoop]: Abstraction has 498 states and 753 transitions. [2020-11-28 03:04:41,278 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 03:04:41,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 753 transitions. [2020-11-28 03:04:41,282 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 440 [2020-11-28 03:04:41,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:41,283 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:41,288 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,288 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,295 INFO L794 eck$LassoCheckResult]: Stem: 2946#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2713#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2714#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3012#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 2711#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2712#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2782#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2845#L311-1 assume !(0 == ~M_E~0); 2789#L433-1 assume !(0 == ~T1_E~0); 2790#L438-1 assume !(0 == ~T2_E~0); 3026#L443-1 assume !(0 == ~T3_E~0); 3034#L448-1 assume !(0 == ~E_M~0); 2980#L453-1 assume !(0 == ~E_1~0); 2981#L458-1 assume !(0 == ~E_2~0); 2997#L463-1 assume !(0 == ~E_3~0); 2885#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2886#L212 assume 1 == ~m_pc~0; 2771#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2772#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2776#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2777#L535 assume !(0 != activate_threads_~tmp~1); 3006#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2940#L231 assume !(1 == ~t1_pc~0); 2926#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 2927#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2942#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2813#L543 assume !(0 != activate_threads_~tmp___0~0); 2778#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2779#L250 assume 1 == ~t2_pc~0; 2804#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2805#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2809#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2810#L551 assume !(0 != activate_threads_~tmp___1~0); 3020#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2977#L269 assume 1 == ~t3_pc~0; 2913#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2914#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2916#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2917#L559 assume !(0 != activate_threads_~tmp___2~0); 3021#L559-2 assume !(1 == ~M_E~0); 3022#L481-1 assume !(1 == ~T1_E~0); 3138#L486-1 assume !(1 == ~T2_E~0); 3136#L491-1 assume !(1 == ~T3_E~0); 3133#L496-1 assume !(1 == ~E_M~0); 3131#L501-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2877#L506-1 assume !(1 == ~E_2~0); 2957#L511-1 assume !(1 == ~E_3~0); 2768#L682-1 [2020-11-28 03:04:41,295 INFO L796 eck$LassoCheckResult]: Loop: 2768#L682-1 assume !false; 3049#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3016#L408 assume !false; 3017#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3044#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2979#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2906#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2907#L361 assume !(0 != eval_~tmp~0); 2975#L423 start_simulation_~kernel_st~0 := 2; 2976#L289-1 start_simulation_~kernel_st~0 := 3; 3039#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2763#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2764#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2822#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3031#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2985#L453-3 assume !(0 == ~E_1~0); 2986#L458-3 assume !(0 == ~E_2~0); 3000#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2902#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2799#L212-15 assume 1 == ~m_pc~0; 2725#L213-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2726#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2728#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2729#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2992#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2908#L231-15 assume !(1 == ~t1_pc~0); 2890#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 2891#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2952#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2760#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2720#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2721#L250-15 assume !(1 == ~t2_pc~0); 2832#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 2833#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2834#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2835#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3005#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2943#L269-15 assume 1 == ~t3_pc~0; 2944#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2939#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2967#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2812#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2774#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2775#L481-3 assume !(1 == ~T1_E~0); 2982#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2983#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2999#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2894#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2895#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2960#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2740#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2741#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2840#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2919#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2920#L701 assume !(0 == start_simulation_~tmp~3); 2935#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3038#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3085#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3084#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3083#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3080#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 3078#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2767#L714 assume !(0 != start_simulation_~tmp___0~1); 2768#L682-1 [2020-11-28 03:04:41,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,296 INFO L82 PathProgramCache]: Analyzing trace with hash 180145436, now seen corresponding path program 1 times [2020-11-28 03:04:41,296 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,297 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949357601] [2020-11-28 03:04:41,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,358 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949357601] [2020-11-28 03:04:41,358 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,358 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:04:41,358 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778180833] [2020-11-28 03:04:41,359 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:41,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,359 INFO L82 PathProgramCache]: Analyzing trace with hash -430778558, now seen corresponding path program 1 times [2020-11-28 03:04:41,360 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,360 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141939986] [2020-11-28 03:04:41,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,410 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141939986] [2020-11-28 03:04:41,410 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,410 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,411 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014566893] [2020-11-28 03:04:41,411 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:41,411 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:41,412 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:41,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:41,412 INFO L87 Difference]: Start difference. First operand 498 states and 753 transitions. cyclomatic complexity: 257 Second operand 3 states. [2020-11-28 03:04:41,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:41,479 INFO L93 Difference]: Finished difference Result 737 states and 1094 transitions. [2020-11-28 03:04:41,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:41,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 737 states and 1094 transitions. [2020-11-28 03:04:41,487 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 679 [2020-11-28 03:04:41,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 737 states to 737 states and 1094 transitions. [2020-11-28 03:04:41,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 737 [2020-11-28 03:04:41,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 737 [2020-11-28 03:04:41,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 737 states and 1094 transitions. [2020-11-28 03:04:41,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:41,497 INFO L691 BuchiCegarLoop]: Abstraction has 737 states and 1094 transitions. [2020-11-28 03:04:41,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 737 states and 1094 transitions. [2020-11-28 03:04:41,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 737 to 711. [2020-11-28 03:04:41,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 711 states. [2020-11-28 03:04:41,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 1058 transitions. [2020-11-28 03:04:41,515 INFO L714 BuchiCegarLoop]: Abstraction has 711 states and 1058 transitions. [2020-11-28 03:04:41,515 INFO L594 BuchiCegarLoop]: Abstraction has 711 states and 1058 transitions. [2020-11-28 03:04:41,516 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 03:04:41,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 711 states and 1058 transitions. [2020-11-28 03:04:41,521 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 653 [2020-11-28 03:04:41,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:41,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:41,522 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,523 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,523 INFO L794 eck$LassoCheckResult]: Stem: 4197#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3955#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3956#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4277#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 3953#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3954#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4020#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4093#L311-1 assume !(0 == ~M_E~0); 4027#L433-1 assume !(0 == ~T1_E~0); 4028#L438-1 assume !(0 == ~T2_E~0); 4297#L443-1 assume !(0 == ~T3_E~0); 4307#L448-1 assume !(0 == ~E_M~0); 4234#L453-1 assume !(0 == ~E_1~0); 4235#L458-1 assume !(0 == ~E_2~0); 4254#L463-1 assume !(0 == ~E_3~0); 4135#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4136#L212 assume !(1 == ~m_pc~0); 4292#L212-2 is_master_triggered_~__retres1~0 := 0; 4293#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4014#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4015#L535 assume !(0 != activate_threads_~tmp~1); 4265#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4191#L231 assume !(1 == ~t1_pc~0); 4177#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 4178#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4193#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4056#L543 assume !(0 != activate_threads_~tmp___0~0); 4016#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4017#L250 assume 1 == ~t2_pc~0; 4043#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4044#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4048#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4049#L551 assume !(0 != activate_threads_~tmp___1~0); 4287#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4229#L269 assume 1 == ~t3_pc~0; 4163#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4164#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4166#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4167#L559 assume !(0 != activate_threads_~tmp___2~0); 4288#L559-2 assume !(1 == ~M_E~0); 4289#L481-1 assume !(1 == ~T1_E~0); 4249#L486-1 assume !(1 == ~T2_E~0); 4250#L491-1 assume !(1 == ~T3_E~0); 4268#L496-1 assume !(1 == ~E_M~0); 4125#L501-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4126#L506-1 assume !(1 == ~E_2~0); 4546#L511-1 assume !(1 == ~E_3~0); 4544#L682-1 [2020-11-28 03:04:41,523 INFO L796 eck$LassoCheckResult]: Loop: 4544#L682-1 assume !false; 4507#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 4281#L408 assume !false; 4282#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4223#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4071#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4156#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4157#L361 assume !(0 != eval_~tmp~0); 4227#L423 start_simulation_~kernel_st~0 := 2; 4228#L289-1 start_simulation_~kernel_st~0 := 3; 4497#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4004#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4005#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4065#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4304#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4239#L453-3 assume !(0 == ~E_1~0); 4240#L458-3 assume !(0 == ~E_2~0); 4258#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4152#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4037#L212-15 assume !(1 == ~m_pc~0); 4038#L212-17 is_master_triggered_~__retres1~0 := 0; 4493#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4492#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4491#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4490#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4489#L231-15 assume 1 == ~t1_pc~0; 4487#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4203#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4204#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4001#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3962#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3963#L250-15 assume 1 == ~t2_pc~0; 4076#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4078#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4081#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4082#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4264#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4194#L269-15 assume 1 == ~t3_pc~0; 4195#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4190#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4220#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4053#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4012#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4013#L481-3 assume !(1 == ~T1_E~0); 4236#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4237#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4257#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4143#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4144#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4212#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3981#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3982#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4088#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4169#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4170#L701 assume !(0 == start_simulation_~tmp~3); 4186#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4224#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4101#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4114#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 4115#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4276#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 4046#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4047#L714 assume !(0 != start_simulation_~tmp___0~1); 4544#L682-1 [2020-11-28 03:04:41,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1591325539, now seen corresponding path program 1 times [2020-11-28 03:04:41,524 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,524 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819305717] [2020-11-28 03:04:41,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,579 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819305717] [2020-11-28 03:04:41,579 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,579 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,579 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143759423] [2020-11-28 03:04:41,580 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:41,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,580 INFO L82 PathProgramCache]: Analyzing trace with hash 1146790755, now seen corresponding path program 1 times [2020-11-28 03:04:41,580 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,581 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526208570] [2020-11-28 03:04:41,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,621 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526208570] [2020-11-28 03:04:41,621 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,621 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,621 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433559825] [2020-11-28 03:04:41,621 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:41,622 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:41,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:41,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:41,622 INFO L87 Difference]: Start difference. First operand 711 states and 1058 transitions. cyclomatic complexity: 350 Second operand 4 states. [2020-11-28 03:04:41,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:41,839 INFO L93 Difference]: Finished difference Result 1662 states and 2432 transitions. [2020-11-28 03:04:41,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:41,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1662 states and 2432 transitions. [2020-11-28 03:04:41,853 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1567 [2020-11-28 03:04:41,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1662 states to 1662 states and 2432 transitions. [2020-11-28 03:04:41,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1662 [2020-11-28 03:04:41,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1662 [2020-11-28 03:04:41,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1662 states and 2432 transitions. [2020-11-28 03:04:41,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:41,873 INFO L691 BuchiCegarLoop]: Abstraction has 1662 states and 2432 transitions. [2020-11-28 03:04:41,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1662 states and 2432 transitions. [2020-11-28 03:04:41,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1662 to 1261. [2020-11-28 03:04:41,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1261 states. [2020-11-28 03:04:41,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1261 states to 1261 states and 1862 transitions. [2020-11-28 03:04:41,902 INFO L714 BuchiCegarLoop]: Abstraction has 1261 states and 1862 transitions. [2020-11-28 03:04:41,902 INFO L594 BuchiCegarLoop]: Abstraction has 1261 states and 1862 transitions. [2020-11-28 03:04:41,902 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 03:04:41,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1261 states and 1862 transitions. [2020-11-28 03:04:41,909 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1203 [2020-11-28 03:04:41,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:41,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:41,911 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,911 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:41,911 INFO L794 eck$LassoCheckResult]: Stem: 6578#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 6338#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6339#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6656#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 6336#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6337#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6406#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6473#L311-1 assume !(0 == ~M_E~0); 6413#L433-1 assume !(0 == ~T1_E~0); 6414#L438-1 assume !(0 == ~T2_E~0); 6682#L443-1 assume !(0 == ~T3_E~0); 6704#L448-1 assume !(0 == ~E_M~0); 6612#L453-1 assume !(0 == ~E_1~0); 6613#L458-1 assume !(0 == ~E_2~0); 6634#L463-1 assume !(0 == ~E_3~0); 6517#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6518#L212 assume !(1 == ~m_pc~0); 6679#L212-2 is_master_triggered_~__retres1~0 := 0; 6680#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6400#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6401#L535 assume !(0 != activate_threads_~tmp~1); 6649#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6572#L231 assume !(1 == ~t1_pc~0); 6558#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 6559#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6574#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6437#L543 assume !(0 != activate_threads_~tmp___0~0); 6402#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6403#L250 assume !(1 == ~t2_pc~0); 6705#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 6706#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6429#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6430#L551 assume !(0 != activate_threads_~tmp___1~0); 6666#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6610#L269 assume 1 == ~t3_pc~0; 6545#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6546#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6548#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6549#L559 assume !(0 != activate_threads_~tmp___2~0); 6671#L559-2 assume !(1 == ~M_E~0); 6672#L481-1 assume !(1 == ~T1_E~0); 6713#L486-1 assume !(1 == ~T2_E~0); 6650#L491-1 assume !(1 == ~T3_E~0); 6651#L496-1 assume !(1 == ~E_M~0); 6507#L501-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6508#L506-1 assume !(1 == ~E_2~0); 6590#L511-1 assume !(1 == ~E_3~0); 7507#L682-1 [2020-11-28 03:04:41,911 INFO L796 eck$LassoCheckResult]: Loop: 7507#L682-1 assume !false; 7505#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 6661#L408 assume !false; 6611#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6603#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6452#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6539#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 6438#L361 assume !(0 != eval_~tmp~0); 6439#L423 start_simulation_~kernel_st~0 := 2; 6609#L289-1 start_simulation_~kernel_st~0 := 3; 6416#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6388#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6389#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6446#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6692#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6617#L453-3 assume !(0 == ~E_1~0); 6618#L458-3 assume !(0 == ~E_2~0); 6637#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6535#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6422#L212-15 assume !(1 == ~m_pc~0); 6423#L212-17 is_master_triggered_~__retres1~0 := 0; 6669#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6670#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6625#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6626#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6540#L231-15 assume !(1 == ~t1_pc~0); 6522#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 6523#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6584#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7563#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7562#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6699#L250-15 assume !(1 == ~t2_pc~0); 6700#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 7561#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6461#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6462#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6648#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6575#L269-15 assume 1 == ~t3_pc~0; 6576#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6571#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7551#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7550#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7548#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6398#L481-3 assume !(1 == ~T1_E~0); 7545#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7542#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7541#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7540#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6526#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7538#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7537#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7536#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7532#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7531#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7529#L701 assume !(0 == start_simulation_~tmp~3); 6567#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6605#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6480#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7523#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 7521#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7519#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 7513#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7509#L714 assume !(0 != start_simulation_~tmp___0~1); 7507#L682-1 [2020-11-28 03:04:41,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,912 INFO L82 PathProgramCache]: Analyzing trace with hash -600160866, now seen corresponding path program 1 times [2020-11-28 03:04:41,912 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,917 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194601683] [2020-11-28 03:04:41,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:41,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:41,968 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194601683] [2020-11-28 03:04:41,968 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:41,968 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:41,968 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071126576] [2020-11-28 03:04:41,969 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:41,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:41,969 INFO L82 PathProgramCache]: Analyzing trace with hash -1705881247, now seen corresponding path program 1 times [2020-11-28 03:04:41,969 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:41,969 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100822630] [2020-11-28 03:04:41,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:41,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:42,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:42,003 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100822630] [2020-11-28 03:04:42,003 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:42,004 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:42,004 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836345805] [2020-11-28 03:04:42,004 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:42,004 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:42,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:42,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:42,005 INFO L87 Difference]: Start difference. First operand 1261 states and 1862 transitions. cyclomatic complexity: 604 Second operand 4 states. [2020-11-28 03:04:42,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:42,193 INFO L93 Difference]: Finished difference Result 2961 states and 4315 transitions. [2020-11-28 03:04:42,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:42,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2961 states and 4315 transitions. [2020-11-28 03:04:42,217 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 2829 [2020-11-28 03:04:42,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2961 states to 2961 states and 4315 transitions. [2020-11-28 03:04:42,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2961 [2020-11-28 03:04:42,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2961 [2020-11-28 03:04:42,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2961 states and 4315 transitions. [2020-11-28 03:04:42,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:42,251 INFO L691 BuchiCegarLoop]: Abstraction has 2961 states and 4315 transitions. [2020-11-28 03:04:42,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2961 states and 4315 transitions. [2020-11-28 03:04:42,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2961 to 2265. [2020-11-28 03:04:42,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2265 states. [2020-11-28 03:04:42,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2265 states to 2265 states and 3329 transitions. [2020-11-28 03:04:42,341 INFO L714 BuchiCegarLoop]: Abstraction has 2265 states and 3329 transitions. [2020-11-28 03:04:42,341 INFO L594 BuchiCegarLoop]: Abstraction has 2265 states and 3329 transitions. [2020-11-28 03:04:42,341 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 03:04:42,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2265 states and 3329 transitions. [2020-11-28 03:04:42,359 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2206 [2020-11-28 03:04:42,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:42,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:42,366 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,366 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,366 INFO L794 eck$LassoCheckResult]: Stem: 10808#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 10570#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10571#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10903#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 10568#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10569#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10638#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10710#L311-1 assume !(0 == ~M_E~0); 10646#L433-1 assume !(0 == ~T1_E~0); 10647#L438-1 assume !(0 == ~T2_E~0); 10928#L443-1 assume !(0 == ~T3_E~0); 10943#L448-1 assume !(0 == ~E_M~0); 10857#L453-1 assume !(0 == ~E_1~0); 10858#L458-1 assume !(0 == ~E_2~0); 10879#L463-1 assume !(0 == ~E_3~0); 10750#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10751#L212 assume !(1 == ~m_pc~0); 10924#L212-2 is_master_triggered_~__retres1~0 := 0; 10925#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10632#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10633#L535 assume !(0 != activate_threads_~tmp~1); 10894#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10803#L231 assume !(1 == ~t1_pc~0); 10790#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 10791#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10805#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10672#L543 assume !(0 != activate_threads_~tmp___0~0); 10636#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10637#L250 assume !(1 == ~t2_pc~0); 10944#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 10945#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10664#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10665#L551 assume !(0 != activate_threads_~tmp___1~0); 10915#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10854#L269 assume !(1 == ~t3_pc~0); 10848#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 10849#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10784#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10785#L559 assume !(0 != activate_threads_~tmp___2~0); 10920#L559-2 assume !(1 == ~M_E~0); 10921#L481-1 assume !(1 == ~T1_E~0); 10952#L486-1 assume !(1 == ~T2_E~0); 10895#L491-1 assume !(1 == ~T3_E~0); 10896#L496-1 assume !(1 == ~E_M~0); 10740#L501-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10741#L506-1 assume !(1 == ~E_2~0); 10821#L511-1 assume !(1 == ~E_3~0); 12534#L682-1 [2020-11-28 03:04:42,366 INFO L796 eck$LassoCheckResult]: Loop: 12534#L682-1 assume !false; 12529#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12526#L408 assume !false; 12525#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12523#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12520#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12519#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12517#L361 assume !(0 != eval_~tmp~0); 12516#L423 start_simulation_~kernel_st~0 := 2; 12514#L289-1 start_simulation_~kernel_st~0 := 3; 12511#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12512#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12790#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12789#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12788#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12499#L453-3 assume !(0 == ~E_1~0); 12497#L458-3 assume !(0 == ~E_2~0); 12495#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12493#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12490#L212-15 assume !(1 == ~m_pc~0); 12491#L212-17 is_master_triggered_~__retres1~0 := 0; 12777#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12775#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12482#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12479#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12474#L231-15 assume 1 == ~t1_pc~0; 12475#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12467#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12464#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12463#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10577#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10578#L250-15 assume !(1 == ~t2_pc~0); 10939#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 12722#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12720#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12718#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12716#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12714#L269-15 assume !(1 == ~t3_pc~0); 12415#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 12711#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12709#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12707#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12592#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 12588#L481-3 assume !(1 == ~T1_E~0); 12586#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12584#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12581#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12579#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10760#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10852#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10853#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12571#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10843#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10782#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10783#L701 assume !(0 == start_simulation_~tmp~3); 12559#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12555#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12551#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12550#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 12548#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12543#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 12540#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12539#L714 assume !(0 != start_simulation_~tmp___0~1); 12534#L682-1 [2020-11-28 03:04:42,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:42,367 INFO L82 PathProgramCache]: Analyzing trace with hash -1879485601, now seen corresponding path program 1 times [2020-11-28 03:04:42,367 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:42,367 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742655914] [2020-11-28 03:04:42,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:42,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:42,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:42,403 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742655914] [2020-11-28 03:04:42,403 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:42,403 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:42,403 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559053836] [2020-11-28 03:04:42,403 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:42,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:42,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1590417439, now seen corresponding path program 1 times [2020-11-28 03:04:42,404 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:42,404 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51662992] [2020-11-28 03:04:42,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:42,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:42,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:42,430 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51662992] [2020-11-28 03:04:42,430 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:42,430 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:42,431 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316810603] [2020-11-28 03:04:42,431 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:42,431 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:42,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:42,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:42,432 INFO L87 Difference]: Start difference. First operand 2265 states and 3329 transitions. cyclomatic complexity: 1067 Second operand 4 states. [2020-11-28 03:04:42,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:42,550 INFO L93 Difference]: Finished difference Result 2342 states and 3348 transitions. [2020-11-28 03:04:42,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:42,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2342 states and 3348 transitions. [2020-11-28 03:04:42,568 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2278 [2020-11-28 03:04:42,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2342 states to 2342 states and 3348 transitions. [2020-11-28 03:04:42,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2342 [2020-11-28 03:04:42,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2342 [2020-11-28 03:04:42,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2342 states and 3348 transitions. [2020-11-28 03:04:42,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:42,592 INFO L691 BuchiCegarLoop]: Abstraction has 2342 states and 3348 transitions. [2020-11-28 03:04:42,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2342 states and 3348 transitions. [2020-11-28 03:04:42,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2342 to 2258. [2020-11-28 03:04:42,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2258 states. [2020-11-28 03:04:42,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2258 states to 2258 states and 3244 transitions. [2020-11-28 03:04:42,639 INFO L714 BuchiCegarLoop]: Abstraction has 2258 states and 3244 transitions. [2020-11-28 03:04:42,639 INFO L594 BuchiCegarLoop]: Abstraction has 2258 states and 3244 transitions. [2020-11-28 03:04:42,640 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 03:04:42,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2258 states and 3244 transitions. [2020-11-28 03:04:42,651 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2206 [2020-11-28 03:04:42,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:42,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:42,653 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,653 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,653 INFO L794 eck$LassoCheckResult]: Stem: 15419#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 15187#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15188#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15506#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 15185#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15186#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15253#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15320#L311-1 assume !(0 == ~M_E~0); 15260#L433-1 assume !(0 == ~T1_E~0); 15261#L438-1 assume !(0 == ~T2_E~0); 15527#L443-1 assume !(0 == ~T3_E~0); 15545#L448-1 assume !(0 == ~E_M~0); 15463#L453-1 assume !(0 == ~E_1~0); 15464#L458-1 assume !(0 == ~E_2~0); 15483#L463-1 assume !(0 == ~E_3~0); 15362#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15363#L212 assume !(1 == ~m_pc~0); 15522#L212-2 is_master_triggered_~__retres1~0 := 0; 15523#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15247#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15248#L535 assume !(0 != activate_threads_~tmp~1); 15498#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15412#L231 assume !(1 == ~t1_pc~0); 15398#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 15399#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15414#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15285#L543 assume !(0 != activate_threads_~tmp___0~0); 15249#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15250#L250 assume !(1 == ~t2_pc~0); 15546#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 15547#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15276#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15277#L551 assume !(0 != activate_threads_~tmp___1~0); 15517#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15460#L269 assume !(1 == ~t3_pc~0); 15455#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 15456#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15389#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15390#L559 assume !(0 != activate_threads_~tmp___2~0); 15518#L559-2 assume !(1 == ~M_E~0); 15519#L481-1 assume !(1 == ~T1_E~0); 15478#L486-1 assume !(1 == ~T2_E~0); 15479#L491-1 assume !(1 == ~T3_E~0); 15501#L496-1 assume !(1 == ~E_M~0); 15353#L501-1 assume !(1 == ~E_1~0); 15354#L506-1 assume !(1 == ~E_2~0); 15432#L511-1 assume !(1 == ~E_3~0); 15453#L682-1 [2020-11-28 03:04:42,653 INFO L796 eck$LassoCheckResult]: Loop: 15453#L682-1 assume !false; 16679#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 16678#L408 assume !false; 16677#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16675#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16672#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16671#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16669#L361 assume !(0 != eval_~tmp~0); 16670#L423 start_simulation_~kernel_st~0 := 2; 17412#L289-1 start_simulation_~kernel_st~0 := 3; 15263#L433-2 assume !(0 == ~M_E~0); 15237#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15238#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15294#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15536#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15468#L453-3 assume !(0 == ~E_1~0); 15469#L458-3 assume !(0 == ~E_2~0); 15487#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15379#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15269#L212-15 assume !(1 == ~m_pc~0); 15270#L212-17 is_master_triggered_~__retres1~0 := 0; 15333#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15201#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15202#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15477#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15384#L231-15 assume !(1 == ~t1_pc~0); 15367#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 15368#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15426#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15234#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15194#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15195#L250-15 assume !(1 == ~t2_pc~0); 16636#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 16630#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16631#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16624#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16625#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16615#L269-15 assume !(1 == ~t3_pc~0); 16611#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 16607#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16603#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16599#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16423#L559-17 assume !(1 == ~M_E~0); 16420#L481-3 assume !(1 == ~T1_E~0); 16419#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16418#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16415#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16413#L501-3 assume !(1 == ~E_1~0); 16411#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16409#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16404#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16399#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16391#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16383#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 16375#L701 assume !(0 == start_simulation_~tmp~3); 16376#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16776#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16728#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16726#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 16724#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16682#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 16681#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 16680#L714 assume !(0 != start_simulation_~tmp___0~1); 15453#L682-1 [2020-11-28 03:04:42,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:42,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2020-11-28 03:04:42,654 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:42,655 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410444303] [2020-11-28 03:04:42,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:42,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:42,669 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:42,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:42,680 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:42,720 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:42,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:42,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1221562622, now seen corresponding path program 1 times [2020-11-28 03:04:42,721 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:42,721 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132941023] [2020-11-28 03:04:42,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:42,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:42,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:42,759 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132941023] [2020-11-28 03:04:42,760 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:42,760 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:42,760 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748040015] [2020-11-28 03:04:42,761 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:42,761 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:42,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:42,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:42,762 INFO L87 Difference]: Start difference. First operand 2258 states and 3244 transitions. cyclomatic complexity: 989 Second operand 3 states. [2020-11-28 03:04:42,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:42,827 INFO L93 Difference]: Finished difference Result 2703 states and 3859 transitions. [2020-11-28 03:04:42,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:42,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2703 states and 3859 transitions. [2020-11-28 03:04:42,851 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2618 [2020-11-28 03:04:42,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2703 states to 2703 states and 3859 transitions. [2020-11-28 03:04:42,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2703 [2020-11-28 03:04:42,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2703 [2020-11-28 03:04:42,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2703 states and 3859 transitions. [2020-11-28 03:04:42,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:42,882 INFO L691 BuchiCegarLoop]: Abstraction has 2703 states and 3859 transitions. [2020-11-28 03:04:42,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2703 states and 3859 transitions. [2020-11-28 03:04:42,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2703 to 2703. [2020-11-28 03:04:42,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2703 states. [2020-11-28 03:04:42,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2703 states to 2703 states and 3859 transitions. [2020-11-28 03:04:42,955 INFO L714 BuchiCegarLoop]: Abstraction has 2703 states and 3859 transitions. [2020-11-28 03:04:42,956 INFO L594 BuchiCegarLoop]: Abstraction has 2703 states and 3859 transitions. [2020-11-28 03:04:42,956 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 03:04:42,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2703 states and 3859 transitions. [2020-11-28 03:04:42,967 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2618 [2020-11-28 03:04:42,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:42,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:42,969 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,969 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:42,969 INFO L794 eck$LassoCheckResult]: Stem: 20385#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20154#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20155#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20464#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 20152#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20153#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20221#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20289#L311-1 assume !(0 == ~M_E~0); 20228#L433-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20229#L438-1 assume !(0 == ~T2_E~0); 20488#L443-1 assume !(0 == ~T3_E~0); 20518#L448-1 assume !(0 == ~E_M~0); 20519#L453-1 assume !(0 == ~E_1~0); 20540#L458-1 assume !(0 == ~E_2~0); 20539#L463-1 assume !(0 == ~E_3~0); 20538#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20492#L212 assume !(1 == ~m_pc~0); 20483#L212-2 is_master_triggered_~__retres1~0 := 0; 20484#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20536#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20535#L535 assume !(0 != activate_threads_~tmp~1); 20534#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20532#L231 assume !(1 == ~t1_pc~0); 20531#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 20530#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20529#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20528#L543 assume !(0 != activate_threads_~tmp___0~0); 20217#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20218#L250 assume !(1 == ~t2_pc~0); 20513#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 20514#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20527#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20526#L551 assume !(0 != activate_threads_~tmp___1~0); 20525#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20524#L269 assume !(1 == ~t3_pc~0); 20418#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 20419#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20357#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20358#L559 assume !(0 != activate_threads_~tmp___2~0); 20521#L559-2 assume !(1 == ~M_E~0); 20517#L481-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20439#L486-1 assume !(1 == ~T2_E~0); 20440#L491-1 assume !(1 == ~T3_E~0); 20459#L496-1 assume !(1 == ~E_M~0); 20321#L501-1 assume !(1 == ~E_1~0); 20322#L506-1 assume !(1 == ~E_2~0); 20396#L511-1 assume !(1 == ~E_3~0); 20417#L682-1 [2020-11-28 03:04:42,970 INFO L796 eck$LassoCheckResult]: Loop: 20417#L682-1 assume !false; 22140#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 22104#L408 assume !false; 22139#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22136#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22132#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22130#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 22127#L361 assume !(0 != eval_~tmp~0); 22128#L423 start_simulation_~kernel_st~0 := 2; 22854#L289-1 start_simulation_~kernel_st~0 := 3; 22667#L433-2 assume !(0 == ~M_E~0); 22664#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22662#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22660#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22658#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22657#L453-3 assume !(0 == ~E_1~0); 22654#L458-3 assume !(0 == ~E_2~0); 22653#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22652#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22645#L212-15 assume !(1 == ~m_pc~0); 22644#L212-17 is_master_triggered_~__retres1~0 := 0; 22643#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22642#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22641#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22640#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22639#L231-15 assume !(1 == ~t1_pc~0); 22637#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 22636#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22635#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22634#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22633#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22347#L250-15 assume !(1 == ~t2_pc~0); 22345#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 22343#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22341#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22339#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22337#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22335#L269-15 assume !(1 == ~t3_pc~0); 21834#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 22332#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22329#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22327#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22325#L559-17 assume !(1 == ~M_E~0); 22323#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22320#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22318#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22316#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22313#L501-3 assume !(1 == ~E_1~0); 22311#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22309#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22307#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22305#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22300#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22299#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 22297#L701 assume !(0 == start_simulation_~tmp~3); 22295#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22178#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22174#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22168#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 22162#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22155#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 22143#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 22141#L714 assume !(0 != start_simulation_~tmp___0~1); 20417#L682-1 [2020-11-28 03:04:42,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:42,970 INFO L82 PathProgramCache]: Analyzing trace with hash -1809123875, now seen corresponding path program 1 times [2020-11-28 03:04:42,971 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:42,971 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614705592] [2020-11-28 03:04:42,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:42,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:43,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:43,002 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1614705592] [2020-11-28 03:04:43,002 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:43,002 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:43,002 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795903547] [2020-11-28 03:04:43,003 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:43,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,003 INFO L82 PathProgramCache]: Analyzing trace with hash -403914172, now seen corresponding path program 1 times [2020-11-28 03:04:43,003 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,004 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261592768] [2020-11-28 03:04:43,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:43,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:43,050 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261592768] [2020-11-28 03:04:43,050 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:43,050 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:04:43,051 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566339243] [2020-11-28 03:04:43,051 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:43,051 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:43,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:43,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:43,052 INFO L87 Difference]: Start difference. First operand 2703 states and 3859 transitions. cyclomatic complexity: 1159 Second operand 4 states. [2020-11-28 03:04:43,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:43,141 INFO L93 Difference]: Finished difference Result 3612 states and 5170 transitions. [2020-11-28 03:04:43,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:43,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3612 states and 5170 transitions. [2020-11-28 03:04:43,172 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3550 [2020-11-28 03:04:43,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3612 states to 3612 states and 5170 transitions. [2020-11-28 03:04:43,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3612 [2020-11-28 03:04:43,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3612 [2020-11-28 03:04:43,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3612 states and 5170 transitions. [2020-11-28 03:04:43,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:43,209 INFO L691 BuchiCegarLoop]: Abstraction has 3612 states and 5170 transitions. [2020-11-28 03:04:43,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3612 states and 5170 transitions. [2020-11-28 03:04:43,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3612 to 3612. [2020-11-28 03:04:43,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3612 states. [2020-11-28 03:04:43,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3612 states to 3612 states and 5170 transitions. [2020-11-28 03:04:43,292 INFO L714 BuchiCegarLoop]: Abstraction has 3612 states and 5170 transitions. [2020-11-28 03:04:43,292 INFO L594 BuchiCegarLoop]: Abstraction has 3612 states and 5170 transitions. [2020-11-28 03:04:43,292 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 03:04:43,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3612 states and 5170 transitions. [2020-11-28 03:04:43,305 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3550 [2020-11-28 03:04:43,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:43,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:43,307 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,307 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,307 INFO L794 eck$LassoCheckResult]: Stem: 26712#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26481#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26482#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26805#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 26479#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26480#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26546#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26617#L311-1 assume !(0 == ~M_E~0); 26553#L433-1 assume !(0 == ~T1_E~0); 26554#L438-1 assume !(0 == ~T2_E~0); 26822#L443-1 assume !(0 == ~T3_E~0); 26836#L448-1 assume !(0 == ~E_M~0); 26762#L453-1 assume !(0 == ~E_1~0); 26763#L458-1 assume !(0 == ~E_2~0); 26781#L463-1 assume !(0 == ~E_3~0); 26655#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26656#L212 assume !(1 == ~m_pc~0); 26819#L212-2 is_master_triggered_~__retres1~0 := 0; 26820#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26540#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26541#L535 assume !(0 != activate_threads_~tmp~1); 26793#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26706#L231 assume !(1 == ~t1_pc~0); 26692#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 26693#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26708#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26579#L543 assume !(0 != activate_threads_~tmp___0~0); 26544#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26545#L250 assume !(1 == ~t2_pc~0); 26837#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 26838#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26573#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26574#L551 assume !(0 != activate_threads_~tmp___1~0); 26813#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26758#L269 assume !(1 == ~t3_pc~0); 26752#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 26753#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26686#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26687#L559 assume !(0 != activate_threads_~tmp___2~0); 26816#L559-2 assume !(1 == ~M_E~0); 26817#L481-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26777#L486-1 assume !(1 == ~T2_E~0); 26778#L491-1 assume !(1 == ~T3_E~0); 26796#L496-1 assume !(1 == ~E_M~0); 26646#L501-1 assume !(1 == ~E_1~0); 26647#L506-1 assume !(1 == ~E_2~0); 26724#L511-1 assume !(1 == ~E_3~0); 26751#L682-1 [2020-11-28 03:04:43,307 INFO L796 eck$LassoCheckResult]: Loop: 26751#L682-1 assume !false; 28944#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 28938#L408 assume !false; 28939#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28934#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28931#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28901#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 28894#L361 assume !(0 != eval_~tmp~0); 26754#L423 start_simulation_~kernel_st~0 := 2; 26755#L289-1 start_simulation_~kernel_st~0 := 3; 26557#L433-2 assume !(0 == ~M_E~0); 26530#L433-4 assume !(0 == ~T1_E~0); 26531#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26588#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26829#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30060#L453-3 assume !(0 == ~E_1~0); 30059#L458-3 assume !(0 == ~E_2~0); 30058#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30056#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30054#L212-15 assume !(1 == ~m_pc~0); 30052#L212-17 is_master_triggered_~__retres1~0 := 0; 30049#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30048#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30047#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30021#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30020#L231-15 assume !(1 == ~t1_pc~0); 30018#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 30015#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30014#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30013#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30011#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30008#L250-15 assume !(1 == ~t2_pc~0); 29930#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 30003#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30001#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30000#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29927#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29928#L269-15 assume !(1 == ~t3_pc~0); 29488#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 29995#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29994#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29993#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29992#L559-17 assume !(1 == ~M_E~0); 29991#L481-3 assume !(1 == ~T1_E~0); 27692#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29990#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29989#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29988#L501-3 assume !(1 == ~E_1~0); 26729#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26730#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26507#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 26508#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 29254#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29057#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 29058#L701 assume !(0 == start_simulation_~tmp~3); 29048#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 29049#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 29036#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29037#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 29025#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29026#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 29018#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 29019#L714 assume !(0 != start_simulation_~tmp___0~1); 26751#L682-1 [2020-11-28 03:04:43,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,308 INFO L82 PathProgramCache]: Analyzing trace with hash 640476255, now seen corresponding path program 1 times [2020-11-28 03:04:43,308 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,309 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119163456] [2020-11-28 03:04:43,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:43,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:43,342 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119163456] [2020-11-28 03:04:43,342 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:43,342 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:43,342 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105596175] [2020-11-28 03:04:43,343 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:43,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,343 INFO L82 PathProgramCache]: Analyzing trace with hash 316777408, now seen corresponding path program 1 times [2020-11-28 03:04:43,343 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,343 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181540747] [2020-11-28 03:04:43,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:43,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:43,391 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181540747] [2020-11-28 03:04:43,391 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:43,391 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:04:43,391 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859011312] [2020-11-28 03:04:43,392 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:43,392 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:43,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:04:43,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:04:43,392 INFO L87 Difference]: Start difference. First operand 3612 states and 5170 transitions. cyclomatic complexity: 1563 Second operand 4 states. [2020-11-28 03:04:43,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:43,460 INFO L93 Difference]: Finished difference Result 3020 states and 4300 transitions. [2020-11-28 03:04:43,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:04:43,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3020 states and 4300 transitions. [2020-11-28 03:04:43,474 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2964 [2020-11-28 03:04:43,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3020 states to 3020 states and 4300 transitions. [2020-11-28 03:04:43,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3020 [2020-11-28 03:04:43,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3020 [2020-11-28 03:04:43,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3020 states and 4300 transitions. [2020-11-28 03:04:43,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:43,511 INFO L691 BuchiCegarLoop]: Abstraction has 3020 states and 4300 transitions. [2020-11-28 03:04:43,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3020 states and 4300 transitions. [2020-11-28 03:04:43,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3020 to 3020. [2020-11-28 03:04:43,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3020 states. [2020-11-28 03:04:43,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3020 states to 3020 states and 4300 transitions. [2020-11-28 03:04:43,576 INFO L714 BuchiCegarLoop]: Abstraction has 3020 states and 4300 transitions. [2020-11-28 03:04:43,576 INFO L594 BuchiCegarLoop]: Abstraction has 3020 states and 4300 transitions. [2020-11-28 03:04:43,576 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 03:04:43,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3020 states and 4300 transitions. [2020-11-28 03:04:43,585 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2964 [2020-11-28 03:04:43,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:43,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:43,586 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,587 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,587 INFO L794 eck$LassoCheckResult]: Stem: 33354#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 33125#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 33126#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33439#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 33123#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33124#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33190#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33257#L311-1 assume !(0 == ~M_E~0); 33197#L433-1 assume !(0 == ~T1_E~0); 33198#L438-1 assume !(0 == ~T2_E~0); 33461#L443-1 assume !(0 == ~T3_E~0); 33479#L448-1 assume !(0 == ~E_M~0); 33398#L453-1 assume !(0 == ~E_1~0); 33399#L458-1 assume !(0 == ~E_2~0); 33420#L463-1 assume !(0 == ~E_3~0); 33296#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33297#L212 assume !(1 == ~m_pc~0); 33457#L212-2 is_master_triggered_~__retres1~0 := 0; 33458#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33184#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33185#L535 assume !(0 != activate_threads_~tmp~1); 33431#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33348#L231 assume !(1 == ~t1_pc~0); 33334#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 33335#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33350#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 33219#L543 assume !(0 != activate_threads_~tmp___0~0); 33186#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33187#L250 assume !(1 == ~t2_pc~0); 33480#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 33481#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33212#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 33213#L551 assume !(0 != activate_threads_~tmp___1~0); 33451#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33395#L269 assume !(1 == ~t3_pc~0); 33391#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 33392#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33328#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 33329#L559 assume !(0 != activate_threads_~tmp___2~0); 33452#L559-2 assume !(1 == ~M_E~0); 33453#L481-1 assume !(1 == ~T1_E~0); 33415#L486-1 assume !(1 == ~T2_E~0); 33416#L491-1 assume !(1 == ~T3_E~0); 33432#L496-1 assume !(1 == ~E_M~0); 33287#L501-1 assume !(1 == ~E_1~0); 33288#L506-1 assume !(1 == ~E_2~0); 33367#L511-1 assume !(1 == ~E_3~0); 33390#L682-1 [2020-11-28 03:04:43,587 INFO L796 eck$LassoCheckResult]: Loop: 33390#L682-1 assume !false; 35634#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 33195#L408 assume !false; 35633#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 35631#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 33397#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 33321#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 33222#L361 assume !(0 != eval_~tmp~0); 33223#L423 start_simulation_~kernel_st~0 := 2; 36009#L289-1 start_simulation_~kernel_st~0 := 3; 36008#L433-2 assume !(0 == ~M_E~0); 36006#L433-4 assume !(0 == ~T1_E~0); 36004#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36002#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36000#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35998#L453-3 assume !(0 == ~E_1~0); 35996#L458-3 assume !(0 == ~E_2~0); 35993#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35991#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35989#L212-15 assume !(1 == ~m_pc~0); 35987#L212-17 is_master_triggered_~__retres1~0 := 0; 35985#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35983#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35981#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35978#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35977#L231-15 assume !(1 == ~t1_pc~0); 35974#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 35972#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35971#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35970#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35969#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33476#L250-15 assume !(1 == ~t2_pc~0); 33462#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 33463#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33244#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 33245#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33430#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33351#L269-15 assume !(1 == ~t3_pc~0); 33352#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 35958#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35836#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35805#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35804#L559-17 assume !(1 == ~M_E~0); 35803#L481-3 assume !(1 == ~T1_E~0); 35802#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35801#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35800#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35799#L501-3 assume !(1 == ~E_1~0); 35798#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35797#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35795#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 35793#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 35788#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 33326#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 33327#L701 assume !(0 == start_simulation_~tmp~3); 33489#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 35660#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 35654#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 35648#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 35645#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35640#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 35637#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 35636#L714 assume !(0 != start_simulation_~tmp___0~1); 33390#L682-1 [2020-11-28 03:04:43,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,587 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2020-11-28 03:04:43,587 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,588 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472643433] [2020-11-28 03:04:43,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:43,596 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:43,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:43,603 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:43,626 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:43,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,626 INFO L82 PathProgramCache]: Analyzing trace with hash 316777408, now seen corresponding path program 2 times [2020-11-28 03:04:43,627 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,627 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918630249] [2020-11-28 03:04:43,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:43,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:43,660 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918630249] [2020-11-28 03:04:43,660 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:43,660 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:04:43,660 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190645500] [2020-11-28 03:04:43,660 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:43,661 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:43,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:04:43,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:04:43,662 INFO L87 Difference]: Start difference. First operand 3020 states and 4300 transitions. cyclomatic complexity: 1284 Second operand 5 states. [2020-11-28 03:04:43,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:43,797 INFO L93 Difference]: Finished difference Result 5232 states and 7328 transitions. [2020-11-28 03:04:43,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:04:43,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5232 states and 7328 transitions. [2020-11-28 03:04:43,823 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5168 [2020-11-28 03:04:43,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5232 states to 5232 states and 7328 transitions. [2020-11-28 03:04:43,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5232 [2020-11-28 03:04:43,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5232 [2020-11-28 03:04:43,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5232 states and 7328 transitions. [2020-11-28 03:04:43,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:43,862 INFO L691 BuchiCegarLoop]: Abstraction has 5232 states and 7328 transitions. [2020-11-28 03:04:43,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5232 states and 7328 transitions. [2020-11-28 03:04:43,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5232 to 3068. [2020-11-28 03:04:43,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3068 states. [2020-11-28 03:04:43,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3068 states to 3068 states and 4348 transitions. [2020-11-28 03:04:43,935 INFO L714 BuchiCegarLoop]: Abstraction has 3068 states and 4348 transitions. [2020-11-28 03:04:43,935 INFO L594 BuchiCegarLoop]: Abstraction has 3068 states and 4348 transitions. [2020-11-28 03:04:43,935 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 03:04:43,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3068 states and 4348 transitions. [2020-11-28 03:04:43,945 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3012 [2020-11-28 03:04:43,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:43,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:43,946 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,946 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:43,946 INFO L794 eck$LassoCheckResult]: Stem: 41628#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 41393#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41394#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41717#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 41391#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41392#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41459#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41528#L311-1 assume !(0 == ~M_E~0); 41466#L433-1 assume !(0 == ~T1_E~0); 41467#L438-1 assume !(0 == ~T2_E~0); 41739#L443-1 assume !(0 == ~T3_E~0); 41751#L448-1 assume !(0 == ~E_M~0); 41672#L453-1 assume !(0 == ~E_1~0); 41673#L458-1 assume !(0 == ~E_2~0); 41694#L463-1 assume !(0 == ~E_3~0); 41569#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41570#L212 assume !(1 == ~m_pc~0); 41734#L212-2 is_master_triggered_~__retres1~0 := 0; 41735#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41453#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41454#L535 assume !(0 != activate_threads_~tmp~1); 41706#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41622#L231 assume !(1 == ~t1_pc~0); 41608#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 41609#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41624#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41491#L543 assume !(0 != activate_threads_~tmp___0~0); 41455#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41456#L250 assume !(1 == ~t2_pc~0); 41752#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 41753#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41483#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41484#L551 assume !(0 != activate_threads_~tmp___1~0); 41728#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41669#L269 assume !(1 == ~t3_pc~0); 41664#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 41665#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41602#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 41603#L559 assume !(0 != activate_threads_~tmp___2~0); 41731#L559-2 assume !(1 == ~M_E~0); 41732#L481-1 assume !(1 == ~T1_E~0); 41689#L486-1 assume !(1 == ~T2_E~0); 41690#L491-1 assume !(1 == ~T3_E~0); 41709#L496-1 assume !(1 == ~E_M~0); 41560#L501-1 assume !(1 == ~E_1~0); 41561#L506-1 assume !(1 == ~E_2~0); 41642#L511-1 assume !(1 == ~E_3~0); 41663#L682-1 [2020-11-28 03:04:43,946 INFO L796 eck$LassoCheckResult]: Loop: 41663#L682-1 assume !false; 43163#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 43160#L408 assume !false; 43159#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43157#L324 assume !(0 == ~m_st~0); 43158#L328 assume !(0 == ~t1_st~0); 43154#L332 assume !(0 == ~t2_st~0); 43155#L336 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 43156#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43085#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 43086#L361 assume !(0 != eval_~tmp~0); 43509#L423 start_simulation_~kernel_st~0 := 2; 43501#L289-1 start_simulation_~kernel_st~0 := 3; 43502#L433-2 assume !(0 == ~M_E~0); 43493#L433-4 assume !(0 == ~T1_E~0); 43494#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43485#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43486#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43477#L453-3 assume !(0 == ~E_1~0); 43478#L458-3 assume !(0 == ~E_2~0); 43469#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43470#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43461#L212-15 assume !(1 == ~m_pc~0); 43462#L212-17 is_master_triggered_~__retres1~0 := 0; 43453#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43454#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43445#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 43446#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43438#L231-15 assume !(1 == ~t1_pc~0); 43437#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 43427#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43428#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 43419#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43420#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43223#L250-15 assume !(1 == ~t2_pc~0); 43224#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 43219#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43220#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 43215#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43216#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43212#L269-15 assume !(1 == ~t3_pc~0); 43211#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 43210#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43209#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43208#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43207#L559-17 assume !(1 == ~M_E~0); 43206#L481-3 assume !(1 == ~T1_E~0); 43205#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43204#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43203#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 43202#L501-3 assume !(1 == ~E_1~0); 43201#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43200#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43199#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43198#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43194#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43193#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 43191#L701 assume !(0 == start_simulation_~tmp~3); 43189#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43187#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43183#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43181#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 43179#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43177#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 43173#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 43171#L714 assume !(0 != start_simulation_~tmp___0~1); 41663#L682-1 [2020-11-28 03:04:43,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2020-11-28 03:04:43,947 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,947 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267898238] [2020-11-28 03:04:43,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:43,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:43,965 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:43,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:43,973 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:43,989 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:43,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:43,990 INFO L82 PathProgramCache]: Analyzing trace with hash 466585598, now seen corresponding path program 1 times [2020-11-28 03:04:43,990 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:43,990 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279304289] [2020-11-28 03:04:43,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:44,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:44,086 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279304289] [2020-11-28 03:04:44,086 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:44,086 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:04:44,086 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399043877] [2020-11-28 03:04:44,086 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:44,087 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:44,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:04:44,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:04:44,087 INFO L87 Difference]: Start difference. First operand 3068 states and 4348 transitions. cyclomatic complexity: 1284 Second operand 5 states. [2020-11-28 03:04:44,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:44,291 INFO L93 Difference]: Finished difference Result 6088 states and 8571 transitions. [2020-11-28 03:04:44,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:04:44,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6088 states and 8571 transitions. [2020-11-28 03:04:44,319 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6032 [2020-11-28 03:04:44,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6088 states to 6088 states and 8571 transitions. [2020-11-28 03:04:44,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6088 [2020-11-28 03:04:44,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6088 [2020-11-28 03:04:44,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6088 states and 8571 transitions. [2020-11-28 03:04:44,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:44,368 INFO L691 BuchiCegarLoop]: Abstraction has 6088 states and 8571 transitions. [2020-11-28 03:04:44,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6088 states and 8571 transitions. [2020-11-28 03:04:44,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6088 to 3176. [2020-11-28 03:04:44,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3176 states. [2020-11-28 03:04:44,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3176 states to 3176 states and 4427 transitions. [2020-11-28 03:04:44,445 INFO L714 BuchiCegarLoop]: Abstraction has 3176 states and 4427 transitions. [2020-11-28 03:04:44,445 INFO L594 BuchiCegarLoop]: Abstraction has 3176 states and 4427 transitions. [2020-11-28 03:04:44,445 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 03:04:44,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3176 states and 4427 transitions. [2020-11-28 03:04:44,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3120 [2020-11-28 03:04:44,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:44,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:44,459 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:44,459 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:44,460 INFO L794 eck$LassoCheckResult]: Stem: 50796#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 50562#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50563#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 50890#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 50560#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50561#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50627#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50695#L311-1 assume !(0 == ~M_E~0); 50634#L433-1 assume !(0 == ~T1_E~0); 50635#L438-1 assume !(0 == ~T2_E~0); 50919#L443-1 assume !(0 == ~T3_E~0); 50941#L448-1 assume !(0 == ~E_M~0); 50840#L453-1 assume !(0 == ~E_1~0); 50841#L458-1 assume !(0 == ~E_2~0); 50864#L463-1 assume !(0 == ~E_3~0); 50736#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50737#L212 assume !(1 == ~m_pc~0); 50914#L212-2 is_master_triggered_~__retres1~0 := 0; 50915#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50621#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 50622#L535 assume !(0 != activate_threads_~tmp~1); 50879#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50790#L231 assume !(1 == ~t1_pc~0); 50776#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 50777#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50792#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 50660#L543 assume !(0 != activate_threads_~tmp___0~0); 50623#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50624#L250 assume !(1 == ~t2_pc~0); 50942#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 50943#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50652#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 50653#L551 assume !(0 != activate_threads_~tmp___1~0); 50902#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50836#L269 assume !(1 == ~t3_pc~0); 50832#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 50833#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50770#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 50771#L559 assume !(0 != activate_threads_~tmp___2~0); 50906#L559-2 assume !(1 == ~M_E~0); 50907#L481-1 assume !(1 == ~T1_E~0); 50856#L486-1 assume !(1 == ~T2_E~0); 50857#L491-1 assume !(1 == ~T3_E~0); 50880#L496-1 assume !(1 == ~E_M~0); 50727#L501-1 assume !(1 == ~E_1~0); 50728#L506-1 assume !(1 == ~E_2~0); 50807#L511-1 assume !(1 == ~E_3~0); 50831#L682-1 [2020-11-28 03:04:44,460 INFO L796 eck$LassoCheckResult]: Loop: 50831#L682-1 assume !false; 51349#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 51347#L408 assume !false; 51345#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 51346#L324 assume !(0 == ~m_st~0); 52087#L328 assume !(0 == ~t1_st~0); 52084#L332 assume !(0 == ~t2_st~0); 52085#L336 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 52086#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 51117#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 51118#L361 assume !(0 != eval_~tmp~0); 52876#L423 start_simulation_~kernel_st~0 := 2; 52875#L289-1 start_simulation_~kernel_st~0 := 3; 52874#L433-2 assume !(0 == ~M_E~0); 52873#L433-4 assume !(0 == ~T1_E~0); 52872#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52871#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52870#L448-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52869#L453-3 assume !(0 == ~E_1~0); 52868#L458-3 assume !(0 == ~E_2~0); 52867#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52866#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52865#L212-15 assume !(1 == ~m_pc~0); 52864#L212-17 is_master_triggered_~__retres1~0 := 0; 52863#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52862#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52861#L535-15 assume !(0 != activate_threads_~tmp~1); 52860#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52859#L231-15 assume !(1 == ~t1_pc~0); 52857#L231-17 is_transmit1_triggered_~__retres1~1 := 0; 52856#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52855#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52854#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52853#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52852#L250-15 assume !(1 == ~t2_pc~0); 52179#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 52851#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52850#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52849#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 52848#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52847#L269-15 assume !(1 == ~t3_pc~0); 51553#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 52846#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52845#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 52844#L559-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 52843#L559-17 assume !(1 == ~M_E~0); 52842#L481-3 assume !(1 == ~T1_E~0); 52841#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52840#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52839#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52837#L501-3 assume !(1 == ~E_1~0); 51109#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51110#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51504#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 51505#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 51486#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 51487#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 51385#L701 assume !(0 == start_simulation_~tmp~3); 51387#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 51375#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 51373#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 51366#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 51367#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 51360#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 51361#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 51353#L714 assume !(0 != start_simulation_~tmp___0~1); 50831#L682-1 [2020-11-28 03:04:44,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:44,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2020-11-28 03:04:44,460 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:44,461 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876716975] [2020-11-28 03:04:44,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,472 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,480 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,490 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:44,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:44,490 INFO L82 PathProgramCache]: Analyzing trace with hash -905221700, now seen corresponding path program 1 times [2020-11-28 03:04:44,490 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:44,493 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718980150] [2020-11-28 03:04:44,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:44,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:44,532 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718980150] [2020-11-28 03:04:44,532 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:44,532 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:44,532 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312020967] [2020-11-28 03:04:44,532 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:04:44,533 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:44,533 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:44,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:44,534 INFO L87 Difference]: Start difference. First operand 3176 states and 4427 transitions. cyclomatic complexity: 1255 Second operand 3 states. [2020-11-28 03:04:44,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:44,596 INFO L93 Difference]: Finished difference Result 4828 states and 6611 transitions. [2020-11-28 03:04:44,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:44,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4828 states and 6611 transitions. [2020-11-28 03:04:44,618 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 4774 [2020-11-28 03:04:44,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4828 states to 4828 states and 6611 transitions. [2020-11-28 03:04:44,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4828 [2020-11-28 03:04:44,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4828 [2020-11-28 03:04:44,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4828 states and 6611 transitions. [2020-11-28 03:04:44,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:44,650 INFO L691 BuchiCegarLoop]: Abstraction has 4828 states and 6611 transitions. [2020-11-28 03:04:44,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4828 states and 6611 transitions. [2020-11-28 03:04:44,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4828 to 4660. [2020-11-28 03:04:44,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4660 states. [2020-11-28 03:04:44,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4660 states to 4660 states and 6387 transitions. [2020-11-28 03:04:44,749 INFO L714 BuchiCegarLoop]: Abstraction has 4660 states and 6387 transitions. [2020-11-28 03:04:44,749 INFO L594 BuchiCegarLoop]: Abstraction has 4660 states and 6387 transitions. [2020-11-28 03:04:44,749 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 03:04:44,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4660 states and 6387 transitions. [2020-11-28 03:04:44,767 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 4606 [2020-11-28 03:04:44,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:44,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:44,767 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:44,768 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:44,768 INFO L794 eck$LassoCheckResult]: Stem: 58803#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 58572#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 58573#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58897#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 58570#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58571#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58639#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58702#L311-1 assume !(0 == ~M_E~0); 58646#L433-1 assume !(0 == ~T1_E~0); 58647#L438-1 assume !(0 == ~T2_E~0); 58921#L443-1 assume !(0 == ~T3_E~0); 58943#L448-1 assume !(0 == ~E_M~0); 58848#L453-1 assume !(0 == ~E_1~0); 58849#L458-1 assume !(0 == ~E_2~0); 58868#L463-1 assume !(0 == ~E_3~0); 58742#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58743#L212 assume !(1 == ~m_pc~0); 58916#L212-2 is_master_triggered_~__retres1~0 := 0; 58917#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58633#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58634#L535 assume !(0 != activate_threads_~tmp~1); 58886#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58797#L231 assume !(1 == ~t1_pc~0); 58783#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 58784#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58799#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58668#L543 assume !(0 != activate_threads_~tmp___0~0); 58635#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58636#L250 assume !(1 == ~t2_pc~0); 58944#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 58945#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58663#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58664#L551 assume !(0 != activate_threads_~tmp___1~0); 58908#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58844#L269 assume !(1 == ~t3_pc~0); 58840#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 58841#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58776#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58777#L559 assume !(0 != activate_threads_~tmp___2~0); 58912#L559-2 assume !(1 == ~M_E~0); 58913#L481-1 assume !(1 == ~T1_E~0); 58862#L486-1 assume !(1 == ~T2_E~0); 58863#L491-1 assume !(1 == ~T3_E~0); 58887#L496-1 assume !(1 == ~E_M~0); 58733#L501-1 assume !(1 == ~E_1~0); 58734#L506-1 assume !(1 == ~E_2~0); 58816#L511-1 assume !(1 == ~E_3~0); 58839#L682-1 assume !false; 60321#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 60260#L408 [2020-11-28 03:04:44,768 INFO L796 eck$LassoCheckResult]: Loop: 60260#L408 assume !false; 60315#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 60310#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 60306#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 60303#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 60296#L361 assume 0 != eval_~tmp~0; 60287#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 60277#L369 assume !(0 != eval_~tmp_ndt_1~0); 60272#L366 assume !(0 == ~t1_st~0); 60264#L380 assume !(0 == ~t2_st~0); 60253#L394 assume !(0 == ~t3_st~0); 60260#L408 [2020-11-28 03:04:44,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:44,768 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2020-11-28 03:04:44,769 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:44,769 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337036737] [2020-11-28 03:04:44,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,779 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,787 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,797 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:44,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:44,798 INFO L82 PathProgramCache]: Analyzing trace with hash 527410952, now seen corresponding path program 1 times [2020-11-28 03:04:44,798 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:44,798 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032085644] [2020-11-28 03:04:44,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,801 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:44,803 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:44,804 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:44,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:44,805 INFO L82 PathProgramCache]: Analyzing trace with hash -1008020890, now seen corresponding path program 1 times [2020-11-28 03:04:44,805 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:44,807 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180917329] [2020-11-28 03:04:44,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:44,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:44,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:44,866 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180917329] [2020-11-28 03:04:44,866 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:44,866 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:44,866 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811509038] [2020-11-28 03:04:44,943 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:44,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:44,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:44,944 INFO L87 Difference]: Start difference. First operand 4660 states and 6387 transitions. cyclomatic complexity: 1732 Second operand 3 states. [2020-11-28 03:04:45,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:45,130 INFO L93 Difference]: Finished difference Result 8203 states and 11120 transitions. [2020-11-28 03:04:45,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:45,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8203 states and 11120 transitions. [2020-11-28 03:04:45,164 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 8100 [2020-11-28 03:04:45,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8203 states to 8203 states and 11120 transitions. [2020-11-28 03:04:45,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8203 [2020-11-28 03:04:45,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8203 [2020-11-28 03:04:45,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8203 states and 11120 transitions. [2020-11-28 03:04:45,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:45,209 INFO L691 BuchiCegarLoop]: Abstraction has 8203 states and 11120 transitions. [2020-11-28 03:04:45,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8203 states and 11120 transitions. [2020-11-28 03:04:45,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8203 to 7755. [2020-11-28 03:04:45,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7755 states. [2020-11-28 03:04:45,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7755 states to 7755 states and 10560 transitions. [2020-11-28 03:04:45,391 INFO L714 BuchiCegarLoop]: Abstraction has 7755 states and 10560 transitions. [2020-11-28 03:04:45,391 INFO L594 BuchiCegarLoop]: Abstraction has 7755 states and 10560 transitions. [2020-11-28 03:04:45,391 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 03:04:45,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7755 states and 10560 transitions. [2020-11-28 03:04:45,418 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 7652 [2020-11-28 03:04:45,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:45,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:45,419 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:45,419 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:45,420 INFO L794 eck$LassoCheckResult]: Stem: 71683#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 71444#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 71445#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 71790#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 71441#L296-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 71442#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71513#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71581#L311-1 assume !(0 == ~M_E~0); 71521#L433-1 assume !(0 == ~T1_E~0); 71522#L438-1 assume !(0 == ~T2_E~0); 71818#L443-1 assume !(0 == ~T3_E~0); 71844#L448-1 assume !(0 == ~E_M~0); 71730#L453-1 assume !(0 == ~E_1~0); 71731#L458-1 assume !(0 == ~E_2~0); 71758#L463-1 assume !(0 == ~E_3~0); 71620#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71621#L212 assume !(1 == ~m_pc~0); 71811#L212-2 is_master_triggered_~__retres1~0 := 0; 71812#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71507#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 71508#L535 assume !(0 != activate_threads_~tmp~1); 71776#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71677#L231 assume !(1 == ~t1_pc~0); 71663#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 71664#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71679#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 71545#L543 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 71546#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74797#L250 assume !(1 == ~t2_pc~0); 74796#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 74795#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74794#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 74793#L551 assume !(0 != activate_threads_~tmp___1~0); 74792#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 74791#L269 assume !(1 == ~t3_pc~0); 74790#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 74789#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 74788#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 74787#L559 assume !(0 != activate_threads_~tmp___2~0); 74786#L559-2 assume !(1 == ~M_E~0); 74785#L481-1 assume !(1 == ~T1_E~0); 74784#L486-1 assume !(1 == ~T2_E~0); 74783#L491-1 assume !(1 == ~T3_E~0); 74782#L496-1 assume !(1 == ~E_M~0); 74781#L501-1 assume !(1 == ~E_1~0); 74780#L506-1 assume !(1 == ~E_2~0); 74779#L511-1 assume !(1 == ~E_3~0); 74778#L682-1 assume !false; 74777#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 73500#L408 [2020-11-28 03:04:45,420 INFO L796 eck$LassoCheckResult]: Loop: 73500#L408 assume !false; 74776#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 74774#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 74772#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 74770#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 74767#L361 assume 0 != eval_~tmp~0; 73483#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 73479#L369 assume !(0 != eval_~tmp_ndt_1~0); 73477#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 73474#L383 assume !(0 != eval_~tmp_ndt_2~0); 73471#L380 assume !(0 == ~t2_st~0); 73469#L394 assume !(0 == ~t3_st~0); 73500#L408 [2020-11-28 03:04:45,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:45,420 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2020-11-28 03:04:45,420 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:45,421 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389155285] [2020-11-28 03:04:45,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:45,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:45,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:45,439 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389155285] [2020-11-28 03:04:45,440 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:45,440 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:45,440 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792844210] [2020-11-28 03:04:45,440 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:04:45,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:45,441 INFO L82 PathProgramCache]: Analyzing trace with hash -834106682, now seen corresponding path program 1 times [2020-11-28 03:04:45,441 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:45,441 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421112576] [2020-11-28 03:04:45,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:45,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,445 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,447 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,455 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:45,551 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:45,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:45,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:45,552 INFO L87 Difference]: Start difference. First operand 7755 states and 10560 transitions. cyclomatic complexity: 2810 Second operand 3 states. [2020-11-28 03:04:45,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:45,592 INFO L93 Difference]: Finished difference Result 7710 states and 10500 transitions. [2020-11-28 03:04:45,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:45,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7710 states and 10500 transitions. [2020-11-28 03:04:45,631 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 7652 [2020-11-28 03:04:45,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7710 states to 7710 states and 10500 transitions. [2020-11-28 03:04:45,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7710 [2020-11-28 03:04:45,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7710 [2020-11-28 03:04:45,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7710 states and 10500 transitions. [2020-11-28 03:04:45,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:45,677 INFO L691 BuchiCegarLoop]: Abstraction has 7710 states and 10500 transitions. [2020-11-28 03:04:45,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7710 states and 10500 transitions. [2020-11-28 03:04:45,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7710 to 7710. [2020-11-28 03:04:45,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7710 states. [2020-11-28 03:04:45,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7710 states to 7710 states and 10500 transitions. [2020-11-28 03:04:45,781 INFO L714 BuchiCegarLoop]: Abstraction has 7710 states and 10500 transitions. [2020-11-28 03:04:45,781 INFO L594 BuchiCegarLoop]: Abstraction has 7710 states and 10500 transitions. [2020-11-28 03:04:45,781 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 03:04:45,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7710 states and 10500 transitions. [2020-11-28 03:04:45,805 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 7652 [2020-11-28 03:04:45,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:45,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:45,806 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:45,806 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:45,806 INFO L794 eck$LassoCheckResult]: Stem: 87149#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 86914#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 86915#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87236#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 86912#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86913#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86983#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87049#L311-1 assume !(0 == ~M_E~0); 86990#L433-1 assume !(0 == ~T1_E~0); 86991#L438-1 assume !(0 == ~T2_E~0); 87261#L443-1 assume !(0 == ~T3_E~0); 87275#L448-1 assume !(0 == ~E_M~0); 87191#L453-1 assume !(0 == ~E_1~0); 87192#L458-1 assume !(0 == ~E_2~0); 87213#L463-1 assume !(0 == ~E_3~0); 87088#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87089#L212 assume !(1 == ~m_pc~0); 87255#L212-2 is_master_triggered_~__retres1~0 := 0; 87256#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86977#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 86978#L535 assume !(0 != activate_threads_~tmp~1); 87226#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87144#L231 assume !(1 == ~t1_pc~0); 87130#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 87131#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87146#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 87015#L543 assume !(0 != activate_threads_~tmp___0~0); 86981#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86982#L250 assume !(1 == ~t2_pc~0); 87276#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 87277#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87009#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 87010#L551 assume !(0 != activate_threads_~tmp___1~0); 87250#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87189#L269 assume !(1 == ~t3_pc~0); 87185#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 87186#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87123#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 87124#L559 assume !(0 != activate_threads_~tmp___2~0); 87252#L559-2 assume !(1 == ~M_E~0); 87253#L481-1 assume !(1 == ~T1_E~0); 87208#L486-1 assume !(1 == ~T2_E~0); 87209#L491-1 assume !(1 == ~T3_E~0); 87229#L496-1 assume !(1 == ~E_M~0); 87079#L501-1 assume !(1 == ~E_1~0); 87080#L506-1 assume !(1 == ~E_2~0); 87160#L511-1 assume !(1 == ~E_3~0); 87184#L682-1 assume !false; 88650#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 88647#L408 [2020-11-28 03:04:45,806 INFO L796 eck$LassoCheckResult]: Loop: 88647#L408 assume !false; 88646#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 88645#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 88643#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 88641#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 88639#L361 assume 0 != eval_~tmp~0; 88637#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 88634#L369 assume !(0 != eval_~tmp_ndt_1~0); 88515#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 88512#L383 assume !(0 != eval_~tmp_ndt_2~0); 88509#L380 assume !(0 == ~t2_st~0); 88507#L394 assume !(0 == ~t3_st~0); 88647#L408 [2020-11-28 03:04:45,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:45,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2020-11-28 03:04:45,807 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:45,807 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043976126] [2020-11-28 03:04:45,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:45,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,817 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,829 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,839 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:45,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:45,840 INFO L82 PathProgramCache]: Analyzing trace with hash -834106682, now seen corresponding path program 2 times [2020-11-28 03:04:45,840 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:45,840 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999794525] [2020-11-28 03:04:45,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:45,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,844 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:45,845 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:45,848 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:45,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:45,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1187853528, now seen corresponding path program 1 times [2020-11-28 03:04:45,849 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:45,849 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825077565] [2020-11-28 03:04:45,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:45,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:45,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:45,876 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825077565] [2020-11-28 03:04:45,876 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:45,876 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:04:45,876 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072337130] [2020-11-28 03:04:45,970 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:45,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:45,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:45,971 INFO L87 Difference]: Start difference. First operand 7710 states and 10500 transitions. cyclomatic complexity: 2795 Second operand 3 states. [2020-11-28 03:04:46,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:46,153 INFO L93 Difference]: Finished difference Result 13714 states and 18528 transitions. [2020-11-28 03:04:46,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:46,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13714 states and 18528 transitions. [2020-11-28 03:04:46,216 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 13648 [2020-11-28 03:04:46,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13714 states to 13714 states and 18528 transitions. [2020-11-28 03:04:46,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13714 [2020-11-28 03:04:46,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13714 [2020-11-28 03:04:46,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13714 states and 18528 transitions. [2020-11-28 03:04:46,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:46,302 INFO L691 BuchiCegarLoop]: Abstraction has 13714 states and 18528 transitions. [2020-11-28 03:04:46,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13714 states and 18528 transitions. [2020-11-28 03:04:46,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13714 to 13448. [2020-11-28 03:04:46,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13448 states. [2020-11-28 03:04:46,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13448 states to 13448 states and 18206 transitions. [2020-11-28 03:04:46,502 INFO L714 BuchiCegarLoop]: Abstraction has 13448 states and 18206 transitions. [2020-11-28 03:04:46,502 INFO L594 BuchiCegarLoop]: Abstraction has 13448 states and 18206 transitions. [2020-11-28 03:04:46,503 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-28 03:04:46,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13448 states and 18206 transitions. [2020-11-28 03:04:46,550 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 13382 [2020-11-28 03:04:46,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:46,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:46,551 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:46,551 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:46,551 INFO L794 eck$LassoCheckResult]: Stem: 108585#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 108346#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 108347#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 108690#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 108344#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108345#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108417#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108484#L311-1 assume !(0 == ~M_E~0); 108424#L433-1 assume !(0 == ~T1_E~0); 108425#L438-1 assume !(0 == ~T2_E~0); 108715#L443-1 assume !(0 == ~T3_E~0); 108737#L448-1 assume !(0 == ~E_M~0); 108631#L453-1 assume !(0 == ~E_1~0); 108632#L458-1 assume !(0 == ~E_2~0); 108660#L463-1 assume !(0 == ~E_3~0); 108522#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 108523#L212 assume !(1 == ~m_pc~0); 108711#L212-2 is_master_triggered_~__retres1~0 := 0; 108712#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 108411#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 108412#L535 assume !(0 != activate_threads_~tmp~1); 108673#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108579#L231 assume !(1 == ~t1_pc~0); 108565#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 108566#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 108581#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 108448#L543 assume !(0 != activate_threads_~tmp___0~0); 108415#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108416#L250 assume !(1 == ~t2_pc~0); 108738#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 108739#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108442#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 108443#L551 assume !(0 != activate_threads_~tmp___1~0); 108703#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108627#L269 assume !(1 == ~t3_pc~0); 108622#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 108623#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108558#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 108559#L559 assume !(0 != activate_threads_~tmp___2~0); 108707#L559-2 assume !(1 == ~M_E~0); 108708#L481-1 assume !(1 == ~T1_E~0); 108653#L486-1 assume !(1 == ~T2_E~0); 108654#L491-1 assume !(1 == ~T3_E~0); 108680#L496-1 assume !(1 == ~E_M~0); 108513#L501-1 assume !(1 == ~E_1~0); 108514#L506-1 assume !(1 == ~E_2~0); 108597#L511-1 assume !(1 == ~E_3~0); 108621#L682-1 assume !false; 112565#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 112505#L408 [2020-11-28 03:04:46,552 INFO L796 eck$LassoCheckResult]: Loop: 112505#L408 assume !false; 112562#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 112557#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 112553#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 112549#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 112545#L361 assume 0 != eval_~tmp~0; 112537#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 112531#L369 assume !(0 != eval_~tmp_ndt_1~0); 112524#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 112520#L383 assume !(0 != eval_~tmp_ndt_2~0); 112517#L380 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 110438#L397 assume !(0 != eval_~tmp_ndt_3~0); 112509#L394 assume !(0 == ~t3_st~0); 112505#L408 [2020-11-28 03:04:46,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:46,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2020-11-28 03:04:46,552 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:46,552 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842999224] [2020-11-28 03:04:46,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:46,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:46,564 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:46,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:46,612 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:46,625 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:46,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:46,626 INFO L82 PathProgramCache]: Analyzing trace with hash -87630703, now seen corresponding path program 1 times [2020-11-28 03:04:46,626 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:46,626 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466234071] [2020-11-28 03:04:46,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:46,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:46,629 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:46,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:46,631 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:46,635 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:46,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:46,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1831118959, now seen corresponding path program 1 times [2020-11-28 03:04:46,636 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:46,637 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102331237] [2020-11-28 03:04:46,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:46,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:04:46,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:04:46,666 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102331237] [2020-11-28 03:04:46,666 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:04:46,666 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:04:46,667 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452444049] [2020-11-28 03:04:46,780 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:04:46,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:04:46,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:04:46,781 INFO L87 Difference]: Start difference. First operand 13448 states and 18206 transitions. cyclomatic complexity: 4763 Second operand 3 states. [2020-11-28 03:04:46,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:04:46,909 INFO L93 Difference]: Finished difference Result 23410 states and 31520 transitions. [2020-11-28 03:04:46,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:04:46,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23410 states and 31520 transitions. [2020-11-28 03:04:47,017 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 23328 [2020-11-28 03:04:47,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23410 states to 23410 states and 31520 transitions. [2020-11-28 03:04:47,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23410 [2020-11-28 03:04:47,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23410 [2020-11-28 03:04:47,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23410 states and 31520 transitions. [2020-11-28 03:04:47,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:04:47,141 INFO L691 BuchiCegarLoop]: Abstraction has 23410 states and 31520 transitions. [2020-11-28 03:04:47,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23410 states and 31520 transitions. [2020-11-28 03:04:47,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23410 to 23242. [2020-11-28 03:04:47,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23242 states. [2020-11-28 03:04:47,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23242 states to 23242 states and 31352 transitions. [2020-11-28 03:04:47,646 INFO L714 BuchiCegarLoop]: Abstraction has 23242 states and 31352 transitions. [2020-11-28 03:04:47,646 INFO L594 BuchiCegarLoop]: Abstraction has 23242 states and 31352 transitions. [2020-11-28 03:04:47,647 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-11-28 03:04:47,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23242 states and 31352 transitions. [2020-11-28 03:04:47,743 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 23160 [2020-11-28 03:04:47,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:04:47,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:04:47,745 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:47,745 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:04:47,745 INFO L794 eck$LassoCheckResult]: Stem: 145459#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 145212#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 145213#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 145559#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 145210#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145211#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145284#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145358#L311-1 assume !(0 == ~M_E~0); 145292#L433-1 assume !(0 == ~T1_E~0); 145293#L438-1 assume !(0 == ~T2_E~0); 145588#L443-1 assume !(0 == ~T3_E~0); 145607#L448-1 assume !(0 == ~E_M~0); 145507#L453-1 assume !(0 == ~E_1~0); 145508#L458-1 assume !(0 == ~E_2~0); 145533#L463-1 assume !(0 == ~E_3~0); 145399#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 145400#L212 assume !(1 == ~m_pc~0); 145583#L212-2 is_master_triggered_~__retres1~0 := 0; 145584#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 145278#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 145279#L535 assume !(0 != activate_threads_~tmp~1); 145547#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 145454#L231 assume !(1 == ~t1_pc~0); 145440#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 145441#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 145456#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 145322#L543 assume !(0 != activate_threads_~tmp___0~0); 145282#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 145283#L250 assume !(1 == ~t2_pc~0); 145608#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 145609#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145311#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 145312#L551 assume !(0 != activate_threads_~tmp___1~0); 145575#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 145505#L269 assume !(1 == ~t3_pc~0); 145501#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 145502#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 145433#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 145434#L559 assume !(0 != activate_threads_~tmp___2~0); 145578#L559-2 assume !(1 == ~M_E~0); 145579#L481-1 assume !(1 == ~T1_E~0); 145528#L486-1 assume !(1 == ~T2_E~0); 145529#L491-1 assume !(1 == ~T3_E~0); 145551#L496-1 assume !(1 == ~E_M~0); 145389#L501-1 assume !(1 == ~E_1~0); 145390#L506-1 assume !(1 == ~E_2~0); 145471#L511-1 assume !(1 == ~E_3~0); 145500#L682-1 assume !false; 152680#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 152429#L408 [2020-11-28 03:04:47,745 INFO L796 eck$LassoCheckResult]: Loop: 152429#L408 assume !false; 152667#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 152650#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 152648#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 152649#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 152381#L361 assume 0 != eval_~tmp~0; 152382#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 152833#L369 assume !(0 != eval_~tmp_ndt_1~0); 152801#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 152797#L383 assume !(0 != eval_~tmp_ndt_2~0); 151806#L380 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 151804#L397 assume !(0 != eval_~tmp_ndt_3~0); 151805#L394 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 152427#L411 assume !(0 != eval_~tmp_ndt_4~0); 152429#L408 [2020-11-28 03:04:47,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:47,746 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2020-11-28 03:04:47,746 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:47,746 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980635661] [2020-11-28 03:04:47,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:47,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,754 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,761 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,770 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:47,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:47,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1578412349, now seen corresponding path program 1 times [2020-11-28 03:04:47,771 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:47,772 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997128393] [2020-11-28 03:04:47,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:47,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,775 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,778 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,780 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:47,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:04:47,781 INFO L82 PathProgramCache]: Analyzing trace with hash 930109727, now seen corresponding path program 1 times [2020-11-28 03:04:47,781 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:04:47,781 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952106567] [2020-11-28 03:04:47,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:04:47,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,789 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:04:47,798 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:04:47,810 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:04:47,916 WARN L193 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 33 [2020-11-28 03:04:49,194 WARN L193 SmtUtils]: Spent 1.22 s on a formula simplification. DAG size of input: 189 DAG size of output: 139 [2020-11-28 03:04:49,519 WARN L193 SmtUtils]: Spent 306.00 ms on a formula simplification that was a NOOP. DAG size: 121 [2020-11-28 03:04:49,572 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:04:49 BoogieIcfgContainer [2020-11-28 03:04:49,572 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 03:04:49,573 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 03:04:49,573 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 03:04:49,573 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 03:04:49,574 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:04:39" (3/4) ... [2020-11-28 03:04:49,576 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 03:04:49,642 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_96c44b71-9717-496f-b17f-8127710d77b6/bin/uautomizer/witness.graphml [2020-11-28 03:04:49,642 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 03:04:49,644 INFO L168 Benchmark]: Toolchain (without parser) took 11661.88 ms. Allocated memory was 136.3 MB in the beginning and 633.3 MB in the end (delta: 497.0 MB). Free memory was 105.6 MB in the beginning and 400.8 MB in the end (delta: -295.2 MB). Peak memory consumption was 201.4 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,645 INFO L168 Benchmark]: CDTParser took 0.26 ms. Allocated memory is still 88.1 MB. Free memory is still 46.2 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 03:04:49,646 INFO L168 Benchmark]: CACSL2BoogieTranslator took 453.48 ms. Allocated memory is still 136.3 MB. Free memory was 105.6 MB in the beginning and 108.1 MB in the end (delta: -2.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,646 INFO L168 Benchmark]: Boogie Procedure Inliner took 107.04 ms. Allocated memory is still 136.3 MB. Free memory was 107.7 MB in the beginning and 104.3 MB in the end (delta: 3.4 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,646 INFO L168 Benchmark]: Boogie Preprocessor took 84.94 ms. Allocated memory is still 136.3 MB. Free memory was 104.3 MB in the beginning and 101.0 MB in the end (delta: 3.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,647 INFO L168 Benchmark]: RCFGBuilder took 1269.78 ms. Allocated memory is still 136.3 MB. Free memory was 101.0 MB in the beginning and 72.6 MB in the end (delta: 28.4 MB). Peak memory consumption was 39.6 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,647 INFO L168 Benchmark]: BuchiAutomizer took 9666.96 ms. Allocated memory was 136.3 MB in the beginning and 633.3 MB in the end (delta: 497.0 MB). Free memory was 72.6 MB in the beginning and 405.0 MB in the end (delta: -332.4 MB). Peak memory consumption was 271.7 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,648 INFO L168 Benchmark]: Witness Printer took 69.04 ms. Allocated memory is still 633.3 MB. Free memory was 405.0 MB in the beginning and 400.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:04:49,649 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26 ms. Allocated memory is still 88.1 MB. Free memory is still 46.2 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 453.48 ms. Allocated memory is still 136.3 MB. Free memory was 105.6 MB in the beginning and 108.1 MB in the end (delta: -2.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 107.04 ms. Allocated memory is still 136.3 MB. Free memory was 107.7 MB in the beginning and 104.3 MB in the end (delta: 3.4 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 84.94 ms. Allocated memory is still 136.3 MB. Free memory was 104.3 MB in the beginning and 101.0 MB in the end (delta: 3.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1269.78 ms. Allocated memory is still 136.3 MB. Free memory was 101.0 MB in the beginning and 72.6 MB in the end (delta: 28.4 MB). Peak memory consumption was 39.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 9666.96 ms. Allocated memory was 136.3 MB in the beginning and 633.3 MB in the end (delta: 497.0 MB). Free memory was 72.6 MB in the beginning and 405.0 MB in the end (delta: -332.4 MB). Peak memory consumption was 271.7 MB. Max. memory is 16.1 GB. * Witness Printer took 69.04 ms. Allocated memory is still 633.3 MB. Free memory was 405.0 MB in the beginning and 400.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 23242 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 9.5s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 1.0s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1.7s AutomataMinimizationTime, 18 MinimizatonAttempts, 7343 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.1s. Biggest automaton had 23242 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 8791 SDtfs, 11482 SDslu, 8678 SDs, 0 SdLazy, 527 SolverSat, 199 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=28549} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=28549, tmp=1, __retres1=0, kernel_st=1, t2_st=0, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@618086f3=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c5a1e09=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@203d431a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44042ab1=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@43fb6618=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7749522=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60871803=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@29e10dd6=0, NULL=28550, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4348e60a=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@159335e6=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, NULL=28552, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=28551, t2_i=1, t3_i=1, m_i=1, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d7ff7b8=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int M_E = 2; [L29] int T1_E = 2; [L30] int T2_E = 2; [L31] int T3_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L34] int E_2 = 2; [L35] int E_3 = 2; [L41] int token ; [L43] int local ; [L727] int __retres1 ; [L640] m_i = 1 [L641] t1_i = 1 [L642] t2_i = 1 [L643] t3_i = 1 [L668] int kernel_st ; [L669] int tmp ; [L670] int tmp___0 ; [L674] kernel_st = 0 [L296] COND TRUE m_i == 1 [L297] m_st = 0 [L301] COND TRUE t1_i == 1 [L302] t1_st = 0 [L306] COND TRUE t2_i == 1 [L307] t2_st = 0 [L311] COND TRUE t3_i == 1 [L312] t3_st = 0 [L433] COND FALSE !(M_E == 0) [L438] COND FALSE !(T1_E == 0) [L443] COND FALSE !(T2_E == 0) [L448] COND FALSE !(T3_E == 0) [L453] COND FALSE !(E_M == 0) [L458] COND FALSE !(E_1 == 0) [L463] COND FALSE !(E_2 == 0) [L468] COND FALSE !(E_3 == 0) [L526] int tmp ; [L527] int tmp___0 ; [L528] int tmp___1 ; [L529] int tmp___2 ; [L209] int __retres1 ; [L212] COND FALSE !(m_pc == 1) [L222] __retres1 = 0 [L224] return (__retres1); [L533] tmp = is_master_triggered() [L535] COND FALSE !(\read(tmp)) [L228] int __retres1 ; [L231] COND FALSE !(t1_pc == 1) [L241] __retres1 = 0 [L243] return (__retres1); [L541] tmp___0 = is_transmit1_triggered() [L543] COND FALSE !(\read(tmp___0)) [L247] int __retres1 ; [L250] COND FALSE !(t2_pc == 1) [L260] __retres1 = 0 [L262] return (__retres1); [L549] tmp___1 = is_transmit2_triggered() [L551] COND FALSE !(\read(tmp___1)) [L266] int __retres1 ; [L269] COND FALSE !(t3_pc == 1) [L279] __retres1 = 0 [L281] return (__retres1); [L557] tmp___2 = is_transmit3_triggered() [L559] COND FALSE !(\read(tmp___2)) [L481] COND FALSE !(M_E == 1) [L486] COND FALSE !(T1_E == 1) [L491] COND FALSE !(T2_E == 1) [L496] COND FALSE !(T3_E == 1) [L501] COND FALSE !(E_M == 1) [L506] COND FALSE !(E_1 == 1) [L511] COND FALSE !(E_2 == 1) [L516] COND FALSE !(E_3 == 1) [L682] COND TRUE 1 [L685] kernel_st = 1 [L352] int tmp ; Loop: [L356] COND TRUE 1 [L321] int __retres1 ; [L324] COND TRUE m_st == 0 [L325] __retres1 = 1 [L347] return (__retres1); [L359] tmp = exists_runnable_thread() [L361] COND TRUE \read(tmp) [L366] COND TRUE m_st == 0 [L367] int tmp_ndt_1; [L368] tmp_ndt_1 = __VERIFIER_nondet_int() [L369] COND FALSE !(\read(tmp_ndt_1)) [L380] COND TRUE t1_st == 0 [L381] int tmp_ndt_2; [L382] tmp_ndt_2 = __VERIFIER_nondet_int() [L383] COND FALSE !(\read(tmp_ndt_2)) [L394] COND TRUE t2_st == 0 [L395] int tmp_ndt_3; [L396] tmp_ndt_3 = __VERIFIER_nondet_int() [L397] COND FALSE !(\read(tmp_ndt_3)) [L408] COND TRUE t3_st == 0 [L409] int tmp_ndt_4; [L410] tmp_ndt_4 = __VERIFIER_nondet_int() [L411] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...