./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6752fd2bdc3c2f1062040263247aacca41c7fdba ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 03:06:14,477 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 03:06:14,482 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 03:06:14,547 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 03:06:14,564 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 03:06:14,566 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 03:06:14,582 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 03:06:14,585 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 03:06:14,587 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 03:06:14,589 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 03:06:14,590 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 03:06:14,592 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 03:06:14,594 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 03:06:14,595 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 03:06:14,597 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 03:06:14,599 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 03:06:14,601 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 03:06:14,602 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 03:06:14,605 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 03:06:14,608 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 03:06:14,611 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 03:06:14,615 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 03:06:14,617 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 03:06:14,620 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 03:06:14,627 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 03:06:14,633 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 03:06:14,633 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 03:06:14,635 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 03:06:14,637 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 03:06:14,638 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 03:06:14,639 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 03:06:14,641 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 03:06:14,643 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 03:06:14,645 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 03:06:14,647 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 03:06:14,647 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 03:06:14,648 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 03:06:14,649 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 03:06:14,649 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 03:06:14,650 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 03:06:14,651 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 03:06:14,658 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 03:06:14,709 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 03:06:14,709 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 03:06:14,710 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 03:06:14,710 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 03:06:14,711 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 03:06:14,711 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 03:06:14,711 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 03:06:14,711 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 03:06:14,711 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 03:06:14,711 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 03:06:14,712 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 03:06:14,712 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 03:06:14,712 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 03:06:14,712 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 03:06:14,713 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 03:06:14,718 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 03:06:14,718 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 03:06:14,718 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 03:06:14,719 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 03:06:14,719 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 03:06:14,719 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 03:06:14,719 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 03:06:14,720 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 03:06:14,720 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 03:06:14,720 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 03:06:14,721 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 03:06:14,721 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 03:06:14,721 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 03:06:14,722 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 03:06:14,722 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 03:06:14,722 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 03:06:14,722 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 03:06:14,724 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 03:06:14,724 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6752fd2bdc3c2f1062040263247aacca41c7fdba [2020-11-28 03:06:15,018 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 03:06:15,056 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 03:06:15,063 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 03:06:15,065 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 03:06:15,066 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 03:06:15,067 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2020-11-28 03:06:15,161 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/data/56e97e98b/ee3a1b94f3bd4bf2a370c4a6408e47c1/FLAG31d2e645e [2020-11-28 03:06:15,823 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 03:06:15,831 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2020-11-28 03:06:15,842 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/data/56e97e98b/ee3a1b94f3bd4bf2a370c4a6408e47c1/FLAG31d2e645e [2020-11-28 03:06:16,152 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/data/56e97e98b/ee3a1b94f3bd4bf2a370c4a6408e47c1 [2020-11-28 03:06:16,154 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 03:06:16,156 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 03:06:16,158 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 03:06:16,159 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 03:06:16,163 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 03:06:16,165 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,167 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@32afd8e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16, skipping insertion in model container [2020-11-28 03:06:16,168 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,177 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 03:06:16,229 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 03:06:16,492 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:06:16,506 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 03:06:16,564 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:06:16,602 INFO L208 MainTranslator]: Completed translation [2020-11-28 03:06:16,603 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16 WrapperNode [2020-11-28 03:06:16,603 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 03:06:16,604 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 03:06:16,605 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 03:06:16,605 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 03:06:16,612 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,623 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,678 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 03:06:16,679 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 03:06:16,679 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 03:06:16,679 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 03:06:16,690 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,690 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,698 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,699 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,730 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,747 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,752 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... [2020-11-28 03:06:16,761 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 03:06:16,762 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 03:06:16,763 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 03:06:16,763 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 03:06:16,777 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 03:06:16,894 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 03:06:16,894 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 03:06:16,895 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 03:06:16,896 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 03:06:18,355 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 03:06:18,356 INFO L298 CfgBuilder]: Removed 132 assume(true) statements. [2020-11-28 03:06:18,358 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:06:18 BoogieIcfgContainer [2020-11-28 03:06:18,358 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 03:06:18,359 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 03:06:18,359 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 03:06:18,365 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 03:06:18,365 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:06:18,366 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:06:16" (1/3) ... [2020-11-28 03:06:18,367 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e10adde and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:06:18, skipping insertion in model container [2020-11-28 03:06:18,367 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:06:18,367 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:06:16" (2/3) ... [2020-11-28 03:06:18,369 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e10adde and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:06:18, skipping insertion in model container [2020-11-28 03:06:18,369 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:06:18,369 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:06:18" (3/3) ... [2020-11-28 03:06:18,371 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2020-11-28 03:06:18,436 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 03:06:18,436 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 03:06:18,436 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 03:06:18,436 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 03:06:18,436 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 03:06:18,437 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 03:06:18,437 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 03:06:18,437 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 03:06:18,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 309 states. [2020-11-28 03:06:18,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 254 [2020-11-28 03:06:18,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:18,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:18,534 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:18,534 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:18,534 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 03:06:18,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 309 states. [2020-11-28 03:06:18,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 254 [2020-11-28 03:06:18,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:18,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:18,559 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:18,559 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:18,568 INFO L794 eck$LassoCheckResult]: Stem: 87#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 11#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 74#L633true havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 164#L277true assume !(1 == ~m_i~0);~m_st~0 := 2; 58#L284-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 242#L289-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 253#L294-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 163#L299-1true assume !(0 == ~M_E~0); 230#L421-1true assume !(0 == ~T1_E~0); 260#L426-1true assume !(0 == ~T2_E~0); 151#L431-1true assume !(0 == ~T3_E~0); 174#L436-1true assume !(0 == ~E_M~0); 192#L441-1true assume 0 == ~E_1~0;~E_1~0 := 1; 67#L446-1true assume !(0 == ~E_2~0); 104#L451-1true assume !(0 == ~E_3~0); 140#L456-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 301#L200true assume 1 == ~m_pc~0; 217#L201true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 302#L211true is_master_triggered_#res := is_master_triggered_~__retres1~0; 218#L212true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 85#L523true assume !(0 != activate_threads_~tmp~1); 63#L523-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6#L219true assume !(1 == ~t1_pc~0); 22#L219-2true is_transmit1_triggered_~__retres1~1 := 0; 7#L230true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 83#L231true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 243#L531true assume !(0 != activate_threads_~tmp___0~0); 245#L531-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 183#L238true assume 1 == ~t2_pc~0; 250#L239true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 184#L249true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 251#L250true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 122#L539true assume !(0 != activate_threads_~tmp___1~0); 101#L539-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52#L257true assume 1 == ~t3_pc~0; 143#L258true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 54#L268true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 144#L269true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 291#L547true assume !(0 != activate_threads_~tmp___2~0); 298#L547-2true assume 1 == ~M_E~0;~M_E~0 := 2; 170#L469-1true assume !(1 == ~T1_E~0); 190#L474-1true assume !(1 == ~T2_E~0); 65#L479-1true assume !(1 == ~T3_E~0); 102#L484-1true assume !(1 == ~E_M~0); 137#L489-1true assume !(1 == ~E_1~0); 27#L494-1true assume !(1 == ~E_2~0); 53#L499-1true assume !(1 == ~E_3~0); 38#L670-1true [2020-11-28 03:06:18,570 INFO L796 eck$LassoCheckResult]: Loop: 38#L670-1true assume !false; 132#L671true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 107#L396true assume !true; 55#L411true start_simulation_~kernel_st~0 := 2; 304#L277-1true start_simulation_~kernel_st~0 := 3; 232#L421-2true assume 0 == ~M_E~0;~M_E~0 := 1; 234#L421-4true assume !(0 == ~T1_E~0); 272#L426-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 155#L431-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 181#L436-3true assume 0 == ~E_M~0;~E_M~0 := 1; 195#L441-3true assume 0 == ~E_1~0;~E_1~0 := 1; 71#L446-3true assume 0 == ~E_2~0;~E_2~0 := 1; 116#L451-3true assume 0 == ~E_3~0;~E_3~0 := 1; 149#L456-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 284#L200-15true assume !(1 == ~m_pc~0); 277#L200-17true is_master_triggered_~__retres1~0 := 0; 311#L211-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 203#L212-5true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 201#L523-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 202#L523-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141#L219-15true assume !(1 == ~t1_pc~0); 134#L219-17true is_transmit1_triggered_~__retres1~1 := 0; 15#L230-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93#L231-5true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 204#L531-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 209#L531-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162#L238-15true assume 1 == ~t2_pc~0; 261#L239-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 161#L249-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 263#L250-5true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 84#L539-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86#L539-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8#L257-15true assume 1 == ~t3_pc~0; 113#L258-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32#L268-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 115#L269-5true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 241#L547-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 244#L547-17true assume 1 == ~M_E~0;~M_E~0 := 2; 178#L469-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 193#L474-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 69#L479-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 111#L484-3true assume !(1 == ~E_M~0); 146#L489-3true assume 1 == ~E_1~0;~E_1~0 := 2; 34#L494-3true assume 1 == ~E_2~0;~E_2~0 := 2; 56#L499-3true assume 1 == ~E_3~0;~E_3~0 := 2; 216#L504-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 46#L312-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45#L334-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 125#L335-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 188#L689true assume !(0 == start_simulation_~tmp~3); 189#L689-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 48#L312-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 47#L334-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 128#L335-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 73#L644true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 169#L651true stop_simulation_#res := stop_simulation_~__retres2~0; 257#L652true start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 220#L702true assume !(0 != start_simulation_~tmp___0~1); 38#L670-1true [2020-11-28 03:06:18,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:18,577 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2020-11-28 03:06:18,587 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:18,588 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958100622] [2020-11-28 03:06:18,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:18,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:18,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:18,846 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958100622] [2020-11-28 03:06:18,847 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:18,847 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:18,861 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407154634] [2020-11-28 03:06:18,867 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:18,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:18,868 INFO L82 PathProgramCache]: Analyzing trace with hash 1443338383, now seen corresponding path program 1 times [2020-11-28 03:06:18,869 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:18,869 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415975209] [2020-11-28 03:06:18,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:18,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:18,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:18,895 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415975209] [2020-11-28 03:06:18,896 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:18,896 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:06:18,896 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096199718] [2020-11-28 03:06:18,898 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:18,899 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:18,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:18,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:18,918 INFO L87 Difference]: Start difference. First operand 309 states. Second operand 3 states. [2020-11-28 03:06:18,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:18,990 INFO L93 Difference]: Finished difference Result 308 states and 466 transitions. [2020-11-28 03:06:18,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:18,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 466 transitions. [2020-11-28 03:06:19,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 303 states and 461 transitions. [2020-11-28 03:06:19,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2020-11-28 03:06:19,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2020-11-28 03:06:19,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 461 transitions. [2020-11-28 03:06:19,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:19,036 INFO L691 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2020-11-28 03:06:19,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 461 transitions. [2020-11-28 03:06:19,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2020-11-28 03:06:19,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2020-11-28 03:06:19,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 461 transitions. [2020-11-28 03:06:19,123 INFO L714 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2020-11-28 03:06:19,123 INFO L594 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2020-11-28 03:06:19,123 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 03:06:19,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 461 transitions. [2020-11-28 03:06:19,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:19,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:19,130 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,131 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,131 INFO L794 eck$LassoCheckResult]: Stem: 760#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 644#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 645#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 748#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 724#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 725#L289-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 917#L294-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 833#L299-1 assume !(0 == ~M_E~0); 834#L421-1 assume !(0 == ~T1_E~0); 908#L426-1 assume !(0 == ~T2_E~0); 811#L431-1 assume !(0 == ~T3_E~0); 812#L436-1 assume !(0 == ~E_M~0); 848#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 739#L446-1 assume !(0 == ~E_2~0); 740#L451-1 assume !(0 == ~E_3~0); 781#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 804#L200 assume 1 == ~m_pc~0; 893#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 894#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 897#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 758#L523 assume !(0 != activate_threads_~tmp~1); 734#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 633#L219 assume !(1 == ~t1_pc~0); 634#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 636#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 637#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 757#L531 assume !(0 != activate_threads_~tmp___0~0); 918#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 859#L238 assume 1 == ~t2_pc~0; 860#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 855#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 861#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 795#L539 assume !(0 != activate_threads_~tmp___1~0); 777#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 718#L257 assume 1 == ~t3_pc~0; 719#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 715#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 720#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 806#L547 assume !(0 != activate_threads_~tmp___2~0); 928#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 843#L469-1 assume !(1 == ~T1_E~0); 844#L474-1 assume !(1 == ~T2_E~0); 735#L479-1 assume !(1 == ~T3_E~0); 736#L484-1 assume !(1 == ~E_M~0); 778#L489-1 assume !(1 == ~E_1~0); 677#L494-1 assume !(1 == ~E_2~0); 678#L499-1 assume !(1 == ~E_3~0); 696#L670-1 [2020-11-28 03:06:19,132 INFO L796 eck$LassoCheckResult]: Loop: 696#L670-1 assume !false; 697#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 750#L396 assume !false; 701#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 702#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 703#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 704#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 810#L349 assume !(0 != eval_~tmp~0); 721#L411 start_simulation_~kernel_st~0 := 2; 722#L277-1 start_simulation_~kernel_st~0 := 3; 910#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 911#L421-4 assume !(0 == ~T1_E~0); 913#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 819#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 820#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 857#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 743#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 744#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 791#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 809#L200-15 assume 1 == ~m_pc~0; 905#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 907#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 872#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 870#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 871#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 805#L219-15 assume 1 == ~t1_pc~0; 766#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 652#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 653#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 768#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 873#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 830#L238-15 assume 1 == ~t2_pc~0; 832#L239-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 828#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 829#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 755#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 756#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 638#L257-15 assume !(1 == ~t3_pc~0); 631#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 632#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 685#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 789#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 916#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 852#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 853#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 741#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 742#L484-3 assume !(1 == ~E_M~0); 785#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 687#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 688#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 723#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 708#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 706#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 707#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 798#L689 assume !(0 == start_simulation_~tmp~3); 641#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 712#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 710#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 711#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 746#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 747#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 842#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 898#L702 assume !(0 != start_simulation_~tmp___0~1); 696#L670-1 [2020-11-28 03:06:19,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,133 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2020-11-28 03:06:19,133 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,133 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16317484] [2020-11-28 03:06:19,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,195 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16317484] [2020-11-28 03:06:19,195 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,195 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,196 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304332710] [2020-11-28 03:06:19,196 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:19,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1646593089, now seen corresponding path program 1 times [2020-11-28 03:06:19,198 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,198 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261408808] [2020-11-28 03:06:19,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,303 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261408808] [2020-11-28 03:06:19,303 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,303 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,304 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978975305] [2020-11-28 03:06:19,304 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:19,305 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:19,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:19,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:19,306 INFO L87 Difference]: Start difference. First operand 303 states and 461 transitions. cyclomatic complexity: 159 Second operand 3 states. [2020-11-28 03:06:19,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:19,327 INFO L93 Difference]: Finished difference Result 303 states and 460 transitions. [2020-11-28 03:06:19,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:19,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 460 transitions. [2020-11-28 03:06:19,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 460 transitions. [2020-11-28 03:06:19,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2020-11-28 03:06:19,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2020-11-28 03:06:19,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 460 transitions. [2020-11-28 03:06:19,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:19,344 INFO L691 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2020-11-28 03:06:19,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 460 transitions. [2020-11-28 03:06:19,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2020-11-28 03:06:19,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2020-11-28 03:06:19,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 460 transitions. [2020-11-28 03:06:19,366 INFO L714 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2020-11-28 03:06:19,366 INFO L594 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2020-11-28 03:06:19,366 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 03:06:19,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 460 transitions. [2020-11-28 03:06:19,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:19,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:19,378 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,378 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,381 INFO L794 eck$LassoCheckResult]: Stem: 1373#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1257#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1258#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1361#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 1337#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1338#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1530#L294-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1446#L299-1 assume !(0 == ~M_E~0); 1447#L421-1 assume !(0 == ~T1_E~0); 1521#L426-1 assume !(0 == ~T2_E~0); 1427#L431-1 assume !(0 == ~T3_E~0); 1428#L436-1 assume !(0 == ~E_M~0); 1461#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1352#L446-1 assume !(0 == ~E_2~0); 1353#L451-1 assume !(0 == ~E_3~0); 1394#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1418#L200 assume 1 == ~m_pc~0; 1506#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1507#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1510#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1371#L523 assume !(0 != activate_threads_~tmp~1); 1347#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1246#L219 assume !(1 == ~t1_pc~0); 1247#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 1249#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1250#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1370#L531 assume !(0 != activate_threads_~tmp___0~0); 1531#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1472#L238 assume 1 == ~t2_pc~0; 1473#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1468#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1474#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1408#L539 assume !(0 != activate_threads_~tmp___1~0); 1390#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1331#L257 assume 1 == ~t3_pc~0; 1332#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1328#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1333#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1419#L547 assume !(0 != activate_threads_~tmp___2~0); 1541#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1456#L469-1 assume !(1 == ~T1_E~0); 1457#L474-1 assume !(1 == ~T2_E~0); 1348#L479-1 assume !(1 == ~T3_E~0); 1349#L484-1 assume !(1 == ~E_M~0); 1391#L489-1 assume !(1 == ~E_1~0); 1290#L494-1 assume !(1 == ~E_2~0); 1291#L499-1 assume !(1 == ~E_3~0); 1309#L670-1 [2020-11-28 03:06:19,388 INFO L796 eck$LassoCheckResult]: Loop: 1309#L670-1 assume !false; 1310#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1363#L396 assume !false; 1314#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1315#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1316#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1317#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1423#L349 assume !(0 != eval_~tmp~0); 1334#L411 start_simulation_~kernel_st~0 := 2; 1335#L277-1 start_simulation_~kernel_st~0 := 3; 1523#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1524#L421-4 assume !(0 == ~T1_E~0); 1526#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1432#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1433#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1470#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1356#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1357#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1404#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1420#L200-15 assume 1 == ~m_pc~0; 1518#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1520#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1485#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1483#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1484#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1416#L219-15 assume 1 == ~t1_pc~0; 1379#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1265#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1266#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1381#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1486#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1443#L238-15 assume !(1 == ~t2_pc~0); 1444#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 1441#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1442#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1368#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1369#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1251#L257-15 assume 1 == ~t3_pc~0; 1252#L258-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1245#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1298#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1402#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1529#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1465#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1466#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1354#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1355#L484-3 assume !(1 == ~E_M~0); 1398#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1300#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1301#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1336#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1321#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1319#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1320#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1411#L689 assume !(0 == start_simulation_~tmp~3); 1254#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1325#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1323#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1324#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1359#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1360#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 1455#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1511#L702 assume !(0 != start_simulation_~tmp___0~1); 1309#L670-1 [2020-11-28 03:06:19,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,390 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2020-11-28 03:06:19,390 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,391 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954419364] [2020-11-28 03:06:19,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,491 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954419364] [2020-11-28 03:06:19,491 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,491 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,492 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210628837] [2020-11-28 03:06:19,492 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:19,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1926783233, now seen corresponding path program 1 times [2020-11-28 03:06:19,493 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,493 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132036300] [2020-11-28 03:06:19,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,591 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132036300] [2020-11-28 03:06:19,591 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,592 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,592 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710400654] [2020-11-28 03:06:19,592 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:19,593 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:19,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:19,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:19,595 INFO L87 Difference]: Start difference. First operand 303 states and 460 transitions. cyclomatic complexity: 158 Second operand 3 states. [2020-11-28 03:06:19,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:19,609 INFO L93 Difference]: Finished difference Result 303 states and 459 transitions. [2020-11-28 03:06:19,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:19,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 459 transitions. [2020-11-28 03:06:19,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 459 transitions. [2020-11-28 03:06:19,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2020-11-28 03:06:19,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2020-11-28 03:06:19,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2020-11-28 03:06:19,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:19,626 INFO L691 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2020-11-28 03:06:19,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2020-11-28 03:06:19,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2020-11-28 03:06:19,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2020-11-28 03:06:19,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2020-11-28 03:06:19,649 INFO L714 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2020-11-28 03:06:19,649 INFO L594 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2020-11-28 03:06:19,649 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 03:06:19,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2020-11-28 03:06:19,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2020-11-28 03:06:19,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:19,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:19,658 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,658 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:19,661 INFO L794 eck$LassoCheckResult]: Stem: 1985#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1870#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1871#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1974#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 1950#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1951#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2143#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2059#L299-1 assume !(0 == ~M_E~0); 2060#L421-1 assume !(0 == ~T1_E~0); 2134#L426-1 assume !(0 == ~T2_E~0); 2037#L431-1 assume !(0 == ~T3_E~0); 2038#L436-1 assume !(0 == ~E_M~0); 2074#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1965#L446-1 assume !(0 == ~E_2~0); 1966#L451-1 assume !(0 == ~E_3~0); 2007#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2029#L200 assume 1 == ~m_pc~0; 2119#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2120#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2122#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1984#L523 assume !(0 != activate_threads_~tmp~1); 1958#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1859#L219 assume !(1 == ~t1_pc~0); 1860#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 1862#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1863#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1981#L531 assume !(0 != activate_threads_~tmp___0~0); 2144#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2085#L238 assume 1 == ~t2_pc~0; 2086#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2081#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2087#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2021#L539 assume !(0 != activate_threads_~tmp___1~0); 2003#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1944#L257 assume 1 == ~t3_pc~0; 1945#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1941#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1946#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2032#L547 assume !(0 != activate_threads_~tmp___2~0); 2154#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2069#L469-1 assume !(1 == ~T1_E~0); 2070#L474-1 assume !(1 == ~T2_E~0); 1961#L479-1 assume !(1 == ~T3_E~0); 1962#L484-1 assume !(1 == ~E_M~0); 2004#L489-1 assume !(1 == ~E_1~0); 1902#L494-1 assume !(1 == ~E_2~0); 1903#L499-1 assume !(1 == ~E_3~0); 1921#L670-1 [2020-11-28 03:06:19,662 INFO L796 eck$LassoCheckResult]: Loop: 1921#L670-1 assume !false; 1922#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1976#L396 assume !false; 1927#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1928#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1929#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1930#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2036#L349 assume !(0 != eval_~tmp~0); 1947#L411 start_simulation_~kernel_st~0 := 2; 1948#L277-1 start_simulation_~kernel_st~0 := 3; 2136#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2137#L421-4 assume !(0 == ~T1_E~0); 2139#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2045#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2046#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2083#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1969#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1970#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2017#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2035#L200-15 assume 1 == ~m_pc~0; 2131#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2133#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2098#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2096#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2097#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2030#L219-15 assume 1 == ~t1_pc~0; 1992#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1878#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1879#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1994#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2099#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2056#L238-15 assume !(1 == ~t2_pc~0); 2057#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 2054#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2055#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1982#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1983#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1864#L257-15 assume !(1 == ~t3_pc~0); 1857#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 1858#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1911#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2016#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2142#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2078#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2079#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1967#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1968#L484-3 assume !(1 == ~E_M~0); 2014#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1913#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1914#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1949#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1934#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1932#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1933#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2024#L689 assume !(0 == start_simulation_~tmp~3); 1867#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1938#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1936#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1937#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1972#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1973#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 2068#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2124#L702 assume !(0 != start_simulation_~tmp___0~1); 1921#L670-1 [2020-11-28 03:06:19,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2020-11-28 03:06:19,664 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,664 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023239161] [2020-11-28 03:06:19,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,788 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023239161] [2020-11-28 03:06:19,788 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,788 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,789 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313704262] [2020-11-28 03:06:19,789 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:19,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:19,790 INFO L82 PathProgramCache]: Analyzing trace with hash -1729399584, now seen corresponding path program 1 times [2020-11-28 03:06:19,790 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:19,790 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931038480] [2020-11-28 03:06:19,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:19,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:19,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:19,850 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931038480] [2020-11-28 03:06:19,850 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:19,850 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:19,851 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889935223] [2020-11-28 03:06:19,851 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:19,851 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:19,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:06:19,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:06:19,852 INFO L87 Difference]: Start difference. First operand 303 states and 459 transitions. cyclomatic complexity: 157 Second operand 4 states. [2020-11-28 03:06:20,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:20,027 INFO L93 Difference]: Finished difference Result 498 states and 751 transitions. [2020-11-28 03:06:20,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:06:20,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 751 transitions. [2020-11-28 03:06:20,035 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2020-11-28 03:06:20,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 751 transitions. [2020-11-28 03:06:20,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2020-11-28 03:06:20,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2020-11-28 03:06:20,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 751 transitions. [2020-11-28 03:06:20,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:20,044 INFO L691 BuchiCegarLoop]: Abstraction has 498 states and 751 transitions. [2020-11-28 03:06:20,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 751 transitions. [2020-11-28 03:06:20,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 493. [2020-11-28 03:06:20,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2020-11-28 03:06:20,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 744 transitions. [2020-11-28 03:06:20,064 INFO L714 BuchiCegarLoop]: Abstraction has 493 states and 744 transitions. [2020-11-28 03:06:20,067 INFO L594 BuchiCegarLoop]: Abstraction has 493 states and 744 transitions. [2020-11-28 03:06:20,068 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 03:06:20,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 744 transitions. [2020-11-28 03:06:20,074 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2020-11-28 03:06:20,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:20,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:20,079 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,079 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,079 INFO L794 eck$LassoCheckResult]: Stem: 2799#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2681#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2682#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2788#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 2764#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2765#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2964#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2878#L299-1 assume !(0 == ~M_E~0); 2879#L421-1 assume !(0 == ~T1_E~0); 2954#L426-1 assume !(0 == ~T2_E~0); 2856#L431-1 assume !(0 == ~T3_E~0); 2857#L436-1 assume !(0 == ~E_M~0); 2893#L441-1 assume !(0 == ~E_1~0); 2779#L446-1 assume !(0 == ~E_2~0); 2780#L451-1 assume !(0 == ~E_3~0); 2821#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2847#L200 assume 1 == ~m_pc~0; 2939#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2940#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2942#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2798#L523 assume !(0 != activate_threads_~tmp~1); 2772#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2670#L219 assume !(1 == ~t1_pc~0); 2671#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 2673#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2674#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2795#L531 assume !(0 != activate_threads_~tmp___0~0); 2965#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2904#L238 assume 1 == ~t2_pc~0; 2905#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2900#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2906#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2837#L539 assume !(0 != activate_threads_~tmp___1~0); 2817#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2757#L257 assume 1 == ~t3_pc~0; 2758#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2754#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2760#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2850#L547 assume !(0 != activate_threads_~tmp___2~0); 2980#L547-2 assume !(1 == ~M_E~0); 2888#L469-1 assume !(1 == ~T1_E~0); 2889#L474-1 assume !(1 == ~T2_E~0); 2775#L479-1 assume !(1 == ~T3_E~0); 2776#L484-1 assume !(1 == ~E_M~0); 2818#L489-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2845#L494-1 assume !(1 == ~E_2~0); 2759#L499-1 assume !(1 == ~E_3~0); 2732#L670-1 [2020-11-28 03:06:20,080 INFO L796 eck$LassoCheckResult]: Loop: 2732#L670-1 assume !false; 2733#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2824#L396 assume !false; 2825#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2987#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2740#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2741#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2976#L349 assume !(0 != eval_~tmp~0); 2977#L411 start_simulation_~kernel_st~0 := 2; 2982#L277-1 start_simulation_~kernel_st~0 := 3; 2983#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2959#L421-4 assume !(0 == ~T1_E~0); 2960#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2864#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2865#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2902#L441-3 assume !(0 == ~E_1~0); 2783#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2784#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2833#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2853#L200-15 assume 1 == ~m_pc~0; 2951#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2953#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2918#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2916#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2917#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2848#L219-15 assume 1 == ~t1_pc~0; 2806#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2689#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2690#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2808#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2919#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2875#L238-15 assume !(1 == ~t2_pc~0); 2876#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 2873#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2874#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2796#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2797#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2675#L257-15 assume 1 == ~t3_pc~0; 2676#L258-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2669#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2722#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2832#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2963#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2897#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2898#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2781#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2782#L484-3 assume !(1 == ~E_M~0); 2830#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2724#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2725#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2763#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2746#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2747#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3012#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2909#L689 assume !(0 == start_simulation_~tmp~3); 2678#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2751#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2749#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2750#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 2786#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2787#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 2887#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2944#L702 assume !(0 != start_simulation_~tmp___0~1); 2732#L670-1 [2020-11-28 03:06:20,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,081 INFO L82 PathProgramCache]: Analyzing trace with hash 180145436, now seen corresponding path program 1 times [2020-11-28 03:06:20,088 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,088 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351832085] [2020-11-28 03:06:20,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,165 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351832085] [2020-11-28 03:06:20,165 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,165 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:06:20,165 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046731326] [2020-11-28 03:06:20,166 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:20,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,167 INFO L82 PathProgramCache]: Analyzing trace with hash -429022017, now seen corresponding path program 1 times [2020-11-28 03:06:20,167 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,167 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449938807] [2020-11-28 03:06:20,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,222 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449938807] [2020-11-28 03:06:20,223 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,223 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:20,224 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613959654] [2020-11-28 03:06:20,225 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:20,226 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:20,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:20,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:20,232 INFO L87 Difference]: Start difference. First operand 493 states and 744 transitions. cyclomatic complexity: 253 Second operand 3 states. [2020-11-28 03:06:20,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:20,321 INFO L93 Difference]: Finished difference Result 732 states and 1085 transitions. [2020-11-28 03:06:20,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:20,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 732 states and 1085 transitions. [2020-11-28 03:06:20,331 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 674 [2020-11-28 03:06:20,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 732 states to 732 states and 1085 transitions. [2020-11-28 03:06:20,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 732 [2020-11-28 03:06:20,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 732 [2020-11-28 03:06:20,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 732 states and 1085 transitions. [2020-11-28 03:06:20,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:20,344 INFO L691 BuchiCegarLoop]: Abstraction has 732 states and 1085 transitions. [2020-11-28 03:06:20,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 732 states and 1085 transitions. [2020-11-28 03:06:20,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 732 to 706. [2020-11-28 03:06:20,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 706 states. [2020-11-28 03:06:20,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 1049 transitions. [2020-11-28 03:06:20,365 INFO L714 BuchiCegarLoop]: Abstraction has 706 states and 1049 transitions. [2020-11-28 03:06:20,365 INFO L594 BuchiCegarLoop]: Abstraction has 706 states and 1049 transitions. [2020-11-28 03:06:20,365 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 03:06:20,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 706 states and 1049 transitions. [2020-11-28 03:06:20,373 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 648 [2020-11-28 03:06:20,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:20,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:20,395 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,395 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,395 INFO L794 eck$LassoCheckResult]: Stem: 4028#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3913#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3914#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4017#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 3993#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3994#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4191#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4107#L299-1 assume !(0 == ~M_E~0); 4108#L421-1 assume !(0 == ~T1_E~0); 4179#L426-1 assume !(0 == ~T2_E~0); 4083#L431-1 assume !(0 == ~T3_E~0); 4084#L436-1 assume !(0 == ~E_M~0); 4122#L441-1 assume !(0 == ~E_1~0); 4008#L446-1 assume !(0 == ~E_2~0); 4009#L451-1 assume !(0 == ~E_3~0); 4050#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4075#L200 assume !(1 == ~m_pc~0); 4215#L200-2 is_master_triggered_~__retres1~0 := 0; 4216#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4167#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4027#L523 assume !(0 != activate_threads_~tmp~1); 4001#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3902#L219 assume !(1 == ~t1_pc~0); 3903#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 3905#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3906#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4024#L531 assume !(0 != activate_threads_~tmp___0~0); 4192#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4133#L238 assume 1 == ~t2_pc~0; 4134#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4129#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4135#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4066#L539 assume !(0 != activate_threads_~tmp___1~0); 4046#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3987#L257 assume 1 == ~t3_pc~0; 3988#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3984#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3989#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4078#L547 assume !(0 != activate_threads_~tmp___2~0); 4214#L547-2 assume !(1 == ~M_E~0); 4218#L469-1 assume !(1 == ~T1_E~0); 4478#L474-1 assume !(1 == ~T2_E~0); 4473#L479-1 assume !(1 == ~T3_E~0); 4470#L484-1 assume !(1 == ~E_M~0); 4465#L489-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3944#L494-1 assume !(1 == ~E_2~0); 3945#L499-1 assume !(1 == ~E_3~0); 3964#L670-1 [2020-11-28 03:06:20,396 INFO L796 eck$LassoCheckResult]: Loop: 3964#L670-1 assume !false; 3965#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 4438#L396 assume !false; 4437#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4435#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4432#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4431#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4430#L349 assume !(0 != eval_~tmp~0); 4429#L411 start_simulation_~kernel_st~0 := 2; 4428#L277-1 start_simulation_~kernel_st~0 := 3; 4426#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4427#L421-4 assume !(0 == ~T1_E~0); 4600#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4599#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4598#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4597#L441-3 assume !(0 == ~E_1~0); 4596#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4595#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4594#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4593#L200-15 assume !(1 == ~m_pc~0); 4592#L200-17 is_master_triggered_~__retres1~0 := 0; 4591#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4590#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4589#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4588#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4587#L219-15 assume 1 == ~t1_pc~0; 4585#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4584#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4583#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4581#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4579#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4577#L238-15 assume 1 == ~t2_pc~0; 4202#L239-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4102#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4103#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4025#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4026#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3907#L257-15 assume 1 == ~t3_pc~0; 3908#L258-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3901#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3953#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4059#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4190#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4126#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4127#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4010#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4011#L484-3 assume !(1 == ~E_M~0); 4057#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3955#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3956#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3992#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3977#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3975#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3976#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4069#L689 assume !(0 == start_simulation_~tmp~3); 3910#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3981#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3979#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3980#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 4015#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4016#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 4116#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4169#L702 assume !(0 != start_simulation_~tmp___0~1); 3964#L670-1 [2020-11-28 03:06:20,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1591325539, now seen corresponding path program 1 times [2020-11-28 03:06:20,398 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,399 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718777809] [2020-11-28 03:06:20,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,450 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718777809] [2020-11-28 03:06:20,450 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,450 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:20,451 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343881597] [2020-11-28 03:06:20,451 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:20,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,452 INFO L82 PathProgramCache]: Analyzing trace with hash 1671867967, now seen corresponding path program 1 times [2020-11-28 03:06:20,452 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,452 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10079088] [2020-11-28 03:06:20,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,515 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10079088] [2020-11-28 03:06:20,515 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,515 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:20,515 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308499354] [2020-11-28 03:06:20,516 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:20,516 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:20,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:06:20,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:06:20,519 INFO L87 Difference]: Start difference. First operand 706 states and 1049 transitions. cyclomatic complexity: 346 Second operand 4 states. [2020-11-28 03:06:20,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:20,729 INFO L93 Difference]: Finished difference Result 1652 states and 2414 transitions. [2020-11-28 03:06:20,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:06:20,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1652 states and 2414 transitions. [2020-11-28 03:06:20,748 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1557 [2020-11-28 03:06:20,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1652 states to 1652 states and 2414 transitions. [2020-11-28 03:06:20,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1652 [2020-11-28 03:06:20,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1652 [2020-11-28 03:06:20,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1652 states and 2414 transitions. [2020-11-28 03:06:20,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:20,772 INFO L691 BuchiCegarLoop]: Abstraction has 1652 states and 2414 transitions. [2020-11-28 03:06:20,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1652 states and 2414 transitions. [2020-11-28 03:06:20,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1652 to 1251. [2020-11-28 03:06:20,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1251 states. [2020-11-28 03:06:20,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1251 states to 1251 states and 1844 transitions. [2020-11-28 03:06:20,805 INFO L714 BuchiCegarLoop]: Abstraction has 1251 states and 1844 transitions. [2020-11-28 03:06:20,805 INFO L594 BuchiCegarLoop]: Abstraction has 1251 states and 1844 transitions. [2020-11-28 03:06:20,805 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 03:06:20,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1251 states and 1844 transitions. [2020-11-28 03:06:20,829 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1193 [2020-11-28 03:06:20,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:20,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:20,831 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,831 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:20,831 INFO L794 eck$LassoCheckResult]: Stem: 6403#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 6281#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6282#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6389#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 6363#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6364#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6586#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6489#L299-1 assume !(0 == ~M_E~0); 6490#L421-1 assume !(0 == ~T1_E~0); 6569#L426-1 assume !(0 == ~T2_E~0); 6467#L431-1 assume !(0 == ~T3_E~0); 6468#L436-1 assume !(0 == ~E_M~0); 6504#L441-1 assume !(0 == ~E_1~0); 6380#L446-1 assume !(0 == ~E_2~0); 6381#L451-1 assume !(0 == ~E_3~0); 6430#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6458#L200 assume !(1 == ~m_pc~0); 6627#L200-2 is_master_triggered_~__retres1~0 := 0; 6628#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6554#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6402#L523 assume !(0 != activate_threads_~tmp~1); 6373#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6270#L219 assume !(1 == ~t1_pc~0); 6271#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 6273#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6274#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6399#L531 assume !(0 != activate_threads_~tmp___0~0); 6587#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6514#L238 assume !(1 == ~t2_pc~0); 6509#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 6510#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6515#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6445#L539 assume !(0 != activate_threads_~tmp___1~0); 6425#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6355#L257 assume 1 == ~t3_pc~0; 6356#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6351#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6358#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6461#L547 assume !(0 != activate_threads_~tmp___2~0); 6624#L547-2 assume !(1 == ~M_E~0); 6499#L469-1 assume !(1 == ~T1_E~0); 6500#L474-1 assume !(1 == ~T2_E~0); 6376#L479-1 assume !(1 == ~T3_E~0); 6377#L484-1 assume !(1 == ~E_M~0); 6455#L489-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6311#L494-1 assume !(1 == ~E_2~0); 6312#L499-1 assume !(1 == ~E_3~0); 7427#L670-1 [2020-11-28 03:06:20,831 INFO L796 eck$LassoCheckResult]: Loop: 7427#L670-1 assume !false; 7422#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 7420#L396 assume !false; 7418#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7414#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7410#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7408#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7404#L349 assume !(0 != eval_~tmp~0); 6359#L411 start_simulation_~kernel_st~0 := 2; 6360#L277-1 start_simulation_~kernel_st~0 := 3; 6632#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7435#L421-4 assume !(0 == ~T1_E~0); 7513#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7512#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7511#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7510#L441-3 assume !(0 == ~E_1~0); 7509#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7508#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7507#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7506#L200-15 assume !(1 == ~m_pc~0); 7505#L200-17 is_master_triggered_~__retres1~0 := 0; 7504#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7503#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7502#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7501#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7500#L219-15 assume 1 == ~t1_pc~0; 7498#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7497#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7496#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7495#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7494#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7493#L238-15 assume !(1 == ~t2_pc~0); 7381#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 7492#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7491#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7490#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7489#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7488#L257-15 assume 1 == ~t3_pc~0; 7486#L258-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7485#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7484#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7483#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7482#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6588#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7481#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7480#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7479#L484-3 assume !(1 == ~E_M~0); 7478#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6462#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6361#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6362#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6344#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6342#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6343#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6448#L689 assume !(0 == start_simulation_~tmp~3); 6278#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6348#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6346#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6347#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 6387#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6388#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 6498#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7431#L702 assume !(0 != start_simulation_~tmp___0~1); 7427#L670-1 [2020-11-28 03:06:20,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,832 INFO L82 PathProgramCache]: Analyzing trace with hash -600160866, now seen corresponding path program 1 times [2020-11-28 03:06:20,832 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,837 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334068281] [2020-11-28 03:06:20,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,894 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334068281] [2020-11-28 03:06:20,894 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,894 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:20,895 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083870318] [2020-11-28 03:06:20,895 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:20,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:20,895 INFO L82 PathProgramCache]: Analyzing trace with hash -1704124706, now seen corresponding path program 1 times [2020-11-28 03:06:20,896 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:20,896 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115124417] [2020-11-28 03:06:20,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:20,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:20,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:20,924 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115124417] [2020-11-28 03:06:20,925 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:20,925 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:20,925 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404130666] [2020-11-28 03:06:20,925 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:20,926 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:20,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:06:20,926 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:06:20,927 INFO L87 Difference]: Start difference. First operand 1251 states and 1844 transitions. cyclomatic complexity: 596 Second operand 4 states. [2020-11-28 03:06:21,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:21,146 INFO L93 Difference]: Finished difference Result 2941 states and 4279 transitions. [2020-11-28 03:06:21,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:06:21,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2941 states and 4279 transitions. [2020-11-28 03:06:21,176 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 2809 [2020-11-28 03:06:21,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2941 states to 2941 states and 4279 transitions. [2020-11-28 03:06:21,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2941 [2020-11-28 03:06:21,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2941 [2020-11-28 03:06:21,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2941 states and 4279 transitions. [2020-11-28 03:06:21,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:21,213 INFO L691 BuchiCegarLoop]: Abstraction has 2941 states and 4279 transitions. [2020-11-28 03:06:21,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2941 states and 4279 transitions. [2020-11-28 03:06:21,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2941 to 2245. [2020-11-28 03:06:21,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2245 states. [2020-11-28 03:06:21,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2245 states to 2245 states and 3293 transitions. [2020-11-28 03:06:21,297 INFO L714 BuchiCegarLoop]: Abstraction has 2245 states and 3293 transitions. [2020-11-28 03:06:21,297 INFO L594 BuchiCegarLoop]: Abstraction has 2245 states and 3293 transitions. [2020-11-28 03:06:21,297 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 03:06:21,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2245 states and 3293 transitions. [2020-11-28 03:06:21,311 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2186 [2020-11-28 03:06:21,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:21,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:21,319 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:21,319 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:21,319 INFO L794 eck$LassoCheckResult]: Stem: 10601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 10482#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10483#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10586#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 10561#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10562#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10818#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10719#L299-1 assume !(0 == ~M_E~0); 10720#L421-1 assume !(0 == ~T1_E~0); 10805#L426-1 assume !(0 == ~T2_E~0); 10696#L431-1 assume !(0 == ~T3_E~0); 10697#L436-1 assume !(0 == ~E_M~0); 10735#L441-1 assume !(0 == ~E_1~0); 10576#L446-1 assume !(0 == ~E_2~0); 10577#L451-1 assume !(0 == ~E_3~0); 10630#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10685#L200 assume !(1 == ~m_pc~0); 10860#L200-2 is_master_triggered_~__retres1~0 := 0; 10861#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10790#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10598#L523 assume !(0 != activate_threads_~tmp~1); 10571#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10471#L219 assume !(1 == ~t1_pc~0); 10472#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 10474#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10475#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10597#L531 assume !(0 != activate_threads_~tmp___0~0); 10819#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10746#L238 assume !(1 == ~t2_pc~0); 10741#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 10742#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10747#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10656#L539 assume !(0 != activate_threads_~tmp___1~0); 10625#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10555#L257 assume !(1 == ~t3_pc~0); 10550#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 10551#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10557#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10687#L547 assume !(0 != activate_threads_~tmp___2~0); 10859#L547-2 assume !(1 == ~M_E~0); 10866#L469-1 assume !(1 == ~T1_E~0); 10755#L474-1 assume !(1 == ~T2_E~0); 10756#L479-1 assume !(1 == ~T3_E~0); 10626#L484-1 assume !(1 == ~E_M~0); 10627#L489-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10679#L494-1 assume !(1 == ~E_2~0); 10556#L499-1 assume !(1 == ~E_3~0); 10532#L670-1 [2020-11-28 03:06:21,319 INFO L796 eck$LassoCheckResult]: Loop: 10532#L670-1 assume !false; 10533#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12343#L396 assume !false; 10537#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10538#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10539#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10540#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10692#L349 assume !(0 != eval_~tmp~0); 10839#L411 start_simulation_~kernel_st~0 := 2; 12706#L277-1 start_simulation_~kernel_st~0 := 3; 12704#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12695#L421-4 assume !(0 == ~T1_E~0); 12694#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12693#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12692#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12691#L441-3 assume !(0 == ~E_1~0); 12690#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12689#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12663#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12662#L200-15 assume !(1 == ~m_pc~0); 12655#L200-17 is_master_triggered_~__retres1~0 := 0; 12654#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12653#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12652#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12650#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12648#L219-15 assume 1 == ~t1_pc~0; 12645#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12643#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12641#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10766#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10767#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10717#L238-15 assume !(1 == ~t2_pc~0); 10718#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 12651#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12649#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12647#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12644#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12642#L257-15 assume !(1 == ~t3_pc~0); 10469#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 10470#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10520#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10647#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10817#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 10739#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10740#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10578#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10579#L484-3 assume !(1 == ~E_M~0); 10642#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10686#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12616#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12613#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12609#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12605#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12603#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10750#L689 assume !(0 == start_simulation_~tmp~3); 10479#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12660#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12657#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10663#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 10584#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 10585#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 10727#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10791#L702 assume !(0 != start_simulation_~tmp___0~1); 10532#L670-1 [2020-11-28 03:06:21,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:21,320 INFO L82 PathProgramCache]: Analyzing trace with hash -1879485601, now seen corresponding path program 1 times [2020-11-28 03:06:21,320 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:21,320 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825979464] [2020-11-28 03:06:21,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:21,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:21,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:21,359 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825979464] [2020-11-28 03:06:21,360 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:21,360 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:21,360 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950358516] [2020-11-28 03:06:21,360 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:21,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:21,361 INFO L82 PathProgramCache]: Analyzing trace with hash -1065340227, now seen corresponding path program 1 times [2020-11-28 03:06:21,361 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:21,361 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280536426] [2020-11-28 03:06:21,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:21,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:21,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:21,394 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280536426] [2020-11-28 03:06:21,396 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:21,396 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:21,396 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569618580] [2020-11-28 03:06:21,397 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:21,397 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:21,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:06:21,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:06:21,398 INFO L87 Difference]: Start difference. First operand 2245 states and 3293 transitions. cyclomatic complexity: 1051 Second operand 4 states. [2020-11-28 03:06:21,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:21,522 INFO L93 Difference]: Finished difference Result 2322 states and 3312 transitions. [2020-11-28 03:06:21,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:06:21,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2322 states and 3312 transitions. [2020-11-28 03:06:21,543 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2258 [2020-11-28 03:06:21,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2322 states to 2322 states and 3312 transitions. [2020-11-28 03:06:21,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2322 [2020-11-28 03:06:21,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2322 [2020-11-28 03:06:21,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2322 states and 3312 transitions. [2020-11-28 03:06:21,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:21,602 INFO L691 BuchiCegarLoop]: Abstraction has 2322 states and 3312 transitions. [2020-11-28 03:06:21,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2322 states and 3312 transitions. [2020-11-28 03:06:21,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2322 to 2238. [2020-11-28 03:06:21,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2238 states. [2020-11-28 03:06:21,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2238 states to 2238 states and 3208 transitions. [2020-11-28 03:06:21,653 INFO L714 BuchiCegarLoop]: Abstraction has 2238 states and 3208 transitions. [2020-11-28 03:06:21,653 INFO L594 BuchiCegarLoop]: Abstraction has 2238 states and 3208 transitions. [2020-11-28 03:06:21,653 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 03:06:21,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2238 states and 3208 transitions. [2020-11-28 03:06:21,668 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2186 [2020-11-28 03:06:21,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:21,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:21,670 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:21,670 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:21,670 INFO L794 eck$LassoCheckResult]: Stem: 15178#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 15059#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15060#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15165#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 15137#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15138#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15363#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15271#L299-1 assume !(0 == ~M_E~0); 15272#L421-1 assume !(0 == ~T1_E~0); 15349#L426-1 assume !(0 == ~T2_E~0); 15247#L431-1 assume !(0 == ~T3_E~0); 15248#L436-1 assume !(0 == ~E_M~0); 15287#L441-1 assume !(0 == ~E_1~0); 15153#L446-1 assume !(0 == ~E_2~0); 15154#L451-1 assume !(0 == ~E_3~0); 15201#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15238#L200 assume !(1 == ~m_pc~0); 15398#L200-2 is_master_triggered_~__retres1~0 := 0; 15399#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15337#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15176#L523 assume !(0 != activate_threads_~tmp~1); 15146#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15048#L219 assume !(1 == ~t1_pc~0); 15049#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 15051#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15052#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15173#L531 assume !(0 != activate_threads_~tmp___0~0); 15364#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15299#L238 assume !(1 == ~t2_pc~0); 15294#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 15295#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15300#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15222#L539 assume !(0 != activate_threads_~tmp___1~0); 15197#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15131#L257 assume !(1 == ~t3_pc~0); 15127#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 15128#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15133#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15241#L547 assume !(0 != activate_threads_~tmp___2~0); 15397#L547-2 assume !(1 == ~M_E~0); 15281#L469-1 assume !(1 == ~T1_E~0); 15282#L474-1 assume !(1 == ~T2_E~0); 15149#L479-1 assume !(1 == ~T3_E~0); 15150#L484-1 assume !(1 == ~E_M~0); 15198#L489-1 assume !(1 == ~E_1~0); 15089#L494-1 assume !(1 == ~E_2~0); 15090#L499-1 assume !(1 == ~E_3~0); 15132#L670-1 [2020-11-28 03:06:21,670 INFO L796 eck$LassoCheckResult]: Loop: 15132#L670-1 assume !false; 16645#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 16643#L396 assume !false; 16641#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16638#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16634#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16632#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16627#L349 assume !(0 != eval_~tmp~0); 16628#L411 start_simulation_~kernel_st~0 := 2; 17062#L277-1 start_simulation_~kernel_st~0 := 3; 17059#L421-2 assume !(0 == ~M_E~0); 17057#L421-4 assume !(0 == ~T1_E~0); 17055#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17053#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17035#L436-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17034#L441-3 assume !(0 == ~E_1~0); 17033#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17032#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17031#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17029#L200-15 assume !(1 == ~m_pc~0); 17027#L200-17 is_master_triggered_~__retres1~0 := 0; 17025#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17024#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17022#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17019#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17014#L219-15 assume !(1 == ~t1_pc~0); 17011#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 17007#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17000#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16996#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16992#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16864#L238-15 assume !(1 == ~t2_pc~0); 16862#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 16859#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16856#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16854#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16851#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16849#L257-15 assume !(1 == ~t3_pc~0); 16797#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 16845#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16843#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16841#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16839#L547-17 assume !(1 == ~M_E~0); 16837#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16835#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16824#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16817#L484-3 assume !(1 == ~E_M~0); 16809#L489-3 assume !(1 == ~E_1~0); 16802#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16795#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16788#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16688#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16684#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16682#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16680#L689 assume !(0 == start_simulation_~tmp~3); 16674#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16667#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16660#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16656#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 16652#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16650#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 16649#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 16648#L702 assume !(0 != start_simulation_~tmp___0~1); 15132#L670-1 [2020-11-28 03:06:21,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:21,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2020-11-28 03:06:21,672 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:21,672 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137576034] [2020-11-28 03:06:21,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:21,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:21,692 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:21,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:21,705 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:21,753 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:21,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:21,754 INFO L82 PathProgramCache]: Analyzing trace with hash -696485410, now seen corresponding path program 1 times [2020-11-28 03:06:21,755 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:21,755 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165288394] [2020-11-28 03:06:21,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:21,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:21,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:21,787 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165288394] [2020-11-28 03:06:21,788 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:21,788 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:21,788 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133555160] [2020-11-28 03:06:21,789 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:21,789 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:21,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:21,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:21,790 INFO L87 Difference]: Start difference. First operand 2238 states and 3208 transitions. cyclomatic complexity: 973 Second operand 3 states. [2020-11-28 03:06:21,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:21,889 INFO L93 Difference]: Finished difference Result 3242 states and 4602 transitions. [2020-11-28 03:06:21,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:21,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3242 states and 4602 transitions. [2020-11-28 03:06:21,915 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3157 [2020-11-28 03:06:21,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3242 states to 3242 states and 4602 transitions. [2020-11-28 03:06:21,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3242 [2020-11-28 03:06:21,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3242 [2020-11-28 03:06:21,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3242 states and 4602 transitions. [2020-11-28 03:06:21,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:21,951 INFO L691 BuchiCegarLoop]: Abstraction has 3242 states and 4602 transitions. [2020-11-28 03:06:21,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3242 states and 4602 transitions. [2020-11-28 03:06:22,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3242 to 3240. [2020-11-28 03:06:22,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3240 states. [2020-11-28 03:06:22,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3240 states to 3240 states and 4600 transitions. [2020-11-28 03:06:22,073 INFO L714 BuchiCegarLoop]: Abstraction has 3240 states and 4600 transitions. [2020-11-28 03:06:22,073 INFO L594 BuchiCegarLoop]: Abstraction has 3240 states and 4600 transitions. [2020-11-28 03:06:22,074 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 03:06:22,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3240 states and 4600 transitions. [2020-11-28 03:06:22,085 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3155 [2020-11-28 03:06:22,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:22,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:22,087 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,087 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,087 INFO L794 eck$LassoCheckResult]: Stem: 20664#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20545#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20546#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20652#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 20623#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20624#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20852#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20764#L299-1 assume !(0 == ~M_E~0); 20765#L421-1 assume !(0 == ~T1_E~0); 20838#L426-1 assume !(0 == ~T2_E~0); 20741#L431-1 assume !(0 == ~T3_E~0); 20742#L436-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20778#L441-1 assume !(0 == ~E_1~0); 20639#L446-1 assume !(0 == ~E_2~0); 20640#L451-1 assume !(0 == ~E_3~0); 20687#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20905#L200 assume !(1 == ~m_pc~0); 20906#L200-2 is_master_triggered_~__retres1~0 := 0; 20907#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20827#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20663#L523 assume !(0 != activate_threads_~tmp~1); 20631#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20632#L219 assume !(1 == ~t1_pc~0); 20928#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 20537#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20538#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20660#L531 assume !(0 != activate_threads_~tmp___0~0); 20853#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20790#L238 assume !(1 == ~t2_pc~0); 20784#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 20785#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20791#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20711#L539 assume !(0 != activate_threads_~tmp___1~0); 20683#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20617#L257 assume !(1 == ~t3_pc~0); 20613#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 20614#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20619#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20895#L547 assume !(0 != activate_threads_~tmp___2~0); 20896#L547-2 assume !(1 == ~M_E~0); 20773#L469-1 assume !(1 == ~T1_E~0); 20774#L474-1 assume !(1 == ~T2_E~0); 20635#L479-1 assume !(1 == ~T3_E~0); 20636#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 20684#L489-1 assume !(1 == ~E_1~0); 20577#L494-1 assume !(1 == ~E_2~0); 20578#L499-1 assume !(1 == ~E_3~0); 20618#L670-1 [2020-11-28 03:06:22,087 INFO L796 eck$LassoCheckResult]: Loop: 20618#L670-1 assume !false; 23356#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 20858#L396 assume !false; 23353#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 23348#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 23343#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21826#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 21823#L349 assume !(0 != eval_~tmp~0); 21824#L411 start_simulation_~kernel_st~0 := 2; 23738#L277-1 start_simulation_~kernel_st~0 := 3; 23736#L421-2 assume !(0 == ~M_E~0); 23734#L421-4 assume !(0 == ~T1_E~0); 23732#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23730#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23728#L436-3 assume !(0 == ~E_M~0); 20800#L441-3 assume !(0 == ~E_1~0); 20801#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23746#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23616#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23613#L200-15 assume !(1 == ~m_pc~0); 23610#L200-17 is_master_triggered_~__retres1~0 := 0; 23606#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23602#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23598#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23594#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23593#L219-15 assume !(1 == ~t1_pc~0); 23586#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 23581#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23577#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23573#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23569#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23565#L238-15 assume !(1 == ~t2_pc~0); 23560#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 23556#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23553#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23549#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23545#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23541#L257-15 assume !(1 == ~t3_pc~0); 23491#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 23535#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23531#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23527#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23523#L547-17 assume !(1 == ~M_E~0); 23518#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23513#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23509#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23504#L484-3 assume !(1 == ~E_M~0); 20699#L489-3 assume !(1 == ~E_1~0); 20735#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23380#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23379#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 23374#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 23370#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 23369#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 23368#L689 assume !(0 == start_simulation_~tmp~3); 23367#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 23365#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 23362#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 23361#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 23360#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 23359#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 23358#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 23357#L702 assume !(0 != start_simulation_~tmp___0~1); 20618#L670-1 [2020-11-28 03:06:22,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,088 INFO L82 PathProgramCache]: Analyzing trace with hash -1485176475, now seen corresponding path program 1 times [2020-11-28 03:06:22,088 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,088 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799082997] [2020-11-28 03:06:22,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:22,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:22,122 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799082997] [2020-11-28 03:06:22,122 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:22,122 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:06:22,123 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086544123] [2020-11-28 03:06:22,123 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:22,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,123 INFO L82 PathProgramCache]: Analyzing trace with hash -712004128, now seen corresponding path program 1 times [2020-11-28 03:06:22,124 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,124 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543216974] [2020-11-28 03:06:22,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:22,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:22,155 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543216974] [2020-11-28 03:06:22,155 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:22,155 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:06:22,156 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786048247] [2020-11-28 03:06:22,156 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:22,156 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:22,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:22,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:22,157 INFO L87 Difference]: Start difference. First operand 3240 states and 4600 transitions. cyclomatic complexity: 1363 Second operand 3 states. [2020-11-28 03:06:22,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:22,205 INFO L93 Difference]: Finished difference Result 2238 states and 3154 transitions. [2020-11-28 03:06:22,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:22,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2238 states and 3154 transitions. [2020-11-28 03:06:22,216 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2186 [2020-11-28 03:06:22,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2238 states to 2238 states and 3154 transitions. [2020-11-28 03:06:22,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2238 [2020-11-28 03:06:22,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2238 [2020-11-28 03:06:22,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2238 states and 3154 transitions. [2020-11-28 03:06:22,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:22,238 INFO L691 BuchiCegarLoop]: Abstraction has 2238 states and 3154 transitions. [2020-11-28 03:06:22,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2238 states and 3154 transitions. [2020-11-28 03:06:22,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2238 to 2238. [2020-11-28 03:06:22,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2238 states. [2020-11-28 03:06:22,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2238 states to 2238 states and 3154 transitions. [2020-11-28 03:06:22,281 INFO L714 BuchiCegarLoop]: Abstraction has 2238 states and 3154 transitions. [2020-11-28 03:06:22,281 INFO L594 BuchiCegarLoop]: Abstraction has 2238 states and 3154 transitions. [2020-11-28 03:06:22,281 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 03:06:22,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2238 states and 3154 transitions. [2020-11-28 03:06:22,289 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2186 [2020-11-28 03:06:22,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:22,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:22,291 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,291 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,291 INFO L794 eck$LassoCheckResult]: Stem: 26151#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26032#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26033#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26136#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 26110#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26111#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26333#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26245#L299-1 assume !(0 == ~M_E~0); 26246#L421-1 assume !(0 == ~T1_E~0); 26320#L426-1 assume !(0 == ~T2_E~0); 26226#L431-1 assume !(0 == ~T3_E~0); 26227#L436-1 assume !(0 == ~E_M~0); 26262#L441-1 assume !(0 == ~E_1~0); 26125#L446-1 assume !(0 == ~E_2~0); 26126#L451-1 assume !(0 == ~E_3~0); 26173#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26215#L200 assume !(1 == ~m_pc~0); 26370#L200-2 is_master_triggered_~__retres1~0 := 0; 26371#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26310#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26148#L523 assume !(0 != activate_threads_~tmp~1); 26120#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26021#L219 assume !(1 == ~t1_pc~0); 26022#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 26024#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26025#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26147#L531 assume !(0 != activate_threads_~tmp___0~0); 26334#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26273#L238 assume !(1 == ~t2_pc~0); 26268#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 26269#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26274#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26198#L539 assume !(0 != activate_threads_~tmp___1~0); 26169#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26104#L257 assume !(1 == ~t3_pc~0); 26100#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 26101#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26106#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26218#L547 assume !(0 != activate_threads_~tmp___2~0); 26369#L547-2 assume !(1 == ~M_E~0); 26256#L469-1 assume !(1 == ~T1_E~0); 26257#L474-1 assume !(1 == ~T2_E~0); 26121#L479-1 assume !(1 == ~T3_E~0); 26122#L484-1 assume !(1 == ~E_M~0); 26170#L489-1 assume !(1 == ~E_1~0); 26065#L494-1 assume !(1 == ~E_2~0); 26066#L499-1 assume !(1 == ~E_3~0); 26105#L670-1 [2020-11-28 03:06:22,291 INFO L796 eck$LassoCheckResult]: Loop: 26105#L670-1 assume !false; 27636#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 27634#L396 assume !false; 27632#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27628#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 27624#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27622#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 27620#L349 assume !(0 != eval_~tmp~0); 27621#L411 start_simulation_~kernel_st~0 := 2; 28249#L277-1 start_simulation_~kernel_st~0 := 3; 28247#L421-2 assume !(0 == ~M_E~0); 28245#L421-4 assume !(0 == ~T1_E~0); 28243#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28241#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28190#L436-3 assume !(0 == ~E_M~0); 26282#L441-3 assume !(0 == ~E_1~0); 26283#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26191#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26192#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26219#L200-15 assume !(1 == ~m_pc~0); 26360#L200-17 is_master_triggered_~__retres1~0 := 0; 26361#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26291#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26289#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26290#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26214#L219-15 assume !(1 == ~t1_pc~0); 26158#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 26040#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26041#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26159#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26292#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26299#L238-15 assume !(1 == ~t2_pc~0); 26374#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 26241#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26242#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26348#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26149#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26026#L257-15 assume !(1 == ~t3_pc~0); 26027#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 26071#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26072#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27703#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27702#L547-17 assume !(1 == ~M_E~0); 27701#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27700#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27698#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27696#L484-3 assume !(1 == ~E_M~0); 27694#L489-3 assume !(1 == ~E_1~0); 27692#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27690#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27685#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27680#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 27676#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27674#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 27671#L689 assume !(0 == start_simulation_~tmp~3); 27669#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27663#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 27659#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27657#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 27655#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 27653#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 27652#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 27647#L702 assume !(0 != start_simulation_~tmp___0~1); 26105#L670-1 [2020-11-28 03:06:22,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2020-11-28 03:06:22,292 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,293 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65058860] [2020-11-28 03:06:22,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:22,342 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:22,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:22,355 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:22,379 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:22,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,380 INFO L82 PathProgramCache]: Analyzing trace with hash -712004128, now seen corresponding path program 2 times [2020-11-28 03:06:22,380 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,380 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123381472] [2020-11-28 03:06:22,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:22,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:22,419 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123381472] [2020-11-28 03:06:22,419 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:22,419 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:06:22,420 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361238484] [2020-11-28 03:06:22,420 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:22,420 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:22,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:06:22,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:06:22,421 INFO L87 Difference]: Start difference. First operand 2238 states and 3154 transitions. cyclomatic complexity: 919 Second operand 5 states. [2020-11-28 03:06:22,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:22,567 INFO L93 Difference]: Finished difference Result 3860 states and 5344 transitions. [2020-11-28 03:06:22,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:06:22,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3860 states and 5344 transitions. [2020-11-28 03:06:22,592 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3804 [2020-11-28 03:06:22,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3860 states to 3860 states and 5344 transitions. [2020-11-28 03:06:22,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3860 [2020-11-28 03:06:22,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3860 [2020-11-28 03:06:22,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3860 states and 5344 transitions. [2020-11-28 03:06:22,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:22,641 INFO L691 BuchiCegarLoop]: Abstraction has 3860 states and 5344 transitions. [2020-11-28 03:06:22,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3860 states and 5344 transitions. [2020-11-28 03:06:22,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3860 to 2274. [2020-11-28 03:06:22,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2274 states. [2020-11-28 03:06:22,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2274 states to 2274 states and 3190 transitions. [2020-11-28 03:06:22,730 INFO L714 BuchiCegarLoop]: Abstraction has 2274 states and 3190 transitions. [2020-11-28 03:06:22,730 INFO L594 BuchiCegarLoop]: Abstraction has 2274 states and 3190 transitions. [2020-11-28 03:06:22,730 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 03:06:22,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2274 states and 3190 transitions. [2020-11-28 03:06:22,739 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2222 [2020-11-28 03:06:22,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:22,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:22,740 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,740 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:22,741 INFO L794 eck$LassoCheckResult]: Stem: 32260#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 32146#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 32147#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32247#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 32223#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32224#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32451#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32360#L299-1 assume !(0 == ~M_E~0); 32361#L421-1 assume !(0 == ~T1_E~0); 32439#L426-1 assume !(0 == ~T2_E~0); 32337#L431-1 assume !(0 == ~T3_E~0); 32338#L436-1 assume !(0 == ~E_M~0); 32375#L441-1 assume !(0 == ~E_1~0); 32238#L446-1 assume !(0 == ~E_2~0); 32239#L451-1 assume !(0 == ~E_3~0); 32286#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32327#L200 assume !(1 == ~m_pc~0); 32494#L200-2 is_master_triggered_~__retres1~0 := 0; 32495#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32429#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32257#L523 assume !(0 != activate_threads_~tmp~1); 32231#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32135#L219 assume !(1 == ~t1_pc~0); 32136#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 32138#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32139#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32254#L531 assume !(0 != activate_threads_~tmp___0~0); 32452#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32386#L238 assume !(1 == ~t2_pc~0); 32380#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 32381#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32387#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32310#L539 assume !(0 != activate_threads_~tmp___1~0); 32282#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32218#L257 assume !(1 == ~t3_pc~0); 32214#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 32215#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32219#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 32330#L547 assume !(0 != activate_threads_~tmp___2~0); 32491#L547-2 assume !(1 == ~M_E~0); 32370#L469-1 assume !(1 == ~T1_E~0); 32371#L474-1 assume !(1 == ~T2_E~0); 32234#L479-1 assume !(1 == ~T3_E~0); 32235#L484-1 assume !(1 == ~E_M~0); 32283#L489-1 assume !(1 == ~E_1~0); 32175#L494-1 assume !(1 == ~E_2~0); 32176#L499-1 assume !(1 == ~E_3~0); 32194#L670-1 [2020-11-28 03:06:22,741 INFO L796 eck$LassoCheckResult]: Loop: 32194#L670-1 assume !false; 32195#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 32292#L396 assume !false; 32200#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 32201#L312 assume !(0 == ~m_st~0); 32205#L316 assume !(0 == ~t1_st~0); 32398#L320 assume !(0 == ~t2_st~0); 32311#L324 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 32202#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 32203#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 34064#L349 assume !(0 != eval_~tmp~0); 32220#L411 start_simulation_~kernel_st~0 := 2; 32221#L277-1 start_simulation_~kernel_st~0 := 3; 32441#L421-2 assume !(0 == ~M_E~0); 32442#L421-4 assume !(0 == ~T1_E~0); 32444#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32346#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32347#L436-3 assume !(0 == ~E_M~0); 32396#L441-3 assume !(0 == ~E_1~0); 32397#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32304#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32305#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32488#L200-15 assume !(1 == ~m_pc~0); 32489#L200-17 is_master_triggered_~__retres1~0 := 0; 32502#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32407#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32408#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 32405#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32406#L219-15 assume !(1 == ~t1_pc~0); 32317#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 32318#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32270#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32271#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32417#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32418#L238-15 assume !(1 == ~t2_pc~0); 33385#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 34341#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34340#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34339#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 34338#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34337#L257-15 assume !(1 == ~t3_pc~0); 33500#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 34336#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32302#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 32303#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32450#L547-17 assume !(1 == ~M_E~0); 32378#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32379#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32240#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32241#L484-3 assume !(1 == ~E_M~0); 32297#L489-3 assume !(1 == ~E_1~0); 32187#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32188#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32222#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 32208#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 32206#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 32207#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 32313#L689 assume !(0 == start_simulation_~tmp~3); 32392#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 32393#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 34363#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 34362#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 34361#L644 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 34348#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 34346#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 32431#L702 assume !(0 != start_simulation_~tmp___0~1); 32194#L670-1 [2020-11-28 03:06:22,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,742 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2020-11-28 03:06:22,742 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,742 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892957116] [2020-11-28 03:06:22,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:22,756 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:22,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:22,765 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:22,788 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:22,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:22,790 INFO L82 PathProgramCache]: Analyzing trace with hash -562195938, now seen corresponding path program 1 times [2020-11-28 03:06:22,790 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:22,790 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052890664] [2020-11-28 03:06:22,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:22,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:22,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:22,838 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052890664] [2020-11-28 03:06:22,838 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:22,838 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:06:22,838 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260293198] [2020-11-28 03:06:22,839 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:22,839 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:22,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:06:22,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:06:22,840 INFO L87 Difference]: Start difference. First operand 2274 states and 3190 transitions. cyclomatic complexity: 919 Second operand 5 states. [2020-11-28 03:06:23,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:23,029 INFO L93 Difference]: Finished difference Result 7192 states and 9964 transitions. [2020-11-28 03:06:23,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:06:23,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7192 states and 9964 transitions. [2020-11-28 03:06:23,107 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7128 [2020-11-28 03:06:23,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7192 states to 7192 states and 9964 transitions. [2020-11-28 03:06:23,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7192 [2020-11-28 03:06:23,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7192 [2020-11-28 03:06:23,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7192 states and 9964 transitions. [2020-11-28 03:06:23,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:23,170 INFO L691 BuchiCegarLoop]: Abstraction has 7192 states and 9964 transitions. [2020-11-28 03:06:23,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7192 states and 9964 transitions. [2020-11-28 03:06:23,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7192 to 2310. [2020-11-28 03:06:23,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2310 states. [2020-11-28 03:06:23,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2310 states to 2310 states and 3226 transitions. [2020-11-28 03:06:23,263 INFO L714 BuchiCegarLoop]: Abstraction has 2310 states and 3226 transitions. [2020-11-28 03:06:23,263 INFO L594 BuchiCegarLoop]: Abstraction has 2310 states and 3226 transitions. [2020-11-28 03:06:23,264 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 03:06:23,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2310 states and 3226 transitions. [2020-11-28 03:06:23,275 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2258 [2020-11-28 03:06:23,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:23,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:23,277 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,277 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,277 INFO L794 eck$LassoCheckResult]: Stem: 41743#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 41628#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41629#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41730#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 41706#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41707#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41931#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41841#L299-1 assume !(0 == ~M_E~0); 41842#L421-1 assume !(0 == ~T1_E~0); 41918#L426-1 assume !(0 == ~T2_E~0); 41818#L431-1 assume !(0 == ~T3_E~0); 41819#L436-1 assume !(0 == ~E_M~0); 41856#L441-1 assume !(0 == ~E_1~0); 41721#L446-1 assume !(0 == ~E_2~0); 41722#L451-1 assume !(0 == ~E_3~0); 41766#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41806#L200 assume !(1 == ~m_pc~0); 41977#L200-2 is_master_triggered_~__retres1~0 := 0; 41978#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41906#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 41740#L523 assume !(0 != activate_threads_~tmp~1); 41714#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41618#L219 assume !(1 == ~t1_pc~0); 41619#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 41621#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41622#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41737#L531 assume !(0 != activate_threads_~tmp___0~0); 41932#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41868#L238 assume !(1 == ~t2_pc~0); 41862#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 41863#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41869#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41789#L539 assume !(0 != activate_threads_~tmp___1~0); 41762#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41701#L257 assume !(1 == ~t3_pc~0); 41697#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 41698#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41702#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41809#L547 assume !(0 != activate_threads_~tmp___2~0); 41975#L547-2 assume !(1 == ~M_E~0); 41851#L469-1 assume !(1 == ~T1_E~0); 41852#L474-1 assume !(1 == ~T2_E~0); 41717#L479-1 assume !(1 == ~T3_E~0); 41718#L484-1 assume !(1 == ~E_M~0); 41763#L489-1 assume !(1 == ~E_1~0); 41657#L494-1 assume !(1 == ~E_2~0); 41658#L499-1 assume !(1 == ~E_3~0); 41676#L670-1 [2020-11-28 03:06:23,278 INFO L796 eck$LassoCheckResult]: Loop: 41676#L670-1 assume !false; 41677#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 41772#L396 assume !false; 41682#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 41683#L312 assume !(0 == ~m_st~0); 41961#L316 assume !(0 == ~t1_st~0); 41962#L320 assume !(0 == ~t2_st~0); 41790#L324 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 41792#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43682#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 43683#L349 assume !(0 != eval_~tmp~0); 41703#L411 start_simulation_~kernel_st~0 := 2; 41704#L277-1 start_simulation_~kernel_st~0 := 3; 41920#L421-2 assume !(0 == ~M_E~0); 41921#L421-4 assume !(0 == ~T1_E~0); 41923#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41960#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41865#L436-3 assume !(0 == ~E_M~0); 41866#L441-3 assume !(0 == ~E_1~0); 41725#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41726#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41814#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41815#L200-15 assume !(1 == ~m_pc~0); 43648#L200-17 is_master_triggered_~__retres1~0 := 0; 43649#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43521#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43522#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 43490#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43491#L219-15 assume !(1 == ~t1_pc~0); 43467#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 43468#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43459#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43460#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43435#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43436#L238-15 assume !(1 == ~t2_pc~0); 43258#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 43429#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41950#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41951#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41741#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41742#L257-15 assume !(1 == ~t3_pc~0); 43383#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 43859#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43858#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 43857#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43856#L547-17 assume !(1 == ~M_E~0); 43855#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43854#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43853#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43852#L484-3 assume !(1 == ~E_M~0); 43851#L489-3 assume !(1 == ~E_1~0); 43850#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43849#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43848#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43846#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43836#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43831#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 43824#L689 assume !(0 == start_simulation_~tmp~3); 43821#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 41694#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 41695#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 41796#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 41728#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41729#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 41941#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 41942#L702 assume !(0 != start_simulation_~tmp___0~1); 41676#L670-1 [2020-11-28 03:06:23,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:23,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2020-11-28 03:06:23,279 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:23,279 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417677772] [2020-11-28 03:06:23,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:23,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,292 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:23,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,302 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:23,317 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:23,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:23,319 INFO L82 PathProgramCache]: Analyzing trace with hash -562255520, now seen corresponding path program 1 times [2020-11-28 03:06:23,319 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:23,319 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536125355] [2020-11-28 03:06:23,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:23,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:23,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:23,422 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536125355] [2020-11-28 03:06:23,423 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:23,423 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:06:23,423 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73659028] [2020-11-28 03:06:23,424 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:23,424 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:23,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:06:23,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:06:23,425 INFO L87 Difference]: Start difference. First operand 2310 states and 3226 transitions. cyclomatic complexity: 919 Second operand 5 states. [2020-11-28 03:06:23,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:23,605 INFO L93 Difference]: Finished difference Result 2608 states and 3611 transitions. [2020-11-28 03:06:23,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:06:23,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2608 states and 3611 transitions. [2020-11-28 03:06:23,619 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2556 [2020-11-28 03:06:23,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2608 states to 2608 states and 3611 transitions. [2020-11-28 03:06:23,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2608 [2020-11-28 03:06:23,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2608 [2020-11-28 03:06:23,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2608 states and 3611 transitions. [2020-11-28 03:06:23,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:23,680 INFO L691 BuchiCegarLoop]: Abstraction has 2608 states and 3611 transitions. [2020-11-28 03:06:23,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2608 states and 3611 transitions. [2020-11-28 03:06:23,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2608 to 2316. [2020-11-28 03:06:23,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2316 states. [2020-11-28 03:06:23,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2316 states to 2316 states and 3185 transitions. [2020-11-28 03:06:23,728 INFO L714 BuchiCegarLoop]: Abstraction has 2316 states and 3185 transitions. [2020-11-28 03:06:23,728 INFO L594 BuchiCegarLoop]: Abstraction has 2316 states and 3185 transitions. [2020-11-28 03:06:23,728 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 03:06:23,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2316 states and 3185 transitions. [2020-11-28 03:06:23,737 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2264 [2020-11-28 03:06:23,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:23,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:23,742 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,742 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,742 INFO L794 eck$LassoCheckResult]: Stem: 46682#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 46560#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 46561#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 46667#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 46643#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46644#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46879#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46783#L299-1 assume !(0 == ~M_E~0); 46784#L421-1 assume !(0 == ~T1_E~0); 46865#L426-1 assume !(0 == ~T2_E~0); 46764#L431-1 assume !(0 == ~T3_E~0); 46765#L436-1 assume !(0 == ~E_M~0); 46799#L441-1 assume !(0 == ~E_1~0); 46658#L446-1 assume !(0 == ~E_2~0); 46659#L451-1 assume !(0 == ~E_3~0); 46709#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46749#L200 assume !(1 == ~m_pc~0); 46921#L200-2 is_master_triggered_~__retres1~0 := 0; 46922#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46856#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 46678#L523 assume !(0 != activate_threads_~tmp~1); 46653#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46549#L219 assume !(1 == ~t1_pc~0); 46550#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 46552#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46553#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 46677#L531 assume !(0 != activate_threads_~tmp___0~0); 46880#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46811#L238 assume !(1 == ~t2_pc~0); 46805#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 46806#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46812#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 46729#L539 assume !(0 != activate_threads_~tmp___1~0); 46705#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46636#L257 assume !(1 == ~t3_pc~0); 46631#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 46632#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46638#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46754#L547 assume !(0 != activate_threads_~tmp___2~0); 46920#L547-2 assume !(1 == ~M_E~0); 46794#L469-1 assume !(1 == ~T1_E~0); 46795#L474-1 assume !(1 == ~T2_E~0); 46654#L479-1 assume !(1 == ~T3_E~0); 46655#L484-1 assume !(1 == ~E_M~0); 46706#L489-1 assume !(1 == ~E_1~0); 46595#L494-1 assume !(1 == ~E_2~0); 46596#L499-1 assume !(1 == ~E_3~0); 46637#L670-1 [2020-11-28 03:06:23,743 INFO L796 eck$LassoCheckResult]: Loop: 46637#L670-1 assume !false; 48516#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 48513#L396 assume !false; 48511#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 48507#L312 assume !(0 == ~m_st~0); 48508#L316 assume !(0 == ~t1_st~0); 48504#L320 assume !(0 == ~t2_st~0); 48505#L324 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 48506#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 48844#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 48843#L349 assume !(0 != eval_~tmp~0); 48842#L411 start_simulation_~kernel_st~0 := 2; 48841#L277-1 start_simulation_~kernel_st~0 := 3; 48840#L421-2 assume !(0 == ~M_E~0); 48838#L421-4 assume !(0 == ~T1_E~0); 48781#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46769#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46770#L436-3 assume !(0 == ~E_M~0); 46808#L441-3 assume !(0 == ~E_1~0); 46824#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48813#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46758#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46759#L200-15 assume !(1 == ~m_pc~0); 48806#L200-17 is_master_triggered_~__retres1~0 := 0; 46936#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46937#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 48799#L523-15 assume !(0 != activate_threads_~tmp~1); 48798#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46748#L219-15 assume !(1 == ~t1_pc~0); 46689#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 46569#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46570#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48790#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 46841#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46842#L238-15 assume !(1 == ~t2_pc~0); 46929#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 46930#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46897#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 46898#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 46679#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46680#L257-15 assume !(1 == ~t3_pc~0); 46547#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 46548#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46601#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46723#L547-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 46878#L547-17 assume !(1 == ~M_E~0); 46881#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48787#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48786#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46715#L484-3 assume !(1 == ~E_M~0); 46716#L489-3 assume !(1 == ~E_1~0); 48731#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46641#L499-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46642#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 46625#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 46623#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 46624#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 46733#L689 assume !(0 == start_simulation_~tmp~3); 48709#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 48705#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 48700#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 48696#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 48692#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 48688#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 48684#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 48659#L702 assume !(0 != start_simulation_~tmp___0~1); 46637#L670-1 [2020-11-28 03:06:23,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:23,745 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 5 times [2020-11-28 03:06:23,745 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:23,745 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136210975] [2020-11-28 03:06:23,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:23,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,755 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:23,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,764 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:23,776 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:23,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:23,780 INFO L82 PathProgramCache]: Analyzing trace with hash -1934062818, now seen corresponding path program 1 times [2020-11-28 03:06:23,781 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:23,781 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869600909] [2020-11-28 03:06:23,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:23,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:23,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:23,823 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869600909] [2020-11-28 03:06:23,823 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:23,823 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:23,823 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198375851] [2020-11-28 03:06:23,824 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:06:23,824 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:23,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:23,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:23,824 INFO L87 Difference]: Start difference. First operand 2316 states and 3185 transitions. cyclomatic complexity: 872 Second operand 3 states. [2020-11-28 03:06:23,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:23,867 INFO L93 Difference]: Finished difference Result 2948 states and 3983 transitions. [2020-11-28 03:06:23,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:23,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2948 states and 3983 transitions. [2020-11-28 03:06:23,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2894 [2020-11-28 03:06:23,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2948 states to 2948 states and 3983 transitions. [2020-11-28 03:06:23,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2948 [2020-11-28 03:06:23,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2948 [2020-11-28 03:06:23,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2948 states and 3983 transitions. [2020-11-28 03:06:23,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:23,907 INFO L691 BuchiCegarLoop]: Abstraction has 2948 states and 3983 transitions. [2020-11-28 03:06:23,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2948 states and 3983 transitions. [2020-11-28 03:06:23,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2948 to 2948. [2020-11-28 03:06:23,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2948 states. [2020-11-28 03:06:23,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2948 states to 2948 states and 3983 transitions. [2020-11-28 03:06:23,960 INFO L714 BuchiCegarLoop]: Abstraction has 2948 states and 3983 transitions. [2020-11-28 03:06:23,960 INFO L594 BuchiCegarLoop]: Abstraction has 2948 states and 3983 transitions. [2020-11-28 03:06:23,960 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 03:06:23,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2948 states and 3983 transitions. [2020-11-28 03:06:23,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2894 [2020-11-28 03:06:23,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:23,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:23,972 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,972 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:23,973 INFO L794 eck$LassoCheckResult]: Stem: 51948#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 51829#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51830#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 51936#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 51910#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51911#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52134#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52049#L299-1 assume !(0 == ~M_E~0); 52050#L421-1 assume !(0 == ~T1_E~0); 52120#L426-1 assume !(0 == ~T2_E~0); 52029#L431-1 assume !(0 == ~T3_E~0); 52030#L436-1 assume !(0 == ~E_M~0); 52066#L441-1 assume !(0 == ~E_1~0); 51925#L446-1 assume !(0 == ~E_2~0); 51926#L451-1 assume !(0 == ~E_3~0); 51970#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52018#L200 assume !(1 == ~m_pc~0); 52174#L200-2 is_master_triggered_~__retres1~0 := 0; 52175#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52111#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51946#L523 assume !(0 != activate_threads_~tmp~1); 51920#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51819#L219 assume !(1 == ~t1_pc~0); 51820#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 51822#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51823#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51945#L531 assume !(0 != activate_threads_~tmp___0~0); 52135#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52077#L238 assume !(1 == ~t2_pc~0); 52071#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 52072#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52078#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51993#L539 assume !(0 != activate_threads_~tmp___1~0); 51966#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51903#L257 assume !(1 == ~t3_pc~0); 51898#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 51899#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51905#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52019#L547 assume !(0 != activate_threads_~tmp___2~0); 52173#L547-2 assume !(1 == ~M_E~0); 52062#L469-1 assume !(1 == ~T1_E~0); 52063#L474-1 assume !(1 == ~T2_E~0); 51921#L479-1 assume !(1 == ~T3_E~0); 51922#L484-1 assume !(1 == ~E_M~0); 51967#L489-1 assume !(1 == ~E_1~0); 51863#L494-1 assume !(1 == ~E_2~0); 51864#L499-1 assume !(1 == ~E_3~0); 51904#L670-1 assume !false; 52743#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 52741#L396 [2020-11-28 03:06:23,973 INFO L796 eck$LassoCheckResult]: Loop: 52741#L396 assume !false; 52739#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 52737#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 52735#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 52733#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 52722#L349 assume 0 != eval_~tmp~0; 52713#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 52526#L357 assume !(0 != eval_~tmp_ndt_1~0); 52527#L354 assume !(0 == ~t1_st~0); 52710#L368 assume !(0 == ~t2_st~0); 52705#L382 assume !(0 == ~t3_st~0); 52741#L396 [2020-11-28 03:06:23,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:23,973 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2020-11-28 03:06:23,974 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:23,974 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470996061] [2020-11-28 03:06:23,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:23,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,983 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:23,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:23,991 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,001 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:24,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,002 INFO L82 PathProgramCache]: Analyzing trace with hash 526364296, now seen corresponding path program 1 times [2020-11-28 03:06:24,002 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,002 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103516484] [2020-11-28 03:06:24,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,006 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,008 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,010 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:24,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,011 INFO L82 PathProgramCache]: Analyzing trace with hash -1009067546, now seen corresponding path program 1 times [2020-11-28 03:06:24,011 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,012 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466860300] [2020-11-28 03:06:24,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:24,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:24,044 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466860300] [2020-11-28 03:06:24,044 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:24,044 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:24,044 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457507225] [2020-11-28 03:06:24,137 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:24,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:24,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:24,138 INFO L87 Difference]: Start difference. First operand 2948 states and 3983 transitions. cyclomatic complexity: 1039 Second operand 3 states. [2020-11-28 03:06:24,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:24,363 INFO L93 Difference]: Finished difference Result 5139 states and 6852 transitions. [2020-11-28 03:06:24,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:24,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5139 states and 6852 transitions. [2020-11-28 03:06:24,389 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5036 [2020-11-28 03:06:24,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5139 states to 5139 states and 6852 transitions. [2020-11-28 03:06:24,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5139 [2020-11-28 03:06:24,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5139 [2020-11-28 03:06:24,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5139 states and 6852 transitions. [2020-11-28 03:06:24,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:24,420 INFO L691 BuchiCegarLoop]: Abstraction has 5139 states and 6852 transitions. [2020-11-28 03:06:24,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5139 states and 6852 transitions. [2020-11-28 03:06:24,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5139 to 4819. [2020-11-28 03:06:24,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4819 states. [2020-11-28 03:06:24,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4819 states to 4819 states and 6452 transitions. [2020-11-28 03:06:24,497 INFO L714 BuchiCegarLoop]: Abstraction has 4819 states and 6452 transitions. [2020-11-28 03:06:24,497 INFO L594 BuchiCegarLoop]: Abstraction has 4819 states and 6452 transitions. [2020-11-28 03:06:24,498 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 03:06:24,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4819 states and 6452 transitions. [2020-11-28 03:06:24,516 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4716 [2020-11-28 03:06:24,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:24,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:24,517 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:24,517 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:24,517 INFO L794 eck$LassoCheckResult]: Stem: 60053#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 59925#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 59926#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 60035#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 60008#L284-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 60009#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60262#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60162#L299-1 assume !(0 == ~M_E~0); 60163#L421-1 assume !(0 == ~T1_E~0); 60288#L426-1 assume !(0 == ~T2_E~0); 60289#L431-1 assume !(0 == ~T3_E~0); 60180#L436-1 assume !(0 == ~E_M~0); 60181#L441-1 assume !(0 == ~E_1~0); 60026#L446-1 assume !(0 == ~E_2~0); 60027#L451-1 assume !(0 == ~E_3~0); 60127#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60128#L200 assume !(1 == ~m_pc~0); 60319#L200-2 is_master_triggered_~__retres1~0 := 0; 60320#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60235#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 60236#L523 assume !(0 != activate_threads_~tmp~1); 60020#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60021#L219 assume !(1 == ~t1_pc~0); 59947#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 59948#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60047#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 60048#L531 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60264#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60191#L238 assume !(1 == ~t2_pc~0); 60192#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 60193#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60194#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 60102#L539 assume !(0 != activate_threads_~tmp___1~0); 60103#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59999#L257 assume !(1 == ~t3_pc~0); 60000#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 60003#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60004#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 60317#L547 assume !(0 != activate_threads_~tmp___2~0); 60318#L547-2 assume !(1 == ~M_E~0); 60175#L469-1 assume !(1 == ~T1_E~0); 60176#L474-1 assume !(1 == ~T2_E~0); 60022#L479-1 assume !(1 == ~T3_E~0); 60023#L484-1 assume !(1 == ~E_M~0); 60123#L489-1 assume !(1 == ~E_1~0); 60124#L494-1 assume !(1 == ~E_2~0); 60001#L499-1 assume !(1 == ~E_3~0); 60002#L670-1 assume !false; 62778#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 60846#L396 [2020-11-28 03:06:24,518 INFO L796 eck$LassoCheckResult]: Loop: 60846#L396 assume !false; 62770#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 62768#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 62766#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 62763#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 62758#L349 assume 0 != eval_~tmp~0; 62757#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 60134#L357 assume !(0 != eval_~tmp_ndt_1~0); 60135#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 60852#L371 assume !(0 != eval_~tmp_ndt_2~0); 60828#L368 assume !(0 == ~t2_st~0); 60825#L382 assume !(0 == ~t3_st~0); 60846#L396 [2020-11-28 03:06:24,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,518 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2020-11-28 03:06:24,518 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,519 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563449956] [2020-11-28 03:06:24,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:24,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:24,546 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563449956] [2020-11-28 03:06:24,546 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:24,546 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:24,546 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64150967] [2020-11-28 03:06:24,547 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:06:24,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,547 INFO L82 PathProgramCache]: Analyzing trace with hash -866553052, now seen corresponding path program 1 times [2020-11-28 03:06:24,547 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,547 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082783065] [2020-11-28 03:06:24,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,551 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,554 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,556 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:24,656 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:24,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:24,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:24,656 INFO L87 Difference]: Start difference. First operand 4819 states and 6452 transitions. cyclomatic complexity: 1637 Second operand 3 states. [2020-11-28 03:06:24,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:24,687 INFO L93 Difference]: Finished difference Result 4774 states and 6392 transitions. [2020-11-28 03:06:24,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:24,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4774 states and 6392 transitions. [2020-11-28 03:06:24,712 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4716 [2020-11-28 03:06:24,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4774 states to 4774 states and 6392 transitions. [2020-11-28 03:06:24,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4774 [2020-11-28 03:06:24,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4774 [2020-11-28 03:06:24,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4774 states and 6392 transitions. [2020-11-28 03:06:24,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:24,738 INFO L691 BuchiCegarLoop]: Abstraction has 4774 states and 6392 transitions. [2020-11-28 03:06:24,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4774 states and 6392 transitions. [2020-11-28 03:06:24,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4774 to 4774. [2020-11-28 03:06:24,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4774 states. [2020-11-28 03:06:24,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4774 states to 4774 states and 6392 transitions. [2020-11-28 03:06:24,805 INFO L714 BuchiCegarLoop]: Abstraction has 4774 states and 6392 transitions. [2020-11-28 03:06:24,805 INFO L594 BuchiCegarLoop]: Abstraction has 4774 states and 6392 transitions. [2020-11-28 03:06:24,805 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 03:06:24,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4774 states and 6392 transitions. [2020-11-28 03:06:24,820 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4716 [2020-11-28 03:06:24,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:24,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:24,821 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:24,821 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:24,821 INFO L794 eck$LassoCheckResult]: Stem: 69642#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 69523#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 69524#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 69628#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 69603#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69604#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69824#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69738#L299-1 assume !(0 == ~M_E~0); 69739#L421-1 assume !(0 == ~T1_E~0); 69810#L426-1 assume !(0 == ~T2_E~0); 69718#L431-1 assume !(0 == ~T3_E~0); 69719#L436-1 assume !(0 == ~E_M~0); 69754#L441-1 assume !(0 == ~E_1~0); 69618#L446-1 assume !(0 == ~E_2~0); 69619#L451-1 assume !(0 == ~E_3~0); 69664#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69708#L200 assume !(1 == ~m_pc~0); 69870#L200-2 is_master_triggered_~__retres1~0 := 0; 69871#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69801#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69639#L523 assume !(0 != activate_threads_~tmp~1); 69613#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69513#L219 assume !(1 == ~t1_pc~0); 69514#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 69516#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69517#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69638#L531 assume !(0 != activate_threads_~tmp___0~0); 69825#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69764#L238 assume !(1 == ~t2_pc~0); 69759#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 69760#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69765#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69685#L539 assume !(0 != activate_threads_~tmp___1~0); 69660#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69597#L257 assume !(1 == ~t3_pc~0); 69592#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 69593#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69599#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69709#L547 assume !(0 != activate_threads_~tmp___2~0); 69869#L547-2 assume !(1 == ~M_E~0); 69749#L469-1 assume !(1 == ~T1_E~0); 69750#L474-1 assume !(1 == ~T2_E~0); 69614#L479-1 assume !(1 == ~T3_E~0); 69615#L484-1 assume !(1 == ~E_M~0); 69661#L489-1 assume !(1 == ~E_1~0); 69557#L494-1 assume !(1 == ~E_2~0); 69558#L499-1 assume !(1 == ~E_3~0); 69598#L670-1 assume !false; 70116#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 70115#L396 [2020-11-28 03:06:24,822 INFO L796 eck$LassoCheckResult]: Loop: 70115#L396 assume !false; 70114#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 70112#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 70111#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 70108#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 70105#L349 assume 0 != eval_~tmp~0; 70102#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 70097#L357 assume !(0 != eval_~tmp_ndt_1~0); 70094#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 70080#L371 assume !(0 != eval_~tmp_ndt_2~0); 70091#L368 assume !(0 == ~t2_st~0); 70119#L382 assume !(0 == ~t3_st~0); 70115#L396 [2020-11-28 03:06:24,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,822 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2020-11-28 03:06:24,822 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,822 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689979492] [2020-11-28 03:06:24,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,835 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,848 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,859 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:24,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,860 INFO L82 PathProgramCache]: Analyzing trace with hash -866553052, now seen corresponding path program 2 times [2020-11-28 03:06:24,860 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,860 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366892394] [2020-11-28 03:06:24,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,864 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:24,866 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:24,868 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:24,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:24,869 INFO L82 PathProgramCache]: Analyzing trace with hash -1220299898, now seen corresponding path program 1 times [2020-11-28 03:06:24,869 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:24,870 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272384481] [2020-11-28 03:06:24,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:24,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:24,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:24,934 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272384481] [2020-11-28 03:06:24,934 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:24,934 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:06:24,935 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058534570] [2020-11-28 03:06:25,032 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:25,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:25,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:25,033 INFO L87 Difference]: Start difference. First operand 4774 states and 6392 transitions. cyclomatic complexity: 1622 Second operand 3 states. [2020-11-28 03:06:25,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:25,126 INFO L93 Difference]: Finished difference Result 8426 states and 11160 transitions. [2020-11-28 03:06:25,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:25,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8426 states and 11160 transitions. [2020-11-28 03:06:25,170 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8360 [2020-11-28 03:06:25,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8426 states to 8426 states and 11160 transitions. [2020-11-28 03:06:25,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8426 [2020-11-28 03:06:25,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8426 [2020-11-28 03:06:25,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8426 states and 11160 transitions. [2020-11-28 03:06:25,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:25,226 INFO L691 BuchiCegarLoop]: Abstraction has 8426 states and 11160 transitions. [2020-11-28 03:06:25,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8426 states and 11160 transitions. [2020-11-28 03:06:25,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8426 to 8236. [2020-11-28 03:06:25,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8236 states. [2020-11-28 03:06:25,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8236 states to 8236 states and 10930 transitions. [2020-11-28 03:06:25,350 INFO L714 BuchiCegarLoop]: Abstraction has 8236 states and 10930 transitions. [2020-11-28 03:06:25,350 INFO L594 BuchiCegarLoop]: Abstraction has 8236 states and 10930 transitions. [2020-11-28 03:06:25,350 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-28 03:06:25,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8236 states and 10930 transitions. [2020-11-28 03:06:25,381 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8170 [2020-11-28 03:06:25,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:25,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:25,382 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:25,382 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:25,382 INFO L794 eck$LassoCheckResult]: Stem: 82845#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 82732#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 82733#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82832#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 82808#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82809#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83041#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82944#L299-1 assume !(0 == ~M_E~0); 82945#L421-1 assume !(0 == ~T1_E~0); 83028#L426-1 assume !(0 == ~T2_E~0); 82923#L431-1 assume !(0 == ~T3_E~0); 82924#L436-1 assume !(0 == ~E_M~0); 82959#L441-1 assume !(0 == ~E_1~0); 82823#L446-1 assume !(0 == ~E_2~0); 82824#L451-1 assume !(0 == ~E_3~0); 82869#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82911#L200 assume !(1 == ~m_pc~0); 83082#L200-2 is_master_triggered_~__retres1~0 := 0; 83083#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 83015#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 82843#L523 assume !(0 != activate_threads_~tmp~1); 82816#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 82721#L219 assume !(1 == ~t1_pc~0); 82722#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 82724#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82725#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 82842#L531 assume !(0 != activate_threads_~tmp___0~0); 83042#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 82972#L238 assume !(1 == ~t2_pc~0); 82967#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 82968#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 82973#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 82885#L539 assume !(0 != activate_threads_~tmp___1~0); 82865#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82802#L257 assume !(1 == ~t3_pc~0); 82798#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 82799#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82804#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 82913#L547 assume !(0 != activate_threads_~tmp___2~0); 83081#L547-2 assume !(1 == ~M_E~0); 82954#L469-1 assume !(1 == ~T1_E~0); 82955#L474-1 assume !(1 == ~T2_E~0); 82819#L479-1 assume !(1 == ~T3_E~0); 82820#L484-1 assume !(1 == ~E_M~0); 82866#L489-1 assume !(1 == ~E_1~0); 82762#L494-1 assume !(1 == ~E_2~0); 82763#L499-1 assume !(1 == ~E_3~0); 82803#L670-1 assume !false; 87070#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 87043#L396 [2020-11-28 03:06:25,383 INFO L796 eck$LassoCheckResult]: Loop: 87043#L396 assume !false; 87429#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 87428#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 87427#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 87426#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 87425#L349 assume 0 != eval_~tmp~0; 87424#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 87422#L357 assume !(0 != eval_~tmp_ndt_1~0); 86913#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 86607#L371 assume !(0 != eval_~tmp_ndt_2~0); 86348#L368 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 85122#L385 assume !(0 != eval_~tmp_ndt_3~0); 85123#L382 assume !(0 == ~t3_st~0); 87043#L396 [2020-11-28 03:06:25,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:25,383 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2020-11-28 03:06:25,384 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:25,384 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655579322] [2020-11-28 03:06:25,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:25,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:25,395 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:25,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:25,403 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:25,421 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:25,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:25,423 INFO L82 PathProgramCache]: Analyzing trace with hash -1093468207, now seen corresponding path program 1 times [2020-11-28 03:06:25,423 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:25,423 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069290043] [2020-11-28 03:06:25,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:25,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:25,427 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:25,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:25,431 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:25,433 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:25,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:25,435 INFO L82 PathProgramCache]: Analyzing trace with hash 825281455, now seen corresponding path program 1 times [2020-11-28 03:06:25,435 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:25,436 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606281855] [2020-11-28 03:06:25,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:25,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:06:25,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:06:25,510 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606281855] [2020-11-28 03:06:25,510 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:06:25,510 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:06:25,510 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661500741] [2020-11-28 03:06:25,613 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:06:25,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:06:25,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:06:25,614 INFO L87 Difference]: Start difference. First operand 8236 states and 10930 transitions. cyclomatic complexity: 2698 Second operand 3 states. [2020-11-28 03:06:25,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:06:25,741 INFO L93 Difference]: Finished difference Result 14166 states and 18648 transitions. [2020-11-28 03:06:25,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:06:25,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14166 states and 18648 transitions. [2020-11-28 03:06:25,833 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14084 [2020-11-28 03:06:25,906 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14166 states to 14166 states and 18648 transitions. [2020-11-28 03:06:25,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14166 [2020-11-28 03:06:25,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14166 [2020-11-28 03:06:25,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14166 states and 18648 transitions. [2020-11-28 03:06:25,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:06:25,935 INFO L691 BuchiCegarLoop]: Abstraction has 14166 states and 18648 transitions. [2020-11-28 03:06:25,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14166 states and 18648 transitions. [2020-11-28 03:06:26,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14166 to 14046. [2020-11-28 03:06:26,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14046 states. [2020-11-28 03:06:26,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14046 states to 14046 states and 18528 transitions. [2020-11-28 03:06:26,200 INFO L714 BuchiCegarLoop]: Abstraction has 14046 states and 18528 transitions. [2020-11-28 03:06:26,201 INFO L594 BuchiCegarLoop]: Abstraction has 14046 states and 18528 transitions. [2020-11-28 03:06:26,201 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-11-28 03:06:26,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14046 states and 18528 transitions. [2020-11-28 03:06:26,261 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13964 [2020-11-28 03:06:26,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:06:26,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:06:26,263 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:26,263 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:06:26,263 INFO L794 eck$LassoCheckResult]: Stem: 105259#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 105141#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 105142#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 105243#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 105218#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105219#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105452#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105361#L299-1 assume !(0 == ~M_E~0); 105362#L421-1 assume !(0 == ~T1_E~0); 105438#L426-1 assume !(0 == ~T2_E~0); 105339#L431-1 assume !(0 == ~T3_E~0); 105340#L436-1 assume !(0 == ~E_M~0); 105376#L441-1 assume !(0 == ~E_1~0); 105233#L446-1 assume !(0 == ~E_2~0); 105234#L451-1 assume !(0 == ~E_3~0); 105283#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 105327#L200 assume !(1 == ~m_pc~0); 105496#L200-2 is_master_triggered_~__retres1~0 := 0; 105497#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 105428#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 105256#L523 assume !(0 != activate_threads_~tmp~1); 105228#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 105131#L219 assume !(1 == ~t1_pc~0); 105132#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 105134#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 105135#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 105255#L531 assume !(0 != activate_threads_~tmp___0~0); 105453#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 105386#L238 assume !(1 == ~t2_pc~0); 105381#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 105382#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 105387#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 105305#L539 assume !(0 != activate_threads_~tmp___1~0); 105279#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 105212#L257 assume !(1 == ~t3_pc~0); 105208#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 105209#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 105214#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 105329#L547 assume !(0 != activate_threads_~tmp___2~0); 105495#L547-2 assume !(1 == ~M_E~0); 105371#L469-1 assume !(1 == ~T1_E~0); 105372#L474-1 assume !(1 == ~T2_E~0); 105229#L479-1 assume !(1 == ~T3_E~0); 105230#L484-1 assume !(1 == ~E_M~0); 105280#L489-1 assume !(1 == ~E_1~0); 105174#L494-1 assume !(1 == ~E_2~0); 105175#L499-1 assume !(1 == ~E_3~0); 105213#L670-1 assume !false; 112085#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 112083#L396 [2020-11-28 03:06:26,264 INFO L796 eck$LassoCheckResult]: Loop: 112083#L396 assume !false; 112080#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 112076#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 112073#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 112070#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 112065#L349 assume 0 != eval_~tmp~0; 112059#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 112052#L357 assume !(0 != eval_~tmp_ndt_1~0); 112047#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 112027#L371 assume !(0 != eval_~tmp_ndt_2~0); 112043#L368 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 111656#L385 assume !(0 != eval_~tmp_ndt_3~0); 112089#L382 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 110947#L399 assume !(0 != eval_~tmp_ndt_4~0); 112083#L396 [2020-11-28 03:06:26,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:26,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2020-11-28 03:06:26,265 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:26,265 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023739390] [2020-11-28 03:06:26,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:26,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,276 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,285 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,296 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:26,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:26,297 INFO L82 PathProgramCache]: Analyzing trace with hash 462220763, now seen corresponding path program 1 times [2020-11-28 03:06:26,298 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:26,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69207861] [2020-11-28 03:06:26,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:26,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,302 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,306 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,308 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:26,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:06:26,309 INFO L82 PathProgramCache]: Analyzing trace with hash -186081859, now seen corresponding path program 1 times [2020-11-28 03:06:26,309 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:06:26,310 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068133476] [2020-11-28 03:06:26,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:06:26,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,321 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:06:26,332 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:06:26,346 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:06:27,534 WARN L193 SmtUtils]: Spent 1.07 s on a formula simplification. DAG size of input: 189 DAG size of output: 139 [2020-11-28 03:06:28,016 WARN L193 SmtUtils]: Spent 455.00 ms on a formula simplification that was a NOOP. DAG size: 121 [2020-11-28 03:06:28,079 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:06:28 BoogieIcfgContainer [2020-11-28 03:06:28,079 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 03:06:28,080 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 03:06:28,080 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 03:06:28,080 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 03:06:28,081 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:06:18" (3/4) ... [2020-11-28 03:06:28,084 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 03:06:28,170 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_d5ae3d90-3f50-49b8-93de-3edc6ff866ed/bin/uautomizer/witness.graphml [2020-11-28 03:06:28,170 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 03:06:28,172 INFO L168 Benchmark]: Toolchain (without parser) took 12015.64 ms. Allocated memory was 92.3 MB in the beginning and 513.8 MB in the end (delta: 421.5 MB). Free memory was 62.9 MB in the beginning and 304.7 MB in the end (delta: -241.9 MB). Peak memory consumption was 179.6 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,172 INFO L168 Benchmark]: CDTParser took 0.95 ms. Allocated memory is still 92.3 MB. Free memory is still 51.3 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 03:06:28,173 INFO L168 Benchmark]: CACSL2BoogieTranslator took 445.23 ms. Allocated memory is still 92.3 MB. Free memory was 62.6 MB in the beginning and 64.7 MB in the end (delta: -2.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,173 INFO L168 Benchmark]: Boogie Procedure Inliner took 73.62 ms. Allocated memory is still 92.3 MB. Free memory was 64.7 MB in the beginning and 61.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,174 INFO L168 Benchmark]: Boogie Preprocessor took 82.73 ms. Allocated memory is still 92.3 MB. Free memory was 61.2 MB in the beginning and 58.1 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,174 INFO L168 Benchmark]: RCFGBuilder took 1595.83 ms. Allocated memory was 92.3 MB in the beginning and 111.1 MB in the end (delta: 18.9 MB). Free memory was 58.1 MB in the beginning and 68.4 MB in the end (delta: -10.2 MB). Peak memory consumption was 29.7 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,175 INFO L168 Benchmark]: BuchiAutomizer took 9720.06 ms. Allocated memory was 111.1 MB in the beginning and 513.8 MB in the end (delta: 402.7 MB). Free memory was 68.4 MB in the beginning and 307.8 MB in the end (delta: -239.4 MB). Peak memory consumption was 363.5 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,175 INFO L168 Benchmark]: Witness Printer took 90.63 ms. Allocated memory is still 513.8 MB. Free memory was 307.8 MB in the beginning and 304.7 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:06:28,177 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.95 ms. Allocated memory is still 92.3 MB. Free memory is still 51.3 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 445.23 ms. Allocated memory is still 92.3 MB. Free memory was 62.6 MB in the beginning and 64.7 MB in the end (delta: -2.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 73.62 ms. Allocated memory is still 92.3 MB. Free memory was 64.7 MB in the beginning and 61.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 82.73 ms. Allocated memory is still 92.3 MB. Free memory was 61.2 MB in the beginning and 58.1 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1595.83 ms. Allocated memory was 92.3 MB in the beginning and 111.1 MB in the end (delta: 18.9 MB). Free memory was 58.1 MB in the beginning and 68.4 MB in the end (delta: -10.2 MB). Peak memory consumption was 29.7 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 9720.06 ms. Allocated memory was 111.1 MB in the beginning and 513.8 MB in the end (delta: 402.7 MB). Free memory was 68.4 MB in the beginning and 307.8 MB in the end (delta: -239.4 MB). Peak memory consumption was 363.5 MB. Max. memory is 16.1 GB. * Witness Printer took 90.63 ms. Allocated memory is still 513.8 MB. Free memory was 307.8 MB in the beginning and 304.7 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 14046 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 9.6s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 4.5s. Construction of modules took 1.1s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1.2s AutomataMinimizationTime, 18 MinimizatonAttempts, 8604 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had 14046 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 8715 SDtfs, 10873 SDslu, 8458 SDs, 0 SdLazy, 519 SolverSat, 216 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 344]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=29597} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=29597, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@292405f8=0, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@679b9fe6=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35a96bd=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@173dad84=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e64d737=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a643f98=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@271583da=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a16e671=0, NULL=29600, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, NULL=29599, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=29598, t2_i=1, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12cf8d55=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f0d76c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f8c5c4d=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 344]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int M_E = 2; [L29] int T1_E = 2; [L30] int T2_E = 2; [L31] int T3_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L34] int E_2 = 2; [L35] int E_3 = 2; [L41] int token ; [L43] int local ; [L715] int __retres1 ; [L628] m_i = 1 [L629] t1_i = 1 [L630] t2_i = 1 [L631] t3_i = 1 [L656] int kernel_st ; [L657] int tmp ; [L658] int tmp___0 ; [L662] kernel_st = 0 [L284] COND TRUE m_i == 1 [L285] m_st = 0 [L289] COND TRUE t1_i == 1 [L290] t1_st = 0 [L294] COND TRUE t2_i == 1 [L295] t2_st = 0 [L299] COND TRUE t3_i == 1 [L300] t3_st = 0 [L421] COND FALSE !(M_E == 0) [L426] COND FALSE !(T1_E == 0) [L431] COND FALSE !(T2_E == 0) [L436] COND FALSE !(T3_E == 0) [L441] COND FALSE !(E_M == 0) [L446] COND FALSE !(E_1 == 0) [L451] COND FALSE !(E_2 == 0) [L456] COND FALSE !(E_3 == 0) [L514] int tmp ; [L515] int tmp___0 ; [L516] int tmp___1 ; [L517] int tmp___2 ; [L197] int __retres1 ; [L200] COND FALSE !(m_pc == 1) [L210] __retres1 = 0 [L212] return (__retres1); [L521] tmp = is_master_triggered() [L523] COND FALSE !(\read(tmp)) [L216] int __retres1 ; [L219] COND FALSE !(t1_pc == 1) [L229] __retres1 = 0 [L231] return (__retres1); [L529] tmp___0 = is_transmit1_triggered() [L531] COND FALSE !(\read(tmp___0)) [L235] int __retres1 ; [L238] COND FALSE !(t2_pc == 1) [L248] __retres1 = 0 [L250] return (__retres1); [L537] tmp___1 = is_transmit2_triggered() [L539] COND FALSE !(\read(tmp___1)) [L254] int __retres1 ; [L257] COND FALSE !(t3_pc == 1) [L267] __retres1 = 0 [L269] return (__retres1); [L545] tmp___2 = is_transmit3_triggered() [L547] COND FALSE !(\read(tmp___2)) [L469] COND FALSE !(M_E == 1) [L474] COND FALSE !(T1_E == 1) [L479] COND FALSE !(T2_E == 1) [L484] COND FALSE !(T3_E == 1) [L489] COND FALSE !(E_M == 1) [L494] COND FALSE !(E_1 == 1) [L499] COND FALSE !(E_2 == 1) [L504] COND FALSE !(E_3 == 1) [L670] COND TRUE 1 [L673] kernel_st = 1 [L340] int tmp ; Loop: [L344] COND TRUE 1 [L309] int __retres1 ; [L312] COND TRUE m_st == 0 [L313] __retres1 = 1 [L335] return (__retres1); [L347] tmp = exists_runnable_thread() [L349] COND TRUE \read(tmp) [L354] COND TRUE m_st == 0 [L355] int tmp_ndt_1; [L356] tmp_ndt_1 = __VERIFIER_nondet_int() [L357] COND FALSE !(\read(tmp_ndt_1)) [L368] COND TRUE t1_st == 0 [L369] int tmp_ndt_2; [L370] tmp_ndt_2 = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp_ndt_2)) [L382] COND TRUE t2_st == 0 [L383] int tmp_ndt_3; [L384] tmp_ndt_3 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp_ndt_3)) [L396] COND TRUE t3_st == 0 [L397] int tmp_ndt_4; [L398] tmp_ndt_4 = __VERIFIER_nondet_int() [L399] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...