./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 37c2f037dea88b70ca73720b5945796ac3b5419f .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 03:03:17,992 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 03:03:17,994 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 03:03:18,081 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 03:03:18,083 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 03:03:18,085 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 03:03:18,089 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 03:03:18,097 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 03:03:18,106 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 03:03:18,108 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 03:03:18,110 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 03:03:18,114 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 03:03:18,115 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 03:03:18,123 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 03:03:18,125 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 03:03:18,128 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 03:03:18,130 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 03:03:18,133 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 03:03:18,137 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 03:03:18,146 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 03:03:18,152 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 03:03:18,154 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 03:03:18,156 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 03:03:18,158 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 03:03:18,167 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 03:03:18,172 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 03:03:18,173 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 03:03:18,174 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 03:03:18,176 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 03:03:18,178 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 03:03:18,178 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 03:03:18,180 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 03:03:18,182 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 03:03:18,184 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 03:03:18,186 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 03:03:18,187 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 03:03:18,187 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 03:03:18,188 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 03:03:18,188 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 03:03:18,191 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 03:03:18,192 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 03:03:18,195 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 03:03:18,247 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 03:03:18,248 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 03:03:18,250 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 03:03:18,250 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 03:03:18,251 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 03:03:18,251 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 03:03:18,251 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 03:03:18,252 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 03:03:18,252 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 03:03:18,252 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 03:03:18,254 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 03:03:18,254 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 03:03:18,255 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 03:03:18,255 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 03:03:18,255 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 03:03:18,255 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 03:03:18,256 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 03:03:18,257 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 03:03:18,257 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 03:03:18,257 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 03:03:18,257 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 03:03:18,258 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 03:03:18,258 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 03:03:18,258 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 03:03:18,259 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 03:03:18,259 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 03:03:18,259 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 03:03:18,260 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 03:03:18,260 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 03:03:18,262 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 03:03:18,263 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 03:03:18,263 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 03:03:18,264 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 03:03:18,265 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37c2f037dea88b70ca73720b5945796ac3b5419f [2020-11-28 03:03:18,638 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 03:03:18,678 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 03:03:18,681 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 03:03:18,683 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 03:03:18,684 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 03:03:18,698 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2020-11-28 03:03:18,812 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/data/3b4dc5194/7cb27d85e527482fb3368b9d1e3b3698/FLAGa6035e3e7 [2020-11-28 03:03:19,547 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 03:03:19,548 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2020-11-28 03:03:19,563 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/data/3b4dc5194/7cb27d85e527482fb3368b9d1e3b3698/FLAGa6035e3e7 [2020-11-28 03:03:19,845 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/data/3b4dc5194/7cb27d85e527482fb3368b9d1e3b3698 [2020-11-28 03:03:19,848 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 03:03:19,850 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 03:03:19,852 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 03:03:19,852 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 03:03:19,856 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 03:03:19,857 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:03:19" (1/1) ... [2020-11-28 03:03:19,860 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@aed9511 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:19, skipping insertion in model container [2020-11-28 03:03:19,860 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:03:19" (1/1) ... [2020-11-28 03:03:19,869 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 03:03:19,912 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 03:03:20,202 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:03:20,215 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 03:03:20,277 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:03:20,306 INFO L208 MainTranslator]: Completed translation [2020-11-28 03:03:20,306 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20 WrapperNode [2020-11-28 03:03:20,307 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 03:03:20,308 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 03:03:20,308 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 03:03:20,309 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 03:03:20,322 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,334 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,433 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 03:03:20,434 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 03:03:20,434 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 03:03:20,434 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 03:03:20,457 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,457 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,481 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,481 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,519 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,551 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,570 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... [2020-11-28 03:03:20,579 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 03:03:20,589 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 03:03:20,589 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 03:03:20,589 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 03:03:20,592 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 03:03:20,668 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 03:03:20,668 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 03:03:20,669 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 03:03:20,669 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 03:03:22,377 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 03:03:22,377 INFO L298 CfgBuilder]: Removed 167 assume(true) statements. [2020-11-28 03:03:22,380 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:03:22 BoogieIcfgContainer [2020-11-28 03:03:22,380 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 03:03:22,381 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 03:03:22,381 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 03:03:22,385 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 03:03:22,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:03:22,386 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:03:19" (1/3) ... [2020-11-28 03:03:22,388 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72580183 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:03:22, skipping insertion in model container [2020-11-28 03:03:22,388 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:03:22,388 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:03:20" (2/3) ... [2020-11-28 03:03:22,389 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72580183 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:03:22, skipping insertion in model container [2020-11-28 03:03:22,389 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:03:22,389 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:03:22" (3/3) ... [2020-11-28 03:03:22,391 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2020-11-28 03:03:22,438 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 03:03:22,439 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 03:03:22,439 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 03:03:22,439 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 03:03:22,439 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 03:03:22,439 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 03:03:22,440 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 03:03:22,440 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 03:03:22,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 421 states. [2020-11-28 03:03:22,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 354 [2020-11-28 03:03:22,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:22,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:22,544 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:22,544 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:22,544 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 03:03:22,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 421 states. [2020-11-28 03:03:22,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 354 [2020-11-28 03:03:22,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:22,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:22,568 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:22,569 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:22,578 INFO L794 eck$LassoCheckResult]: Stem: 316#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 241#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 350#L770true havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 280#L350true assume !(1 == ~m_i~0);~m_st~0 := 2; 71#L357-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 243#L362-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 19#L367-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 282#L372-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 183#L377-1true assume !(0 == ~M_E~0); 156#L518-1true assume !(0 == ~T1_E~0); 62#L523-1true assume !(0 == ~T2_E~0); 348#L528-1true assume !(0 == ~T3_E~0); 77#L533-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 253#L538-1true assume !(0 == ~E_M~0); 29#L543-1true assume !(0 == ~E_1~0); 392#L548-1true assume !(0 == ~E_2~0); 195#L553-1true assume !(0 == ~E_3~0); 416#L558-1true assume !(0 == ~E_4~0); 98#L563-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124#L254true assume 1 == ~m_pc~0; 94#L255true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 125#L265true is_master_triggered_#res := is_master_triggered_~__retres1~0; 95#L266true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 204#L641true assume !(0 != activate_threads_~tmp~1); 205#L641-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 277#L273true assume !(1 == ~t1_pc~0); 273#L273-2true is_transmit1_triggered_~__retres1~1 := 0; 278#L284true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 240#L285true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 343#L649true assume !(0 != activate_threads_~tmp___0~0); 344#L649-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59#L292true assume 1 == ~t2_pc~0; 357#L293true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 42#L303true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 369#L304true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 422#L657true assume !(0 != activate_threads_~tmp___1~0); 423#L657-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 186#L311true assume !(1 == ~t3_pc~0); 190#L311-2true is_transmit3_triggered_~__retres1~3 := 0; 185#L322true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20#L323true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3#L665true assume !(0 != activate_threads_~tmp___2~0); 4#L665-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 342#L330true assume 1 == ~t4_pc~0; 149#L331true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 341#L341true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148#L342true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 106#L673true assume !(0 != activate_threads_~tmp___3~0); 110#L673-2true assume !(1 == ~M_E~0); 36#L576-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 391#L581-1true assume !(1 == ~T2_E~0); 193#L586-1true assume !(1 == ~T3_E~0); 414#L591-1true assume !(1 == ~T4_E~0); 97#L596-1true assume !(1 == ~E_M~0); 375#L601-1true assume !(1 == ~E_1~0); 153#L606-1true assume !(1 == ~E_2~0); 60#L611-1true assume !(1 == ~E_3~0); 345#L616-1true assume 1 == ~E_4~0;~E_4~0 := 2; 39#L807-1true [2020-11-28 03:03:22,580 INFO L796 eck$LassoCheckResult]: Loop: 39#L807-1true assume !false; 7#L808true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 393#L493true assume false; 99#L508true start_simulation_~kernel_st~0 := 2; 285#L350-1true start_simulation_~kernel_st~0 := 3; 146#L518-2true assume 0 == ~M_E~0;~M_E~0 := 1; 147#L518-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 48#L523-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 335#L528-3true assume !(0 == ~T3_E~0); 80#L533-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 255#L538-3true assume 0 == ~E_M~0;~E_M~0 := 1; 31#L543-3true assume 0 == ~E_1~0;~E_1~0 := 1; 396#L548-3true assume 0 == ~E_2~0;~E_2~0 := 1; 200#L553-3true assume 0 == ~E_3~0;~E_3~0 := 1; 419#L558-3true assume 0 == ~E_4~0;~E_4~0 := 1; 103#L563-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 112#L254-18true assume 1 == ~m_pc~0; 228#L255-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 140#L265-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 229#L266-6true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 180#L641-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 160#L641-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 269#L273-18true assume !(1 == ~t1_pc~0); 260#L273-20true is_transmit1_triggered_~__retres1~1 := 0; 286#L284-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 248#L285-6true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 310#L649-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 312#L649-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 376#L292-18true assume !(1 == ~t2_pc~0); 374#L292-20true is_transmit2_triggered_~__retres1~2 := 0; 385#L303-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 362#L304-6true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 408#L657-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 402#L657-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41#L311-18true assume 1 == ~t3_pc~0; 16#L312-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 174#L322-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15#L323-6true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 69#L665-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70#L665-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 296#L330-18true assume !(1 == ~t4_pc~0); 297#L330-20true is_transmit4_triggered_~__retres1~4 := 0; 330#L341-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141#L342-6true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 230#L673-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 212#L673-20true assume !(1 == ~M_E~0); 30#L576-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 395#L581-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 196#L586-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 418#L591-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 101#L596-3true assume 1 == ~E_M~0;~E_M~0 := 2; 377#L601-3true assume 1 == ~E_1~0;~E_1~0 := 2; 154#L606-3true assume 1 == ~E_2~0;~E_2~0 := 2; 61#L611-3true assume !(1 == ~E_3~0); 347#L616-3true assume 1 == ~E_4~0;~E_4~0 := 2; 6#L621-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 84#L390-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 261#L417-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 338#L418-1true start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 305#L826true assume !(0 == start_simulation_~tmp~3); 295#L826-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 72#L390-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 263#L417-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 340#L418-2true stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 349#L781true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 379#L788true stop_simulation_#res := stop_simulation_~__retres2~0; 353#L789true start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 206#L839true assume !(0 != start_simulation_~tmp___0~1); 39#L807-1true [2020-11-28 03:03:22,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:22,588 INFO L82 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2020-11-28 03:03:22,598 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:22,599 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240527077] [2020-11-28 03:03:22,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:22,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:22,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:22,857 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240527077] [2020-11-28 03:03:22,858 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:22,858 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:22,860 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274501898] [2020-11-28 03:03:22,868 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:22,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:22,872 INFO L82 PathProgramCache]: Analyzing trace with hash -255393426, now seen corresponding path program 1 times [2020-11-28 03:03:22,873 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:22,873 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478297297] [2020-11-28 03:03:22,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:22,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:22,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:22,955 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478297297] [2020-11-28 03:03:22,956 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:22,957 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:22,957 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128109626] [2020-11-28 03:03:22,960 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:22,961 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:22,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:22,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:22,989 INFO L87 Difference]: Start difference. First operand 421 states. Second operand 3 states. [2020-11-28 03:03:23,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:23,078 INFO L93 Difference]: Finished difference Result 419 states and 635 transitions. [2020-11-28 03:03:23,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:23,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 635 transitions. [2020-11-28 03:03:23,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 413 states and 629 transitions. [2020-11-28 03:03:23,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2020-11-28 03:03:23,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2020-11-28 03:03:23,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 629 transitions. [2020-11-28 03:03:23,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:23,108 INFO L691 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2020-11-28 03:03:23,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 629 transitions. [2020-11-28 03:03:23,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2020-11-28 03:03:23,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2020-11-28 03:03:23,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 629 transitions. [2020-11-28 03:03:23,191 INFO L714 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2020-11-28 03:03:23,192 INFO L594 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2020-11-28 03:03:23,192 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 03:03:23,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 629 transitions. [2020-11-28 03:03:23,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:23,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:23,201 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,201 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,201 INFO L794 eck$LassoCheckResult]: Stem: 1218#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1179#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1180#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1206#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 976#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 977#L362-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 884#L367-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 885#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1125#L377-1 assume !(0 == ~M_E~0); 1103#L518-1 assume !(0 == ~T1_E~0); 962#L523-1 assume !(0 == ~T2_E~0); 963#L528-1 assume !(0 == ~T3_E~0); 984#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 985#L538-1 assume !(0 == ~E_M~0); 906#L543-1 assume !(0 == ~E_1~0); 907#L548-1 assume !(0 == ~E_2~0); 1135#L553-1 assume !(0 == ~E_3~0); 1136#L558-1 assume !(0 == ~E_4~0); 1015#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1016#L254 assume 1 == ~m_pc~0; 1006#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1007#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1009#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1010#L641 assume !(0 != activate_threads_~tmp~1); 1149#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1150#L273 assume !(1 == ~t1_pc~0); 1175#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 1176#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1177#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1178#L649 assume !(0 != activate_threads_~tmp___0~0); 1225#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 956#L292 assume 1 == ~t2_pc~0; 957#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 920#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 921#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1250#L657 assume !(0 != activate_threads_~tmp___1~0); 1261#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1128#L311 assume !(1 == ~t3_pc~0); 889#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 888#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 886#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 849#L665 assume !(0 != activate_threads_~tmp___2~0); 850#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 851#L330 assume 1 == ~t4_pc~0; 1093#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1094#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1092#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1030#L673 assume !(0 != activate_threads_~tmp___3~0); 1031#L673-2 assume !(1 == ~M_E~0); 915#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 916#L581-1 assume !(1 == ~T2_E~0); 1131#L586-1 assume !(1 == ~T3_E~0); 1132#L591-1 assume !(1 == ~T4_E~0); 1013#L596-1 assume !(1 == ~E_M~0); 1014#L601-1 assume !(1 == ~E_1~0); 1100#L606-1 assume !(1 == ~E_2~0); 958#L611-1 assume !(1 == ~E_3~0); 959#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 918#L807-1 [2020-11-28 03:03:23,202 INFO L796 eck$LassoCheckResult]: Loop: 918#L807-1 assume !false; 856#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 857#L493 assume !false; 1202#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 991#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 940#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1203#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1146#L432 assume !(0 != eval_~tmp~0); 1017#L508 start_simulation_~kernel_st~0 := 2; 1018#L350-1 start_simulation_~kernel_st~0 := 3; 1090#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1091#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 933#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 934#L528-3 assume !(0 == ~T3_E~0); 988#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 989#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 910#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 911#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1143#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1144#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1023#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1024#L254-18 assume 1 == ~m_pc~0; 1040#L255-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1039#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1081#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1122#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1108#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1109#L273-18 assume 1 == ~t1_pc~0; 1187#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1188#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1190#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1191#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1214#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1215#L292-18 assume 1 == ~t2_pc~0; 1241#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1242#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1239#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1240#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1254#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 919#L311-18 assume 1 == ~t3_pc~0; 876#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 877#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 874#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 875#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 974#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 975#L330-18 assume 1 == ~t4_pc~0; 1084#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1085#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1082#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1083#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1153#L673-20 assume !(1 == ~M_E~0); 908#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 909#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1137#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1138#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1020#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1021#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1101#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 960#L611-3 assume !(1 == ~E_3~0); 961#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 854#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 855#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 948#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1204#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1211#L826 assume !(0 == start_simulation_~tmp~3); 1207#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 978#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 953#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1205#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 1224#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1226#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 1228#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1151#L839 assume !(0 != start_simulation_~tmp___0~1); 918#L807-1 [2020-11-28 03:03:23,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,203 INFO L82 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2020-11-28 03:03:23,203 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,203 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784692023] [2020-11-28 03:03:23,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,283 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784692023] [2020-11-28 03:03:23,284 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,284 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,284 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372058383] [2020-11-28 03:03:23,285 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:23,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,286 INFO L82 PathProgramCache]: Analyzing trace with hash -2045319408, now seen corresponding path program 1 times [2020-11-28 03:03:23,286 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,286 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704050814] [2020-11-28 03:03:23,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,369 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704050814] [2020-11-28 03:03:23,370 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,370 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,370 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11565735] [2020-11-28 03:03:23,371 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:23,371 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:23,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:23,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:23,373 INFO L87 Difference]: Start difference. First operand 413 states and 629 transitions. cyclomatic complexity: 217 Second operand 3 states. [2020-11-28 03:03:23,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:23,389 INFO L93 Difference]: Finished difference Result 413 states and 628 transitions. [2020-11-28 03:03:23,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:23,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 628 transitions. [2020-11-28 03:03:23,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 628 transitions. [2020-11-28 03:03:23,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2020-11-28 03:03:23,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2020-11-28 03:03:23,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 628 transitions. [2020-11-28 03:03:23,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:23,406 INFO L691 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2020-11-28 03:03:23,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 628 transitions. [2020-11-28 03:03:23,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2020-11-28 03:03:23,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2020-11-28 03:03:23,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 628 transitions. [2020-11-28 03:03:23,461 INFO L714 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2020-11-28 03:03:23,461 INFO L594 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2020-11-28 03:03:23,461 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 03:03:23,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 628 transitions. [2020-11-28 03:03:23,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:23,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:23,468 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,468 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,468 INFO L794 eck$LassoCheckResult]: Stem: 2051#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2012#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2013#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2039#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 1809#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1810#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1717#L367-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1718#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1958#L377-1 assume !(0 == ~M_E~0); 1936#L518-1 assume !(0 == ~T1_E~0); 1795#L523-1 assume !(0 == ~T2_E~0); 1796#L528-1 assume !(0 == ~T3_E~0); 1817#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1818#L538-1 assume !(0 == ~E_M~0); 1739#L543-1 assume !(0 == ~E_1~0); 1740#L548-1 assume !(0 == ~E_2~0); 1968#L553-1 assume !(0 == ~E_3~0); 1969#L558-1 assume !(0 == ~E_4~0); 1848#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1849#L254 assume 1 == ~m_pc~0; 1839#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1840#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1842#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1843#L641 assume !(0 != activate_threads_~tmp~1); 1982#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1983#L273 assume !(1 == ~t1_pc~0); 2008#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 2009#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2010#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2011#L649 assume !(0 != activate_threads_~tmp___0~0); 2058#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1789#L292 assume 1 == ~t2_pc~0; 1790#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1753#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1754#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2083#L657 assume !(0 != activate_threads_~tmp___1~0); 2094#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1961#L311 assume !(1 == ~t3_pc~0); 1722#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 1721#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1719#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1682#L665 assume !(0 != activate_threads_~tmp___2~0); 1683#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1684#L330 assume 1 == ~t4_pc~0; 1926#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1927#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1925#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1863#L673 assume !(0 != activate_threads_~tmp___3~0); 1864#L673-2 assume !(1 == ~M_E~0); 1748#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1749#L581-1 assume !(1 == ~T2_E~0); 1964#L586-1 assume !(1 == ~T3_E~0); 1965#L591-1 assume !(1 == ~T4_E~0); 1846#L596-1 assume !(1 == ~E_M~0); 1847#L601-1 assume !(1 == ~E_1~0); 1933#L606-1 assume !(1 == ~E_2~0); 1791#L611-1 assume !(1 == ~E_3~0); 1792#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1751#L807-1 [2020-11-28 03:03:23,469 INFO L796 eck$LassoCheckResult]: Loop: 1751#L807-1 assume !false; 1689#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1690#L493 assume !false; 2035#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1824#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1773#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2036#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1979#L432 assume !(0 != eval_~tmp~0); 1850#L508 start_simulation_~kernel_st~0 := 2; 1851#L350-1 start_simulation_~kernel_st~0 := 3; 1923#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1924#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1766#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1767#L528-3 assume !(0 == ~T3_E~0); 1821#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1822#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1743#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1744#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1976#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1977#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1856#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1857#L254-18 assume 1 == ~m_pc~0; 1873#L255-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1872#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1914#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1955#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1941#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1942#L273-18 assume 1 == ~t1_pc~0; 2020#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2021#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2023#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2024#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2047#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2048#L292-18 assume 1 == ~t2_pc~0; 2074#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2075#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2072#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2073#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2087#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1752#L311-18 assume 1 == ~t3_pc~0; 1709#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1710#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1707#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1708#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1807#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1808#L330-18 assume 1 == ~t4_pc~0; 1917#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1918#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1915#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1916#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1986#L673-20 assume !(1 == ~M_E~0); 1741#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1742#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1970#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1971#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1853#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1854#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1934#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1793#L611-3 assume !(1 == ~E_3~0); 1794#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1687#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1688#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1781#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2037#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2044#L826 assume !(0 == start_simulation_~tmp~3); 2040#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1811#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1786#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2038#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 2057#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2059#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 2061#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1984#L839 assume !(0 != start_simulation_~tmp___0~1); 1751#L807-1 [2020-11-28 03:03:23,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,470 INFO L82 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2020-11-28 03:03:23,470 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,471 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687353132] [2020-11-28 03:03:23,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,531 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687353132] [2020-11-28 03:03:23,531 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,531 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,531 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648618904] [2020-11-28 03:03:23,532 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:23,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,532 INFO L82 PathProgramCache]: Analyzing trace with hash -2045319408, now seen corresponding path program 2 times [2020-11-28 03:03:23,532 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,533 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805157114] [2020-11-28 03:03:23,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,609 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805157114] [2020-11-28 03:03:23,610 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,610 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,610 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493726791] [2020-11-28 03:03:23,611 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:23,611 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:23,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:23,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:23,612 INFO L87 Difference]: Start difference. First operand 413 states and 628 transitions. cyclomatic complexity: 216 Second operand 3 states. [2020-11-28 03:03:23,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:23,645 INFO L93 Difference]: Finished difference Result 413 states and 627 transitions. [2020-11-28 03:03:23,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:23,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 627 transitions. [2020-11-28 03:03:23,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 627 transitions. [2020-11-28 03:03:23,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2020-11-28 03:03:23,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2020-11-28 03:03:23,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 627 transitions. [2020-11-28 03:03:23,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:23,659 INFO L691 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2020-11-28 03:03:23,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 627 transitions. [2020-11-28 03:03:23,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2020-11-28 03:03:23,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2020-11-28 03:03:23,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 627 transitions. [2020-11-28 03:03:23,681 INFO L714 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2020-11-28 03:03:23,681 INFO L594 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2020-11-28 03:03:23,681 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 03:03:23,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 627 transitions. [2020-11-28 03:03:23,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:23,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:23,693 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,693 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,694 INFO L794 eck$LassoCheckResult]: Stem: 2884#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2846#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2872#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 2642#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2643#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2550#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2551#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2791#L377-1 assume !(0 == ~M_E~0); 2769#L518-1 assume !(0 == ~T1_E~0); 2628#L523-1 assume !(0 == ~T2_E~0); 2629#L528-1 assume !(0 == ~T3_E~0); 2650#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2651#L538-1 assume !(0 == ~E_M~0); 2572#L543-1 assume !(0 == ~E_1~0); 2573#L548-1 assume !(0 == ~E_2~0); 2801#L553-1 assume !(0 == ~E_3~0); 2802#L558-1 assume !(0 == ~E_4~0); 2681#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2682#L254 assume 1 == ~m_pc~0; 2672#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2673#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2675#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2676#L641 assume !(0 != activate_threads_~tmp~1); 2815#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2816#L273 assume !(1 == ~t1_pc~0); 2841#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 2842#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2843#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2844#L649 assume !(0 != activate_threads_~tmp___0~0); 2891#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2622#L292 assume 1 == ~t2_pc~0; 2623#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2586#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2587#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2916#L657 assume !(0 != activate_threads_~tmp___1~0); 2927#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2794#L311 assume !(1 == ~t3_pc~0); 2555#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 2554#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2552#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2515#L665 assume !(0 != activate_threads_~tmp___2~0); 2516#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2517#L330 assume 1 == ~t4_pc~0; 2759#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2760#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2758#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2696#L673 assume !(0 != activate_threads_~tmp___3~0); 2697#L673-2 assume !(1 == ~M_E~0); 2581#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2582#L581-1 assume !(1 == ~T2_E~0); 2797#L586-1 assume !(1 == ~T3_E~0); 2798#L591-1 assume !(1 == ~T4_E~0); 2679#L596-1 assume !(1 == ~E_M~0); 2680#L601-1 assume !(1 == ~E_1~0); 2766#L606-1 assume !(1 == ~E_2~0); 2624#L611-1 assume !(1 == ~E_3~0); 2625#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2584#L807-1 [2020-11-28 03:03:23,694 INFO L796 eck$LassoCheckResult]: Loop: 2584#L807-1 assume !false; 2522#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2523#L493 assume !false; 2868#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2657#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2606#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2869#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2812#L432 assume !(0 != eval_~tmp~0); 2683#L508 start_simulation_~kernel_st~0 := 2; 2684#L350-1 start_simulation_~kernel_st~0 := 3; 2756#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2757#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2599#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2600#L528-3 assume !(0 == ~T3_E~0); 2654#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2655#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2576#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2577#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2809#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2810#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2689#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2690#L254-18 assume !(1 == ~m_pc~0); 2704#L254-20 is_master_triggered_~__retres1~0 := 0; 2705#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2747#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2788#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2774#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2775#L273-18 assume 1 == ~t1_pc~0; 2853#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2854#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2856#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2857#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2880#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2881#L292-18 assume 1 == ~t2_pc~0; 2907#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2908#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2905#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2906#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2920#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2585#L311-18 assume !(1 == ~t3_pc~0); 2544#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 2543#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2540#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2541#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2640#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2641#L330-18 assume !(1 == ~t4_pc~0); 2752#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 2751#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2748#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2749#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2819#L673-20 assume !(1 == ~M_E~0); 2574#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2575#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2803#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2804#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2686#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2687#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2767#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2626#L611-3 assume !(1 == ~E_3~0); 2627#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2520#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2521#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2614#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2870#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2877#L826 assume !(0 == start_simulation_~tmp~3); 2873#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2644#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2619#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2871#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 2890#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2892#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 2894#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2817#L839 assume !(0 != start_simulation_~tmp___0~1); 2584#L807-1 [2020-11-28 03:03:23,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,695 INFO L82 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2020-11-28 03:03:23,696 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,696 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528820653] [2020-11-28 03:03:23,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,782 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528820653] [2020-11-28 03:03:23,782 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,782 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,783 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074821823] [2020-11-28 03:03:23,783 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:23,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,784 INFO L82 PathProgramCache]: Analyzing trace with hash -389009619, now seen corresponding path program 1 times [2020-11-28 03:03:23,784 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,786 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599339987] [2020-11-28 03:03:23,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:23,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:23,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:23,906 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599339987] [2020-11-28 03:03:23,907 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:23,908 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:23,909 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304051821] [2020-11-28 03:03:23,909 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:23,909 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:23,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:23,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:23,912 INFO L87 Difference]: Start difference. First operand 413 states and 627 transitions. cyclomatic complexity: 215 Second operand 3 states. [2020-11-28 03:03:23,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:23,927 INFO L93 Difference]: Finished difference Result 413 states and 626 transitions. [2020-11-28 03:03:23,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:23,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 626 transitions. [2020-11-28 03:03:23,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 626 transitions. [2020-11-28 03:03:23,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2020-11-28 03:03:23,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2020-11-28 03:03:23,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 626 transitions. [2020-11-28 03:03:23,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:23,943 INFO L691 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2020-11-28 03:03:23,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 626 transitions. [2020-11-28 03:03:23,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2020-11-28 03:03:23,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2020-11-28 03:03:23,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 626 transitions. [2020-11-28 03:03:23,955 INFO L714 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2020-11-28 03:03:23,959 INFO L594 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2020-11-28 03:03:23,960 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 03:03:23,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 626 transitions. [2020-11-28 03:03:23,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:23,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:23,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:23,967 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,967 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:23,968 INFO L794 eck$LassoCheckResult]: Stem: 3717#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3678#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3679#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3705#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 3477#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3478#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3383#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3384#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3626#L377-1 assume !(0 == ~M_E~0); 3602#L518-1 assume !(0 == ~T1_E~0); 3461#L523-1 assume !(0 == ~T2_E~0); 3462#L528-1 assume !(0 == ~T3_E~0); 3484#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3485#L538-1 assume !(0 == ~E_M~0); 3405#L543-1 assume !(0 == ~E_1~0); 3406#L548-1 assume !(0 == ~E_2~0); 3634#L553-1 assume !(0 == ~E_3~0); 3635#L558-1 assume !(0 == ~E_4~0); 3514#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3515#L254 assume 1 == ~m_pc~0; 3505#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3506#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3508#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3509#L641 assume !(0 != activate_threads_~tmp~1); 3648#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3649#L273 assume !(1 == ~t1_pc~0); 3674#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 3675#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3676#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3677#L649 assume !(0 != activate_threads_~tmp___0~0); 3724#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3455#L292 assume 1 == ~t2_pc~0; 3456#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3419#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3420#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3751#L657 assume !(0 != activate_threads_~tmp___1~0); 3760#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3627#L311 assume !(1 == ~t3_pc~0); 3388#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 3387#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3385#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3348#L665 assume !(0 != activate_threads_~tmp___2~0); 3349#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3350#L330 assume 1 == ~t4_pc~0; 3592#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3593#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3591#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3531#L673 assume !(0 != activate_threads_~tmp___3~0); 3532#L673-2 assume !(1 == ~M_E~0); 3414#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3415#L581-1 assume !(1 == ~T2_E~0); 3630#L586-1 assume !(1 == ~T3_E~0); 3631#L591-1 assume !(1 == ~T4_E~0); 3512#L596-1 assume !(1 == ~E_M~0); 3513#L601-1 assume !(1 == ~E_1~0); 3599#L606-1 assume !(1 == ~E_2~0); 3457#L611-1 assume !(1 == ~E_3~0); 3458#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3417#L807-1 [2020-11-28 03:03:23,968 INFO L796 eck$LassoCheckResult]: Loop: 3417#L807-1 assume !false; 3355#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3356#L493 assume !false; 3701#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3490#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3441#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3702#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3645#L432 assume !(0 != eval_~tmp~0); 3517#L508 start_simulation_~kernel_st~0 := 2; 3518#L350-1 start_simulation_~kernel_st~0 := 3; 3589#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3590#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3434#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3435#L528-3 assume !(0 == ~T3_E~0); 3487#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3488#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3409#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3410#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3640#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3641#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3522#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3523#L254-18 assume !(1 == ~m_pc~0); 3537#L254-20 is_master_triggered_~__retres1~0 := 0; 3538#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3580#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3621#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3607#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3608#L273-18 assume 1 == ~t1_pc~0; 3686#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3687#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3689#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3690#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3713#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3714#L292-18 assume 1 == ~t2_pc~0; 3740#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3741#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3738#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3739#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3753#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3418#L311-18 assume !(1 == ~t3_pc~0); 3377#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 3376#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3373#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3374#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3473#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3474#L330-18 assume !(1 == ~t4_pc~0); 3585#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 3584#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3581#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3582#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3652#L673-20 assume !(1 == ~M_E~0); 3407#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3408#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3636#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3637#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3519#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3520#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3600#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3459#L611-3 assume !(1 == ~E_3~0); 3460#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3353#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3354#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3446#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3703#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3710#L826 assume !(0 == start_simulation_~tmp~3); 3706#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3475#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3452#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3704#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 3723#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3725#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 3727#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3650#L839 assume !(0 != start_simulation_~tmp___0~1); 3417#L807-1 [2020-11-28 03:03:23,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:23,969 INFO L82 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2020-11-28 03:03:23,975 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:23,976 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53022434] [2020-11-28 03:03:23,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,041 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53022434] [2020-11-28 03:03:24,041 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,042 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:24,042 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378290425] [2020-11-28 03:03:24,042 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:24,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,043 INFO L82 PathProgramCache]: Analyzing trace with hash -389009619, now seen corresponding path program 2 times [2020-11-28 03:03:24,043 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,044 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429470186] [2020-11-28 03:03:24,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,096 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429470186] [2020-11-28 03:03:24,096 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,096 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,096 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282969536] [2020-11-28 03:03:24,097 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:24,097 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:24,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:24,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:24,098 INFO L87 Difference]: Start difference. First operand 413 states and 626 transitions. cyclomatic complexity: 214 Second operand 3 states. [2020-11-28 03:03:24,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:24,119 INFO L93 Difference]: Finished difference Result 413 states and 621 transitions. [2020-11-28 03:03:24,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:24,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 621 transitions. [2020-11-28 03:03:24,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:24,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 621 transitions. [2020-11-28 03:03:24,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2020-11-28 03:03:24,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2020-11-28 03:03:24,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 621 transitions. [2020-11-28 03:03:24,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:24,130 INFO L691 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2020-11-28 03:03:24,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 621 transitions. [2020-11-28 03:03:24,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2020-11-28 03:03:24,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2020-11-28 03:03:24,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 621 transitions. [2020-11-28 03:03:24,141 INFO L714 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2020-11-28 03:03:24,141 INFO L594 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2020-11-28 03:03:24,142 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 03:03:24,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 621 transitions. [2020-11-28 03:03:24,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2020-11-28 03:03:24,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:24,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:24,147 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,147 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,148 INFO L794 eck$LassoCheckResult]: Stem: 4550#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4511#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4512#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4538#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 4310#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4311#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4216#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4217#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4457#L377-1 assume !(0 == ~M_E~0); 4435#L518-1 assume !(0 == ~T1_E~0); 4294#L523-1 assume !(0 == ~T2_E~0); 4295#L528-1 assume !(0 == ~T3_E~0); 4316#L533-1 assume !(0 == ~T4_E~0); 4317#L538-1 assume !(0 == ~E_M~0); 4238#L543-1 assume !(0 == ~E_1~0); 4239#L548-1 assume !(0 == ~E_2~0); 4467#L553-1 assume !(0 == ~E_3~0); 4468#L558-1 assume !(0 == ~E_4~0); 4347#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4348#L254 assume 1 == ~m_pc~0; 4338#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4339#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4341#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4342#L641 assume !(0 != activate_threads_~tmp~1); 4481#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4482#L273 assume !(1 == ~t1_pc~0); 4507#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 4508#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4509#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4510#L649 assume !(0 != activate_threads_~tmp___0~0); 4557#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4288#L292 assume 1 == ~t2_pc~0; 4289#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4252#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4253#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4582#L657 assume !(0 != activate_threads_~tmp___1~0); 4593#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4460#L311 assume !(1 == ~t3_pc~0); 4221#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 4220#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4218#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4181#L665 assume !(0 != activate_threads_~tmp___2~0); 4182#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4183#L330 assume 1 == ~t4_pc~0; 4425#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4426#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4424#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4364#L673 assume !(0 != activate_threads_~tmp___3~0); 4365#L673-2 assume !(1 == ~M_E~0); 4247#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4248#L581-1 assume !(1 == ~T2_E~0); 4463#L586-1 assume !(1 == ~T3_E~0); 4464#L591-1 assume !(1 == ~T4_E~0); 4345#L596-1 assume !(1 == ~E_M~0); 4346#L601-1 assume !(1 == ~E_1~0); 4432#L606-1 assume !(1 == ~E_2~0); 4290#L611-1 assume !(1 == ~E_3~0); 4291#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4250#L807-1 [2020-11-28 03:03:24,148 INFO L796 eck$LassoCheckResult]: Loop: 4250#L807-1 assume !false; 4188#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4189#L493 assume !false; 4534#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4323#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4272#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4535#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4478#L432 assume !(0 != eval_~tmp~0); 4349#L508 start_simulation_~kernel_st~0 := 2; 4350#L350-1 start_simulation_~kernel_st~0 := 3; 4422#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4423#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4265#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4266#L528-3 assume !(0 == ~T3_E~0); 4320#L533-3 assume !(0 == ~T4_E~0); 4321#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4242#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4243#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4475#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4476#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4355#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4356#L254-18 assume !(1 == ~m_pc~0); 4370#L254-20 is_master_triggered_~__retres1~0 := 0; 4371#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4415#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4454#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4440#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4441#L273-18 assume 1 == ~t1_pc~0; 4519#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4520#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4522#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4523#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4546#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4547#L292-18 assume 1 == ~t2_pc~0; 4573#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4574#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4571#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4572#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4586#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4251#L311-18 assume 1 == ~t3_pc~0; 4208#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4209#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4206#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4207#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4306#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4307#L330-18 assume 1 == ~t4_pc~0; 4416#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4417#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4413#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4414#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4485#L673-20 assume !(1 == ~M_E~0); 4240#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4241#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4469#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4470#L591-3 assume !(1 == ~T4_E~0); 4352#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4353#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4433#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4292#L611-3 assume !(1 == ~E_3~0); 4293#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4186#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4187#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4279#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4536#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4543#L826 assume !(0 == start_simulation_~tmp~3); 4539#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4308#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4285#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4537#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 4556#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4558#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 4560#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4483#L839 assume !(0 != start_simulation_~tmp___0~1); 4250#L807-1 [2020-11-28 03:03:24,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2020-11-28 03:03:24,149 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,149 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318915480] [2020-11-28 03:03:24,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,198 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318915480] [2020-11-28 03:03:24,199 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,199 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:24,199 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151619914] [2020-11-28 03:03:24,200 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:24,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,201 INFO L82 PathProgramCache]: Analyzing trace with hash 419835699, now seen corresponding path program 1 times [2020-11-28 03:03:24,201 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,201 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225045635] [2020-11-28 03:03:24,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,289 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225045635] [2020-11-28 03:03:24,289 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,289 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,290 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237904184] [2020-11-28 03:03:24,290 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:24,290 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:24,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:24,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:24,292 INFO L87 Difference]: Start difference. First operand 413 states and 621 transitions. cyclomatic complexity: 209 Second operand 3 states. [2020-11-28 03:03:24,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:24,385 INFO L93 Difference]: Finished difference Result 748 states and 1108 transitions. [2020-11-28 03:03:24,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:24,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 748 states and 1108 transitions. [2020-11-28 03:03:24,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 685 [2020-11-28 03:03:24,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 748 states to 748 states and 1108 transitions. [2020-11-28 03:03:24,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 748 [2020-11-28 03:03:24,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 748 [2020-11-28 03:03:24,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 748 states and 1108 transitions. [2020-11-28 03:03:24,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:24,405 INFO L691 BuchiCegarLoop]: Abstraction has 748 states and 1108 transitions. [2020-11-28 03:03:24,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 748 states and 1108 transitions. [2020-11-28 03:03:24,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 748 to 715. [2020-11-28 03:03:24,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 715 states. [2020-11-28 03:03:24,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 715 states to 715 states and 1062 transitions. [2020-11-28 03:03:24,427 INFO L714 BuchiCegarLoop]: Abstraction has 715 states and 1062 transitions. [2020-11-28 03:03:24,427 INFO L594 BuchiCegarLoop]: Abstraction has 715 states and 1062 transitions. [2020-11-28 03:03:24,427 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 03:03:24,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 715 states and 1062 transitions. [2020-11-28 03:03:24,432 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2020-11-28 03:03:24,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:24,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:24,434 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,434 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,435 INFO L794 eck$LassoCheckResult]: Stem: 5730#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5689#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5690#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5716#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 5478#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5479#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5384#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5385#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5619#L377-1 assume !(0 == ~M_E~0); 5597#L518-1 assume !(0 == ~T1_E~0); 5462#L523-1 assume !(0 == ~T2_E~0); 5463#L528-1 assume !(0 == ~T3_E~0); 5485#L533-1 assume !(0 == ~T4_E~0); 5486#L538-1 assume !(0 == ~E_M~0); 5406#L543-1 assume !(0 == ~E_1~0); 5407#L548-1 assume !(0 == ~E_2~0); 5629#L553-1 assume !(0 == ~E_3~0); 5630#L558-1 assume !(0 == ~E_4~0); 5511#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5512#L254 assume !(1 == ~m_pc~0); 5545#L254-2 is_master_triggered_~__retres1~0 := 0; 5546#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5505#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5506#L641 assume !(0 != activate_threads_~tmp~1); 5644#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5645#L273 assume !(1 == ~t1_pc~0); 5685#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 5686#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5687#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5688#L649 assume !(0 != activate_threads_~tmp___0~0); 5737#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5456#L292 assume 1 == ~t2_pc~0; 5457#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5420#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5421#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5763#L657 assume !(0 != activate_threads_~tmp___1~0); 5776#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5622#L311 assume !(1 == ~t3_pc~0); 5389#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 5388#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5386#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5349#L665 assume !(0 != activate_threads_~tmp___2~0); 5350#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5351#L330 assume 1 == ~t4_pc~0; 5587#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5588#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5586#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5527#L673 assume !(0 != activate_threads_~tmp___3~0); 5528#L673-2 assume !(1 == ~M_E~0); 5415#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5416#L581-1 assume !(1 == ~T2_E~0); 5625#L586-1 assume !(1 == ~T3_E~0); 5626#L591-1 assume !(1 == ~T4_E~0); 5509#L596-1 assume !(1 == ~E_M~0); 5510#L601-1 assume !(1 == ~E_1~0); 5594#L606-1 assume !(1 == ~E_2~0); 5458#L611-1 assume !(1 == ~E_3~0); 5459#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5418#L807-1 [2020-11-28 03:03:24,435 INFO L796 eck$LassoCheckResult]: Loop: 5418#L807-1 assume !false; 5356#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5357#L493 assume !false; 5712#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5491#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5442#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5713#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5640#L432 assume !(0 != eval_~tmp~0); 5514#L508 start_simulation_~kernel_st~0 := 2; 5515#L350-1 start_simulation_~kernel_st~0 := 3; 5584#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5585#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5433#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5434#L528-3 assume !(0 == ~T3_E~0); 5488#L533-3 assume !(0 == ~T4_E~0); 5489#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5410#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5411#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5637#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5638#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5519#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5520#L254-18 assume !(1 == ~m_pc~0); 5532#L254-20 is_master_triggered_~__retres1~0 := 0; 5533#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5577#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5616#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5602#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5603#L273-18 assume 1 == ~t1_pc~0; 5697#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5698#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5700#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5701#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5726#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5727#L292-18 assume 1 == ~t2_pc~0; 5753#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5754#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5751#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5752#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5767#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5419#L311-18 assume 1 == ~t3_pc~0; 5376#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5377#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5374#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5375#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5474#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5475#L330-18 assume 1 == ~t4_pc~0; 5578#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5579#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5575#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5576#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5653#L673-20 assume !(1 == ~M_E~0); 5408#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5409#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5631#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5632#L591-3 assume !(1 == ~T4_E~0); 5516#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5517#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5595#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5460#L611-3 assume !(1 == ~E_3~0); 5461#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5354#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5355#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5447#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5714#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5723#L826 assume !(0 == start_simulation_~tmp~3); 5719#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5476#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5453#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5715#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 5736#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5738#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 5740#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5646#L839 assume !(0 != start_simulation_~tmp___0~1); 5418#L807-1 [2020-11-28 03:03:24,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2020-11-28 03:03:24,436 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,443 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316950339] [2020-11-28 03:03:24,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,484 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316950339] [2020-11-28 03:03:24,485 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,487 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,488 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029689987] [2020-11-28 03:03:24,488 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:24,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,490 INFO L82 PathProgramCache]: Analyzing trace with hash 419835699, now seen corresponding path program 2 times [2020-11-28 03:03:24,491 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,491 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565876610] [2020-11-28 03:03:24,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,530 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565876610] [2020-11-28 03:03:24,530 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,532 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,533 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815179557] [2020-11-28 03:03:24,533 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:24,533 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:24,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:24,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:24,534 INFO L87 Difference]: Start difference. First operand 715 states and 1062 transitions. cyclomatic complexity: 349 Second operand 4 states. [2020-11-28 03:03:24,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:24,779 INFO L93 Difference]: Finished difference Result 1618 states and 2368 transitions. [2020-11-28 03:03:24,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:24,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1618 states and 2368 transitions. [2020-11-28 03:03:24,797 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1515 [2020-11-28 03:03:24,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1618 states to 1618 states and 2368 transitions. [2020-11-28 03:03:24,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1618 [2020-11-28 03:03:24,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1618 [2020-11-28 03:03:24,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1618 states and 2368 transitions. [2020-11-28 03:03:24,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:24,820 INFO L691 BuchiCegarLoop]: Abstraction has 1618 states and 2368 transitions. [2020-11-28 03:03:24,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states and 2368 transitions. [2020-11-28 03:03:24,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1281. [2020-11-28 03:03:24,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1281 states. [2020-11-28 03:03:24,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 1889 transitions. [2020-11-28 03:03:24,854 INFO L714 BuchiCegarLoop]: Abstraction has 1281 states and 1889 transitions. [2020-11-28 03:03:24,854 INFO L594 BuchiCegarLoop]: Abstraction has 1281 states and 1889 transitions. [2020-11-28 03:03:24,854 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 03:03:24,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1281 states and 1889 transitions. [2020-11-28 03:03:24,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1218 [2020-11-28 03:03:24,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:24,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:24,863 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,863 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:24,864 INFO L794 eck$LassoCheckResult]: Stem: 8074#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8034#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8035#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8061#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 7817#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7818#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7727#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7728#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7958#L377-1 assume !(0 == ~M_E~0); 7936#L518-1 assume !(0 == ~T1_E~0); 7803#L523-1 assume !(0 == ~T2_E~0); 7804#L528-1 assume !(0 == ~T3_E~0); 7825#L533-1 assume !(0 == ~T4_E~0); 7826#L538-1 assume !(0 == ~E_M~0); 7749#L543-1 assume !(0 == ~E_1~0); 7750#L548-1 assume !(0 == ~E_2~0); 7968#L553-1 assume !(0 == ~E_3~0); 7969#L558-1 assume !(0 == ~E_4~0); 7852#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7853#L254 assume !(1 == ~m_pc~0); 7885#L254-2 is_master_triggered_~__retres1~0 := 0; 7886#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7846#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7847#L641 assume !(0 != activate_threads_~tmp~1); 7983#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7984#L273 assume !(1 == ~t1_pc~0); 8030#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 8031#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8032#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8033#L649 assume !(0 != activate_threads_~tmp___0~0); 8082#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7798#L292 assume !(1 == ~t2_pc~0); 7788#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 7763#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7764#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8111#L657 assume !(0 != activate_threads_~tmp___1~0); 8136#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7961#L311 assume !(1 == ~t3_pc~0); 7732#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 7731#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7729#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7692#L665 assume !(0 != activate_threads_~tmp___2~0); 7693#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7694#L330 assume 1 == ~t4_pc~0; 7926#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7927#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7925#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7866#L673 assume !(0 != activate_threads_~tmp___3~0); 7867#L673-2 assume !(1 == ~M_E~0); 7758#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7759#L581-1 assume !(1 == ~T2_E~0); 7964#L586-1 assume !(1 == ~T3_E~0); 7965#L591-1 assume !(1 == ~T4_E~0); 7850#L596-1 assume !(1 == ~E_M~0); 7851#L601-1 assume !(1 == ~E_1~0); 7933#L606-1 assume !(1 == ~E_2~0); 7799#L611-1 assume !(1 == ~E_3~0); 7800#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7761#L807-1 [2020-11-28 03:03:24,864 INFO L796 eck$LassoCheckResult]: Loop: 7761#L807-1 assume !false; 7699#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7700#L493 assume !false; 8057#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7832#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7783#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 8058#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7979#L432 assume !(0 != eval_~tmp~0); 7854#L508 start_simulation_~kernel_st~0 := 2; 7855#L350-1 start_simulation_~kernel_st~0 := 3; 7923#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7924#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7776#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7777#L528-3 assume !(0 == ~T3_E~0); 7829#L533-3 assume !(0 == ~T4_E~0); 7830#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7753#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7754#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7976#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7977#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7860#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7861#L254-18 assume !(1 == ~m_pc~0); 7873#L254-20 is_master_triggered_~__retres1~0 := 0; 7874#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7914#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7955#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7941#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7942#L273-18 assume 1 == ~t1_pc~0; 8042#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8043#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8045#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8046#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8070#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8071#L292-18 assume !(1 == ~t2_pc~0); 8120#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 8121#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8097#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8098#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8129#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7762#L311-18 assume 1 == ~t3_pc~0; 7719#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7720#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7717#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7718#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7815#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7816#L330-18 assume 1 == ~t4_pc~0; 7917#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7918#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7915#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7916#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7994#L673-20 assume !(1 == ~M_E~0); 7751#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7752#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7970#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7971#L591-3 assume !(1 == ~T4_E~0); 7857#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7858#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7934#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7801#L611-3 assume !(1 == ~E_3~0); 7802#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7697#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7698#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7790#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 8059#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 8067#L826 assume !(0 == start_simulation_~tmp~3); 8063#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7819#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7795#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 8060#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 8081#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 8083#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 8085#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7985#L839 assume !(0 != start_simulation_~tmp___0~1); 7761#L807-1 [2020-11-28 03:03:24,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,865 INFO L82 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2020-11-28 03:03:24,865 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,865 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292821836] [2020-11-28 03:03:24,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,911 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292821836] [2020-11-28 03:03:24,911 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,911 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,912 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130788648] [2020-11-28 03:03:24,912 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:24,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:24,913 INFO L82 PathProgramCache]: Analyzing trace with hash 819826898, now seen corresponding path program 1 times [2020-11-28 03:03:24,913 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:24,913 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143349512] [2020-11-28 03:03:24,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:24,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:24,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:24,950 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143349512] [2020-11-28 03:03:24,952 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:24,953 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:24,953 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124907002] [2020-11-28 03:03:24,953 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:24,954 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:24,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:24,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:24,954 INFO L87 Difference]: Start difference. First operand 1281 states and 1889 transitions. cyclomatic complexity: 610 Second operand 4 states. [2020-11-28 03:03:25,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:25,154 INFO L93 Difference]: Finished difference Result 2909 states and 4235 transitions. [2020-11-28 03:03:25,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:25,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2909 states and 4235 transitions. [2020-11-28 03:03:25,184 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2766 [2020-11-28 03:03:25,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2909 states to 2909 states and 4235 transitions. [2020-11-28 03:03:25,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2909 [2020-11-28 03:03:25,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2909 [2020-11-28 03:03:25,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2909 states and 4235 transitions. [2020-11-28 03:03:25,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:25,221 INFO L691 BuchiCegarLoop]: Abstraction has 2909 states and 4235 transitions. [2020-11-28 03:03:25,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2909 states and 4235 transitions. [2020-11-28 03:03:25,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2909 to 2332. [2020-11-28 03:03:25,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2332 states. [2020-11-28 03:03:25,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2332 states to 2332 states and 3420 transitions. [2020-11-28 03:03:25,274 INFO L714 BuchiCegarLoop]: Abstraction has 2332 states and 3420 transitions. [2020-11-28 03:03:25,274 INFO L594 BuchiCegarLoop]: Abstraction has 2332 states and 3420 transitions. [2020-11-28 03:03:25,274 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 03:03:25,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2332 states and 3420 transitions. [2020-11-28 03:03:25,288 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2268 [2020-11-28 03:03:25,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:25,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:25,290 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:25,291 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:25,291 INFO L794 eck$LassoCheckResult]: Stem: 12311#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12252#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12253#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12280#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 12021#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12022#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11927#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11928#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12174#L377-1 assume !(0 == ~M_E~0); 12144#L518-1 assume !(0 == ~T1_E~0); 12006#L523-1 assume !(0 == ~T2_E~0); 12007#L528-1 assume !(0 == ~T3_E~0); 12031#L533-1 assume !(0 == ~T4_E~0); 12032#L538-1 assume !(0 == ~E_M~0); 11949#L543-1 assume !(0 == ~E_1~0); 11950#L548-1 assume !(0 == ~E_2~0); 12185#L553-1 assume !(0 == ~E_3~0); 12186#L558-1 assume !(0 == ~E_4~0); 12059#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12060#L254 assume !(1 == ~m_pc~0); 12094#L254-2 is_master_triggered_~__retres1~0 := 0; 12095#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12053#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12054#L641 assume !(0 != activate_threads_~tmp~1); 12200#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12201#L273 assume !(1 == ~t1_pc~0); 12248#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 12249#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12250#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12251#L649 assume !(0 != activate_threads_~tmp___0~0); 12322#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12001#L292 assume !(1 == ~t2_pc~0); 11991#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 11965#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11966#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12349#L657 assume !(0 != activate_threads_~tmp___1~0); 12370#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12177#L311 assume !(1 == ~t3_pc~0); 11932#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 11931#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11929#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11892#L665 assume !(0 != activate_threads_~tmp___2~0); 11893#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11894#L330 assume !(1 == ~t4_pc~0); 12312#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 12313#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12134#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12074#L673 assume !(0 != activate_threads_~tmp___3~0); 12075#L673-2 assume !(1 == ~M_E~0); 11958#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11959#L581-1 assume !(1 == ~T2_E~0); 12181#L586-1 assume !(1 == ~T3_E~0); 12182#L591-1 assume !(1 == ~T4_E~0); 12057#L596-1 assume !(1 == ~E_M~0); 12058#L601-1 assume !(1 == ~E_1~0); 12141#L606-1 assume !(1 == ~E_2~0); 12002#L611-1 assume !(1 == ~E_3~0); 12003#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11963#L807-1 [2020-11-28 03:03:25,291 INFO L796 eck$LassoCheckResult]: Loop: 11963#L807-1 assume !false; 11899#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11900#L493 assume !false; 12275#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12039#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11985#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12276#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12196#L432 assume !(0 != eval_~tmp~0); 12061#L508 start_simulation_~kernel_st~0 := 2; 12062#L350-1 start_simulation_~kernel_st~0 := 3; 12132#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12133#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11978#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11979#L528-3 assume !(0 == ~T3_E~0); 12036#L533-3 assume !(0 == ~T4_E~0); 12037#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11953#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11954#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12193#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12194#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12068#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12069#L254-18 assume !(1 == ~m_pc~0); 12081#L254-20 is_master_triggered_~__retres1~0 := 0; 12082#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12122#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12171#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12149#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12150#L273-18 assume 1 == ~t1_pc~0; 12260#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12261#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12263#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12264#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12304#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12306#L292-18 assume !(1 == ~t2_pc~0); 12356#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 14163#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14161#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14158#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14156#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14154#L311-18 assume 1 == ~t3_pc~0; 14151#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12163#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12164#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13938#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13937#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12285#L330-18 assume !(1 == ~t4_pc~0); 12286#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 12287#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12123#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12124#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12211#L673-20 assume !(1 == ~M_E~0); 11951#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11952#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12187#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12188#L591-3 assume !(1 == ~T4_E~0); 12065#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12066#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12142#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12004#L611-3 assume !(1 == ~E_3~0); 12005#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11897#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11898#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11993#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12277#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 12297#L826 assume !(0 == start_simulation_~tmp~3); 12284#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12023#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11998#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12278#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 12321#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 12323#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 12325#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 12202#L839 assume !(0 != start_simulation_~tmp___0~1); 11963#L807-1 [2020-11-28 03:03:25,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:25,292 INFO L82 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2020-11-28 03:03:25,292 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:25,292 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475457341] [2020-11-28 03:03:25,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:25,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:25,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:25,331 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475457341] [2020-11-28 03:03:25,331 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:25,331 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:25,331 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001414398] [2020-11-28 03:03:25,332 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:25,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:25,333 INFO L82 PathProgramCache]: Analyzing trace with hash 511387889, now seen corresponding path program 1 times [2020-11-28 03:03:25,333 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:25,333 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116340052] [2020-11-28 03:03:25,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:25,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:25,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:25,360 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116340052] [2020-11-28 03:03:25,361 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:25,361 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:25,361 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134545970] [2020-11-28 03:03:25,361 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:25,362 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:25,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:25,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:25,362 INFO L87 Difference]: Start difference. First operand 2332 states and 3420 transitions. cyclomatic complexity: 1090 Second operand 4 states. [2020-11-28 03:03:25,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:25,515 INFO L93 Difference]: Finished difference Result 4697 states and 6854 transitions. [2020-11-28 03:03:25,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:25,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4697 states and 6854 transitions. [2020-11-28 03:03:25,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4536 [2020-11-28 03:03:25,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4697 states to 4697 states and 6854 transitions. [2020-11-28 03:03:25,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4697 [2020-11-28 03:03:25,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4697 [2020-11-28 03:03:25,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4697 states and 6854 transitions. [2020-11-28 03:03:25,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:25,613 INFO L691 BuchiCegarLoop]: Abstraction has 4697 states and 6854 transitions. [2020-11-28 03:03:25,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4697 states and 6854 transitions. [2020-11-28 03:03:25,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4697 to 4697. [2020-11-28 03:03:25,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4697 states. [2020-11-28 03:03:25,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4697 states to 4697 states and 6854 transitions. [2020-11-28 03:03:25,724 INFO L714 BuchiCegarLoop]: Abstraction has 4697 states and 6854 transitions. [2020-11-28 03:03:25,724 INFO L594 BuchiCegarLoop]: Abstraction has 4697 states and 6854 transitions. [2020-11-28 03:03:25,724 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 03:03:25,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4697 states and 6854 transitions. [2020-11-28 03:03:25,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4536 [2020-11-28 03:03:25,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:25,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:25,746 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:25,746 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:25,747 INFO L794 eck$LassoCheckResult]: Stem: 19355#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 19297#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19298#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19329#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 19063#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19064#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18967#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18968#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19220#L377-1 assume 0 == ~M_E~0;~M_E~0 := 1; 19221#L518-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19191#L523-1 assume !(0 == ~T2_E~0); 19488#L528-1 assume !(0 == ~T3_E~0); 19487#L533-1 assume !(0 == ~T4_E~0); 19486#L538-1 assume !(0 == ~E_M~0); 19485#L543-1 assume !(0 == ~E_1~0); 19484#L548-1 assume !(0 == ~E_2~0); 19483#L553-1 assume !(0 == ~E_3~0); 19482#L558-1 assume !(0 == ~E_4~0); 19481#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19480#L254 assume !(1 == ~m_pc~0); 19479#L254-2 is_master_triggered_~__retres1~0 := 0; 19478#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19477#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19476#L641 assume !(0 != activate_threads_~tmp~1); 19475#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19474#L273 assume !(1 == ~t1_pc~0); 19472#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 19471#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19470#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19469#L649 assume !(0 != activate_threads_~tmp___0~0); 19468#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19467#L292 assume !(1 == ~t2_pc~0); 19466#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 19465#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19464#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19463#L657 assume !(0 != activate_threads_~tmp___1~0); 19462#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19461#L311 assume !(1 == ~t3_pc~0); 19459#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 19458#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19457#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 19456#L665 assume !(0 != activate_threads_~tmp___2~0); 19455#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19454#L330 assume !(1 == ~t4_pc~0); 19453#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 19452#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19451#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 19450#L673 assume !(0 != activate_threads_~tmp___3~0); 19449#L673-2 assume !(1 == ~M_E~0); 19447#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19448#L581-1 assume !(1 == ~T2_E~0); 22193#L586-1 assume !(1 == ~T3_E~0); 22192#L591-1 assume !(1 == ~T4_E~0); 22191#L596-1 assume !(1 == ~E_M~0); 22190#L601-1 assume !(1 == ~E_1~0); 22189#L606-1 assume !(1 == ~E_2~0); 22188#L611-1 assume !(1 == ~E_3~0); 21885#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21884#L807-1 [2020-11-28 03:03:25,747 INFO L796 eck$LassoCheckResult]: Loop: 21884#L807-1 assume !false; 21883#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 21880#L493 assume !false; 21879#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21878#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21873#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21872#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 21870#L432 assume !(0 != eval_~tmp~0); 21871#L508 start_simulation_~kernel_st~0 := 2; 23308#L350-1 start_simulation_~kernel_st~0 := 3; 23309#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20896#L518-4 assume !(0 == ~T1_E~0); 20897#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23614#L528-3 assume !(0 == ~T3_E~0); 23612#L533-3 assume !(0 == ~T4_E~0); 23610#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23608#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23606#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23604#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23602#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23600#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23598#L254-18 assume !(1 == ~m_pc~0); 23596#L254-20 is_master_triggered_~__retres1~0 := 0; 23594#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19273#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19214#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19215#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23585#L273-18 assume 1 == ~t1_pc~0; 23569#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23568#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23567#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23566#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19349#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19350#L292-18 assume !(1 == ~t2_pc~0); 20779#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 20778#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20777#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20775#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20773#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20771#L311-18 assume 1 == ~t3_pc~0; 20766#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20763#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20751#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20745#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20739#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20735#L330-18 assume !(1 == ~t4_pc~0); 20733#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 20731#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20729#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20727#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20722#L673-20 assume !(1 == ~M_E~0); 20723#L576-3 assume !(1 == ~T1_E~0); 20684#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22907#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22906#L591-3 assume !(1 == ~T4_E~0); 22905#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22904#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22903#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22902#L611-3 assume !(1 == ~E_3~0); 22901#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22900#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22899#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22894#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20654#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 20639#L826 assume !(0 == start_simulation_~tmp~3); 20636#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20637#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21891#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21890#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 21889#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 21888#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 21887#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 21886#L839 assume !(0 != start_simulation_~tmp___0~1); 21884#L807-1 [2020-11-28 03:03:25,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:25,748 INFO L82 PathProgramCache]: Analyzing trace with hash -323288768, now seen corresponding path program 1 times [2020-11-28 03:03:25,748 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:25,748 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849583110] [2020-11-28 03:03:25,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:25,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:25,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:25,771 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849583110] [2020-11-28 03:03:25,771 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:25,771 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:25,771 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380326545] [2020-11-28 03:03:25,772 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:25,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:25,772 INFO L82 PathProgramCache]: Analyzing trace with hash 1409514861, now seen corresponding path program 1 times [2020-11-28 03:03:25,772 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:25,772 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337400151] [2020-11-28 03:03:25,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:25,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:25,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:25,833 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337400151] [2020-11-28 03:03:25,833 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:25,833 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:25,833 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103777082] [2020-11-28 03:03:25,834 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:25,834 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:25,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:25,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:25,835 INFO L87 Difference]: Start difference. First operand 4697 states and 6854 transitions. cyclomatic complexity: 2161 Second operand 3 states. [2020-11-28 03:03:25,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:25,902 INFO L93 Difference]: Finished difference Result 6998 states and 10211 transitions. [2020-11-28 03:03:25,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:25,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6998 states and 10211 transitions. [2020-11-28 03:03:25,955 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6876 [2020-11-28 03:03:26,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6998 states to 6998 states and 10211 transitions. [2020-11-28 03:03:26,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6998 [2020-11-28 03:03:26,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6998 [2020-11-28 03:03:26,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6998 states and 10211 transitions. [2020-11-28 03:03:26,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:26,039 INFO L691 BuchiCegarLoop]: Abstraction has 6998 states and 10211 transitions. [2020-11-28 03:03:26,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6998 states and 10211 transitions. [2020-11-28 03:03:26,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6998 to 5066. [2020-11-28 03:03:26,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5066 states. [2020-11-28 03:03:26,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5066 states to 5066 states and 7404 transitions. [2020-11-28 03:03:26,222 INFO L714 BuchiCegarLoop]: Abstraction has 5066 states and 7404 transitions. [2020-11-28 03:03:26,222 INFO L594 BuchiCegarLoop]: Abstraction has 5066 states and 7404 transitions. [2020-11-28 03:03:26,222 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 03:03:26,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5066 states and 7404 transitions. [2020-11-28 03:03:26,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4956 [2020-11-28 03:03:26,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:26,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:26,250 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:26,250 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:26,251 INFO L794 eck$LassoCheckResult]: Stem: 31058#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 30996#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 30997#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 31030#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 30764#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30765#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30669#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30670#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30915#L377-1 assume !(0 == ~M_E~0); 30887#L518-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30888#L523-1 assume !(0 == ~T2_E~0); 31077#L528-1 assume !(0 == ~T3_E~0); 31078#L533-1 assume !(0 == ~T4_E~0); 31157#L538-1 assume !(0 == ~E_M~0); 31156#L543-1 assume !(0 == ~E_1~0); 31126#L548-1 assume !(0 == ~E_2~0); 31127#L553-1 assume !(0 == ~E_3~0); 31155#L558-1 assume !(0 == ~E_4~0); 30802#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30803#L254 assume !(1 == ~m_pc~0); 30837#L254-2 is_master_triggered_~__retres1~0 := 0; 30838#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30845#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 31151#L641 assume !(0 != activate_threads_~tmp~1); 31150#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31026#L273 assume !(1 == ~t1_pc~0); 31027#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 31029#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30994#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30995#L649 assume !(0 != activate_threads_~tmp___0~0); 31075#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30743#L292 assume !(1 == ~t2_pc~0); 30732#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 30733#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31107#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31108#L657 assume !(0 != activate_threads_~tmp___1~0); 31141#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31142#L311 assume !(1 == ~t3_pc~0); 30675#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 30674#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30671#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30672#L665 assume !(0 != activate_threads_~tmp___2~0); 30635#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30636#L330 assume !(1 == ~t4_pc~0); 31059#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 31060#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30879#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30817#L673 assume !(0 != activate_threads_~tmp___3~0); 30818#L673-2 assume !(1 == ~M_E~0); 30824#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30702#L581-1 assume !(1 == ~T2_E~0); 30925#L586-1 assume !(1 == ~T3_E~0); 30926#L591-1 assume !(1 == ~T4_E~0); 30800#L596-1 assume !(1 == ~E_M~0); 30801#L601-1 assume !(1 == ~E_1~0); 30884#L606-1 assume !(1 == ~E_2~0); 30744#L611-1 assume !(1 == ~E_3~0); 30745#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 31076#L807-1 [2020-11-28 03:03:26,252 INFO L796 eck$LassoCheckResult]: Loop: 31076#L807-1 assume !false; 35242#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34884#L493 assume !false; 35241#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30780#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30727#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31021#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 30941#L432 assume !(0 != eval_~tmp~0); 30804#L508 start_simulation_~kernel_st~0 := 2; 30805#L350-1 start_simulation_~kernel_st~0 := 3; 30876#L518-2 assume !(0 == ~M_E~0); 30877#L518-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30878#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35542#L528-3 assume !(0 == ~T3_E~0); 35541#L533-3 assume !(0 == ~T4_E~0); 35540#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35539#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35538#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35537#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35536#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35535#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35534#L254-18 assume !(1 == ~m_pc~0); 35533#L254-20 is_master_triggered_~__retres1~0 := 0; 35532#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35531#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35530#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35529#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35528#L273-18 assume 1 == ~t1_pc~0; 35526#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35525#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35524#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35523#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35522#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35521#L292-18 assume !(1 == ~t2_pc~0); 34050#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 35520#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35519#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35518#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35517#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35516#L311-18 assume 1 == ~t3_pc~0; 35514#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 35513#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35512#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 35511#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35510#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35509#L330-18 assume !(1 == ~t4_pc~0); 34311#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 35508#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35507#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 35506#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 35505#L673-20 assume !(1 == ~M_E~0); 32584#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30695#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30931#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30932#L591-3 assume !(1 == ~T4_E~0); 30807#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30808#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30885#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30746#L611-3 assume !(1 == ~E_3~0); 30747#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30639#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30640#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30735#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31022#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 31045#L826 assume !(0 == start_simulation_~tmp~3); 31034#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30766#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30740#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31023#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 31068#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 31079#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 31082#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 31083#L839 assume !(0 != start_simulation_~tmp___0~1); 31076#L807-1 [2020-11-28 03:03:26,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:26,253 INFO L82 PathProgramCache]: Analyzing trace with hash -804369026, now seen corresponding path program 1 times [2020-11-28 03:03:26,253 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:26,254 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475486906] [2020-11-28 03:03:26,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:26,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:26,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:26,302 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475486906] [2020-11-28 03:03:26,302 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:26,303 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:26,303 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40192418] [2020-11-28 03:03:26,303 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:26,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:26,304 INFO L82 PathProgramCache]: Analyzing trace with hash 93991283, now seen corresponding path program 1 times [2020-11-28 03:03:26,304 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:26,305 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078727204] [2020-11-28 03:03:26,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:26,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:26,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:26,369 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078727204] [2020-11-28 03:03:26,369 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:26,369 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:26,370 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547023208] [2020-11-28 03:03:26,370 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:26,370 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:26,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:26,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:26,371 INFO L87 Difference]: Start difference. First operand 5066 states and 7404 transitions. cyclomatic complexity: 2340 Second operand 4 states. [2020-11-28 03:03:26,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:26,461 INFO L93 Difference]: Finished difference Result 6252 states and 9088 transitions. [2020-11-28 03:03:26,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:26,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6252 states and 9088 transitions. [2020-11-28 03:03:26,497 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6180 [2020-11-28 03:03:26,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6252 states to 6252 states and 9088 transitions. [2020-11-28 03:03:26,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6252 [2020-11-28 03:03:26,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6252 [2020-11-28 03:03:26,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6252 states and 9088 transitions. [2020-11-28 03:03:26,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:26,563 INFO L691 BuchiCegarLoop]: Abstraction has 6252 states and 9088 transitions. [2020-11-28 03:03:26,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6252 states and 9088 transitions. [2020-11-28 03:03:26,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6252 to 4328. [2020-11-28 03:03:26,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4328 states. [2020-11-28 03:03:26,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4328 states to 4328 states and 6304 transitions. [2020-11-28 03:03:26,733 INFO L714 BuchiCegarLoop]: Abstraction has 4328 states and 6304 transitions. [2020-11-28 03:03:26,733 INFO L594 BuchiCegarLoop]: Abstraction has 4328 states and 6304 transitions. [2020-11-28 03:03:26,733 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 03:03:26,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4328 states and 6304 transitions. [2020-11-28 03:03:26,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4260 [2020-11-28 03:03:26,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:26,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:26,754 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:26,755 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:26,755 INFO L794 eck$LassoCheckResult]: Stem: 42371#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 42312#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 42313#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 42342#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 42088#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42089#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41996#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41997#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42241#L377-1 assume !(0 == ~M_E~0); 42214#L518-1 assume !(0 == ~T1_E~0); 42072#L523-1 assume !(0 == ~T2_E~0); 42073#L528-1 assume !(0 == ~T3_E~0); 42096#L533-1 assume !(0 == ~T4_E~0); 42097#L538-1 assume !(0 == ~E_M~0); 42018#L543-1 assume !(0 == ~E_1~0); 42019#L548-1 assume !(0 == ~E_2~0); 42253#L553-1 assume !(0 == ~E_3~0); 42254#L558-1 assume !(0 == ~E_4~0); 42125#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42126#L254 assume !(1 == ~m_pc~0); 42160#L254-2 is_master_triggered_~__retres1~0 := 0; 42161#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42119#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42120#L641 assume !(0 != activate_threads_~tmp~1); 42268#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42269#L273 assume !(1 == ~t1_pc~0); 42308#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 42309#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42310#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42311#L649 assume !(0 != activate_threads_~tmp___0~0); 42383#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42067#L292 assume !(1 == ~t2_pc~0); 42057#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 42032#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42033#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42413#L657 assume !(0 != activate_threads_~tmp___1~0); 42441#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42244#L311 assume !(1 == ~t3_pc~0); 42001#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 42000#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41998#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 41961#L665 assume !(0 != activate_threads_~tmp___2~0); 41962#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41963#L330 assume !(1 == ~t4_pc~0); 42372#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 42373#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42203#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 42140#L673 assume !(0 != activate_threads_~tmp___3~0); 42141#L673-2 assume !(1 == ~M_E~0); 42027#L576-1 assume !(1 == ~T1_E~0); 42028#L581-1 assume !(1 == ~T2_E~0); 42249#L586-1 assume !(1 == ~T3_E~0); 42250#L591-1 assume !(1 == ~T4_E~0); 42123#L596-1 assume !(1 == ~E_M~0); 42124#L601-1 assume !(1 == ~E_1~0); 42210#L606-1 assume !(1 == ~E_2~0); 42068#L611-1 assume !(1 == ~E_3~0); 42069#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 42384#L807-1 [2020-11-28 03:03:26,755 INFO L796 eck$LassoCheckResult]: Loop: 42384#L807-1 assume !false; 46181#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 42075#L493 assume !false; 42335#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 42336#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 45767#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 45739#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 45731#L432 assume !(0 != eval_~tmp~0); 45732#L508 start_simulation_~kernel_st~0 := 2; 46219#L350-1 start_simulation_~kernel_st~0 := 3; 46218#L518-2 assume !(0 == ~M_E~0); 46217#L518-4 assume !(0 == ~T1_E~0); 42045#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42046#L528-3 assume !(0 == ~T3_E~0); 42100#L533-3 assume !(0 == ~T4_E~0); 42101#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42022#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42023#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42261#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42262#L558-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42133#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42134#L254-18 assume !(1 == ~m_pc~0); 42148#L254-20 is_master_triggered_~__retres1~0 := 0; 42149#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42191#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 46242#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 46241#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46240#L273-18 assume 1 == ~t1_pc~0; 46237#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 46236#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42323#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42324#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 42364#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42367#L292-18 assume !(1 == ~t2_pc~0); 42423#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 42424#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42400#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42401#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42432#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42031#L311-18 assume 1 == ~t3_pc~0; 41988#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 41989#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41986#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 41987#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42086#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42087#L330-18 assume !(1 == ~t4_pc~0); 42349#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 42350#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42192#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 42193#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 42274#L673-20 assume !(1 == ~M_E~0); 42020#L576-3 assume !(1 == ~T1_E~0); 42021#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42255#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42256#L591-3 assume !(1 == ~T4_E~0); 42439#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46212#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46211#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42070#L611-3 assume !(1 == ~E_3~0); 42071#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41966#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41967#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 42059#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 42338#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 42357#L826 assume !(0 == start_simulation_~tmp~3); 42358#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 46198#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 46194#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 46192#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 46190#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 46188#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 46186#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 46184#L839 assume !(0 != start_simulation_~tmp___0~1); 42384#L807-1 [2020-11-28 03:03:26,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:26,756 INFO L82 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2020-11-28 03:03:26,756 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:26,756 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680490093] [2020-11-28 03:03:26,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:26,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:26,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:26,793 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680490093] [2020-11-28 03:03:26,793 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:26,794 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:26,794 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503578496] [2020-11-28 03:03:26,794 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:26,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:26,795 INFO L82 PathProgramCache]: Analyzing trace with hash 992118255, now seen corresponding path program 1 times [2020-11-28 03:03:26,795 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:26,795 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551373646] [2020-11-28 03:03:26,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:26,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:26,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:26,821 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551373646] [2020-11-28 03:03:26,821 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:26,821 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:26,822 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227388455] [2020-11-28 03:03:26,822 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:26,822 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:26,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:26,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:26,823 INFO L87 Difference]: Start difference. First operand 4328 states and 6304 transitions. cyclomatic complexity: 1978 Second operand 4 states. [2020-11-28 03:03:27,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:27,008 INFO L93 Difference]: Finished difference Result 6746 states and 9729 transitions. [2020-11-28 03:03:27,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:27,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6746 states and 9729 transitions. [2020-11-28 03:03:27,045 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6624 [2020-11-28 03:03:27,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6746 states to 6746 states and 9729 transitions. [2020-11-28 03:03:27,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6746 [2020-11-28 03:03:27,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6746 [2020-11-28 03:03:27,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6746 states and 9729 transitions. [2020-11-28 03:03:27,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:27,089 INFO L691 BuchiCegarLoop]: Abstraction has 6746 states and 9729 transitions. [2020-11-28 03:03:27,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6746 states and 9729 transitions. [2020-11-28 03:03:27,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6746 to 5058. [2020-11-28 03:03:27,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5058 states. [2020-11-28 03:03:27,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5058 states to 5058 states and 7293 transitions. [2020-11-28 03:03:27,272 INFO L714 BuchiCegarLoop]: Abstraction has 5058 states and 7293 transitions. [2020-11-28 03:03:27,272 INFO L594 BuchiCegarLoop]: Abstraction has 5058 states and 7293 transitions. [2020-11-28 03:03:27,273 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 03:03:27,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5058 states and 7293 transitions. [2020-11-28 03:03:27,293 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4948 [2020-11-28 03:03:27,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:27,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:27,296 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:27,296 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:27,296 INFO L794 eck$LassoCheckResult]: Stem: 53473#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 53409#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53410#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53445#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 53178#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53179#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53081#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53082#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53327#L377-1 assume !(0 == ~M_E~0); 53299#L518-1 assume !(0 == ~T1_E~0); 53160#L523-1 assume !(0 == ~T2_E~0); 53161#L528-1 assume !(0 == ~T3_E~0); 53187#L533-1 assume !(0 == ~T4_E~0); 53188#L538-1 assume !(0 == ~E_M~0); 53104#L543-1 assume !(0 == ~E_1~0); 53105#L548-1 assume !(0 == ~E_2~0); 53340#L553-1 assume !(0 == ~E_3~0); 53341#L558-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53213#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53214#L254 assume !(1 == ~m_pc~0); 53249#L254-2 is_master_triggered_~__retres1~0 := 0; 53250#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53207#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53208#L641 assume !(0 != activate_threads_~tmp~1); 53357#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53358#L273 assume !(1 == ~t1_pc~0); 53405#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 53406#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53407#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53408#L649 assume !(0 != activate_threads_~tmp___0~0); 53493#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53494#L292 assume !(1 == ~t2_pc~0); 53146#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 53147#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53526#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53527#L657 assume !(0 != activate_threads_~tmp___1~0); 53566#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53567#L311 assume !(1 == ~t3_pc~0); 53087#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 53086#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53083#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 53084#L665 assume !(0 != activate_threads_~tmp___2~0); 53047#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53048#L330 assume !(1 == ~t4_pc~0); 53474#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 53475#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53288#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 53289#L673 assume !(0 != activate_threads_~tmp___3~0); 53235#L673-2 assume !(1 == ~M_E~0); 53236#L576-1 assume !(1 == ~T1_E~0); 53545#L581-1 assume !(1 == ~T2_E~0); 53546#L586-1 assume !(1 == ~T3_E~0); 53560#L591-1 assume !(1 == ~T4_E~0); 53561#L596-1 assume !(1 == ~E_M~0); 53536#L601-1 assume !(1 == ~E_1~0); 53537#L606-1 assume !(1 == ~E_2~0); 53156#L611-1 assume !(1 == ~E_3~0); 53157#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53116#L807-1 [2020-11-28 03:03:27,297 INFO L796 eck$LassoCheckResult]: Loop: 53116#L807-1 assume !false; 53053#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 53054#L493 assume !false; 53433#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53193#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53138#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53434#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 53351#L432 assume !(0 != eval_~tmp~0); 53215#L508 start_simulation_~kernel_st~0 := 2; 53216#L350-1 start_simulation_~kernel_st~0 := 3; 53286#L518-2 assume !(0 == ~M_E~0); 53287#L518-4 assume !(0 == ~T1_E~0); 53133#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53134#L528-3 assume !(0 == ~T3_E~0); 53190#L533-3 assume !(0 == ~T4_E~0); 53191#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53108#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53109#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53348#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53349#L558-3 assume !(0 == ~E_4~0); 53221#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53222#L254-18 assume !(1 == ~m_pc~0); 53239#L254-20 is_master_triggered_~__retres1~0 := 0; 58101#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58100#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58099#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53304#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53305#L273-18 assume 1 == ~t1_pc~0; 53418#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 53419#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53421#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53422#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53465#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53468#L292-18 assume !(1 == ~t2_pc~0); 53534#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 53535#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53510#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53511#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57949#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57948#L311-18 assume 1 == ~t3_pc~0; 57940#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 57939#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57938#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 57936#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 57934#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56505#L330-18 assume !(1 == ~t4_pc~0); 56496#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 56486#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56478#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56470#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 56462#L673-20 assume !(1 == ~M_E~0); 55875#L576-3 assume !(1 == ~T1_E~0); 56446#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56439#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56431#L591-3 assume !(1 == ~T4_E~0); 56423#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56415#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56392#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56334#L611-3 assume !(1 == ~E_3~0); 56157#L616-3 assume !(1 == ~E_4~0); 56155#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 56153#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 56147#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 56146#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 53630#L826 assume !(0 == start_simulation_~tmp~3); 53632#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 57665#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53436#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53437#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 57475#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 57418#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 53499#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 53359#L839 assume !(0 != start_simulation_~tmp___0~1); 53116#L807-1 [2020-11-28 03:03:27,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:27,297 INFO L82 PathProgramCache]: Analyzing trace with hash -563476096, now seen corresponding path program 1 times [2020-11-28 03:03:27,297 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:27,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938828304] [2020-11-28 03:03:27,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:27,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:27,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:27,333 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938828304] [2020-11-28 03:03:27,333 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:27,333 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:27,334 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982515874] [2020-11-28 03:03:27,335 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:27,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:27,335 INFO L82 PathProgramCache]: Analyzing trace with hash 857020011, now seen corresponding path program 1 times [2020-11-28 03:03:27,336 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:27,336 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461270439] [2020-11-28 03:03:27,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:27,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:27,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:27,365 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461270439] [2020-11-28 03:03:27,368 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:27,369 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:27,369 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217603887] [2020-11-28 03:03:27,370 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:27,370 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:27,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:03:27,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:03:27,371 INFO L87 Difference]: Start difference. First operand 5058 states and 7293 transitions. cyclomatic complexity: 2237 Second operand 4 states. [2020-11-28 03:03:27,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:27,636 INFO L93 Difference]: Finished difference Result 5984 states and 8606 transitions. [2020-11-28 03:03:27,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:03:27,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5984 states and 8606 transitions. [2020-11-28 03:03:27,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5904 [2020-11-28 03:03:27,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5984 states to 5984 states and 8606 transitions. [2020-11-28 03:03:27,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5984 [2020-11-28 03:03:27,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5984 [2020-11-28 03:03:27,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5984 states and 8606 transitions. [2020-11-28 03:03:27,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:27,712 INFO L691 BuchiCegarLoop]: Abstraction has 5984 states and 8606 transitions. [2020-11-28 03:03:27,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5984 states and 8606 transitions. [2020-11-28 03:03:27,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5984 to 4328. [2020-11-28 03:03:27,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4328 states. [2020-11-28 03:03:27,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4328 states to 4328 states and 6218 transitions. [2020-11-28 03:03:27,794 INFO L714 BuchiCegarLoop]: Abstraction has 4328 states and 6218 transitions. [2020-11-28 03:03:27,794 INFO L594 BuchiCegarLoop]: Abstraction has 4328 states and 6218 transitions. [2020-11-28 03:03:27,794 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 03:03:27,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4328 states and 6218 transitions. [2020-11-28 03:03:27,812 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4260 [2020-11-28 03:03:27,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:27,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:27,815 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:27,815 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:27,816 INFO L794 eck$LassoCheckResult]: Stem: 64515#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64453#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64454#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 64485#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 64227#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64228#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64132#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64133#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64378#L377-1 assume !(0 == ~M_E~0); 64348#L518-1 assume !(0 == ~T1_E~0); 64211#L523-1 assume !(0 == ~T2_E~0); 64212#L528-1 assume !(0 == ~T3_E~0); 64235#L533-1 assume !(0 == ~T4_E~0); 64236#L538-1 assume !(0 == ~E_M~0); 64154#L543-1 assume !(0 == ~E_1~0); 64155#L548-1 assume !(0 == ~E_2~0); 64389#L553-1 assume !(0 == ~E_3~0); 64390#L558-1 assume !(0 == ~E_4~0); 64265#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64266#L254 assume !(1 == ~m_pc~0); 64300#L254-2 is_master_triggered_~__retres1~0 := 0; 64301#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64259#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 64260#L641 assume !(0 != activate_threads_~tmp~1); 64405#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64406#L273 assume !(1 == ~t1_pc~0); 64449#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 64450#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64451#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 64452#L649 assume !(0 != activate_threads_~tmp___0~0); 64530#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64206#L292 assume !(1 == ~t2_pc~0); 64196#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 64170#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64171#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 64558#L657 assume !(0 != activate_threads_~tmp___1~0); 64584#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64381#L311 assume !(1 == ~t3_pc~0); 64137#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 64136#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64134#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 64097#L665 assume !(0 != activate_threads_~tmp___2~0); 64098#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64099#L330 assume !(1 == ~t4_pc~0); 64516#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 64517#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64339#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 64280#L673 assume !(0 != activate_threads_~tmp___3~0); 64281#L673-2 assume !(1 == ~M_E~0); 64165#L576-1 assume !(1 == ~T1_E~0); 64166#L581-1 assume !(1 == ~T2_E~0); 64385#L586-1 assume !(1 == ~T3_E~0); 64386#L591-1 assume !(1 == ~T4_E~0); 64263#L596-1 assume !(1 == ~E_M~0); 64264#L601-1 assume !(1 == ~E_1~0); 64345#L606-1 assume !(1 == ~E_2~0); 64207#L611-1 assume !(1 == ~E_3~0); 64208#L616-1 assume !(1 == ~E_4~0); 64168#L807-1 [2020-11-28 03:03:27,816 INFO L796 eck$LassoCheckResult]: Loop: 64168#L807-1 assume !false; 64104#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 64105#L493 assume !false; 64476#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 64242#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 64190#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 64477#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 64400#L432 assume !(0 != eval_~tmp~0); 64402#L508 start_simulation_~kernel_st~0 := 2; 68348#L350-1 start_simulation_~kernel_st~0 := 3; 68346#L518-2 assume !(0 == ~M_E~0); 68344#L518-4 assume !(0 == ~T1_E~0); 68342#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68340#L528-3 assume !(0 == ~T3_E~0); 68338#L533-3 assume !(0 == ~T4_E~0); 68335#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68333#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68331#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68329#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68327#L558-3 assume !(0 == ~E_4~0); 68325#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68324#L254-18 assume !(1 == ~m_pc~0); 68322#L254-20 is_master_triggered_~__retres1~0 := 0; 68321#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68320#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 68319#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 68318#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 68317#L273-18 assume 1 == ~t1_pc~0; 68315#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 68314#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68313#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 68312#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 68311#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68081#L292-18 assume !(1 == ~t2_pc~0); 68080#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 68078#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68075#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 68073#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 68071#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 68069#L311-18 assume !(1 == ~t3_pc~0); 68067#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 68064#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 68063#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 68062#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 68060#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68058#L330-18 assume !(1 == ~t4_pc~0); 66958#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 68040#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 68036#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 68035#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 68034#L673-20 assume !(1 == ~M_E~0); 66472#L576-3 assume !(1 == ~T1_E~0); 68017#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68011#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68006#L591-3 assume !(1 == ~T4_E~0); 68003#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 67951#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67950#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67949#L611-3 assume !(1 == ~E_3~0); 67948#L616-3 assume !(1 == ~E_4~0); 67947#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 67946#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 67940#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 67869#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 64680#L826 assume !(0 == start_simulation_~tmp~3); 64681#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 68162#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 68157#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 68155#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 68153#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 68151#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 68149#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 68147#L839 assume !(0 != start_simulation_~tmp___0~1); 64168#L807-1 [2020-11-28 03:03:27,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:27,817 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2020-11-28 03:03:27,817 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:27,819 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183784168] [2020-11-28 03:03:27,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:27,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:27,837 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:27,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:27,850 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:27,896 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:27,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:27,897 INFO L82 PathProgramCache]: Analyzing trace with hash -771630262, now seen corresponding path program 1 times [2020-11-28 03:03:27,898 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:27,898 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406560176] [2020-11-28 03:03:27,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:27,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:27,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:27,939 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406560176] [2020-11-28 03:03:27,940 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:27,940 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:27,940 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117647028] [2020-11-28 03:03:27,940 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:27,941 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:27,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:27,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:27,943 INFO L87 Difference]: Start difference. First operand 4328 states and 6218 transitions. cyclomatic complexity: 1892 Second operand 3 states. [2020-11-28 03:03:28,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:28,066 INFO L93 Difference]: Finished difference Result 7774 states and 11061 transitions. [2020-11-28 03:03:28,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:28,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7774 states and 11061 transitions. [2020-11-28 03:03:28,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7656 [2020-11-28 03:03:28,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7774 states to 7774 states and 11061 transitions. [2020-11-28 03:03:28,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7774 [2020-11-28 03:03:28,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7774 [2020-11-28 03:03:28,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7774 states and 11061 transitions. [2020-11-28 03:03:28,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:28,241 INFO L691 BuchiCegarLoop]: Abstraction has 7774 states and 11061 transitions. [2020-11-28 03:03:28,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7774 states and 11061 transitions. [2020-11-28 03:03:28,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7774 to 7766. [2020-11-28 03:03:28,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7766 states. [2020-11-28 03:03:28,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7766 states to 7766 states and 11053 transitions. [2020-11-28 03:03:28,347 INFO L714 BuchiCegarLoop]: Abstraction has 7766 states and 11053 transitions. [2020-11-28 03:03:28,348 INFO L594 BuchiCegarLoop]: Abstraction has 7766 states and 11053 transitions. [2020-11-28 03:03:28,348 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 03:03:28,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7766 states and 11053 transitions. [2020-11-28 03:03:28,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7648 [2020-11-28 03:03:28,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:28,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:28,379 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:28,379 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:28,380 INFO L794 eck$LassoCheckResult]: Stem: 76633#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 76567#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 76568#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 76598#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 76336#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76337#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76237#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76238#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76486#L377-1 assume !(0 == ~M_E~0); 76458#L518-1 assume !(0 == ~T1_E~0); 76320#L523-1 assume !(0 == ~T2_E~0); 76321#L528-1 assume !(0 == ~T3_E~0); 76344#L533-1 assume !(0 == ~T4_E~0); 76345#L538-1 assume !(0 == ~E_M~0); 76256#L543-1 assume !(0 == ~E_1~0); 76257#L548-1 assume !(0 == ~E_2~0); 76502#L553-1 assume 0 == ~E_3~0;~E_3~0 := 1; 76503#L558-1 assume !(0 == ~E_4~0); 76714#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76742#L254 assume !(1 == ~m_pc~0); 76741#L254-2 is_master_triggered_~__retres1~0 := 0; 76740#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76367#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76368#L641 assume !(0 != activate_threads_~tmp~1); 76519#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76597#L273 assume !(1 == ~t1_pc~0); 76563#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 76564#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76565#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 76566#L649 assume !(0 != activate_threads_~tmp___0~0); 76660#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76315#L292 assume !(1 == ~t2_pc~0); 76304#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 76305#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76691#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 76692#L657 assume !(0 != activate_threads_~tmp___1~0); 76717#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76718#L311 assume !(1 == ~t3_pc~0); 76730#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 76242#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76489#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 76205#L665 assume !(0 != activate_threads_~tmp___2~0); 76206#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76207#L330 assume !(1 == ~t4_pc~0); 76634#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 76635#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76447#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 76388#L673 assume !(0 != activate_threads_~tmp___3~0); 76389#L673-2 assume !(1 == ~M_E~0); 76268#L576-1 assume !(1 == ~T1_E~0); 76269#L581-1 assume !(1 == ~T2_E~0); 76498#L586-1 assume !(1 == ~T3_E~0); 76499#L591-1 assume !(1 == ~T4_E~0); 76371#L596-1 assume !(1 == ~E_M~0); 76372#L601-1 assume !(1 == ~E_1~0); 76453#L606-1 assume !(1 == ~E_2~0); 76316#L611-1 assume 1 == ~E_3~0;~E_3~0 := 2; 76317#L616-1 assume !(1 == ~E_4~0); 76274#L807-1 [2020-11-28 03:03:28,380 INFO L796 eck$LassoCheckResult]: Loop: 76274#L807-1 assume !false; 76212#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 76213#L493 assume !false; 83610#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 76352#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 76298#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 76592#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 76514#L432 assume !(0 != eval_~tmp~0); 76516#L508 start_simulation_~kernel_st~0 := 2; 83424#L350-1 start_simulation_~kernel_st~0 := 3; 83422#L518-2 assume !(0 == ~M_E~0); 83420#L518-4 assume !(0 == ~T1_E~0); 83418#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83416#L528-3 assume !(0 == ~T3_E~0); 83414#L533-3 assume !(0 == ~T4_E~0); 83412#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83410#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83408#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83403#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83401#L558-3 assume !(0 == ~E_4~0); 83399#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 83397#L254-18 assume !(1 == ~m_pc~0); 83395#L254-20 is_master_triggered_~__retres1~0 := 0; 83393#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 83391#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 83389#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 83387#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 83384#L273-18 assume 1 == ~t1_pc~0; 83381#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 83379#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 83377#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 83375#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 83373#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83372#L292-18 assume !(1 == ~t2_pc~0); 78746#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 83369#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 83367#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 83365#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 83361#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 83360#L311-18 assume !(1 == ~t3_pc~0); 83359#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 83357#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83356#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 83355#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 83354#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 83353#L330-18 assume !(1 == ~t4_pc~0); 81894#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 83352#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 83351#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 83350#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 76525#L673-20 assume !(1 == ~M_E~0); 76526#L576-3 assume !(1 == ~T1_E~0); 82114#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82107#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76835#L591-3 assume !(1 == ~T4_E~0); 76831#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76826#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76821#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76815#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76811#L616-3 assume !(1 == ~E_4~0); 76807#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 76803#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 76792#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 76788#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 76785#L826 assume !(0 == start_simulation_~tmp~3); 76605#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 76338#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 76312#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 76594#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 76653#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 76661#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 76663#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 76522#L839 assume !(0 != start_simulation_~tmp___0~1); 76274#L807-1 [2020-11-28 03:03:28,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:28,381 INFO L82 PathProgramCache]: Analyzing trace with hash -387975928, now seen corresponding path program 1 times [2020-11-28 03:03:28,381 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:28,384 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210702238] [2020-11-28 03:03:28,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:28,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:28,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:28,412 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210702238] [2020-11-28 03:03:28,412 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:28,412 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:28,412 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778407632] [2020-11-28 03:03:28,412 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:28,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:28,415 INFO L82 PathProgramCache]: Analyzing trace with hash 508233416, now seen corresponding path program 1 times [2020-11-28 03:03:28,415 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:28,415 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634269296] [2020-11-28 03:03:28,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:28,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:28,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:28,462 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634269296] [2020-11-28 03:03:28,462 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:28,463 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:03:28,463 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19171614] [2020-11-28 03:03:28,463 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:28,463 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:28,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:28,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:28,464 INFO L87 Difference]: Start difference. First operand 7766 states and 11053 transitions. cyclomatic complexity: 3289 Second operand 3 states. [2020-11-28 03:03:28,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:28,523 INFO L93 Difference]: Finished difference Result 4328 states and 6087 transitions. [2020-11-28 03:03:28,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:28,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4328 states and 6087 transitions. [2020-11-28 03:03:28,544 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4260 [2020-11-28 03:03:28,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4328 states to 4328 states and 6087 transitions. [2020-11-28 03:03:28,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4328 [2020-11-28 03:03:28,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4328 [2020-11-28 03:03:28,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4328 states and 6087 transitions. [2020-11-28 03:03:28,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:28,568 INFO L691 BuchiCegarLoop]: Abstraction has 4328 states and 6087 transitions. [2020-11-28 03:03:28,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4328 states and 6087 transitions. [2020-11-28 03:03:28,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4328 to 4328. [2020-11-28 03:03:28,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4328 states. [2020-11-28 03:03:28,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4328 states to 4328 states and 6087 transitions. [2020-11-28 03:03:28,637 INFO L714 BuchiCegarLoop]: Abstraction has 4328 states and 6087 transitions. [2020-11-28 03:03:28,637 INFO L594 BuchiCegarLoop]: Abstraction has 4328 states and 6087 transitions. [2020-11-28 03:03:28,637 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 03:03:28,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4328 states and 6087 transitions. [2020-11-28 03:03:28,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4260 [2020-11-28 03:03:28,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:28,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:28,657 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:28,657 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:28,658 INFO L794 eck$LassoCheckResult]: Stem: 88709#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 88652#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 88653#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 88684#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 88430#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88431#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88339#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88340#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88575#L377-1 assume !(0 == ~M_E~0); 88548#L518-1 assume !(0 == ~T1_E~0); 88416#L523-1 assume !(0 == ~T2_E~0); 88417#L528-1 assume !(0 == ~T3_E~0); 88438#L533-1 assume !(0 == ~T4_E~0); 88439#L538-1 assume !(0 == ~E_M~0); 88357#L543-1 assume !(0 == ~E_1~0); 88358#L548-1 assume !(0 == ~E_2~0); 88586#L553-1 assume !(0 == ~E_3~0); 88587#L558-1 assume !(0 == ~E_4~0); 88466#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 88467#L254 assume !(1 == ~m_pc~0); 88502#L254-2 is_master_triggered_~__retres1~0 := 0; 88503#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 88460#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 88461#L641 assume !(0 != activate_threads_~tmp~1); 88604#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88605#L273 assume !(1 == ~t1_pc~0); 88648#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 88649#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 88650#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 88651#L649 assume !(0 != activate_threads_~tmp___0~0); 88725#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88411#L292 assume !(1 == ~t2_pc~0); 88401#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 88375#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88376#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 88753#L657 assume !(0 != activate_threads_~tmp___1~0); 88777#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 88579#L311 assume !(1 == ~t3_pc~0); 88343#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 88578#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 88341#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 88308#L665 assume !(0 != activate_threads_~tmp___2~0); 88309#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 88310#L330 assume !(1 == ~t4_pc~0); 88710#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 88711#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 88539#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 88480#L673 assume !(0 != activate_threads_~tmp___3~0); 88481#L673-2 assume !(1 == ~M_E~0); 88368#L576-1 assume !(1 == ~T1_E~0); 88369#L581-1 assume !(1 == ~T2_E~0); 88582#L586-1 assume !(1 == ~T3_E~0); 88583#L591-1 assume !(1 == ~T4_E~0); 88464#L596-1 assume !(1 == ~E_M~0); 88465#L601-1 assume !(1 == ~E_1~0); 88545#L606-1 assume !(1 == ~E_2~0); 88412#L611-1 assume !(1 == ~E_3~0); 88413#L616-1 assume !(1 == ~E_4~0); 88372#L807-1 [2020-11-28 03:03:28,658 INFO L796 eck$LassoCheckResult]: Loop: 88372#L807-1 assume !false; 88315#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 88316#L493 assume !false; 88678#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 88445#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 88395#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 91937#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 91935#L432 assume !(0 != eval_~tmp~0); 91936#L508 start_simulation_~kernel_st~0 := 2; 92608#L350-1 start_simulation_~kernel_st~0 := 3; 92606#L518-2 assume !(0 == ~M_E~0); 92604#L518-4 assume !(0 == ~T1_E~0); 92602#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92600#L528-3 assume !(0 == ~T3_E~0); 92598#L533-3 assume !(0 == ~T4_E~0); 92595#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92592#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92589#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 92586#L553-3 assume !(0 == ~E_3~0); 92583#L558-3 assume !(0 == ~E_4~0); 92580#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 92577#L254-18 assume !(1 == ~m_pc~0); 92574#L254-20 is_master_triggered_~__retres1~0 := 0; 92571#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 92568#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 92565#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 92562#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92558#L273-18 assume !(1 == ~t1_pc~0); 92555#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 92551#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92548#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 92546#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 92545#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88760#L292-18 assume !(1 == ~t2_pc~0); 88761#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 92500#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92497#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 92495#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 92494#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 88374#L311-18 assume !(1 == ~t3_pc~0); 88334#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 88365#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 88568#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 92476#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 92475#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 88689#L330-18 assume !(1 == ~t4_pc~0); 88690#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 92384#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92383#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 92382#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 92381#L673-20 assume !(1 == ~M_E~0); 92318#L576-3 assume !(1 == ~T1_E~0); 92380#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92379#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92378#L591-3 assume !(1 == ~T4_E~0); 92377#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 92376#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 92375#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 92373#L611-3 assume !(1 == ~E_3~0); 92371#L616-3 assume !(1 == ~E_4~0); 92369#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 92367#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 88681#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 88682#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 88723#L826 assume !(0 == start_simulation_~tmp~3); 88688#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 88432#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 88408#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 88683#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 88724#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 88726#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 88728#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 88606#L839 assume !(0 != start_simulation_~tmp___0~1); 88372#L807-1 [2020-11-28 03:03:28,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:28,659 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2020-11-28 03:03:28,659 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:28,659 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178105487] [2020-11-28 03:03:28,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:28,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:28,673 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:28,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:28,684 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:28,715 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:28,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:28,716 INFO L82 PathProgramCache]: Analyzing trace with hash -692849621, now seen corresponding path program 1 times [2020-11-28 03:03:28,716 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:28,716 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758131447] [2020-11-28 03:03:28,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:28,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:28,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:28,771 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758131447] [2020-11-28 03:03:28,772 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:28,772 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:03:28,772 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585310003] [2020-11-28 03:03:28,773 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:28,773 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:28,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:03:28,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:03:28,774 INFO L87 Difference]: Start difference. First operand 4328 states and 6087 transitions. cyclomatic complexity: 1761 Second operand 5 states. [2020-11-28 03:03:28,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:28,938 INFO L93 Difference]: Finished difference Result 7628 states and 10607 transitions. [2020-11-28 03:03:28,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:03:28,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7628 states and 10607 transitions. [2020-11-28 03:03:28,981 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7552 [2020-11-28 03:03:29,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7628 states to 7628 states and 10607 transitions. [2020-11-28 03:03:29,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7628 [2020-11-28 03:03:29,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7628 [2020-11-28 03:03:29,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7628 states and 10607 transitions. [2020-11-28 03:03:29,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:29,028 INFO L691 BuchiCegarLoop]: Abstraction has 7628 states and 10607 transitions. [2020-11-28 03:03:29,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7628 states and 10607 transitions. [2020-11-28 03:03:29,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7628 to 4376. [2020-11-28 03:03:29,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4376 states. [2020-11-28 03:03:29,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4376 states to 4376 states and 6135 transitions. [2020-11-28 03:03:29,186 INFO L714 BuchiCegarLoop]: Abstraction has 4376 states and 6135 transitions. [2020-11-28 03:03:29,187 INFO L594 BuchiCegarLoop]: Abstraction has 4376 states and 6135 transitions. [2020-11-28 03:03:29,187 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 03:03:29,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4376 states and 6135 transitions. [2020-11-28 03:03:29,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4308 [2020-11-28 03:03:29,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:29,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:29,205 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:29,206 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:29,206 INFO L794 eck$LassoCheckResult]: Stem: 100706#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 100636#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 100637#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 100671#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 100407#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100408#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100311#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100312#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100557#L377-1 assume !(0 == ~M_E~0); 100525#L518-1 assume !(0 == ~T1_E~0); 100389#L523-1 assume !(0 == ~T2_E~0); 100390#L528-1 assume !(0 == ~T3_E~0); 100416#L533-1 assume !(0 == ~T4_E~0); 100417#L538-1 assume !(0 == ~E_M~0); 100329#L543-1 assume !(0 == ~E_1~0); 100330#L548-1 assume !(0 == ~E_2~0); 100567#L553-1 assume !(0 == ~E_3~0); 100568#L558-1 assume !(0 == ~E_4~0); 100445#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100446#L254 assume !(1 == ~m_pc~0); 100478#L254-2 is_master_triggered_~__retres1~0 := 0; 100479#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100439#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100440#L641 assume !(0 != activate_threads_~tmp~1); 100582#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100583#L273 assume !(1 == ~t1_pc~0); 100632#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 100633#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100634#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 100635#L649 assume !(0 != activate_threads_~tmp___0~0); 100722#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100384#L292 assume !(1 == ~t2_pc~0); 100377#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 100349#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100350#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 100761#L657 assume !(0 != activate_threads_~tmp___1~0); 100794#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100559#L311 assume !(1 == ~t3_pc~0); 100315#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 100558#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 100313#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 100280#L665 assume !(0 != activate_threads_~tmp___2~0); 100281#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 100282#L330 assume !(1 == ~t4_pc~0); 100707#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 100708#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100515#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 100460#L673 assume !(0 != activate_threads_~tmp___3~0); 100461#L673-2 assume !(1 == ~M_E~0); 100342#L576-1 assume !(1 == ~T1_E~0); 100343#L581-1 assume !(1 == ~T2_E~0); 100563#L586-1 assume !(1 == ~T3_E~0); 100564#L591-1 assume !(1 == ~T4_E~0); 100443#L596-1 assume !(1 == ~E_M~0); 100444#L601-1 assume !(1 == ~E_1~0); 100521#L606-1 assume !(1 == ~E_2~0); 100385#L611-1 assume !(1 == ~E_3~0); 100386#L616-1 assume !(1 == ~E_4~0); 100723#L807-1 [2020-11-28 03:03:29,206 INFO L796 eck$LassoCheckResult]: Loop: 100723#L807-1 assume !false; 104602#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 104188#L493 assume !false; 104445#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 104437#L390 assume !(0 == ~m_st~0); 104433#L394 assume !(0 == ~t1_st~0); 104434#L398 assume !(0 == ~t2_st~0); 104435#L402 assume !(0 == ~t3_st~0); 104436#L406 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 104438#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 102635#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 102636#L432 assume !(0 != eval_~tmp~0); 100448#L508 start_simulation_~kernel_st~0 := 2; 100449#L350-1 start_simulation_~kernel_st~0 := 3; 100513#L518-2 assume !(0 == ~M_E~0); 100514#L518-4 assume !(0 == ~T1_E~0); 100364#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100365#L528-3 assume !(0 == ~T3_E~0); 100419#L533-3 assume !(0 == ~T4_E~0); 100420#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100333#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100334#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104416#L553-3 assume !(0 == ~E_3~0); 100792#L558-3 assume !(0 == ~E_4~0); 100453#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100454#L254-18 assume !(1 == ~m_pc~0); 100468#L254-20 is_master_triggered_~__retres1~0 := 0; 104417#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100612#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100552#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 100532#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100533#L273-18 assume 1 == ~t1_pc~0; 100644#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 100645#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100647#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 100648#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 100699#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100701#L292-18 assume !(1 == ~t2_pc~0); 100769#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 104403#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104402#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 104401#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 104400#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104399#L311-18 assume !(1 == ~t3_pc~0); 100337#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 100338#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 100303#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 100304#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 104395#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 104394#L330-18 assume !(1 == ~t4_pc~0); 100682#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 100683#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100505#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 100506#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 100595#L673-20 assume !(1 == ~M_E~0); 100596#L576-3 assume !(1 == ~T1_E~0); 100778#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100779#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100790#L591-3 assume !(1 == ~T4_E~0); 100791#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100770#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100771#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100387#L611-3 assume !(1 == ~E_3~0); 100388#L616-3 assume !(1 == ~E_4~0); 104293#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 104294#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 104618#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 104617#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 104616#L826 assume !(0 == start_simulation_~tmp~3); 104614#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 104611#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 104608#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 104607#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 104606#L781 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 104605#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 104604#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 104603#L839 assume !(0 != start_simulation_~tmp___0~1); 100723#L807-1 [2020-11-28 03:03:29,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:29,207 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2020-11-28 03:03:29,207 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:29,208 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126816395] [2020-11-28 03:03:29,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:29,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:29,217 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:29,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:29,227 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:29,253 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:29,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:29,254 INFO L82 PathProgramCache]: Analyzing trace with hash 2069576792, now seen corresponding path program 1 times [2020-11-28 03:03:29,254 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:29,254 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715026119] [2020-11-28 03:03:29,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:29,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:29,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:29,302 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715026119] [2020-11-28 03:03:29,303 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:29,303 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:03:29,303 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406449316] [2020-11-28 03:03:29,303 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:29,304 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:29,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:03:29,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:03:29,304 INFO L87 Difference]: Start difference. First operand 4376 states and 6135 transitions. cyclomatic complexity: 1761 Second operand 5 states. [2020-11-28 03:03:29,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:29,533 INFO L93 Difference]: Finished difference Result 14508 states and 20159 transitions. [2020-11-28 03:03:29,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:03:29,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14508 states and 20159 transitions. [2020-11-28 03:03:29,610 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14416 [2020-11-28 03:03:29,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14508 states to 14508 states and 20159 transitions. [2020-11-28 03:03:29,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14508 [2020-11-28 03:03:29,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14508 [2020-11-28 03:03:29,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14508 states and 20159 transitions. [2020-11-28 03:03:29,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:29,698 INFO L691 BuchiCegarLoop]: Abstraction has 14508 states and 20159 transitions. [2020-11-28 03:03:29,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14508 states and 20159 transitions. [2020-11-28 03:03:29,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14508 to 4424. [2020-11-28 03:03:29,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4424 states. [2020-11-28 03:03:29,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4424 states to 4424 states and 6183 transitions. [2020-11-28 03:03:29,807 INFO L714 BuchiCegarLoop]: Abstraction has 4424 states and 6183 transitions. [2020-11-28 03:03:29,807 INFO L594 BuchiCegarLoop]: Abstraction has 4424 states and 6183 transitions. [2020-11-28 03:03:29,807 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-28 03:03:29,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4424 states and 6183 transitions. [2020-11-28 03:03:29,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4356 [2020-11-28 03:03:29,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:29,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:29,827 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:29,827 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:29,828 INFO L794 eck$LassoCheckResult]: Stem: 119591#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 119529#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 119530#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 119562#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 119303#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119304#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119212#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119213#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119447#L377-1 assume !(0 == ~M_E~0); 119421#L518-1 assume !(0 == ~T1_E~0); 119289#L523-1 assume !(0 == ~T2_E~0); 119290#L528-1 assume !(0 == ~T3_E~0); 119311#L533-1 assume !(0 == ~T4_E~0); 119312#L538-1 assume !(0 == ~E_M~0); 119230#L543-1 assume !(0 == ~E_1~0); 119231#L548-1 assume !(0 == ~E_2~0); 119460#L553-1 assume !(0 == ~E_3~0); 119461#L558-1 assume !(0 == ~E_4~0); 119342#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119343#L254 assume !(1 == ~m_pc~0); 119376#L254-2 is_master_triggered_~__retres1~0 := 0; 119377#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 119336#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 119337#L641 assume !(0 != activate_threads_~tmp~1); 119474#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 119475#L273 assume !(1 == ~t1_pc~0); 119525#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 119526#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119527#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 119528#L649 assume !(0 != activate_threads_~tmp___0~0); 119607#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 119284#L292 assume !(1 == ~t2_pc~0); 119274#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 119248#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 119249#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 119637#L657 assume !(0 != activate_threads_~tmp___1~0); 119669#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 119451#L311 assume !(1 == ~t3_pc~0); 119216#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 119450#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119214#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 119181#L665 assume !(0 != activate_threads_~tmp___2~0); 119182#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119183#L330 assume !(1 == ~t4_pc~0); 119592#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 119593#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 119411#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 119356#L673 assume !(0 != activate_threads_~tmp___3~0); 119357#L673-2 assume !(1 == ~M_E~0); 119241#L576-1 assume !(1 == ~T1_E~0); 119242#L581-1 assume !(1 == ~T2_E~0); 119456#L586-1 assume !(1 == ~T3_E~0); 119457#L591-1 assume !(1 == ~T4_E~0); 119340#L596-1 assume !(1 == ~E_M~0); 119341#L601-1 assume !(1 == ~E_1~0); 119417#L606-1 assume !(1 == ~E_2~0); 119285#L611-1 assume !(1 == ~E_3~0); 119286#L616-1 assume !(1 == ~E_4~0); 119608#L807-1 [2020-11-28 03:03:29,828 INFO L796 eck$LassoCheckResult]: Loop: 119608#L807-1 assume !false; 121702#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 121697#L493 assume !false; 121696#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 121695#L390 assume !(0 == ~m_st~0); 121690#L394 assume !(0 == ~t1_st~0); 121691#L398 assume !(0 == ~t2_st~0); 121694#L402 assume !(0 == ~t3_st~0); 121692#L406 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 121693#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 121683#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 121684#L432 assume !(0 != eval_~tmp~0); 121924#L508 start_simulation_~kernel_st~0 := 2; 121920#L350-1 start_simulation_~kernel_st~0 := 3; 121916#L518-2 assume !(0 == ~M_E~0); 121912#L518-4 assume !(0 == ~T1_E~0); 121908#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121904#L528-3 assume !(0 == ~T3_E~0); 121900#L533-3 assume !(0 == ~T4_E~0); 121896#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121892#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121888#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121884#L553-3 assume !(0 == ~E_3~0); 121880#L558-3 assume !(0 == ~E_4~0); 121876#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121872#L254-18 assume !(1 == ~m_pc~0); 121868#L254-20 is_master_triggered_~__retres1~0 := 0; 121864#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121860#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121856#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 121852#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121847#L273-18 assume !(1 == ~t1_pc~0); 121841#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 121835#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121831#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 121827#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 121823#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121819#L292-18 assume !(1 == ~t2_pc~0); 120320#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 121815#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121811#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 121807#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 121802#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121795#L311-18 assume !(1 == ~t3_pc~0); 121790#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 121786#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121782#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 121778#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 121774#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121769#L330-18 assume !(1 == ~t4_pc~0); 121767#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 121765#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121763#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 121761#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 121758#L673-20 assume !(1 == ~M_E~0); 121757#L576-3 assume !(1 == ~T1_E~0); 121756#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121755#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121754#L591-3 assume !(1 == ~T4_E~0); 121753#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 121752#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121751#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121750#L611-3 assume !(1 == ~E_3~0); 121749#L616-3 assume !(1 == ~E_4~0); 121748#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 121747#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 121741#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 121739#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 121738#L826 assume !(0 == start_simulation_~tmp~3); 121717#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 121714#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 121711#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 121709#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 121707#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 121705#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 121704#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 121703#L839 assume !(0 != start_simulation_~tmp___0~1); 119608#L807-1 [2020-11-28 03:03:29,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:29,829 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2020-11-28 03:03:29,829 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:29,829 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379332317] [2020-11-28 03:03:29,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:29,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:29,839 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:29,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:29,848 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:29,862 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:29,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:29,863 INFO L82 PathProgramCache]: Analyzing trace with hash 761512441, now seen corresponding path program 1 times [2020-11-28 03:03:29,863 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:29,863 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767214947] [2020-11-28 03:03:29,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:29,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:29,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:29,979 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767214947] [2020-11-28 03:03:29,979 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:29,979 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:03:29,979 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648966123] [2020-11-28 03:03:29,980 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:29,980 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:29,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:03:29,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:03:29,981 INFO L87 Difference]: Start difference. First operand 4424 states and 6183 transitions. cyclomatic complexity: 1761 Second operand 5 states. [2020-11-28 03:03:30,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:30,282 INFO L93 Difference]: Finished difference Result 8780 states and 12190 transitions. [2020-11-28 03:03:30,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:03:30,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8780 states and 12190 transitions. [2020-11-28 03:03:30,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8712 [2020-11-28 03:03:30,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8780 states to 8780 states and 12190 transitions. [2020-11-28 03:03:30,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8780 [2020-11-28 03:03:30,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8780 [2020-11-28 03:03:30,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8780 states and 12190 transitions. [2020-11-28 03:03:30,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:30,392 INFO L691 BuchiCegarLoop]: Abstraction has 8780 states and 12190 transitions. [2020-11-28 03:03:30,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8780 states and 12190 transitions. [2020-11-28 03:03:30,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8780 to 4556. [2020-11-28 03:03:30,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4556 states. [2020-11-28 03:03:30,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6278 transitions. [2020-11-28 03:03:30,489 INFO L714 BuchiCegarLoop]: Abstraction has 4556 states and 6278 transitions. [2020-11-28 03:03:30,489 INFO L594 BuchiCegarLoop]: Abstraction has 4556 states and 6278 transitions. [2020-11-28 03:03:30,489 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-11-28 03:03:30,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6278 transitions. [2020-11-28 03:03:30,510 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4488 [2020-11-28 03:03:30,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:30,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:30,513 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:30,514 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:30,514 INFO L794 eck$LassoCheckResult]: Stem: 132827#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 132769#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 132770#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 132800#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 132520#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132521#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132429#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132430#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132679#L377-1 assume !(0 == ~M_E~0); 132652#L518-1 assume !(0 == ~T1_E~0); 132505#L523-1 assume !(0 == ~T2_E~0); 132506#L528-1 assume !(0 == ~T3_E~0); 132529#L533-1 assume !(0 == ~T4_E~0); 132530#L538-1 assume !(0 == ~E_M~0); 132447#L543-1 assume !(0 == ~E_1~0); 132448#L548-1 assume !(0 == ~E_2~0); 132691#L553-1 assume !(0 == ~E_3~0); 132692#L558-1 assume !(0 == ~E_4~0); 132561#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132562#L254 assume !(1 == ~m_pc~0); 132599#L254-2 is_master_triggered_~__retres1~0 := 0; 132600#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132555#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132556#L641 assume !(0 != activate_threads_~tmp~1); 132705#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132706#L273 assume !(1 == ~t1_pc~0); 132765#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 132766#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132767#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132768#L649 assume !(0 != activate_threads_~tmp___0~0); 132841#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132500#L292 assume !(1 == ~t2_pc~0); 132493#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 132465#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132466#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 132872#L657 assume !(0 != activate_threads_~tmp___1~0); 132902#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 132683#L311 assume !(1 == ~t3_pc~0); 132433#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 132682#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132431#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 132398#L665 assume !(0 != activate_threads_~tmp___2~0); 132399#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132400#L330 assume !(1 == ~t4_pc~0); 132828#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 132829#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132643#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 132575#L673 assume !(0 != activate_threads_~tmp___3~0); 132576#L673-2 assume !(1 == ~M_E~0); 132458#L576-1 assume !(1 == ~T1_E~0); 132459#L581-1 assume !(1 == ~T2_E~0); 132687#L586-1 assume !(1 == ~T3_E~0); 132688#L591-1 assume !(1 == ~T4_E~0); 132559#L596-1 assume !(1 == ~E_M~0); 132560#L601-1 assume !(1 == ~E_1~0); 132649#L606-1 assume !(1 == ~E_2~0); 132501#L611-1 assume !(1 == ~E_3~0); 132502#L616-1 assume !(1 == ~E_4~0); 132842#L807-1 [2020-11-28 03:03:30,514 INFO L796 eck$LassoCheckResult]: Loop: 132842#L807-1 assume !false; 134724#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 134474#L493 assume !false; 134723#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 134722#L390 assume !(0 == ~m_st~0); 134717#L394 assume !(0 == ~t1_st~0); 134718#L398 assume !(0 == ~t2_st~0); 134721#L402 assume !(0 == ~t3_st~0); 134719#L406 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 134720#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 134135#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 134136#L432 assume !(0 != eval_~tmp~0); 134926#L508 start_simulation_~kernel_st~0 := 2; 134924#L350-1 start_simulation_~kernel_st~0 := 3; 134922#L518-2 assume !(0 == ~M_E~0); 134920#L518-4 assume !(0 == ~T1_E~0); 134918#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134916#L528-3 assume !(0 == ~T3_E~0); 134914#L533-3 assume !(0 == ~T4_E~0); 134912#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134910#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134908#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134906#L553-3 assume !(0 == ~E_3~0); 134904#L558-3 assume !(0 == ~E_4~0); 134902#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134900#L254-18 assume !(1 == ~m_pc~0); 134898#L254-20 is_master_triggered_~__retres1~0 := 0; 134896#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134894#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134892#L641-18 assume !(0 != activate_threads_~tmp~1); 134890#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134888#L273-18 assume 1 == ~t1_pc~0; 134883#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 134880#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134877#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134874#L649-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 134871#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134867#L292-18 assume !(1 == ~t2_pc~0); 133051#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 134863#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134860#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 134857#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 134854#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134851#L311-18 assume !(1 == ~t3_pc~0); 134847#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 134844#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134841#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 134838#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 134834#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134830#L330-18 assume !(1 == ~t4_pc~0); 134427#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 134824#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134820#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 134816#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 134811#L673-20 assume !(1 == ~M_E~0); 134808#L576-3 assume !(1 == ~T1_E~0); 134804#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134801#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134793#L591-3 assume !(1 == ~T4_E~0); 134787#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 134782#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134777#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134773#L611-3 assume !(1 == ~E_3~0); 134769#L616-3 assume !(1 == ~E_4~0); 134767#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 134758#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 134750#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 134715#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 134716#L826 assume !(0 == start_simulation_~tmp~3); 134739#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 134736#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 134733#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 134731#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 134729#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 134727#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 134726#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 134725#L839 assume !(0 != start_simulation_~tmp___0~1); 132842#L807-1 [2020-11-28 03:03:30,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:30,515 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 5 times [2020-11-28 03:03:30,516 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:30,516 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914579650] [2020-11-28 03:03:30,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:30,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,528 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,538 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,554 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:30,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:30,555 INFO L82 PathProgramCache]: Analyzing trace with hash -286288040, now seen corresponding path program 1 times [2020-11-28 03:03:30,555 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:30,555 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265211659] [2020-11-28 03:03:30,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:30,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:30,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:30,601 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265211659] [2020-11-28 03:03:30,601 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:30,602 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:30,602 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374765510] [2020-11-28 03:03:30,602 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:03:30,603 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:30,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:30,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:30,604 INFO L87 Difference]: Start difference. First operand 4556 states and 6278 transitions. cyclomatic complexity: 1724 Second operand 3 states. [2020-11-28 03:03:30,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:30,694 INFO L93 Difference]: Finished difference Result 7088 states and 9633 transitions. [2020-11-28 03:03:30,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:30,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7088 states and 9633 transitions. [2020-11-28 03:03:30,736 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7022 [2020-11-28 03:03:30,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7088 states to 7088 states and 9633 transitions. [2020-11-28 03:03:30,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7088 [2020-11-28 03:03:30,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7088 [2020-11-28 03:03:30,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7088 states and 9633 transitions. [2020-11-28 03:03:30,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:30,779 INFO L691 BuchiCegarLoop]: Abstraction has 7088 states and 9633 transitions. [2020-11-28 03:03:30,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7088 states and 9633 transitions. [2020-11-28 03:03:30,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7088 to 6864. [2020-11-28 03:03:30,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6864 states. [2020-11-28 03:03:30,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6864 states to 6864 states and 9341 transitions. [2020-11-28 03:03:30,888 INFO L714 BuchiCegarLoop]: Abstraction has 6864 states and 9341 transitions. [2020-11-28 03:03:30,889 INFO L594 BuchiCegarLoop]: Abstraction has 6864 states and 9341 transitions. [2020-11-28 03:03:30,889 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2020-11-28 03:03:30,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6864 states and 9341 transitions. [2020-11-28 03:03:30,921 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6798 [2020-11-28 03:03:30,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:30,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:30,922 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:30,922 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:30,923 INFO L794 eck$LassoCheckResult]: Stem: 144475#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 144408#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 144409#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 144443#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 144174#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144175#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144079#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144080#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144332#L377-1 assume !(0 == ~M_E~0); 144302#L518-1 assume !(0 == ~T1_E~0); 144159#L523-1 assume !(0 == ~T2_E~0); 144160#L528-1 assume !(0 == ~T3_E~0); 144183#L533-1 assume !(0 == ~T4_E~0); 144184#L538-1 assume !(0 == ~E_M~0); 144097#L543-1 assume !(0 == ~E_1~0); 144098#L548-1 assume !(0 == ~E_2~0); 144344#L553-1 assume !(0 == ~E_3~0); 144345#L558-1 assume !(0 == ~E_4~0); 144216#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 144217#L254 assume !(1 == ~m_pc~0); 144252#L254-2 is_master_triggered_~__retres1~0 := 0; 144253#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 144210#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 144211#L641 assume !(0 != activate_threads_~tmp~1); 144359#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 144360#L273 assume !(1 == ~t1_pc~0); 144404#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 144405#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 144406#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 144407#L649 assume !(0 != activate_threads_~tmp___0~0); 144502#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 144154#L292 assume !(1 == ~t2_pc~0); 144144#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 144117#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 144118#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 144533#L657 assume !(0 != activate_threads_~tmp___1~0); 144569#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 144336#L311 assume !(1 == ~t3_pc~0); 144083#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 144335#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 144081#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 144048#L665 assume !(0 != activate_threads_~tmp___2~0); 144049#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 144050#L330 assume !(1 == ~t4_pc~0); 144476#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 144477#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 144292#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 144232#L673 assume !(0 != activate_threads_~tmp___3~0); 144233#L673-2 assume !(1 == ~M_E~0); 144110#L576-1 assume !(1 == ~T1_E~0); 144111#L581-1 assume !(1 == ~T2_E~0); 144340#L586-1 assume !(1 == ~T3_E~0); 144341#L591-1 assume !(1 == ~T4_E~0); 144214#L596-1 assume !(1 == ~E_M~0); 144215#L601-1 assume !(1 == ~E_1~0); 144299#L606-1 assume !(1 == ~E_2~0); 144155#L611-1 assume !(1 == ~E_3~0); 144156#L616-1 assume !(1 == ~E_4~0); 144503#L807-1 assume !false; 146673#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 146659#L493 [2020-11-28 03:03:30,923 INFO L796 eck$LassoCheckResult]: Loop: 146659#L493 assume !false; 146652#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 146647#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 146646#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 146645#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 146643#L432 assume 0 != eval_~tmp~0; 146640#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 146638#L440 assume !(0 != eval_~tmp_ndt_1~0); 146629#L437 assume !(0 == ~t1_st~0); 146625#L451 assume !(0 == ~t2_st~0); 146623#L465 assume !(0 == ~t3_st~0); 146671#L479 assume !(0 == ~t4_st~0); 146659#L493 [2020-11-28 03:03:30,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:30,924 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2020-11-28 03:03:30,924 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:30,924 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031338904] [2020-11-28 03:03:30,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:30,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,936 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,946 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,962 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:30,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:30,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1361600343, now seen corresponding path program 1 times [2020-11-28 03:03:30,963 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:30,964 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433271334] [2020-11-28 03:03:30,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:30,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,968 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:30,970 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:30,973 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:30,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:30,974 INFO L82 PathProgramCache]: Analyzing trace with hash -1569955396, now seen corresponding path program 1 times [2020-11-28 03:03:30,974 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:30,974 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547217521] [2020-11-28 03:03:30,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:30,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:31,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:31,030 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547217521] [2020-11-28 03:03:31,030 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:31,030 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:31,031 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154615052] [2020-11-28 03:03:31,139 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:31,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:31,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:31,140 INFO L87 Difference]: Start difference. First operand 6864 states and 9341 transitions. cyclomatic complexity: 2480 Second operand 3 states. [2020-11-28 03:03:31,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:31,277 INFO L93 Difference]: Finished difference Result 12483 states and 16784 transitions. [2020-11-28 03:03:31,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:31,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12483 states and 16784 transitions. [2020-11-28 03:03:31,353 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12356 [2020-11-28 03:03:31,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12483 states to 12483 states and 16784 transitions. [2020-11-28 03:03:31,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12483 [2020-11-28 03:03:31,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12483 [2020-11-28 03:03:31,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12483 states and 16784 transitions. [2020-11-28 03:03:31,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:31,430 INFO L691 BuchiCegarLoop]: Abstraction has 12483 states and 16784 transitions. [2020-11-28 03:03:31,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12483 states and 16784 transitions. [2020-11-28 03:03:31,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12483 to 11839. [2020-11-28 03:03:31,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11839 states. [2020-11-28 03:03:31,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11839 states to 11839 states and 15986 transitions. [2020-11-28 03:03:31,619 INFO L714 BuchiCegarLoop]: Abstraction has 11839 states and 15986 transitions. [2020-11-28 03:03:31,619 INFO L594 BuchiCegarLoop]: Abstraction has 11839 states and 15986 transitions. [2020-11-28 03:03:31,619 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2020-11-28 03:03:31,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11839 states and 15986 transitions. [2020-11-28 03:03:31,672 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11712 [2020-11-28 03:03:31,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:31,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:31,674 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:31,674 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:31,674 INFO L794 eck$LassoCheckResult]: Stem: 163855#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 163778#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 163779#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 163820#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 163532#L357-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 163533#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163435#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163436#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163684#L377-1 assume !(0 == ~M_E~0); 163685#L518-1 assume !(0 == ~T1_E~0); 163516#L523-1 assume !(0 == ~T2_E~0); 163517#L528-1 assume !(0 == ~T3_E~0); 163541#L533-1 assume !(0 == ~T4_E~0); 163542#L538-1 assume !(0 == ~E_M~0); 163454#L543-1 assume !(0 == ~E_1~0); 163455#L548-1 assume !(0 == ~E_2~0); 163701#L553-1 assume !(0 == ~E_3~0); 163702#L558-1 assume !(0 == ~E_4~0); 163569#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 163570#L254 assume !(1 == ~m_pc~0); 163604#L254-2 is_master_triggered_~__retres1~0 := 0; 163605#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 163563#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 163564#L641 assume !(0 != activate_threads_~tmp~1); 163719#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 163720#L273 assume !(1 == ~t1_pc~0); 163774#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 163775#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 163776#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 163777#L649 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 163880#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 163510#L292 assume !(1 == ~t2_pc~0); 163511#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 163472#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 163473#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 163950#L657 assume !(0 != activate_threads_~tmp___1~0); 163951#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 163690#L311 assume !(1 == ~t3_pc~0); 163440#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 163688#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 163689#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 163403#L665 assume !(0 != activate_threads_~tmp___2~0); 163404#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 163877#L330 assume !(1 == ~t4_pc~0); 163878#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 163875#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 163876#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 163583#L673 assume !(0 != activate_threads_~tmp___3~0); 163584#L673-2 assume !(1 == ~M_E~0); 163465#L576-1 assume !(1 == ~T1_E~0); 163466#L581-1 assume !(1 == ~T2_E~0); 163697#L586-1 assume !(1 == ~T3_E~0); 163698#L591-1 assume !(1 == ~T4_E~0); 163567#L596-1 assume !(1 == ~E_M~0); 163568#L601-1 assume !(1 == ~E_1~0); 163652#L606-1 assume !(1 == ~E_2~0); 163653#L611-1 assume !(1 == ~E_3~0); 163883#L616-1 assume !(1 == ~E_4~0); 163884#L807-1 assume !false; 170214#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 170210#L493 [2020-11-28 03:03:31,675 INFO L796 eck$LassoCheckResult]: Loop: 170210#L493 assume !false; 170206#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 170203#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 170200#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 170197#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 170195#L432 assume 0 != eval_~tmp~0; 170192#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 170190#L440 assume !(0 != eval_~tmp_ndt_1~0); 170188#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 169694#L454 assume !(0 != eval_~tmp_ndt_2~0); 170183#L451 assume !(0 == ~t2_st~0); 170181#L465 assume !(0 == ~t3_st~0); 170212#L479 assume !(0 == ~t4_st~0); 170210#L493 [2020-11-28 03:03:31,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:31,675 INFO L82 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2020-11-28 03:03:31,676 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:31,676 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840301798] [2020-11-28 03:03:31,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:31,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:31,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:31,704 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840301798] [2020-11-28 03:03:31,704 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:31,704 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:31,704 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749014817] [2020-11-28 03:03:31,705 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:03:31,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:31,706 INFO L82 PathProgramCache]: Analyzing trace with hash -885327886, now seen corresponding path program 1 times [2020-11-28 03:03:31,707 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:31,707 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620436082] [2020-11-28 03:03:31,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:31,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:31,713 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:31,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:31,716 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:31,719 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:31,875 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:31,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:31,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:31,876 INFO L87 Difference]: Start difference. First operand 11839 states and 15986 transitions. cyclomatic complexity: 4150 Second operand 3 states. [2020-11-28 03:03:31,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:31,928 INFO L93 Difference]: Finished difference Result 11782 states and 15911 transitions. [2020-11-28 03:03:31,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:31,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11782 states and 15911 transitions. [2020-11-28 03:03:32,078 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11712 [2020-11-28 03:03:32,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11782 states to 11782 states and 15911 transitions. [2020-11-28 03:03:32,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11782 [2020-11-28 03:03:32,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11782 [2020-11-28 03:03:32,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11782 states and 15911 transitions. [2020-11-28 03:03:32,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:32,133 INFO L691 BuchiCegarLoop]: Abstraction has 11782 states and 15911 transitions. [2020-11-28 03:03:32,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11782 states and 15911 transitions. [2020-11-28 03:03:32,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11782 to 11782. [2020-11-28 03:03:32,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11782 states. [2020-11-28 03:03:32,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11782 states to 11782 states and 15911 transitions. [2020-11-28 03:03:32,290 INFO L714 BuchiCegarLoop]: Abstraction has 11782 states and 15911 transitions. [2020-11-28 03:03:32,290 INFO L594 BuchiCegarLoop]: Abstraction has 11782 states and 15911 transitions. [2020-11-28 03:03:32,291 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2020-11-28 03:03:32,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11782 states and 15911 transitions. [2020-11-28 03:03:32,338 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11712 [2020-11-28 03:03:32,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:32,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:32,341 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:32,341 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:32,341 INFO L794 eck$LassoCheckResult]: Stem: 187471#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 187392#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 187393#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 187434#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 187157#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 187158#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 187061#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 187062#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 187315#L377-1 assume !(0 == ~M_E~0); 187286#L518-1 assume !(0 == ~T1_E~0); 187138#L523-1 assume !(0 == ~T2_E~0); 187139#L528-1 assume !(0 == ~T3_E~0); 187165#L533-1 assume !(0 == ~T4_E~0); 187166#L538-1 assume !(0 == ~E_M~0); 187079#L543-1 assume !(0 == ~E_1~0); 187080#L548-1 assume !(0 == ~E_2~0); 187325#L553-1 assume !(0 == ~E_3~0); 187326#L558-1 assume !(0 == ~E_4~0); 187195#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 187196#L254 assume !(1 == ~m_pc~0); 187234#L254-2 is_master_triggered_~__retres1~0 := 0; 187235#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 187189#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 187190#L641 assume !(0 != activate_threads_~tmp~1); 187340#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 187341#L273 assume !(1 == ~t1_pc~0); 187387#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 187388#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 187389#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 187390#L649 assume !(0 != activate_threads_~tmp___0~0); 187495#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 187133#L292 assume !(1 == ~t2_pc~0); 187126#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 187097#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 187098#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 187529#L657 assume !(0 != activate_threads_~tmp___1~0); 187555#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 187317#L311 assume !(1 == ~t3_pc~0); 187065#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 187316#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 187063#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 187030#L665 assume !(0 != activate_threads_~tmp___2~0); 187031#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 187032#L330 assume !(1 == ~t4_pc~0); 187472#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 187473#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 187278#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 187215#L673 assume !(0 != activate_threads_~tmp___3~0); 187216#L673-2 assume !(1 == ~M_E~0); 187090#L576-1 assume !(1 == ~T1_E~0); 187091#L581-1 assume !(1 == ~T2_E~0); 187321#L586-1 assume !(1 == ~T3_E~0); 187322#L591-1 assume !(1 == ~T4_E~0); 187193#L596-1 assume !(1 == ~E_M~0); 187194#L601-1 assume !(1 == ~E_1~0); 187283#L606-1 assume !(1 == ~E_2~0); 187134#L611-1 assume !(1 == ~E_3~0); 187135#L616-1 assume !(1 == ~E_4~0); 187496#L807-1 assume !false; 188297#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 188088#L493 [2020-11-28 03:03:32,342 INFO L796 eck$LassoCheckResult]: Loop: 188088#L493 assume !false; 188085#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 188082#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 188080#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 188079#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 188076#L432 assume 0 != eval_~tmp~0; 188071#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 188067#L440 assume !(0 != eval_~tmp_ndt_1~0); 188065#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 187990#L454 assume !(0 != eval_~tmp_ndt_2~0); 188063#L451 assume !(0 == ~t2_st~0); 188307#L465 assume !(0 == ~t3_st~0); 188295#L479 assume !(0 == ~t4_st~0); 188088#L493 [2020-11-28 03:03:32,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:32,343 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2020-11-28 03:03:32,343 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:32,345 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773278772] [2020-11-28 03:03:32,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:32,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:32,356 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:32,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:32,369 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:32,397 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:32,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:32,397 INFO L82 PathProgramCache]: Analyzing trace with hash -885327886, now seen corresponding path program 2 times [2020-11-28 03:03:32,398 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:32,398 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599697569] [2020-11-28 03:03:32,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:32,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:32,402 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:32,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:32,406 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:32,408 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:32,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:32,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1569242579, now seen corresponding path program 1 times [2020-11-28 03:03:32,409 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:32,409 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314975319] [2020-11-28 03:03:32,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:32,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:32,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:32,466 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314975319] [2020-11-28 03:03:32,466 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:32,467 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:32,467 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982513150] [2020-11-28 03:03:32,581 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:32,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:32,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:32,582 INFO L87 Difference]: Start difference. First operand 11782 states and 15911 transitions. cyclomatic complexity: 4132 Second operand 3 states. [2020-11-28 03:03:32,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:32,752 INFO L93 Difference]: Finished difference Result 21718 states and 29091 transitions. [2020-11-28 03:03:32,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:32,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21718 states and 29091 transitions. [2020-11-28 03:03:32,871 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21640 [2020-11-28 03:03:32,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21718 states to 21718 states and 29091 transitions. [2020-11-28 03:03:32,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21718 [2020-11-28 03:03:32,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21718 [2020-11-28 03:03:32,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21718 states and 29091 transitions. [2020-11-28 03:03:32,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:32,984 INFO L691 BuchiCegarLoop]: Abstraction has 21718 states and 29091 transitions. [2020-11-28 03:03:33,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21718 states and 29091 transitions. [2020-11-28 03:03:33,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21718 to 21256. [2020-11-28 03:03:33,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21256 states. [2020-11-28 03:03:33,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21256 states to 21256 states and 28531 transitions. [2020-11-28 03:03:33,263 INFO L714 BuchiCegarLoop]: Abstraction has 21256 states and 28531 transitions. [2020-11-28 03:03:33,263 INFO L594 BuchiCegarLoop]: Abstraction has 21256 states and 28531 transitions. [2020-11-28 03:03:33,263 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2020-11-28 03:03:33,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21256 states and 28531 transitions. [2020-11-28 03:03:33,354 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21178 [2020-11-28 03:03:33,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:33,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:33,356 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:33,356 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:33,356 INFO L794 eck$LassoCheckResult]: Stem: 221001#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 220919#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 220920#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 220960#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 220664#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220665#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 220569#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220570#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220823#L377-1 assume !(0 == ~M_E~0); 220795#L518-1 assume !(0 == ~T1_E~0); 220649#L523-1 assume !(0 == ~T2_E~0); 220650#L528-1 assume !(0 == ~T3_E~0); 220672#L533-1 assume !(0 == ~T4_E~0); 220673#L538-1 assume !(0 == ~E_M~0); 220588#L543-1 assume !(0 == ~E_1~0); 220589#L548-1 assume !(0 == ~E_2~0); 220838#L553-1 assume !(0 == ~E_3~0); 220839#L558-1 assume !(0 == ~E_4~0); 220706#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 220707#L254 assume !(1 == ~m_pc~0); 220744#L254-2 is_master_triggered_~__retres1~0 := 0; 220745#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 220700#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 220701#L641 assume !(0 != activate_threads_~tmp~1); 220854#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 220855#L273 assume !(1 == ~t1_pc~0); 220915#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 220916#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 220917#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 220918#L649 assume !(0 != activate_threads_~tmp___0~0); 221023#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 220644#L292 assume !(1 == ~t2_pc~0); 220634#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 220608#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 220609#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 221055#L657 assume !(0 != activate_threads_~tmp___1~0); 221090#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 220827#L311 assume !(1 == ~t3_pc~0); 220573#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 220826#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 220571#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 220538#L665 assume !(0 != activate_threads_~tmp___2~0); 220539#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 220540#L330 assume !(1 == ~t4_pc~0); 221003#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 221004#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 220786#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 220721#L673 assume !(0 != activate_threads_~tmp___3~0); 220722#L673-2 assume !(1 == ~M_E~0); 220600#L576-1 assume !(1 == ~T1_E~0); 220601#L581-1 assume !(1 == ~T2_E~0); 220834#L586-1 assume !(1 == ~T3_E~0); 220835#L591-1 assume !(1 == ~T4_E~0); 220704#L596-1 assume !(1 == ~E_M~0); 220705#L601-1 assume !(1 == ~E_1~0); 220792#L606-1 assume !(1 == ~E_2~0); 220645#L611-1 assume !(1 == ~E_3~0); 220646#L616-1 assume !(1 == ~E_4~0); 221024#L807-1 assume !false; 226144#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 226140#L493 [2020-11-28 03:03:33,357 INFO L796 eck$LassoCheckResult]: Loop: 226140#L493 assume !false; 226104#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 226099#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 226097#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 226095#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 226093#L432 assume 0 != eval_~tmp~0; 226090#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 226091#L440 assume !(0 != eval_~tmp_ndt_1~0); 226729#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 226079#L454 assume !(0 != eval_~tmp_ndt_2~0); 226081#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 226291#L468 assume !(0 != eval_~tmp_ndt_3~0); 226271#L465 assume !(0 == ~t3_st~0); 226142#L479 assume !(0 == ~t4_st~0); 226140#L493 [2020-11-28 03:03:33,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:33,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2020-11-28 03:03:33,358 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:33,358 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748105631] [2020-11-28 03:03:33,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:33,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:33,368 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:33,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:33,381 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:33,395 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:33,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:33,396 INFO L82 PathProgramCache]: Analyzing trace with hash -1680045403, now seen corresponding path program 1 times [2020-11-28 03:03:33,397 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:33,397 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544395765] [2020-11-28 03:03:33,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:33,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:33,402 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:33,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:33,404 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:33,407 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:33,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:33,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1406564406, now seen corresponding path program 1 times [2020-11-28 03:03:33,408 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:33,408 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139408923] [2020-11-28 03:03:33,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:33,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:33,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:33,446 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139408923] [2020-11-28 03:03:33,446 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:33,446 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:03:33,448 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739117221] [2020-11-28 03:03:33,586 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:33,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:33,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:33,587 INFO L87 Difference]: Start difference. First operand 21256 states and 28531 transitions. cyclomatic complexity: 7278 Second operand 3 states. [2020-11-28 03:03:33,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:33,875 INFO L93 Difference]: Finished difference Result 37274 states and 49783 transitions. [2020-11-28 03:03:33,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:33,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37274 states and 49783 transitions. [2020-11-28 03:03:34,045 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 37180 [2020-11-28 03:03:34,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37274 states to 37274 states and 49783 transitions. [2020-11-28 03:03:34,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37274 [2020-11-28 03:03:34,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37274 [2020-11-28 03:03:34,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37274 states and 49783 transitions. [2020-11-28 03:03:34,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:34,207 INFO L691 BuchiCegarLoop]: Abstraction has 37274 states and 49783 transitions. [2020-11-28 03:03:34,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37274 states and 49783 transitions. [2020-11-28 03:03:34,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37274 to 36210. [2020-11-28 03:03:34,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36210 states. [2020-11-28 03:03:34,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36210 states to 36210 states and 48495 transitions. [2020-11-28 03:03:34,708 INFO L714 BuchiCegarLoop]: Abstraction has 36210 states and 48495 transitions. [2020-11-28 03:03:34,708 INFO L594 BuchiCegarLoop]: Abstraction has 36210 states and 48495 transitions. [2020-11-28 03:03:34,708 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2020-11-28 03:03:34,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36210 states and 48495 transitions. [2020-11-28 03:03:34,828 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 36116 [2020-11-28 03:03:34,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:34,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:34,829 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:34,829 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:34,829 INFO L794 eck$LassoCheckResult]: Stem: 279544#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 279461#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 279462#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 279503#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 279204#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279205#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 279107#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 279108#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 279374#L377-1 assume !(0 == ~M_E~0); 279340#L518-1 assume !(0 == ~T1_E~0); 279184#L523-1 assume !(0 == ~T2_E~0); 279185#L528-1 assume !(0 == ~T3_E~0); 279213#L533-1 assume !(0 == ~T4_E~0); 279214#L538-1 assume !(0 == ~E_M~0); 279125#L543-1 assume !(0 == ~E_1~0); 279126#L548-1 assume !(0 == ~E_2~0); 279386#L553-1 assume !(0 == ~E_3~0); 279387#L558-1 assume !(0 == ~E_4~0); 279249#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 279250#L254 assume !(1 == ~m_pc~0); 279286#L254-2 is_master_triggered_~__retres1~0 := 0; 279287#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 279243#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 279244#L641 assume !(0 != activate_threads_~tmp~1); 279402#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 279403#L273 assume !(1 == ~t1_pc~0); 279454#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 279455#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 279456#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 279457#L649 assume !(0 != activate_threads_~tmp___0~0); 279574#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 279179#L292 assume !(1 == ~t2_pc~0); 279172#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 279145#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 279146#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 279610#L657 assume !(0 != activate_threads_~tmp___1~0); 279652#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 279376#L311 assume !(1 == ~t3_pc~0); 279111#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 279375#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 279109#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 279076#L665 assume !(0 != activate_threads_~tmp___2~0); 279077#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 279078#L330 assume !(1 == ~t4_pc~0); 279545#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 279546#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 279330#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 279269#L673 assume !(0 != activate_threads_~tmp___3~0); 279270#L673-2 assume !(1 == ~M_E~0); 279137#L576-1 assume !(1 == ~T1_E~0); 279138#L581-1 assume !(1 == ~T2_E~0); 279382#L586-1 assume !(1 == ~T3_E~0); 279383#L591-1 assume !(1 == ~T4_E~0); 279247#L596-1 assume !(1 == ~E_M~0); 279248#L601-1 assume !(1 == ~E_1~0); 279336#L606-1 assume !(1 == ~E_2~0); 279180#L611-1 assume !(1 == ~E_3~0); 279181#L616-1 assume !(1 == ~E_4~0); 279575#L807-1 assume !false; 291261#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 289514#L493 [2020-11-28 03:03:34,829 INFO L796 eck$LassoCheckResult]: Loop: 289514#L493 assume !false; 291255#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 291251#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 291248#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 291090#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 291089#L432 assume 0 != eval_~tmp~0; 291087#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 291085#L440 assume !(0 != eval_~tmp_ndt_1~0); 287529#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 287526#L454 assume !(0 != eval_~tmp_ndt_2~0); 284836#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 284834#L468 assume !(0 != eval_~tmp_ndt_3~0); 284835#L465 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 287188#L482 assume !(0 != eval_~tmp_ndt_4~0); 289515#L479 assume !(0 == ~t4_st~0); 289514#L493 [2020-11-28 03:03:34,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:34,830 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2020-11-28 03:03:34,830 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:34,830 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698695113] [2020-11-28 03:03:34,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:34,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:34,840 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:34,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:34,849 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:34,863 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:34,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:34,864 INFO L82 PathProgramCache]: Analyzing trace with hash -541949788, now seen corresponding path program 1 times [2020-11-28 03:03:34,864 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:34,864 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347847508] [2020-11-28 03:03:34,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:34,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:34,868 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:34,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:34,871 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:34,874 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:34,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:34,875 INFO L82 PathProgramCache]: Analyzing trace with hash -653973473, now seen corresponding path program 1 times [2020-11-28 03:03:34,875 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:34,875 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535712411] [2020-11-28 03:03:34,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:34,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:03:34,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:03:34,914 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535712411] [2020-11-28 03:03:34,914 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:03:34,914 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:03:34,915 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219115756] [2020-11-28 03:03:35,052 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:03:35,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:03:35,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:03:35,053 INFO L87 Difference]: Start difference. First operand 36210 states and 48495 transitions. cyclomatic complexity: 12288 Second operand 3 states. [2020-11-28 03:03:35,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:03:35,742 INFO L93 Difference]: Finished difference Result 64766 states and 86495 transitions. [2020-11-28 03:03:35,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:03:35,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64766 states and 86495 transitions. [2020-11-28 03:03:36,111 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 64640 [2020-11-28 03:03:36,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64766 states to 64766 states and 86495 transitions. [2020-11-28 03:03:36,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64766 [2020-11-28 03:03:36,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64766 [2020-11-28 03:03:36,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64766 states and 86495 transitions. [2020-11-28 03:03:36,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:03:36,441 INFO L691 BuchiCegarLoop]: Abstraction has 64766 states and 86495 transitions. [2020-11-28 03:03:36,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64766 states and 86495 transitions. [2020-11-28 03:03:37,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64766 to 64430. [2020-11-28 03:03:37,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64430 states. [2020-11-28 03:03:37,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64430 states to 64430 states and 86159 transitions. [2020-11-28 03:03:37,412 INFO L714 BuchiCegarLoop]: Abstraction has 64430 states and 86159 transitions. [2020-11-28 03:03:37,412 INFO L594 BuchiCegarLoop]: Abstraction has 64430 states and 86159 transitions. [2020-11-28 03:03:37,412 INFO L427 BuchiCegarLoop]: ======== Iteration 25============ [2020-11-28 03:03:37,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64430 states and 86159 transitions. [2020-11-28 03:03:37,766 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 64304 [2020-11-28 03:03:37,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:03:37,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:03:37,768 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:37,768 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:03:37,768 INFO L794 eck$LassoCheckResult]: Stem: 380508#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 380430#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 380431#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 380468#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 380186#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 380187#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 380091#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 380092#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 380349#L377-1 assume !(0 == ~M_E~0); 380321#L518-1 assume !(0 == ~T1_E~0); 380169#L523-1 assume !(0 == ~T2_E~0); 380170#L528-1 assume !(0 == ~T3_E~0); 380195#L533-1 assume !(0 == ~T4_E~0); 380196#L538-1 assume !(0 == ~E_M~0); 380109#L543-1 assume !(0 == ~E_1~0); 380110#L548-1 assume !(0 == ~E_2~0); 380361#L553-1 assume !(0 == ~E_3~0); 380362#L558-1 assume !(0 == ~E_4~0); 380229#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 380230#L254 assume !(1 == ~m_pc~0); 380267#L254-2 is_master_triggered_~__retres1~0 := 0; 380268#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 380223#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 380224#L641 assume !(0 != activate_threads_~tmp~1); 380377#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 380378#L273 assume !(1 == ~t1_pc~0); 380426#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 380427#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 380428#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 380429#L649 assume !(0 != activate_threads_~tmp___0~0); 380538#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 380164#L292 assume !(1 == ~t2_pc~0); 380156#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 380130#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 380131#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 380568#L657 assume !(0 != activate_threads_~tmp___1~0); 380612#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 380353#L311 assume !(1 == ~t3_pc~0); 380095#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 380352#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 380093#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 380060#L665 assume !(0 != activate_threads_~tmp___2~0); 380061#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 380062#L330 assume !(1 == ~t4_pc~0); 380509#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 380510#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 380309#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 380245#L673 assume !(0 != activate_threads_~tmp___3~0); 380246#L673-2 assume !(1 == ~M_E~0); 380121#L576-1 assume !(1 == ~T1_E~0); 380122#L581-1 assume !(1 == ~T2_E~0); 380357#L586-1 assume !(1 == ~T3_E~0); 380358#L591-1 assume !(1 == ~T4_E~0); 380227#L596-1 assume !(1 == ~E_M~0); 380228#L601-1 assume !(1 == ~E_1~0); 380316#L606-1 assume !(1 == ~E_2~0); 380165#L611-1 assume !(1 == ~E_3~0); 380166#L616-1 assume !(1 == ~E_4~0); 380539#L807-1 assume !false; 398870#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 394586#L493 [2020-11-28 03:03:37,769 INFO L796 eck$LassoCheckResult]: Loop: 394586#L493 assume !false; 398850#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 398487#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 398483#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 398481#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 398478#L432 assume 0 != eval_~tmp~0; 398479#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 401615#L440 assume !(0 != eval_~tmp_ndt_1~0); 399254#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 399252#L454 assume !(0 != eval_~tmp_ndt_2~0); 395678#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 395567#L468 assume !(0 != eval_~tmp_ndt_3~0); 395533#L465 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 394844#L482 assume !(0 != eval_~tmp_ndt_4~0); 394588#L479 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 394585#L496 assume !(0 != eval_~tmp_ndt_5~0); 394586#L493 [2020-11-28 03:03:37,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:37,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2020-11-28 03:03:37,770 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:37,770 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222055522] [2020-11-28 03:03:37,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:37,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,781 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,790 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,805 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:37,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:37,806 INFO L82 PathProgramCache]: Analyzing trace with hash 379422195, now seen corresponding path program 1 times [2020-11-28 03:03:37,807 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:37,807 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657473202] [2020-11-28 03:03:37,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:37,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,811 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,814 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,816 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:37,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:03:37,817 INFO L82 PathProgramCache]: Analyzing trace with hash 1201655256, now seen corresponding path program 1 times [2020-11-28 03:03:37,817 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:03:37,817 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123778923] [2020-11-28 03:03:37,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:03:37,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,828 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:03:37,837 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:03:37,858 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:03:37,967 WARN L193 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2020-11-28 03:03:39,463 WARN L193 SmtUtils]: Spent 1.43 s on a formula simplification. DAG size of input: 220 DAG size of output: 159 [2020-11-28 03:03:39,860 WARN L193 SmtUtils]: Spent 373.00 ms on a formula simplification that was a NOOP. DAG size: 137 [2020-11-28 03:03:39,923 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:03:39 BoogieIcfgContainer [2020-11-28 03:03:39,923 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 03:03:39,926 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 03:03:39,926 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 03:03:39,926 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 03:03:39,927 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:03:22" (3/4) ... [2020-11-28 03:03:39,930 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 03:03:40,016 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c0763964-0559-4f19-b325-6c99d89f0490/bin/uautomizer/witness.graphml [2020-11-28 03:03:40,016 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 03:03:40,018 INFO L168 Benchmark]: Toolchain (without parser) took 20167.82 ms. Allocated memory was 100.7 MB in the beginning and 3.5 GB in the end (delta: 3.4 GB). Free memory was 68.6 MB in the beginning and 3.0 GB in the end (delta: -2.9 GB). Peak memory consumption was 441.5 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,018 INFO L168 Benchmark]: CDTParser took 1.60 ms. Allocated memory is still 79.7 MB. Free memory was 53.9 MB in the beginning and 53.9 MB in the end (delta: 25.3 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 03:03:40,018 INFO L168 Benchmark]: CACSL2BoogieTranslator took 455.33 ms. Allocated memory is still 100.7 MB. Free memory was 68.5 MB in the beginning and 73.3 MB in the end (delta: -4.8 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,019 INFO L168 Benchmark]: Boogie Procedure Inliner took 124.77 ms. Allocated memory is still 100.7 MB. Free memory was 73.3 MB in the beginning and 69.1 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,019 INFO L168 Benchmark]: Boogie Preprocessor took 154.47 ms. Allocated memory is still 100.7 MB. Free memory was 69.1 MB in the beginning and 65.4 MB in the end (delta: 3.7 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,020 INFO L168 Benchmark]: RCFGBuilder took 1791.27 ms. Allocated memory is still 100.7 MB. Free memory was 65.4 MB in the beginning and 55.5 MB in the end (delta: 9.9 MB). Peak memory consumption was 45.9 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,020 INFO L168 Benchmark]: BuchiAutomizer took 17541.80 ms. Allocated memory was 100.7 MB in the beginning and 3.5 GB in the end (delta: 3.4 GB). Free memory was 54.9 MB in the beginning and 3.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 576.5 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,021 INFO L168 Benchmark]: Witness Printer took 90.56 ms. Allocated memory is still 3.5 GB. Free memory was 3.0 GB in the beginning and 3.0 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:03:40,023 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.60 ms. Allocated memory is still 79.7 MB. Free memory was 53.9 MB in the beginning and 53.9 MB in the end (delta: 25.3 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 455.33 ms. Allocated memory is still 100.7 MB. Free memory was 68.5 MB in the beginning and 73.3 MB in the end (delta: -4.8 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 124.77 ms. Allocated memory is still 100.7 MB. Free memory was 73.3 MB in the beginning and 69.1 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 154.47 ms. Allocated memory is still 100.7 MB. Free memory was 69.1 MB in the beginning and 65.4 MB in the end (delta: 3.7 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1791.27 ms. Allocated memory is still 100.7 MB. Free memory was 65.4 MB in the beginning and 55.5 MB in the end (delta: 9.9 MB). Peak memory consumption was 45.9 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 17541.80 ms. Allocated memory was 100.7 MB in the beginning and 3.5 GB in the end (delta: 3.4 GB). Free memory was 54.9 MB in the beginning and 3.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 576.5 MB. Max. memory is 16.1 GB. * Witness Printer took 90.56 ms. Allocated memory is still 3.5 GB. Free memory was 3.0 GB in the beginning and 3.0 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 64430 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 17.4s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 5.6s. Construction of modules took 1.4s. Büchi inclusion checks took 2.4s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 3.7s AutomataMinimizationTime, 24 MinimizatonAttempts, 28445 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 2.5s Buchi closure took 0.1s. Biggest automaton had 64430 states and ocurred in iteration 24. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 16330 SDtfs, 20370 SDslu, 15811 SDs, 0 SdLazy, 690 SolverSat, 289 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 427]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=18698} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=18698, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@134dca7b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@db42417=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@840e21c=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e58fc0d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@cf7e15a=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7da56dcd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72fa2067=0, tmp=0, \result=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7db03049=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4e438a20=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@124cca0=0, NULL=18699, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f7cb3fc=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6af1624b=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47f8dd29=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=18700, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=18701, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 427]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int T2_E = 2; [L34] int T3_E = 2; [L35] int T4_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L47] int token ; [L49] int local ; [L852] int __retres1 ; [L764] m_i = 1 [L765] t1_i = 1 [L766] t2_i = 1 [L767] t3_i = 1 [L768] t4_i = 1 [L793] int kernel_st ; [L794] int tmp ; [L795] int tmp___0 ; [L799] kernel_st = 0 [L357] COND TRUE m_i == 1 [L358] m_st = 0 [L362] COND TRUE t1_i == 1 [L363] t1_st = 0 [L367] COND TRUE t2_i == 1 [L368] t2_st = 0 [L372] COND TRUE t3_i == 1 [L373] t3_st = 0 [L377] COND TRUE t4_i == 1 [L378] t4_st = 0 [L518] COND FALSE !(M_E == 0) [L523] COND FALSE !(T1_E == 0) [L528] COND FALSE !(T2_E == 0) [L533] COND FALSE !(T3_E == 0) [L538] COND FALSE !(T4_E == 0) [L543] COND FALSE !(E_M == 0) [L548] COND FALSE !(E_1 == 0) [L553] COND FALSE !(E_2 == 0) [L558] COND FALSE !(E_3 == 0) [L563] COND FALSE !(E_4 == 0) [L631] int tmp ; [L632] int tmp___0 ; [L633] int tmp___1 ; [L634] int tmp___2 ; [L635] int tmp___3 ; [L251] int __retres1 ; [L254] COND FALSE !(m_pc == 1) [L264] __retres1 = 0 [L266] return (__retres1); [L639] tmp = is_master_triggered() [L641] COND FALSE !(\read(tmp)) [L270] int __retres1 ; [L273] COND FALSE !(t1_pc == 1) [L283] __retres1 = 0 [L285] return (__retres1); [L647] tmp___0 = is_transmit1_triggered() [L649] COND FALSE !(\read(tmp___0)) [L289] int __retres1 ; [L292] COND FALSE !(t2_pc == 1) [L302] __retres1 = 0 [L304] return (__retres1); [L655] tmp___1 = is_transmit2_triggered() [L657] COND FALSE !(\read(tmp___1)) [L308] int __retres1 ; [L311] COND FALSE !(t3_pc == 1) [L321] __retres1 = 0 [L323] return (__retres1); [L663] tmp___2 = is_transmit3_triggered() [L665] COND FALSE !(\read(tmp___2)) [L327] int __retres1 ; [L330] COND FALSE !(t4_pc == 1) [L340] __retres1 = 0 [L342] return (__retres1); [L671] tmp___3 = is_transmit4_triggered() [L673] COND FALSE !(\read(tmp___3)) [L576] COND FALSE !(M_E == 1) [L581] COND FALSE !(T1_E == 1) [L586] COND FALSE !(T2_E == 1) [L591] COND FALSE !(T3_E == 1) [L596] COND FALSE !(T4_E == 1) [L601] COND FALSE !(E_M == 1) [L606] COND FALSE !(E_1 == 1) [L611] COND FALSE !(E_2 == 1) [L616] COND FALSE !(E_3 == 1) [L621] COND FALSE !(E_4 == 1) [L807] COND TRUE 1 [L810] kernel_st = 1 [L423] int tmp ; Loop: [L427] COND TRUE 1 [L387] int __retres1 ; [L390] COND TRUE m_st == 0 [L391] __retres1 = 1 [L418] return (__retres1); [L430] tmp = exists_runnable_thread() [L432] COND TRUE \read(tmp) [L437] COND TRUE m_st == 0 [L438] int tmp_ndt_1; [L439] tmp_ndt_1 = __VERIFIER_nondet_int() [L440] COND FALSE !(\read(tmp_ndt_1)) [L451] COND TRUE t1_st == 0 [L452] int tmp_ndt_2; [L453] tmp_ndt_2 = __VERIFIER_nondet_int() [L454] COND FALSE !(\read(tmp_ndt_2)) [L465] COND TRUE t2_st == 0 [L466] int tmp_ndt_3; [L467] tmp_ndt_3 = __VERIFIER_nondet_int() [L468] COND FALSE !(\read(tmp_ndt_3)) [L479] COND TRUE t3_st == 0 [L480] int tmp_ndt_4; [L481] tmp_ndt_4 = __VERIFIER_nondet_int() [L482] COND FALSE !(\read(tmp_ndt_4)) [L493] COND TRUE t4_st == 0 [L494] int tmp_ndt_5; [L495] tmp_ndt_5 = __VERIFIER_nondet_int() [L496] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...