./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5937481bc19468f59d919de13c534d2ea0f2da0e ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 03:11:17,396 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 03:11:17,398 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 03:11:17,444 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 03:11:17,444 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 03:11:17,466 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 03:11:17,468 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 03:11:17,477 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 03:11:17,479 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 03:11:17,498 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 03:11:17,499 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 03:11:17,500 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 03:11:17,501 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 03:11:17,502 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 03:11:17,504 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 03:11:17,505 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 03:11:17,506 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 03:11:17,508 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 03:11:17,510 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 03:11:17,538 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 03:11:17,541 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 03:11:17,542 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 03:11:17,548 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 03:11:17,550 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 03:11:17,554 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 03:11:17,554 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 03:11:17,555 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 03:11:17,557 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 03:11:17,558 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 03:11:17,559 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 03:11:17,559 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 03:11:17,561 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 03:11:17,563 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 03:11:17,564 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 03:11:17,565 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 03:11:17,566 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 03:11:17,567 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 03:11:17,567 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 03:11:17,567 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 03:11:17,568 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 03:11:17,569 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 03:11:17,572 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 03:11:17,621 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 03:11:17,624 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 03:11:17,626 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 03:11:17,626 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 03:11:17,626 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 03:11:17,627 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 03:11:17,627 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 03:11:17,627 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 03:11:17,627 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 03:11:17,628 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 03:11:17,629 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 03:11:17,629 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 03:11:17,630 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 03:11:17,630 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 03:11:17,630 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 03:11:17,630 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 03:11:17,630 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 03:11:17,631 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 03:11:17,631 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 03:11:17,631 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 03:11:17,631 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 03:11:17,632 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 03:11:17,632 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 03:11:17,632 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 03:11:17,632 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 03:11:17,633 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 03:11:17,633 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 03:11:17,633 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 03:11:17,633 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 03:11:17,635 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 03:11:17,636 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 03:11:17,636 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 03:11:17,637 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 03:11:17,637 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5937481bc19468f59d919de13c534d2ea0f2da0e [2020-11-28 03:11:17,892 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 03:11:17,929 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 03:11:17,933 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 03:11:17,935 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 03:11:17,936 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 03:11:17,937 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2020-11-28 03:11:18,037 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/data/6f7541105/e99171b112674a14ba1988d0d42a97ce/FLAG3d2d88ea6 [2020-11-28 03:11:18,566 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 03:11:18,566 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2020-11-28 03:11:18,582 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/data/6f7541105/e99171b112674a14ba1988d0d42a97ce/FLAG3d2d88ea6 [2020-11-28 03:11:18,882 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/data/6f7541105/e99171b112674a14ba1988d0d42a97ce [2020-11-28 03:11:18,885 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 03:11:18,888 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 03:11:18,892 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 03:11:18,892 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 03:11:18,895 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 03:11:18,897 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:11:18" (1/1) ... [2020-11-28 03:11:18,899 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4abacec7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:18, skipping insertion in model container [2020-11-28 03:11:18,899 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:11:18" (1/1) ... [2020-11-28 03:11:18,906 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 03:11:18,957 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 03:11:19,206 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:11:19,217 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 03:11:19,275 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:11:19,300 INFO L208 MainTranslator]: Completed translation [2020-11-28 03:11:19,301 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19 WrapperNode [2020-11-28 03:11:19,301 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 03:11:19,302 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 03:11:19,302 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 03:11:19,302 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 03:11:19,310 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,327 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,397 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 03:11:19,398 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 03:11:19,398 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 03:11:19,398 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 03:11:19,406 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,407 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,416 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,416 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,436 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,467 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,474 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... [2020-11-28 03:11:19,496 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 03:11:19,497 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 03:11:19,497 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 03:11:19,497 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 03:11:19,503 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 03:11:19,617 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 03:11:19,617 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 03:11:19,618 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 03:11:19,618 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 03:11:21,345 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 03:11:21,348 INFO L298 CfgBuilder]: Removed 202 assume(true) statements. [2020-11-28 03:11:21,351 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:11:21 BoogieIcfgContainer [2020-11-28 03:11:21,351 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 03:11:21,353 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 03:11:21,353 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 03:11:21,356 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 03:11:21,357 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:11:21,357 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:11:18" (1/3) ... [2020-11-28 03:11:21,358 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56ef8c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:11:21, skipping insertion in model container [2020-11-28 03:11:21,359 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:11:21,359 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:11:19" (2/3) ... [2020-11-28 03:11:21,360 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56ef8c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:11:21, skipping insertion in model container [2020-11-28 03:11:21,360 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:11:21,360 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:11:21" (3/3) ... [2020-11-28 03:11:21,362 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2020-11-28 03:11:21,412 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 03:11:21,413 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 03:11:21,413 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 03:11:21,413 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 03:11:21,413 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 03:11:21,413 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 03:11:21,413 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 03:11:21,413 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 03:11:21,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 540 states. [2020-11-28 03:11:21,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 461 [2020-11-28 03:11:21,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:21,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:21,541 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:21,542 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:21,542 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 03:11:21,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 540 states. [2020-11-28 03:11:21,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 461 [2020-11-28 03:11:21,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:21,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:21,565 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:21,565 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:21,584 INFO L794 eck$LassoCheckResult]: Stem: 359#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 253#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 210#L895true havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56#L411true assume !(1 == ~m_i~0);~m_st~0 := 2; 371#L418-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 136#L423-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 285#L428-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 57#L433-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 488#L438-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 218#L443-1true assume !(0 == ~M_E~0); 502#L603-1true assume !(0 == ~T1_E~0); 222#L608-1true assume !(0 == ~T2_E~0); 529#L613-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 149#L618-1true assume !(0 == ~T4_E~0); 450#L623-1true assume !(0 == ~T5_E~0); 203#L628-1true assume !(0 == ~E_M~0); 98#L633-1true assume !(0 == ~E_1~0); 376#L638-1true assume !(0 == ~E_2~0); 5#L643-1true assume !(0 == ~E_3~0); 295#L648-1true assume !(0 == ~E_4~0); 64#L653-1true assume 0 == ~E_5~0;~E_5~0 := 1; 496#L658-1true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 251#L296true assume 1 == ~m_pc~0; 357#L297true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 257#L307true is_master_triggered_#res := is_master_triggered_~__retres1~0; 358#L308true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 307#L747true assume !(0 != activate_threads_~tmp~1); 291#L747-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 440#L315true assume !(1 == ~t1_pc~0); 410#L315-2true is_transmit1_triggered_~__retres1~1 := 0; 438#L326true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 522#L327true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 457#L755true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 460#L755-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37#L334true assume 1 == ~t2_pc~0; 139#L335true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 36#L345true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 138#L346true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70#L763true assume !(0 != activate_threads_~tmp___1~0); 61#L763-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 196#L353true assume !(1 == ~t3_pc~0); 200#L353-2true is_transmit3_triggered_~__retres1~3 := 0; 195#L364true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141#L365true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 343#L771true assume !(0 != activate_threads_~tmp___2~0); 344#L771-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 326#L372true assume 1 == ~t4_pc~0; 288#L373true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 490#L383true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 286#L384true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 505#L779true assume !(0 != activate_threads_~tmp___3~0); 492#L779-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 89#L391true assume !(1 == ~t5_pc~0); 93#L391-2true is_transmit5_triggered_~__retres1~5 := 0; 87#L402true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 430#L403true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 105#L787true assume !(0 != activate_threads_~tmp___4~0); 107#L787-2true assume !(1 == ~M_E~0); 374#L671-1true assume !(1 == ~T1_E~0); 4#L676-1true assume !(1 == ~T2_E~0); 292#L681-1true assume !(1 == ~T3_E~0); 63#L686-1true assume !(1 == ~T4_E~0); 494#L691-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 220#L696-1true assume !(1 == ~E_M~0); 540#L701-1true assume !(1 == ~E_1~0); 158#L706-1true assume !(1 == ~E_2~0); 461#L711-1true assume !(1 == ~E_3~0); 345#L716-1true assume !(1 == ~E_4~0); 108#L721-1true assume !(1 == ~E_5~0); 394#L932-1true [2020-11-28 03:11:21,586 INFO L796 eck$LassoCheckResult]: Loop: 394#L932-1true assume !false; 507#L933true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 100#L578true assume !true; 297#L593true start_simulation_~kernel_st~0 := 2; 59#L411-1true start_simulation_~kernel_st~0 := 3; 481#L603-2true assume 0 == ~M_E~0;~M_E~0 := 1; 484#L603-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 215#L608-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 534#L613-3true assume !(0 == ~T3_E~0); 151#L618-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 454#L623-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 205#L628-3true assume 0 == ~E_M~0;~E_M~0 := 1; 102#L633-3true assume 0 == ~E_1~0;~E_1~0 := 1; 380#L638-3true assume 0 == ~E_2~0;~E_2~0 := 1; 9#L643-3true assume 0 == ~E_3~0;~E_3~0 := 1; 300#L648-3true assume 0 == ~E_4~0;~E_4~0 := 1; 68#L653-3true assume !(0 == ~E_5~0); 503#L658-3true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 372#L296-21true assume !(1 == ~m_pc~0); 370#L296-23true is_master_triggered_~__retres1~0 := 0; 249#L307-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 352#L308-7true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 250#L747-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 386#L747-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 541#L315-21true assume !(1 == ~t1_pc~0); 530#L315-23true is_transmit1_triggered_~__retres1~1 := 0; 428#L326-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 517#L327-7true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 399#L755-21true assume !(0 != activate_threads_~tmp___0~0); 403#L755-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3#L334-21true assume 1 == ~t2_pc~0; 115#L335-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 30#L345-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114#L346-7true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 34#L763-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16#L763-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157#L353-21true assume 1 == ~t3_pc~0; 234#L354-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 191#L364-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 233#L365-7true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 169#L771-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 174#L771-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 309#L372-21true assume 1 == ~t4_pc~0; 242#L373-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 320#L383-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 239#L384-7true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 324#L779-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 310#L779-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 459#L391-21true assume 1 == ~t5_pc~0; 422#L392-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 80#L402-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 419#L403-7true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 476#L787-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 478#L787-23true assume 1 == ~M_E~0;~M_E~0 := 2; 377#L671-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 7#L676-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 299#L681-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 66#L686-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 499#L691-3true assume !(1 == ~T5_E~0); 221#L696-3true assume 1 == ~E_M~0;~E_M~0 := 2; 542#L701-3true assume 1 == ~E_1~0;~E_1~0 := 2; 160#L706-3true assume 1 == ~E_2~0;~E_2~0 := 2; 449#L711-3true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L716-3true assume 1 == ~E_4~0;~E_4~0 := 2; 97#L721-3true assume 1 == ~E_5~0;~E_5~0 := 2; 375#L726-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 134#L456-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54#L488-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 132#L489-1true start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 20#L951true assume !(0 == start_simulation_~tmp~3); 22#L951-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 137#L456-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55#L488-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 135#L489-2true stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 209#L906true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 390#L913true stop_simulation_#res := stop_simulation_~__retres2~0; 347#L914true start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 465#L964true assume !(0 != start_simulation_~tmp___0~1); 394#L932-1true [2020-11-28 03:11:21,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:21,592 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2020-11-28 03:11:21,600 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:21,600 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760323252] [2020-11-28 03:11:21,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:21,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:21,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:21,848 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760323252] [2020-11-28 03:11:21,849 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:21,849 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:21,850 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977834036] [2020-11-28 03:11:21,856 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:21,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:21,861 INFO L82 PathProgramCache]: Analyzing trace with hash 801195427, now seen corresponding path program 1 times [2020-11-28 03:11:21,861 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:21,861 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522638837] [2020-11-28 03:11:21,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:21,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:21,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:21,933 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522638837] [2020-11-28 03:11:21,934 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:21,934 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:11:21,934 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519545214] [2020-11-28 03:11:21,938 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:21,940 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:21,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:21,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:21,956 INFO L87 Difference]: Start difference. First operand 540 states. Second operand 3 states. [2020-11-28 03:11:22,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:22,041 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2020-11-28 03:11:22,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:22,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2020-11-28 03:11:22,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2020-11-28 03:11:22,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2020-11-28 03:11:22,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2020-11-28 03:11:22,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2020-11-28 03:11:22,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:22,078 INFO L691 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2020-11-28 03:11:22,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2020-11-28 03:11:22,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2020-11-28 03:11:22,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2020-11-28 03:11:22,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2020-11-28 03:11:22,160 INFO L714 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2020-11-28 03:11:22,160 INFO L594 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2020-11-28 03:11:22,161 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 03:11:22,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2020-11-28 03:11:22,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:22,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:22,172 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,172 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,173 INFO L794 eck$LassoCheckResult]: Stem: 1520#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1424#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1370#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1185#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 1186#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1282#L423-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1283#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1187#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1188#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1379#L443-1 assume !(0 == ~M_E~0); 1380#L603-1 assume !(0 == ~T1_E~0); 1385#L608-1 assume !(0 == ~T2_E~0); 1386#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1308#L618-1 assume !(0 == ~T4_E~0); 1309#L623-1 assume !(0 == ~T5_E~0); 1363#L628-1 assume !(0 == ~E_M~0); 1255#L633-1 assume !(0 == ~E_1~0); 1256#L638-1 assume !(0 == ~E_2~0); 1092#L643-1 assume !(0 == ~E_3~0); 1093#L648-1 assume !(0 == ~E_4~0); 1199#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1200#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1422#L296 assume 1 == ~m_pc~0; 1423#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1410#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1432#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1496#L747 assume !(0 != activate_threads_~tmp~1); 1488#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1489#L315 assume !(1 == ~t1_pc~0); 1558#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 1559#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1587#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1599#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1600#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1152#L334 assume 1 == ~t2_pc~0; 1153#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1150#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1151#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1209#L763 assume !(0 != activate_threads_~tmp___1~0); 1193#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1194#L353 assume !(1 == ~t3_pc~0); 1289#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 1290#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1286#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1287#L771 assume !(0 != activate_threads_~tmp___2~0); 1511#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1503#L372 assume 1 == ~t4_pc~0; 1482#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1483#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1479#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1480#L779 assume !(0 != activate_threads_~tmp___3~0); 1610#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1243#L391 assume !(1 == ~t5_pc~0); 1244#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 1241#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1242#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1268#L787 assume !(0 != activate_threads_~tmp___4~0); 1269#L787-2 assume !(1 == ~M_E~0); 1270#L671-1 assume !(1 == ~T1_E~0); 1090#L676-1 assume !(1 == ~T2_E~0); 1091#L681-1 assume !(1 == ~T3_E~0); 1197#L686-1 assume !(1 == ~T4_E~0); 1198#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1381#L696-1 assume !(1 == ~E_M~0); 1382#L701-1 assume !(1 == ~E_1~0); 1320#L706-1 assume !(1 == ~E_2~0); 1321#L711-1 assume !(1 == ~E_3~0); 1512#L716-1 assume !(1 == ~E_4~0); 1271#L721-1 assume !(1 == ~E_5~0); 1272#L932-1 [2020-11-28 03:11:22,175 INFO L796 eck$LassoCheckResult]: Loop: 1272#L932-1 assume !false; 1536#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1259#L578 assume !false; 1171#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1172#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1177#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1178#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1276#L503 assume !(0 != eval_~tmp~0); 1492#L593 start_simulation_~kernel_st~0 := 2; 1190#L411-1 start_simulation_~kernel_st~0 := 3; 1191#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1607#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1374#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1375#L613-3 assume !(0 == ~T3_E~0); 1311#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1312#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1365#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1262#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1263#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1100#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1101#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1205#L653-3 assume !(0 == ~E_5~0); 1206#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1529#L296-21 assume 1 == ~m_pc~0; 1523#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1416#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1417#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1418#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1419#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1531#L315-21 assume 1 == ~t1_pc~0; 1616#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1581#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1582#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1544#L755-21 assume !(0 != activate_threads_~tmp___0~0); 1545#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1087#L334-21 assume 1 == ~t2_pc~0; 1088#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1094#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1142#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1147#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1116#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1117#L353-21 assume !(1 == ~t3_pc~0); 1318#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 1322#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1353#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1336#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1337#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1342#L372-21 assume 1 == ~t4_pc~0; 1401#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1402#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1394#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1395#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1497#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1498#L391-21 assume 1 == ~t5_pc~0; 1572#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1227#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1228#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1568#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1606#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1530#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1095#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1096#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1202#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1203#L691-3 assume !(1 == ~T5_E~0); 1383#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1384#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1323#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1324#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1360#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1253#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1254#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1280#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1181#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1182#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1125#L951 assume !(0 == start_simulation_~tmp~3); 1126#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1129#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1183#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1184#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 1279#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1369#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 1513#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 1514#L964 assume !(0 != start_simulation_~tmp___0~1); 1272#L932-1 [2020-11-28 03:11:22,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,176 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2020-11-28 03:11:22,177 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,177 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251666444] [2020-11-28 03:11:22,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,277 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251666444] [2020-11-28 03:11:22,278 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,278 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,278 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977877962] [2020-11-28 03:11:22,278 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:22,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1477075777, now seen corresponding path program 1 times [2020-11-28 03:11:22,279 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,280 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608339485] [2020-11-28 03:11:22,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,395 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608339485] [2020-11-28 03:11:22,396 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,396 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,396 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926473430] [2020-11-28 03:11:22,397 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:22,398 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:22,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:22,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:22,400 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand 3 states. [2020-11-28 03:11:22,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:22,415 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2020-11-28 03:11:22,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:22,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2020-11-28 03:11:22,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2020-11-28 03:11:22,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2020-11-28 03:11:22,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2020-11-28 03:11:22,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2020-11-28 03:11:22,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:22,431 INFO L691 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2020-11-28 03:11:22,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2020-11-28 03:11:22,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2020-11-28 03:11:22,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2020-11-28 03:11:22,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2020-11-28 03:11:22,444 INFO L714 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2020-11-28 03:11:22,444 INFO L594 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2020-11-28 03:11:22,444 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 03:11:22,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2020-11-28 03:11:22,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:22,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:22,451 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,452 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,452 INFO L794 eck$LassoCheckResult]: Stem: 2591#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2495#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2441#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2256#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 2257#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2354#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2355#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2258#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2259#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2450#L443-1 assume !(0 == ~M_E~0); 2451#L603-1 assume !(0 == ~T1_E~0); 2456#L608-1 assume !(0 == ~T2_E~0); 2457#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2379#L618-1 assume !(0 == ~T4_E~0); 2380#L623-1 assume !(0 == ~T5_E~0); 2434#L628-1 assume !(0 == ~E_M~0); 2326#L633-1 assume !(0 == ~E_1~0); 2327#L638-1 assume !(0 == ~E_2~0); 2163#L643-1 assume !(0 == ~E_3~0); 2164#L648-1 assume !(0 == ~E_4~0); 2270#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2271#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2493#L296 assume 1 == ~m_pc~0; 2494#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2481#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2503#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2567#L747 assume !(0 != activate_threads_~tmp~1); 2559#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2560#L315 assume !(1 == ~t1_pc~0); 2629#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 2630#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2658#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2670#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2671#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2223#L334 assume 1 == ~t2_pc~0; 2224#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2221#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2222#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2280#L763 assume !(0 != activate_threads_~tmp___1~0); 2264#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2265#L353 assume !(1 == ~t3_pc~0); 2360#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 2361#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2357#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2358#L771 assume !(0 != activate_threads_~tmp___2~0); 2582#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2574#L372 assume 1 == ~t4_pc~0; 2553#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2554#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2550#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2551#L779 assume !(0 != activate_threads_~tmp___3~0); 2681#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2316#L391 assume !(1 == ~t5_pc~0); 2317#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 2312#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2313#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2339#L787 assume !(0 != activate_threads_~tmp___4~0); 2340#L787-2 assume !(1 == ~M_E~0); 2341#L671-1 assume !(1 == ~T1_E~0); 2161#L676-1 assume !(1 == ~T2_E~0); 2162#L681-1 assume !(1 == ~T3_E~0); 2268#L686-1 assume !(1 == ~T4_E~0); 2269#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2452#L696-1 assume !(1 == ~E_M~0); 2453#L701-1 assume !(1 == ~E_1~0); 2391#L706-1 assume !(1 == ~E_2~0); 2392#L711-1 assume !(1 == ~E_3~0); 2583#L716-1 assume !(1 == ~E_4~0); 2342#L721-1 assume !(1 == ~E_5~0); 2343#L932-1 [2020-11-28 03:11:22,453 INFO L796 eck$LassoCheckResult]: Loop: 2343#L932-1 assume !false; 2607#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2330#L578 assume !false; 2242#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2243#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2248#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2249#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2347#L503 assume !(0 != eval_~tmp~0); 2563#L593 start_simulation_~kernel_st~0 := 2; 2261#L411-1 start_simulation_~kernel_st~0 := 3; 2262#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2678#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2445#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2446#L613-3 assume !(0 == ~T3_E~0); 2382#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2383#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2436#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2333#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2334#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2171#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2172#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2276#L653-3 assume !(0 == ~E_5~0); 2277#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2600#L296-21 assume 1 == ~m_pc~0; 2594#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2487#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2488#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2489#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2490#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2602#L315-21 assume !(1 == ~t1_pc~0); 2688#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 2652#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2653#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2615#L755-21 assume !(0 != activate_threads_~tmp___0~0); 2616#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2158#L334-21 assume !(1 == ~t2_pc~0); 2160#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 2165#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2213#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2218#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2187#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2188#L353-21 assume !(1 == ~t3_pc~0); 2389#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 2393#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2424#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2407#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2408#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2413#L372-21 assume 1 == ~t4_pc~0; 2472#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2473#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2463#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2464#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2568#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2569#L391-21 assume 1 == ~t5_pc~0; 2640#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2298#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2299#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2639#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2676#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2601#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2166#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2167#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2273#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2274#L691-3 assume !(1 == ~T5_E~0); 2454#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2455#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2394#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2395#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2431#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2323#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2324#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2350#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2252#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2253#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2196#L951 assume !(0 == start_simulation_~tmp~3); 2197#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2200#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2254#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2255#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 2352#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2440#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 2584#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 2585#L964 assume !(0 != start_simulation_~tmp___0~1); 2343#L932-1 [2020-11-28 03:11:22,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,454 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2020-11-28 03:11:22,454 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,454 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802476479] [2020-11-28 03:11:22,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,543 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802476479] [2020-11-28 03:11:22,543 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,543 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,544 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101422922] [2020-11-28 03:11:22,544 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:22,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,545 INFO L82 PathProgramCache]: Analyzing trace with hash 58560189, now seen corresponding path program 1 times [2020-11-28 03:11:22,545 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,546 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296241045] [2020-11-28 03:11:22,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,651 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296241045] [2020-11-28 03:11:22,652 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,652 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,652 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063524913] [2020-11-28 03:11:22,653 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:22,653 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:22,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:22,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:22,654 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand 3 states. [2020-11-28 03:11:22,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:22,668 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2020-11-28 03:11:22,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:22,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2020-11-28 03:11:22,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2020-11-28 03:11:22,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2020-11-28 03:11:22,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2020-11-28 03:11:22,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2020-11-28 03:11:22,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:22,681 INFO L691 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2020-11-28 03:11:22,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2020-11-28 03:11:22,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2020-11-28 03:11:22,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2020-11-28 03:11:22,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2020-11-28 03:11:22,692 INFO L714 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2020-11-28 03:11:22,693 INFO L594 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2020-11-28 03:11:22,693 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 03:11:22,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2020-11-28 03:11:22,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:22,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:22,699 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,699 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,699 INFO L794 eck$LassoCheckResult]: Stem: 3662#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3566#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3512#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3327#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 3328#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3425#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3426#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3329#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3330#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3521#L443-1 assume !(0 == ~M_E~0); 3522#L603-1 assume !(0 == ~T1_E~0); 3527#L608-1 assume !(0 == ~T2_E~0); 3528#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3450#L618-1 assume !(0 == ~T4_E~0); 3451#L623-1 assume !(0 == ~T5_E~0); 3505#L628-1 assume !(0 == ~E_M~0); 3397#L633-1 assume !(0 == ~E_1~0); 3398#L638-1 assume !(0 == ~E_2~0); 3234#L643-1 assume !(0 == ~E_3~0); 3235#L648-1 assume !(0 == ~E_4~0); 3341#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3342#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3564#L296 assume 1 == ~m_pc~0; 3565#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3552#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3574#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3638#L747 assume !(0 != activate_threads_~tmp~1); 3630#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3631#L315 assume !(1 == ~t1_pc~0); 3700#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 3701#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3729#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3741#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3742#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3294#L334 assume 1 == ~t2_pc~0; 3295#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3292#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3293#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3351#L763 assume !(0 != activate_threads_~tmp___1~0); 3335#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3336#L353 assume !(1 == ~t3_pc~0); 3431#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 3432#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3428#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3429#L771 assume !(0 != activate_threads_~tmp___2~0); 3653#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3645#L372 assume 1 == ~t4_pc~0; 3624#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3625#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3621#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3622#L779 assume !(0 != activate_threads_~tmp___3~0); 3752#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3387#L391 assume !(1 == ~t5_pc~0); 3388#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 3383#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3384#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3410#L787 assume !(0 != activate_threads_~tmp___4~0); 3411#L787-2 assume !(1 == ~M_E~0); 3412#L671-1 assume !(1 == ~T1_E~0); 3232#L676-1 assume !(1 == ~T2_E~0); 3233#L681-1 assume !(1 == ~T3_E~0); 3339#L686-1 assume !(1 == ~T4_E~0); 3340#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3523#L696-1 assume !(1 == ~E_M~0); 3524#L701-1 assume !(1 == ~E_1~0); 3462#L706-1 assume !(1 == ~E_2~0); 3463#L711-1 assume !(1 == ~E_3~0); 3654#L716-1 assume !(1 == ~E_4~0); 3414#L721-1 assume !(1 == ~E_5~0); 3415#L932-1 [2020-11-28 03:11:22,700 INFO L796 eck$LassoCheckResult]: Loop: 3415#L932-1 assume !false; 3678#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3401#L578 assume !false; 3313#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3314#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3319#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3320#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3418#L503 assume !(0 != eval_~tmp~0); 3634#L593 start_simulation_~kernel_st~0 := 2; 3332#L411-1 start_simulation_~kernel_st~0 := 3; 3333#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3749#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3516#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3517#L613-3 assume !(0 == ~T3_E~0); 3453#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3454#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3507#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3404#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3405#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3242#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3243#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3347#L653-3 assume !(0 == ~E_5~0); 3348#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3671#L296-21 assume 1 == ~m_pc~0; 3665#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3558#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3559#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3560#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3561#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3673#L315-21 assume 1 == ~t1_pc~0; 3758#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3723#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3724#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3686#L755-21 assume !(0 != activate_threads_~tmp___0~0); 3687#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3229#L334-21 assume 1 == ~t2_pc~0; 3230#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3236#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3284#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3289#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3258#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3259#L353-21 assume !(1 == ~t3_pc~0); 3460#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 3464#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3495#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3478#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3479#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3484#L372-21 assume 1 == ~t4_pc~0; 3538#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3539#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3534#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3535#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3639#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3640#L391-21 assume !(1 == ~t5_pc~0); 3712#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 3369#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3370#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3710#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3748#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3672#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3237#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3238#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3344#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3345#L691-3 assume !(1 == ~T5_E~0); 3525#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3526#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3465#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3466#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3502#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3395#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3396#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3421#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3323#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3324#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3267#L951 assume !(0 == start_simulation_~tmp~3); 3268#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3271#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3325#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3326#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 3423#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3511#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 3655#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 3656#L964 assume !(0 != start_simulation_~tmp___0~1); 3415#L932-1 [2020-11-28 03:11:22,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,701 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2020-11-28 03:11:22,701 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,704 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836738094] [2020-11-28 03:11:22,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,774 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836738094] [2020-11-28 03:11:22,775 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,775 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,775 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896608354] [2020-11-28 03:11:22,775 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:22,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,776 INFO L82 PathProgramCache]: Analyzing trace with hash -1534220002, now seen corresponding path program 1 times [2020-11-28 03:11:22,777 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,777 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10441123] [2020-11-28 03:11:22,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,818 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10441123] [2020-11-28 03:11:22,819 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,819 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,819 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113746584] [2020-11-28 03:11:22,820 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:22,820 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:22,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:22,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:22,821 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand 3 states. [2020-11-28 03:11:22,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:22,834 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2020-11-28 03:11:22,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:22,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2020-11-28 03:11:22,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2020-11-28 03:11:22,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2020-11-28 03:11:22,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2020-11-28 03:11:22,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2020-11-28 03:11:22,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:22,847 INFO L691 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2020-11-28 03:11:22,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2020-11-28 03:11:22,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2020-11-28 03:11:22,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2020-11-28 03:11:22,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2020-11-28 03:11:22,858 INFO L714 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2020-11-28 03:11:22,858 INFO L594 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2020-11-28 03:11:22,858 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 03:11:22,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2020-11-28 03:11:22,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:22,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:22,864 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,864 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,865 INFO L794 eck$LassoCheckResult]: Stem: 4733#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4640#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4583#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4398#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 4399#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4496#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4497#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4400#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4401#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4592#L443-1 assume !(0 == ~M_E~0); 4593#L603-1 assume !(0 == ~T1_E~0); 4598#L608-1 assume !(0 == ~T2_E~0); 4599#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4521#L618-1 assume !(0 == ~T4_E~0); 4522#L623-1 assume !(0 == ~T5_E~0); 4576#L628-1 assume !(0 == ~E_M~0); 4468#L633-1 assume !(0 == ~E_1~0); 4469#L638-1 assume !(0 == ~E_2~0); 4305#L643-1 assume !(0 == ~E_3~0); 4306#L648-1 assume !(0 == ~E_4~0); 4412#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4413#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4635#L296 assume 1 == ~m_pc~0; 4636#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4623#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4648#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4709#L747 assume !(0 != activate_threads_~tmp~1); 4701#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4702#L315 assume !(1 == ~t1_pc~0); 4771#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 4772#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4800#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4812#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4813#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4365#L334 assume 1 == ~t2_pc~0; 4366#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4363#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4364#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4422#L763 assume !(0 != activate_threads_~tmp___1~0); 4406#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4407#L353 assume !(1 == ~t3_pc~0); 4502#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 4503#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4499#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4500#L771 assume !(0 != activate_threads_~tmp___2~0); 4724#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4716#L372 assume 1 == ~t4_pc~0; 4695#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4696#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4692#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4693#L779 assume !(0 != activate_threads_~tmp___3~0); 4823#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4458#L391 assume !(1 == ~t5_pc~0); 4459#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 4454#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4455#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4481#L787 assume !(0 != activate_threads_~tmp___4~0); 4482#L787-2 assume !(1 == ~M_E~0); 4483#L671-1 assume !(1 == ~T1_E~0); 4303#L676-1 assume !(1 == ~T2_E~0); 4304#L681-1 assume !(1 == ~T3_E~0); 4410#L686-1 assume !(1 == ~T4_E~0); 4411#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4594#L696-1 assume !(1 == ~E_M~0); 4595#L701-1 assume !(1 == ~E_1~0); 4533#L706-1 assume !(1 == ~E_2~0); 4534#L711-1 assume !(1 == ~E_3~0); 4725#L716-1 assume !(1 == ~E_4~0); 4485#L721-1 assume !(1 == ~E_5~0); 4486#L932-1 [2020-11-28 03:11:22,865 INFO L796 eck$LassoCheckResult]: Loop: 4486#L932-1 assume !false; 4749#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4472#L578 assume !false; 4384#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4385#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4390#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4391#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4489#L503 assume !(0 != eval_~tmp~0); 4705#L593 start_simulation_~kernel_st~0 := 2; 4403#L411-1 start_simulation_~kernel_st~0 := 3; 4404#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4820#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4587#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4588#L613-3 assume !(0 == ~T3_E~0); 4524#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4525#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4578#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4475#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4476#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4313#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4314#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4418#L653-3 assume !(0 == ~E_5~0); 4419#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4742#L296-21 assume 1 == ~m_pc~0; 4736#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4629#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4630#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4631#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4632#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4744#L315-21 assume 1 == ~t1_pc~0; 4829#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4794#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4795#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4757#L755-21 assume !(0 != activate_threads_~tmp___0~0); 4758#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4300#L334-21 assume 1 == ~t2_pc~0; 4301#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4307#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4355#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4359#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4329#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4330#L353-21 assume !(1 == ~t3_pc~0); 4531#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 4535#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4566#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4549#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4550#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4555#L372-21 assume 1 == ~t4_pc~0; 4609#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4610#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4605#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4606#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4710#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4711#L391-21 assume 1 == ~t5_pc~0; 4782#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4440#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4441#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4781#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4819#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4743#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4308#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4309#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4415#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4416#L691-3 assume !(1 == ~T5_E~0); 4596#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4597#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4536#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4537#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4573#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4466#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4467#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4492#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4394#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4395#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4338#L951 assume !(0 == start_simulation_~tmp~3); 4339#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4342#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4396#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4397#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 4494#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4582#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 4726#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 4727#L964 assume !(0 != start_simulation_~tmp___0~1); 4486#L932-1 [2020-11-28 03:11:22,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,866 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2020-11-28 03:11:22,866 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,866 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179453164] [2020-11-28 03:11:22,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,892 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179453164] [2020-11-28 03:11:22,892 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,892 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,892 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734107897] [2020-11-28 03:11:22,892 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:22,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1477075777, now seen corresponding path program 2 times [2020-11-28 03:11:22,893 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,894 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836519278] [2020-11-28 03:11:22,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:22,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:22,930 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836519278] [2020-11-28 03:11:22,930 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:22,930 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:22,930 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388836787] [2020-11-28 03:11:22,931 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:22,931 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:22,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:22,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:22,932 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand 3 states. [2020-11-28 03:11:22,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:22,950 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2020-11-28 03:11:22,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:22,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2020-11-28 03:11:22,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2020-11-28 03:11:22,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2020-11-28 03:11:22,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2020-11-28 03:11:22,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2020-11-28 03:11:22,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:22,963 INFO L691 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2020-11-28 03:11:22,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2020-11-28 03:11:22,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2020-11-28 03:11:22,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2020-11-28 03:11:22,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2020-11-28 03:11:22,973 INFO L714 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2020-11-28 03:11:22,973 INFO L594 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2020-11-28 03:11:22,973 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 03:11:22,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2020-11-28 03:11:22,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2020-11-28 03:11:22,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:22,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:22,979 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,979 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:22,980 INFO L794 eck$LassoCheckResult]: Stem: 5804#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5711#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5654#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5469#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 5470#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5567#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5568#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5472#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5473#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5663#L443-1 assume !(0 == ~M_E~0); 5664#L603-1 assume !(0 == ~T1_E~0); 5669#L608-1 assume !(0 == ~T2_E~0); 5670#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5592#L618-1 assume !(0 == ~T4_E~0); 5593#L623-1 assume !(0 == ~T5_E~0); 5647#L628-1 assume !(0 == ~E_M~0); 5539#L633-1 assume !(0 == ~E_1~0); 5540#L638-1 assume !(0 == ~E_2~0); 5376#L643-1 assume !(0 == ~E_3~0); 5377#L648-1 assume !(0 == ~E_4~0); 5483#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5484#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5706#L296 assume 1 == ~m_pc~0; 5707#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5694#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5719#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5780#L747 assume !(0 != activate_threads_~tmp~1); 5772#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5773#L315 assume !(1 == ~t1_pc~0); 5842#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 5843#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5871#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5883#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5884#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5436#L334 assume 1 == ~t2_pc~0; 5437#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5434#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5435#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5493#L763 assume !(0 != activate_threads_~tmp___1~0); 5477#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5478#L353 assume !(1 == ~t3_pc~0); 5573#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 5574#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5570#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5571#L771 assume !(0 != activate_threads_~tmp___2~0); 5795#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5787#L372 assume 1 == ~t4_pc~0; 5766#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5767#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5763#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5764#L779 assume !(0 != activate_threads_~tmp___3~0); 5894#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5529#L391 assume !(1 == ~t5_pc~0); 5530#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 5525#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5526#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5552#L787 assume !(0 != activate_threads_~tmp___4~0); 5553#L787-2 assume !(1 == ~M_E~0); 5554#L671-1 assume !(1 == ~T1_E~0); 5374#L676-1 assume !(1 == ~T2_E~0); 5375#L681-1 assume !(1 == ~T3_E~0); 5481#L686-1 assume !(1 == ~T4_E~0); 5482#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L696-1 assume !(1 == ~E_M~0); 5666#L701-1 assume !(1 == ~E_1~0); 5604#L706-1 assume !(1 == ~E_2~0); 5605#L711-1 assume !(1 == ~E_3~0); 5796#L716-1 assume !(1 == ~E_4~0); 5556#L721-1 assume !(1 == ~E_5~0); 5557#L932-1 [2020-11-28 03:11:22,980 INFO L796 eck$LassoCheckResult]: Loop: 5557#L932-1 assume !false; 5820#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5543#L578 assume !false; 5455#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5456#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5461#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5462#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5560#L503 assume !(0 != eval_~tmp~0); 5776#L593 start_simulation_~kernel_st~0 := 2; 5474#L411-1 start_simulation_~kernel_st~0 := 3; 5475#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5891#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5658#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5659#L613-3 assume !(0 == ~T3_E~0); 5595#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5596#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5649#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5546#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5547#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5384#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5385#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5489#L653-3 assume !(0 == ~E_5~0); 5490#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5813#L296-21 assume !(1 == ~m_pc~0); 5808#L296-23 is_master_triggered_~__retres1~0 := 0; 5700#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5701#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5702#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5703#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5815#L315-21 assume 1 == ~t1_pc~0; 5900#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5865#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5866#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5826#L755-21 assume !(0 != activate_threads_~tmp___0~0); 5827#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5371#L334-21 assume 1 == ~t2_pc~0; 5372#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5378#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5426#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5430#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5400#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5401#L353-21 assume !(1 == ~t3_pc~0); 5602#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 5606#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5637#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5620#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5621#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5626#L372-21 assume 1 == ~t4_pc~0; 5680#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5681#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5676#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5677#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5781#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5782#L391-21 assume 1 == ~t5_pc~0; 5853#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5511#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5512#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5852#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5890#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5814#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5379#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5380#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5486#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5487#L691-3 assume !(1 == ~T5_E~0); 5667#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5668#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5607#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5608#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5644#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5537#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5538#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5563#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5465#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5466#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5409#L951 assume !(0 == start_simulation_~tmp~3); 5410#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5413#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5467#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5468#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 5565#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5653#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 5797#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 5798#L964 assume !(0 != start_simulation_~tmp___0~1); 5557#L932-1 [2020-11-28 03:11:22,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:22,981 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2020-11-28 03:11:22,981 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:22,981 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177103125] [2020-11-28 03:11:22,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:22,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,024 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177103125] [2020-11-28 03:11:23,024 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,024 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:23,025 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10976193] [2020-11-28 03:11:23,025 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:23,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,026 INFO L82 PathProgramCache]: Analyzing trace with hash 911407326, now seen corresponding path program 1 times [2020-11-28 03:11:23,026 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,026 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183369590] [2020-11-28 03:11:23,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,081 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183369590] [2020-11-28 03:11:23,081 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,081 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:23,081 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329461424] [2020-11-28 03:11:23,082 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:23,082 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:23,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:11:23,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:11:23,083 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand 4 states. [2020-11-28 03:11:23,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:23,173 INFO L93 Difference]: Finished difference Result 946 states and 1423 transitions. [2020-11-28 03:11:23,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:11:23,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 946 states and 1423 transitions. [2020-11-28 03:11:23,182 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 860 [2020-11-28 03:11:23,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 946 states to 946 states and 1423 transitions. [2020-11-28 03:11:23,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 946 [2020-11-28 03:11:23,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 946 [2020-11-28 03:11:23,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 946 states and 1423 transitions. [2020-11-28 03:11:23,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:23,194 INFO L691 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2020-11-28 03:11:23,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 946 states and 1423 transitions. [2020-11-28 03:11:23,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 946 to 946. [2020-11-28 03:11:23,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 946 states. [2020-11-28 03:11:23,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 1423 transitions. [2020-11-28 03:11:23,217 INFO L714 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2020-11-28 03:11:23,217 INFO L594 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2020-11-28 03:11:23,217 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 03:11:23,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 946 states and 1423 transitions. [2020-11-28 03:11:23,224 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 860 [2020-11-28 03:11:23,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:23,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:23,226 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,226 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,226 INFO L794 eck$LassoCheckResult]: Stem: 7311#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7212#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7153#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6958#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 6959#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7065#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7066#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6961#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6962#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7163#L443-1 assume !(0 == ~M_E~0); 7164#L603-1 assume !(0 == ~T1_E~0); 7169#L608-1 assume !(0 == ~T2_E~0); 7170#L613-1 assume !(0 == ~T3_E~0); 7090#L618-1 assume !(0 == ~T4_E~0); 7091#L623-1 assume !(0 == ~T5_E~0); 7145#L628-1 assume !(0 == ~E_M~0); 7032#L633-1 assume !(0 == ~E_1~0); 7033#L638-1 assume !(0 == ~E_2~0); 6864#L643-1 assume !(0 == ~E_3~0); 6865#L648-1 assume !(0 == ~E_4~0); 6972#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6973#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7207#L296 assume 1 == ~m_pc~0; 7208#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7197#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7220#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7281#L747 assume !(0 != activate_threads_~tmp~1); 7273#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7274#L315 assume !(1 == ~t1_pc~0); 7352#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 7353#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7383#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7396#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7397#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6924#L334 assume 1 == ~t2_pc~0; 6925#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6922#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6923#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6982#L763 assume !(0 != activate_threads_~tmp___1~0); 6966#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6967#L353 assume !(1 == ~t3_pc~0); 7071#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 7072#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7068#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7069#L771 assume !(0 != activate_threads_~tmp___2~0); 7301#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7290#L372 assume 1 == ~t4_pc~0; 7267#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7268#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7265#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7266#L779 assume !(0 != activate_threads_~tmp___3~0); 7409#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7021#L391 assume !(1 == ~t5_pc~0); 7022#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 7017#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7018#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7046#L787 assume !(0 != activate_threads_~tmp___4~0); 7047#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7048#L671-1 assume !(1 == ~T1_E~0); 6862#L676-1 assume !(1 == ~T2_E~0); 6863#L681-1 assume !(1 == ~T3_E~0); 6970#L686-1 assume !(1 == ~T4_E~0); 6971#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7165#L696-1 assume !(1 == ~E_M~0); 7166#L701-1 assume !(1 == ~E_1~0); 7102#L706-1 assume !(1 == ~E_2~0); 7103#L711-1 assume !(1 == ~E_3~0); 7302#L716-1 assume !(1 == ~E_4~0); 7051#L721-1 assume !(1 == ~E_5~0); 7052#L932-1 [2020-11-28 03:11:23,227 INFO L796 eck$LassoCheckResult]: Loop: 7052#L932-1 assume !false; 7330#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7036#L578 assume !false; 6946#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6947#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6950#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6951#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7423#L503 assume !(0 != eval_~tmp~0); 7422#L593 start_simulation_~kernel_st~0 := 2; 7421#L411-1 start_simulation_~kernel_st~0 := 3; 7420#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7408#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7158#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7159#L613-3 assume !(0 == ~T3_E~0); 7093#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7094#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7147#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7039#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7040#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6872#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6873#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6978#L653-3 assume !(0 == ~E_5~0); 6979#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7320#L296-21 assume 1 == ~m_pc~0; 7314#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7201#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7202#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7203#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7204#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7323#L315-21 assume 1 == ~t1_pc~0; 7415#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7375#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7376#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7336#L755-21 assume !(0 != activate_threads_~tmp___0~0); 7337#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6859#L334-21 assume 1 == ~t2_pc~0; 6860#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6866#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6914#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6919#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6888#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6889#L353-21 assume !(1 == ~t3_pc~0); 7100#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 7104#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7135#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7118#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7119#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7124#L372-21 assume !(1 == ~t4_pc~0); 7185#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 7184#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7179#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7180#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7282#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7283#L391-21 assume 1 == ~t5_pc~0; 7366#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7001#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7002#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7362#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7404#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7321#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6867#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6868#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6975#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6976#L691-3 assume !(1 == ~T5_E~0); 7167#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7168#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7105#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7106#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7142#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7030#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7031#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7060#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6954#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6955#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6897#L951 assume !(0 == start_simulation_~tmp~3); 6898#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6901#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7015#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7062#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 7063#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7325#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 7326#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 7399#L964 assume !(0 != start_simulation_~tmp___0~1); 7052#L932-1 [2020-11-28 03:11:23,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,227 INFO L82 PathProgramCache]: Analyzing trace with hash -515799174, now seen corresponding path program 1 times [2020-11-28 03:11:23,227 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,227 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412795052] [2020-11-28 03:11:23,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,259 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412795052] [2020-11-28 03:11:23,259 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,259 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:23,259 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397788926] [2020-11-28 03:11:23,260 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:23,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,260 INFO L82 PathProgramCache]: Analyzing trace with hash 1053074910, now seen corresponding path program 1 times [2020-11-28 03:11:23,260 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,260 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510432058] [2020-11-28 03:11:23,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,293 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510432058] [2020-11-28 03:11:23,293 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,293 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:23,293 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99488802] [2020-11-28 03:11:23,293 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:23,294 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:23,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:11:23,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:11:23,294 INFO L87 Difference]: Start difference. First operand 946 states and 1423 transitions. cyclomatic complexity: 479 Second operand 4 states. [2020-11-28 03:11:23,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:23,455 INFO L93 Difference]: Finished difference Result 1676 states and 2514 transitions. [2020-11-28 03:11:23,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:11:23,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1676 states and 2514 transitions. [2020-11-28 03:11:23,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1580 [2020-11-28 03:11:23,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1676 states to 1676 states and 2514 transitions. [2020-11-28 03:11:23,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1676 [2020-11-28 03:11:23,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1676 [2020-11-28 03:11:23,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1676 states and 2514 transitions. [2020-11-28 03:11:23,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:23,510 INFO L691 BuchiCegarLoop]: Abstraction has 1676 states and 2514 transitions. [2020-11-28 03:11:23,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1676 states and 2514 transitions. [2020-11-28 03:11:23,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1676 to 1674. [2020-11-28 03:11:23,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1674 states. [2020-11-28 03:11:23,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1674 states to 1674 states and 2512 transitions. [2020-11-28 03:11:23,548 INFO L714 BuchiCegarLoop]: Abstraction has 1674 states and 2512 transitions. [2020-11-28 03:11:23,548 INFO L594 BuchiCegarLoop]: Abstraction has 1674 states and 2512 transitions. [2020-11-28 03:11:23,548 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 03:11:23,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1674 states and 2512 transitions. [2020-11-28 03:11:23,560 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1580 [2020-11-28 03:11:23,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:23,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:23,562 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,562 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,562 INFO L794 eck$LassoCheckResult]: Stem: 9962#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9853#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9793#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9589#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 9590#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9701#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9702#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9592#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9593#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9802#L443-1 assume !(0 == ~M_E~0); 9803#L603-1 assume !(0 == ~T1_E~0); 9808#L608-1 assume !(0 == ~T2_E~0); 9809#L613-1 assume !(0 == ~T3_E~0); 9726#L618-1 assume !(0 == ~T4_E~0); 9727#L623-1 assume !(0 == ~T5_E~0); 9785#L628-1 assume !(0 == ~E_M~0); 9663#L633-1 assume !(0 == ~E_1~0); 9664#L638-1 assume !(0 == ~E_2~0); 9496#L643-1 assume !(0 == ~E_3~0); 9497#L648-1 assume !(0 == ~E_4~0); 9603#L653-1 assume !(0 == ~E_5~0); 9604#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9848#L296 assume 1 == ~m_pc~0; 9849#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9838#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9861#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9927#L747 assume !(0 != activate_threads_~tmp~1); 9915#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9916#L315 assume !(1 == ~t1_pc~0); 10002#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 10003#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10034#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10046#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10047#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9556#L334 assume 1 == ~t2_pc~0; 9557#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9554#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9555#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9613#L763 assume !(0 != activate_threads_~tmp___1~0); 9597#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9598#L353 assume !(1 == ~t3_pc~0); 9707#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 9708#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9704#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9705#L771 assume !(0 != activate_threads_~tmp___2~0); 9950#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9937#L372 assume 1 == ~t4_pc~0; 9909#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9910#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9907#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9908#L779 assume !(0 != activate_threads_~tmp___3~0); 10058#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9651#L391 assume !(1 == ~t5_pc~0); 9652#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 9647#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9648#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9678#L787 assume !(0 != activate_threads_~tmp___4~0); 9679#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 9680#L671-1 assume !(1 == ~T1_E~0); 9494#L676-1 assume !(1 == ~T2_E~0); 9495#L681-1 assume !(1 == ~T3_E~0); 9919#L686-1 assume !(1 == ~T4_E~0); 10174#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9804#L696-1 assume !(1 == ~E_M~0); 9805#L701-1 assume !(1 == ~E_1~0); 9740#L706-1 assume !(1 == ~E_2~0); 9741#L711-1 assume !(1 == ~E_3~0); 9951#L716-1 assume !(1 == ~E_4~0); 9952#L721-1 assume !(1 == ~E_5~0); 10092#L932-1 [2020-11-28 03:11:23,562 INFO L796 eck$LassoCheckResult]: Loop: 10092#L932-1 assume !false; 10087#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10086#L578 assume !false; 10085#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10079#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10078#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10077#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 10075#L503 assume !(0 != eval_~tmp~0); 10074#L593 start_simulation_~kernel_st~0 := 2; 10073#L411-1 start_simulation_~kernel_st~0 := 3; 10071#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10072#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10449#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10448#L613-3 assume !(0 == ~T3_E~0); 10447#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10446#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10445#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10444#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10443#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10441#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10439#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10436#L653-3 assume !(0 == ~E_5~0); 10434#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10432#L296-21 assume !(1 == ~m_pc~0); 10430#L296-23 is_master_triggered_~__retres1~0 := 0; 10429#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10428#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10427#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10426#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10423#L315-21 assume 1 == ~t1_pc~0; 10420#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10418#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10415#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10413#L755-21 assume !(0 != activate_threads_~tmp___0~0); 10411#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10409#L334-21 assume 1 == ~t2_pc~0; 10406#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10404#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10401#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9551#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9520#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9521#L353-21 assume !(1 == ~t3_pc~0); 10377#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 10375#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10373#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10371#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10368#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10366#L372-21 assume 1 == ~t4_pc~0; 9824#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9825#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9820#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9821#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9930#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9931#L391-21 assume 1 == ~t5_pc~0; 10018#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9633#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9634#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10014#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10054#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9974#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9499#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9500#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9923#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10313#L691-3 assume !(1 == ~T5_E~0); 10311#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10309#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10307#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10305#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10303#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10301#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10299#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10298#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10292#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10290#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 10287#L951 assume !(0 == start_simulation_~tmp~3); 9956#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10168#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10162#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10161#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 10138#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10136#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 10112#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 10100#L964 assume !(0 != start_simulation_~tmp___0~1); 10092#L932-1 [2020-11-28 03:11:23,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,563 INFO L82 PathProgramCache]: Analyzing trace with hash -531317892, now seen corresponding path program 1 times [2020-11-28 03:11:23,563 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,563 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797618015] [2020-11-28 03:11:23,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,600 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797618015] [2020-11-28 03:11:23,600 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,600 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:11:23,600 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934026740] [2020-11-28 03:11:23,600 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:23,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,601 INFO L82 PathProgramCache]: Analyzing trace with hash 911407326, now seen corresponding path program 2 times [2020-11-28 03:11:23,601 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,601 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745482320] [2020-11-28 03:11:23,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,632 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745482320] [2020-11-28 03:11:23,632 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,632 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:23,632 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165747008] [2020-11-28 03:11:23,633 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:23,635 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:23,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:23,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:23,635 INFO L87 Difference]: Start difference. First operand 1674 states and 2512 transitions. cyclomatic complexity: 842 Second operand 3 states. [2020-11-28 03:11:23,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:23,730 INFO L93 Difference]: Finished difference Result 3198 states and 4735 transitions. [2020-11-28 03:11:23,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:23,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3198 states and 4735 transitions. [2020-11-28 03:11:23,763 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3101 [2020-11-28 03:11:23,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3198 states to 3198 states and 4735 transitions. [2020-11-28 03:11:23,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3198 [2020-11-28 03:11:23,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3198 [2020-11-28 03:11:23,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3198 states and 4735 transitions. [2020-11-28 03:11:23,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:23,802 INFO L691 BuchiCegarLoop]: Abstraction has 3198 states and 4735 transitions. [2020-11-28 03:11:23,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states and 4735 transitions. [2020-11-28 03:11:23,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3038. [2020-11-28 03:11:23,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3038 states. [2020-11-28 03:11:23,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3038 states to 3038 states and 4511 transitions. [2020-11-28 03:11:23,910 INFO L714 BuchiCegarLoop]: Abstraction has 3038 states and 4511 transitions. [2020-11-28 03:11:23,910 INFO L594 BuchiCegarLoop]: Abstraction has 3038 states and 4511 transitions. [2020-11-28 03:11:23,910 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 03:11:23,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3038 states and 4511 transitions. [2020-11-28 03:11:23,933 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2941 [2020-11-28 03:11:23,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:23,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:23,934 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,935 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:23,935 INFO L794 eck$LassoCheckResult]: Stem: 14850#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 14737#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14680#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14471#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 14472#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14584#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14585#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14473#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14474#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14689#L443-1 assume !(0 == ~M_E~0); 14690#L603-1 assume !(0 == ~T1_E~0); 14696#L608-1 assume !(0 == ~T2_E~0); 14697#L613-1 assume !(0 == ~T3_E~0); 14609#L618-1 assume !(0 == ~T4_E~0); 14610#L623-1 assume !(0 == ~T5_E~0); 14673#L628-1 assume !(0 == ~E_M~0); 14546#L633-1 assume !(0 == ~E_1~0); 14547#L638-1 assume !(0 == ~E_2~0); 14375#L643-1 assume !(0 == ~E_3~0); 14376#L648-1 assume !(0 == ~E_4~0); 14485#L653-1 assume !(0 == ~E_5~0); 14486#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14734#L296 assume !(1 == ~m_pc~0); 14720#L296-2 is_master_triggered_~__retres1~0 := 0; 14721#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14744#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14813#L747 assume !(0 != activate_threads_~tmp~1); 14803#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14804#L315 assume !(1 == ~t1_pc~0); 14908#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 14909#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14940#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14952#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14953#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14438#L334 assume 1 == ~t2_pc~0; 14439#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14436#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14437#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14495#L763 assume !(0 != activate_threads_~tmp___1~0); 14479#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14480#L353 assume !(1 == ~t3_pc~0); 14592#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 14593#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14589#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14590#L771 assume !(0 != activate_threads_~tmp___2~0); 14830#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14821#L372 assume 1 == ~t4_pc~0; 14797#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14798#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14793#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14794#L779 assume !(0 != activate_threads_~tmp___3~0); 14970#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14531#L391 assume !(1 == ~t5_pc~0); 14532#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 14527#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14528#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14559#L787 assume !(0 != activate_threads_~tmp___4~0); 14560#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 14563#L671-1 assume !(1 == ~T1_E~0); 14373#L676-1 assume !(1 == ~T2_E~0); 14374#L681-1 assume !(1 == ~T3_E~0); 14483#L686-1 assume !(1 == ~T4_E~0); 14484#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17331#L696-1 assume !(1 == ~E_M~0); 14991#L701-1 assume !(1 == ~E_1~0); 14626#L706-1 assume !(1 == ~E_2~0); 14627#L711-1 assume !(1 == ~E_3~0); 14954#L716-1 assume !(1 == ~E_4~0); 14565#L721-1 assume !(1 == ~E_5~0); 14566#L932-1 [2020-11-28 03:11:23,935 INFO L796 eck$LassoCheckResult]: Loop: 14566#L932-1 assume !false; 17141#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 17140#L578 assume !false; 14457#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14458#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17134#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14573#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 14574#L503 assume !(0 != eval_~tmp~0); 14807#L593 start_simulation_~kernel_st~0 := 2; 14476#L411-1 start_simulation_~kernel_st~0 := 3; 14477#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14969#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14685#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14686#L613-3 assume !(0 == ~T3_E~0); 14613#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14614#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14675#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14555#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14556#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14383#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14384#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14491#L653-3 assume !(0 == ~E_5~0); 14492#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14868#L296-21 assume !(1 == ~m_pc~0); 14869#L296-23 is_master_triggered_~__retres1~0 := 0; 14730#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14731#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14732#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14733#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14992#L315-21 assume !(1 == ~t1_pc~0); 14993#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 17397#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17396#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17395#L755-21 assume !(0 != activate_threads_~tmp___0~0); 17394#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17393#L334-21 assume !(1 == ~t2_pc~0); 17392#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 17390#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17389#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17388#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17373#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14623#L353-21 assume !(1 == ~t3_pc~0); 14624#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 14628#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14663#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14644#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14645#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14651#L372-21 assume 1 == ~t4_pc~0; 14715#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14716#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17363#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 17362#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17361#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17360#L391-21 assume !(1 == ~t5_pc~0); 17358#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 17357#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17356#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17355#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17354#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 14964#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17353#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17352#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16779#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17351#L691-3 assume !(1 == ~T5_E~0); 17350#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17349#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17348#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17347#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17346#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17345#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14544#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17344#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17338#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15007#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 15008#L951 assume !(0 == start_simulation_~tmp~3); 14413#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14414#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17332#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14582#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 14583#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14679#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 14833#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 14834#L964 assume !(0 != start_simulation_~tmp___0~1); 14566#L932-1 [2020-11-28 03:11:23,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,936 INFO L82 PathProgramCache]: Analyzing trace with hash 1870207229, now seen corresponding path program 1 times [2020-11-28 03:11:23,936 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,936 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361270255] [2020-11-28 03:11:23,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:23,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:23,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:23,989 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361270255] [2020-11-28 03:11:23,989 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:23,989 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:11:23,989 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75615871] [2020-11-28 03:11:23,990 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:23,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:23,990 INFO L82 PathProgramCache]: Analyzing trace with hash -1905068229, now seen corresponding path program 1 times [2020-11-28 03:11:23,991 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:23,991 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534883037] [2020-11-28 03:11:23,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:24,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:24,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:24,035 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534883037] [2020-11-28 03:11:24,036 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:24,036 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:24,036 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416773019] [2020-11-28 03:11:24,036 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:24,036 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:24,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:11:24,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:11:24,037 INFO L87 Difference]: Start difference. First operand 3038 states and 4511 transitions. cyclomatic complexity: 1481 Second operand 5 states. [2020-11-28 03:11:24,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:24,323 INFO L93 Difference]: Finished difference Result 8268 states and 12255 transitions. [2020-11-28 03:11:24,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:11:24,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8268 states and 12255 transitions. [2020-11-28 03:11:24,446 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8042 [2020-11-28 03:11:24,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8268 states to 8268 states and 12255 transitions. [2020-11-28 03:11:24,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8268 [2020-11-28 03:11:24,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8268 [2020-11-28 03:11:24,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8268 states and 12255 transitions. [2020-11-28 03:11:24,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:24,539 INFO L691 BuchiCegarLoop]: Abstraction has 8268 states and 12255 transitions. [2020-11-28 03:11:24,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8268 states and 12255 transitions. [2020-11-28 03:11:24,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8268 to 3191. [2020-11-28 03:11:24,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3191 states. [2020-11-28 03:11:24,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3191 states to 3191 states and 4664 transitions. [2020-11-28 03:11:24,675 INFO L714 BuchiCegarLoop]: Abstraction has 3191 states and 4664 transitions. [2020-11-28 03:11:24,675 INFO L594 BuchiCegarLoop]: Abstraction has 3191 states and 4664 transitions. [2020-11-28 03:11:24,675 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 03:11:24,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3191 states and 4664 transitions. [2020-11-28 03:11:24,693 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3091 [2020-11-28 03:11:24,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:24,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:24,694 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:24,695 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:24,695 INFO L794 eck$LassoCheckResult]: Stem: 26195#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 26057#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25999#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25789#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 25790#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25900#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25901#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25791#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25792#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26007#L443-1 assume !(0 == ~M_E~0); 26008#L603-1 assume !(0 == ~T1_E~0); 26014#L608-1 assume !(0 == ~T2_E~0); 26015#L613-1 assume !(0 == ~T3_E~0); 25925#L618-1 assume !(0 == ~T4_E~0); 25926#L623-1 assume !(0 == ~T5_E~0); 25991#L628-1 assume !(0 == ~E_M~0); 25863#L633-1 assume !(0 == ~E_1~0); 25864#L638-1 assume !(0 == ~E_2~0); 25694#L643-1 assume !(0 == ~E_3~0); 25695#L648-1 assume !(0 == ~E_4~0); 25803#L653-1 assume !(0 == ~E_5~0); 25804#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26054#L296 assume !(1 == ~m_pc~0); 26040#L296-2 is_master_triggered_~__retres1~0 := 0; 26041#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26065#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26143#L747 assume !(0 != activate_threads_~tmp~1); 26126#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26127#L315 assume !(1 == ~t1_pc~0); 26272#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 26273#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26315#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26331#L755 assume !(0 != activate_threads_~tmp___0~0); 26332#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25756#L334 assume 1 == ~t2_pc~0; 25757#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25754#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25755#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25813#L763 assume !(0 != activate_threads_~tmp___1~0); 25797#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25798#L353 assume !(1 == ~t3_pc~0); 25908#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 25909#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25905#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25906#L771 assume !(0 != activate_threads_~tmp___2~0); 26175#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26161#L372 assume 1 == ~t4_pc~0; 26119#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26120#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26115#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26116#L779 assume !(0 != activate_threads_~tmp___3~0); 26356#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25849#L391 assume !(1 == ~t5_pc~0); 25850#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 25845#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25846#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 25874#L787 assume !(0 != activate_threads_~tmp___4~0); 25875#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 25878#L671-1 assume !(1 == ~T1_E~0); 26217#L676-1 assume !(1 == ~T2_E~0); 26128#L681-1 assume !(1 == ~T3_E~0); 25801#L686-1 assume !(1 == ~T4_E~0); 25802#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26010#L696-1 assume !(1 == ~E_M~0); 26011#L701-1 assume !(1 == ~E_1~0); 25942#L706-1 assume !(1 == ~E_2~0); 25943#L711-1 assume !(1 == ~E_3~0); 26176#L716-1 assume !(1 == ~E_4~0); 26177#L721-1 assume !(1 == ~E_5~0); 26862#L932-1 [2020-11-28 03:11:24,695 INFO L796 eck$LassoCheckResult]: Loop: 26862#L932-1 assume !false; 26857#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 26856#L578 assume !false; 26855#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26849#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26848#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26847#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 26845#L503 assume !(0 != eval_~tmp~0); 26844#L593 start_simulation_~kernel_st~0 := 2; 26843#L411-1 start_simulation_~kernel_st~0 := 3; 26840#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 26841#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27198#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27196#L613-3 assume !(0 == ~T3_E~0); 27194#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27192#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27190#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27189#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27188#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27172#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27170#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27168#L653-3 assume !(0 == ~E_5~0); 27165#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27164#L296-21 assume !(1 == ~m_pc~0); 27163#L296-23 is_master_triggered_~__retres1~0 := 0; 27162#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27161#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27160#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27159#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27158#L315-21 assume !(1 == ~t1_pc~0); 27156#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 27154#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27152#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27150#L755-21 assume !(0 != activate_threads_~tmp___0~0); 27148#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27146#L334-21 assume 1 == ~t2_pc~0; 27143#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 27141#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27139#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27136#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27135#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27134#L353-21 assume !(1 == ~t3_pc~0); 27117#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 27115#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27113#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27110#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27108#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27107#L372-21 assume 1 == ~t4_pc~0; 27105#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27089#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27087#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27085#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27082#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27080#L391-21 assume !(1 == ~t5_pc~0); 27078#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 27054#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27032#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 27031#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 27028#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 26692#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27025#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27009#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26685#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26991#L691-3 assume !(1 == ~T5_E~0); 26979#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26963#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26960#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26958#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26942#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26923#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26919#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26917#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26910#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26909#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 26908#L951 assume !(0 == start_simulation_~tmp~3); 26181#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26905#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26899#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26897#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 26895#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26893#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 26882#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 26870#L964 assume !(0 != start_simulation_~tmp___0~1); 26862#L932-1 [2020-11-28 03:11:24,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:24,696 INFO L82 PathProgramCache]: Analyzing trace with hash -1765228545, now seen corresponding path program 1 times [2020-11-28 03:11:24,696 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:24,696 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381411823] [2020-11-28 03:11:24,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:24,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:24,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:24,731 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381411823] [2020-11-28 03:11:24,731 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:24,732 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:24,732 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168044649] [2020-11-28 03:11:24,733 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:24,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:24,734 INFO L82 PathProgramCache]: Analyzing trace with hash 957064348, now seen corresponding path program 1 times [2020-11-28 03:11:24,734 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:24,737 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833865721] [2020-11-28 03:11:24,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:24,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:24,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:24,775 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833865721] [2020-11-28 03:11:24,775 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:24,775 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:24,776 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143952566] [2020-11-28 03:11:24,776 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:24,777 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:24,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:11:24,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:11:24,778 INFO L87 Difference]: Start difference. First operand 3191 states and 4664 transitions. cyclomatic complexity: 1481 Second operand 4 states. [2020-11-28 03:11:25,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:25,038 INFO L93 Difference]: Finished difference Result 7490 states and 10816 transitions. [2020-11-28 03:11:25,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:11:25,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7490 states and 10816 transitions. [2020-11-28 03:11:25,092 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7187 [2020-11-28 03:11:25,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7490 states to 7490 states and 10816 transitions. [2020-11-28 03:11:25,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7490 [2020-11-28 03:11:25,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7490 [2020-11-28 03:11:25,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7490 states and 10816 transitions. [2020-11-28 03:11:25,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:25,168 INFO L691 BuchiCegarLoop]: Abstraction has 7490 states and 10816 transitions. [2020-11-28 03:11:25,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7490 states and 10816 transitions. [2020-11-28 03:11:25,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7490 to 5863. [2020-11-28 03:11:25,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5863 states. [2020-11-28 03:11:25,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5863 states to 5863 states and 8522 transitions. [2020-11-28 03:11:25,347 INFO L714 BuchiCegarLoop]: Abstraction has 5863 states and 8522 transitions. [2020-11-28 03:11:25,348 INFO L594 BuchiCegarLoop]: Abstraction has 5863 states and 8522 transitions. [2020-11-28 03:11:25,348 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 03:11:25,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5863 states and 8522 transitions. [2020-11-28 03:11:25,381 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5760 [2020-11-28 03:11:25,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:25,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:25,383 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:25,383 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:25,383 INFO L794 eck$LassoCheckResult]: Stem: 36866#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36747#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36691#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36472#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 36473#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36600#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36601#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36475#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36476#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36700#L443-1 assume !(0 == ~M_E~0); 36701#L603-1 assume !(0 == ~T1_E~0); 36706#L608-1 assume !(0 == ~T2_E~0); 36707#L613-1 assume !(0 == ~T3_E~0); 36625#L618-1 assume !(0 == ~T4_E~0); 36626#L623-1 assume !(0 == ~T5_E~0); 36683#L628-1 assume !(0 == ~E_M~0); 36548#L633-1 assume !(0 == ~E_1~0); 36549#L638-1 assume !(0 == ~E_2~0); 36384#L643-1 assume !(0 == ~E_3~0); 36385#L648-1 assume !(0 == ~E_4~0); 36486#L653-1 assume !(0 == ~E_5~0); 36487#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36745#L296 assume !(1 == ~m_pc~0); 36734#L296-2 is_master_triggered_~__retres1~0 := 0; 36735#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36758#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36823#L747 assume !(0 != activate_threads_~tmp~1); 36811#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36812#L315 assume !(1 == ~t1_pc~0); 36915#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 36916#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36946#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36961#L755 assume !(0 != activate_threads_~tmp___0~0); 36962#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36441#L334 assume !(1 == ~t2_pc~0); 36442#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 36439#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36440#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36497#L763 assume !(0 != activate_threads_~tmp___1~0); 36480#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36481#L353 assume !(1 == ~t3_pc~0); 36606#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 36607#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36603#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36604#L771 assume !(0 != activate_threads_~tmp___2~0); 36846#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36833#L372 assume 1 == ~t4_pc~0; 36805#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36806#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36803#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36804#L779 assume !(0 != activate_threads_~tmp___3~0); 36977#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36536#L391 assume !(1 == ~t5_pc~0); 36537#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 36532#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36533#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 36562#L787 assume !(0 != activate_threads_~tmp___4~0); 36563#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 36564#L671-1 assume !(1 == ~T1_E~0); 36883#L676-1 assume !(1 == ~T2_E~0); 36815#L681-1 assume !(1 == ~T3_E~0); 36816#L686-1 assume !(1 == ~T4_E~0); 36979#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36980#L696-1 assume !(1 == ~E_M~0); 37005#L701-1 assume !(1 == ~E_1~0); 36637#L706-1 assume !(1 == ~E_2~0); 36638#L711-1 assume !(1 == ~E_3~0); 36847#L716-1 assume !(1 == ~E_4~0); 36848#L721-1 assume !(1 == ~E_5~0); 40624#L932-1 [2020-11-28 03:11:25,384 INFO L796 eck$LassoCheckResult]: Loop: 40624#L932-1 assume !false; 41501#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 41498#L578 assume !false; 41497#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 41488#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 41486#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 41484#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 41480#L503 assume !(0 != eval_~tmp~0); 41481#L593 start_simulation_~kernel_st~0 := 2; 42006#L411-1 start_simulation_~kernel_st~0 := 3; 42004#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42003#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42002#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42000#L613-3 assume !(0 == ~T3_E~0); 41999#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41998#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41997#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41995#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41993#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41991#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41989#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41987#L653-3 assume !(0 == ~E_5~0); 41985#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41981#L296-21 assume !(1 == ~m_pc~0); 41979#L296-23 is_master_triggered_~__retres1~0 := 0; 41977#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41975#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41972#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41970#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41969#L315-21 assume !(1 == ~t1_pc~0); 41968#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 41966#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41964#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 41961#L755-21 assume !(0 != activate_threads_~tmp___0~0); 41960#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41958#L334-21 assume !(1 == ~t2_pc~0); 37912#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 41955#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41931#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 41930#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41929#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41928#L353-21 assume !(1 == ~t3_pc~0); 41926#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 41924#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41922#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 41920#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 41918#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41916#L372-21 assume 1 == ~t4_pc~0; 41913#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 41911#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41910#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 41909#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 41902#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41901#L391-21 assume !(1 == ~t5_pc~0); 41897#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 41895#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 41893#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 41891#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 41888#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 36973#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41887#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41886#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36819#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41883#L691-3 assume !(1 == ~T5_E~0); 41881#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41879#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41877#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41875#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41874#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41873#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41259#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 41799#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 41788#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 41782#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 41778#L951 assume !(0 == start_simulation_~tmp~3); 36852#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 41594#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 41588#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 41585#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 41583#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41581#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 41580#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 41517#L964 assume !(0 != start_simulation_~tmp___0~1); 40624#L932-1 [2020-11-28 03:11:25,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:25,384 INFO L82 PathProgramCache]: Analyzing trace with hash -713779456, now seen corresponding path program 1 times [2020-11-28 03:11:25,385 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:25,385 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152317792] [2020-11-28 03:11:25,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:25,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:25,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:25,437 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152317792] [2020-11-28 03:11:25,437 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:25,438 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:25,438 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317567226] [2020-11-28 03:11:25,438 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:25,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:25,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1905068229, now seen corresponding path program 2 times [2020-11-28 03:11:25,439 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:25,440 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60593288] [2020-11-28 03:11:25,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:25,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:25,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:25,473 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60593288] [2020-11-28 03:11:25,473 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:25,473 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:25,474 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24772777] [2020-11-28 03:11:25,474 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:25,474 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:25,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:11:25,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:11:25,475 INFO L87 Difference]: Start difference. First operand 5863 states and 8522 transitions. cyclomatic complexity: 2667 Second operand 4 states. [2020-11-28 03:11:25,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:25,802 INFO L93 Difference]: Finished difference Result 14043 states and 20152 transitions. [2020-11-28 03:11:25,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:11:25,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14043 states and 20152 transitions. [2020-11-28 03:11:25,906 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13537 [2020-11-28 03:11:25,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14043 states to 14043 states and 20152 transitions. [2020-11-28 03:11:25,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14043 [2020-11-28 03:11:26,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14043 [2020-11-28 03:11:26,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14043 states and 20152 transitions. [2020-11-28 03:11:26,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:26,021 INFO L691 BuchiCegarLoop]: Abstraction has 14043 states and 20152 transitions. [2020-11-28 03:11:26,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14043 states and 20152 transitions. [2020-11-28 03:11:26,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14043 to 11154. [2020-11-28 03:11:26,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11154 states. [2020-11-28 03:11:26,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11154 states to 11154 states and 16103 transitions. [2020-11-28 03:11:26,358 INFO L714 BuchiCegarLoop]: Abstraction has 11154 states and 16103 transitions. [2020-11-28 03:11:26,358 INFO L594 BuchiCegarLoop]: Abstraction has 11154 states and 16103 transitions. [2020-11-28 03:11:26,358 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 03:11:26,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11154 states and 16103 transitions. [2020-11-28 03:11:26,406 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11044 [2020-11-28 03:11:26,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:26,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:26,408 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:26,408 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:26,408 INFO L794 eck$LassoCheckResult]: Stem: 56795#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56668#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56608#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56390#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 56391#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56514#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56515#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56392#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56393#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56616#L443-1 assume !(0 == ~M_E~0); 56617#L603-1 assume !(0 == ~T1_E~0); 56623#L608-1 assume !(0 == ~T2_E~0); 56624#L613-1 assume !(0 == ~T3_E~0); 56538#L618-1 assume !(0 == ~T4_E~0); 56539#L623-1 assume !(0 == ~T5_E~0); 56601#L628-1 assume !(0 == ~E_M~0); 56461#L633-1 assume !(0 == ~E_1~0); 56462#L638-1 assume !(0 == ~E_2~0); 56300#L643-1 assume !(0 == ~E_3~0); 56301#L648-1 assume !(0 == ~E_4~0); 56404#L653-1 assume !(0 == ~E_5~0); 56405#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56665#L296 assume !(1 == ~m_pc~0); 56651#L296-2 is_master_triggered_~__retres1~0 := 0; 56652#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56676#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56748#L747 assume !(0 != activate_threads_~tmp~1); 56732#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56733#L315 assume !(1 == ~t1_pc~0); 56850#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 56851#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56886#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 56901#L755 assume !(0 != activate_threads_~tmp___0~0); 56902#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56359#L334 assume !(1 == ~t2_pc~0); 56360#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 56357#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56358#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56414#L763 assume !(0 != activate_threads_~tmp___1~0); 56398#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56399#L353 assume !(1 == ~t3_pc~0); 56521#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 56522#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56518#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56519#L771 assume !(0 != activate_threads_~tmp___2~0); 56780#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56763#L372 assume !(1 == ~t4_pc~0); 56764#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 56770#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56726#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56727#L779 assume !(0 != activate_threads_~tmp___3~0); 56915#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56448#L391 assume !(1 == ~t5_pc~0); 56449#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 56444#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56445#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 56473#L787 assume !(0 != activate_threads_~tmp___4~0); 56474#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 56477#L671-1 assume !(1 == ~T1_E~0); 56298#L676-1 assume !(1 == ~T2_E~0); 56299#L681-1 assume !(1 == ~T3_E~0); 56734#L686-1 assume !(1 == ~T4_E~0); 56917#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56918#L696-1 assume !(1 == ~E_M~0); 56948#L701-1 assume !(1 == ~E_1~0); 56949#L706-1 assume !(1 == ~E_2~0); 56903#L711-1 assume !(1 == ~E_3~0); 56904#L716-1 assume !(1 == ~E_4~0); 56479#L721-1 assume !(1 == ~E_5~0); 56480#L932-1 [2020-11-28 03:11:26,409 INFO L796 eck$LassoCheckResult]: Loop: 56480#L932-1 assume !false; 56824#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 56465#L578 assume !false; 56376#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56377#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56382#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56383#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 56505#L503 assume !(0 != eval_~tmp~0); 56943#L593 start_simulation_~kernel_st~0 := 2; 66802#L411-1 start_simulation_~kernel_st~0 := 3; 66801#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 66800#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66799#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66798#L613-3 assume !(0 == ~T3_E~0); 66796#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66795#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66794#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66793#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66792#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66789#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66783#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66781#L653-3 assume !(0 == ~E_5~0); 66779#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56809#L296-21 assume !(1 == ~m_pc~0); 56810#L296-23 is_master_triggered_~__retres1~0 := 0; 67028#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67026#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66576#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 56814#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56815#L315-21 assume 1 == ~t1_pc~0; 56933#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56934#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66206#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 66204#L755-21 assume !(0 != activate_threads_~tmp___0~0); 56833#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56296#L334-21 assume !(1 == ~t2_pc~0); 56297#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 56302#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56348#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56354#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56323#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56324#L353-21 assume !(1 == ~t3_pc~0); 56551#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 56555#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56589#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56571#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56572#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56576#L372-21 assume !(1 == ~t4_pc~0); 56737#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 56738#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56640#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56641#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 56750#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56751#L391-21 assume 1 == ~t5_pc~0; 56867#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56432#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56433#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 56862#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 56910#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 56812#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56303#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56304#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56742#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67246#L691-3 assume !(1 == ~T5_E~0); 67244#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 67242#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67240#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67217#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66987#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66958#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56811#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56511#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56386#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56387#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 56331#L951 assume !(0 == start_simulation_~tmp~3); 56332#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56335#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56388#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56389#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 56513#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56607#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 56784#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 56785#L964 assume !(0 != start_simulation_~tmp___0~1); 56480#L932-1 [2020-11-28 03:11:26,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:26,409 INFO L82 PathProgramCache]: Analyzing trace with hash 66201473, now seen corresponding path program 1 times [2020-11-28 03:11:26,410 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:26,410 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961226230] [2020-11-28 03:11:26,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:26,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:26,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:26,443 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961226230] [2020-11-28 03:11:26,443 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:26,443 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:11:26,443 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377708804] [2020-11-28 03:11:26,444 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:26,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:26,444 INFO L82 PathProgramCache]: Analyzing trace with hash 579425436, now seen corresponding path program 1 times [2020-11-28 03:11:26,444 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:26,445 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896035708] [2020-11-28 03:11:26,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:26,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:26,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:26,473 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896035708] [2020-11-28 03:11:26,474 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:26,474 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:26,474 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839397287] [2020-11-28 03:11:26,474 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:26,475 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:26,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:26,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:26,475 INFO L87 Difference]: Start difference. First operand 11154 states and 16103 transitions. cyclomatic complexity: 4957 Second operand 3 states. [2020-11-28 03:11:26,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:26,573 INFO L93 Difference]: Finished difference Result 13975 states and 20168 transitions. [2020-11-28 03:11:26,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:26,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13975 states and 20168 transitions. [2020-11-28 03:11:26,733 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13872 [2020-11-28 03:11:26,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13975 states to 13975 states and 20168 transitions. [2020-11-28 03:11:26,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13975 [2020-11-28 03:11:26,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13975 [2020-11-28 03:11:26,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13975 states and 20168 transitions. [2020-11-28 03:11:26,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:26,821 INFO L691 BuchiCegarLoop]: Abstraction has 13975 states and 20168 transitions. [2020-11-28 03:11:26,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13975 states and 20168 transitions. [2020-11-28 03:11:26,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13975 to 6095. [2020-11-28 03:11:26,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6095 states. [2020-11-28 03:11:26,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6095 states to 6095 states and 8832 transitions. [2020-11-28 03:11:26,954 INFO L714 BuchiCegarLoop]: Abstraction has 6095 states and 8832 transitions. [2020-11-28 03:11:26,954 INFO L594 BuchiCegarLoop]: Abstraction has 6095 states and 8832 transitions. [2020-11-28 03:11:26,954 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 03:11:26,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6095 states and 8832 transitions. [2020-11-28 03:11:26,975 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2020-11-28 03:11:26,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:26,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:26,978 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:26,978 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:26,978 INFO L794 eck$LassoCheckResult]: Stem: 81912#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81792#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81736#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81527#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 81528#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81644#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81645#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81529#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81530#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81744#L443-1 assume !(0 == ~M_E~0); 81745#L603-1 assume !(0 == ~T1_E~0); 81751#L608-1 assume !(0 == ~T2_E~0); 81752#L613-1 assume !(0 == ~T3_E~0); 81668#L618-1 assume !(0 == ~T4_E~0); 81669#L623-1 assume !(0 == ~T5_E~0); 81729#L628-1 assume !(0 == ~E_M~0); 81597#L633-1 assume !(0 == ~E_1~0); 81598#L638-1 assume !(0 == ~E_2~0); 81436#L643-1 assume !(0 == ~E_3~0); 81437#L648-1 assume !(0 == ~E_4~0); 81541#L653-1 assume !(0 == ~E_5~0); 81542#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81789#L296 assume !(1 == ~m_pc~0); 81775#L296-2 is_master_triggered_~__retres1~0 := 0; 81776#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81800#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81871#L747 assume !(0 != activate_threads_~tmp~1); 81855#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81856#L315 assume !(1 == ~t1_pc~0); 81972#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 81973#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82005#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 82019#L755 assume !(0 != activate_threads_~tmp___0~0); 82020#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81495#L334 assume !(1 == ~t2_pc~0); 81496#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 81493#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81494#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81551#L763 assume !(0 != activate_threads_~tmp___1~0); 81535#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81536#L353 assume !(1 == ~t3_pc~0); 81651#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 81652#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81648#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81649#L771 assume !(0 != activate_threads_~tmp___2~0); 81898#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81887#L372 assume !(1 == ~t4_pc~0); 81888#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 81892#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81849#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 81850#L779 assume !(0 != activate_threads_~tmp___3~0); 82036#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81585#L391 assume !(1 == ~t5_pc~0); 81586#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 81581#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81582#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 81608#L787 assume !(0 != activate_threads_~tmp___4~0); 81609#L787-2 assume !(1 == ~M_E~0); 81612#L671-1 assume !(1 == ~T1_E~0); 81434#L676-1 assume !(1 == ~T2_E~0); 81435#L681-1 assume !(1 == ~T3_E~0); 81539#L686-1 assume !(1 == ~T4_E~0); 81540#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81747#L696-1 assume !(1 == ~E_M~0); 81748#L701-1 assume !(1 == ~E_1~0); 81686#L706-1 assume !(1 == ~E_2~0); 81687#L711-1 assume !(1 == ~E_3~0); 81899#L716-1 assume !(1 == ~E_4~0); 81613#L721-1 assume !(1 == ~E_5~0); 81614#L932-1 [2020-11-28 03:11:26,978 INFO L796 eck$LassoCheckResult]: Loop: 81614#L932-1 assume !false; 84815#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 84814#L578 assume !false; 84813#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 84791#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 84789#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 84787#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 84785#L503 assume !(0 != eval_~tmp~0); 84786#L593 start_simulation_~kernel_st~0 := 2; 81532#L411-1 start_simulation_~kernel_st~0 := 3; 81533#L603-2 assume !(0 == ~M_E~0); 82033#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81740#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81741#L613-3 assume !(0 == ~T3_E~0); 81673#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81674#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81731#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 81604#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81605#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81444#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81445#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81547#L653-3 assume !(0 == ~E_5~0); 81548#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81924#L296-21 assume !(1 == ~m_pc~0); 81925#L296-23 is_master_triggered_~__retres1~0 := 0; 87493#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87492#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 87491#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87490#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87489#L315-21 assume !(1 == ~t1_pc~0); 87488#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 87486#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87484#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 87481#L755-21 assume !(0 != activate_threads_~tmp___0~0); 87478#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87472#L334-21 assume !(1 == ~t2_pc~0); 85008#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 87469#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87467#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 87466#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87464#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87463#L353-21 assume !(1 == ~t3_pc~0); 87461#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 87459#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87457#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 87455#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 87453#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87451#L372-21 assume !(1 == ~t4_pc~0); 83898#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 87448#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87446#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 87400#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 87399#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87398#L391-21 assume 1 == ~t5_pc~0; 87397#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 87395#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87394#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 87393#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 87390#L787-23 assume !(1 == ~M_E~0); 83488#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87386#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87382#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87379#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87376#L691-3 assume !(1 == ~T5_E~0); 87370#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87362#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87177#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87176#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81726#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81595#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81596#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81641#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81523#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81524#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 81467#L951 assume !(0 == start_simulation_~tmp~3); 81468#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 84841#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 84835#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 84833#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 84831#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 84828#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 84826#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 84824#L964 assume !(0 != start_simulation_~tmp___0~1); 81614#L932-1 [2020-11-28 03:11:26,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:26,979 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2020-11-28 03:11:26,979 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:26,979 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892785794] [2020-11-28 03:11:26,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:27,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:27,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:27,060 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892785794] [2020-11-28 03:11:27,060 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:27,060 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:11:27,060 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623547728] [2020-11-28 03:11:27,061 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:27,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:27,062 INFO L82 PathProgramCache]: Analyzing trace with hash -1088267265, now seen corresponding path program 1 times [2020-11-28 03:11:27,062 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:27,062 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254474015] [2020-11-28 03:11:27,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:27,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:27,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:27,097 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254474015] [2020-11-28 03:11:27,101 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:27,102 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:27,103 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866234861] [2020-11-28 03:11:27,103 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:27,104 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:27,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:27,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:27,104 INFO L87 Difference]: Start difference. First operand 6095 states and 8832 transitions. cyclomatic complexity: 2739 Second operand 3 states. [2020-11-28 03:11:27,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:27,150 INFO L93 Difference]: Finished difference Result 6095 states and 8782 transitions. [2020-11-28 03:11:27,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:27,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6095 states and 8782 transitions. [2020-11-28 03:11:27,180 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2020-11-28 03:11:27,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6095 states to 6095 states and 8782 transitions. [2020-11-28 03:11:27,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6095 [2020-11-28 03:11:27,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6095 [2020-11-28 03:11:27,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6095 states and 8782 transitions. [2020-11-28 03:11:27,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:27,214 INFO L691 BuchiCegarLoop]: Abstraction has 6095 states and 8782 transitions. [2020-11-28 03:11:27,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6095 states and 8782 transitions. [2020-11-28 03:11:27,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6095 to 6095. [2020-11-28 03:11:27,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6095 states. [2020-11-28 03:11:27,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6095 states to 6095 states and 8782 transitions. [2020-11-28 03:11:27,304 INFO L714 BuchiCegarLoop]: Abstraction has 6095 states and 8782 transitions. [2020-11-28 03:11:27,305 INFO L594 BuchiCegarLoop]: Abstraction has 6095 states and 8782 transitions. [2020-11-28 03:11:27,305 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 03:11:27,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6095 states and 8782 transitions. [2020-11-28 03:11:27,350 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2020-11-28 03:11:27,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:27,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:27,353 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:27,353 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:27,354 INFO L794 eck$LassoCheckResult]: Stem: 94115#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 93992#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 93929#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 93727#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 93728#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93839#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93840#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93730#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93731#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93938#L443-1 assume !(0 == ~M_E~0); 93939#L603-1 assume !(0 == ~T1_E~0); 93944#L608-1 assume !(0 == ~T2_E~0); 93945#L613-1 assume !(0 == ~T3_E~0); 93864#L618-1 assume !(0 == ~T4_E~0); 93865#L623-1 assume !(0 == ~T5_E~0); 93921#L628-1 assume !(0 == ~E_M~0); 93799#L633-1 assume !(0 == ~E_1~0); 93800#L638-1 assume !(0 == ~E_2~0); 93633#L643-1 assume !(0 == ~E_3~0); 93634#L648-1 assume !(0 == ~E_4~0); 93741#L653-1 assume !(0 == ~E_5~0); 93742#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93987#L296 assume !(1 == ~m_pc~0); 93976#L296-2 is_master_triggered_~__retres1~0 := 0; 93977#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94000#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 94062#L747 assume !(0 != activate_threads_~tmp~1); 94048#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94049#L315 assume !(1 == ~t1_pc~0); 94167#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 94168#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94199#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 94213#L755 assume !(0 != activate_threads_~tmp___0~0); 94214#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93694#L334 assume !(1 == ~t2_pc~0); 93695#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 93692#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93693#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 93751#L763 assume !(0 != activate_threads_~tmp___1~0); 93735#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93736#L353 assume !(1 == ~t3_pc~0); 93845#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 93846#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93842#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 93843#L771 assume !(0 != activate_threads_~tmp___2~0); 94096#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94082#L372 assume !(1 == ~t4_pc~0); 94083#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 94088#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94043#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 94044#L779 assume !(0 != activate_threads_~tmp___3~0); 94230#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 93788#L391 assume !(1 == ~t5_pc~0); 93789#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 93784#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93785#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 93813#L787 assume !(0 != activate_threads_~tmp___4~0); 93814#L787-2 assume !(1 == ~M_E~0); 93815#L671-1 assume !(1 == ~T1_E~0); 93631#L676-1 assume !(1 == ~T2_E~0); 93632#L681-1 assume !(1 == ~T3_E~0); 93739#L686-1 assume !(1 == ~T4_E~0); 93740#L691-1 assume !(1 == ~T5_E~0); 93940#L696-1 assume !(1 == ~E_M~0); 93941#L701-1 assume !(1 == ~E_1~0); 93877#L706-1 assume !(1 == ~E_2~0); 93878#L711-1 assume !(1 == ~E_3~0); 94097#L716-1 assume !(1 == ~E_4~0); 93817#L721-1 assume !(1 == ~E_5~0); 93818#L932-1 [2020-11-28 03:11:27,354 INFO L796 eck$LassoCheckResult]: Loop: 93818#L932-1 assume !false; 94144#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 93803#L578 assume !false; 93713#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 93714#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 93719#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 93720#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 93829#L503 assume !(0 != eval_~tmp~0); 94055#L593 start_simulation_~kernel_st~0 := 2; 93732#L411-1 start_simulation_~kernel_st~0 := 3; 93733#L603-2 assume !(0 == ~M_E~0); 94227#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 93933#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93934#L613-3 assume !(0 == ~T3_E~0); 93868#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93869#L623-3 assume !(0 == ~T5_E~0); 93923#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93924#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99715#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99714#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 99713#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 99712#L653-3 assume !(0 == ~E_5~0); 99710#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99708#L296-21 assume !(1 == ~m_pc~0); 99706#L296-23 is_master_triggered_~__retres1~0 := 0; 99704#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 99702#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 93983#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 93984#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94137#L315-21 assume 1 == ~t1_pc~0; 94243#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 94244#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99700#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 99699#L755-21 assume !(0 != activate_threads_~tmp___0~0); 94153#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93629#L334-21 assume !(1 == ~t2_pc~0); 93630#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 99675#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 99673#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 93689#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 93657#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93658#L353-21 assume !(1 == ~t3_pc~0); 93875#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 93879#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93951#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 93952#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 99564#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97925#L372-21 assume !(1 == ~t4_pc~0); 97923#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 97921#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97919#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97918#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 97915#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97913#L391-21 assume 1 == ~t5_pc~0; 97911#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 97903#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97901#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 97892#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 97818#L787-23 assume !(1 == ~M_E~0); 97814#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97812#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97811#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97809#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97807#L691-3 assume !(1 == ~T5_E~0); 97776#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97767#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97764#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97750#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97749#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97748#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97747#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97746#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 97740#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97739#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 97410#L951 assume !(0 == start_simulation_~tmp~3); 93669#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 93670#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 93725#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 93726#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 93836#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 93928#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 94098#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 94099#L964 assume !(0 != start_simulation_~tmp___0~1); 93818#L932-1 [2020-11-28 03:11:27,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:27,355 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2020-11-28 03:11:27,355 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:27,356 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456926899] [2020-11-28 03:11:27,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:27,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:27,375 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:27,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:27,387 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:27,439 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:27,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:27,439 INFO L82 PathProgramCache]: Analyzing trace with hash -237128354, now seen corresponding path program 1 times [2020-11-28 03:11:27,440 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:27,440 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602956888] [2020-11-28 03:11:27,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:27,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:27,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:27,493 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602956888] [2020-11-28 03:11:27,493 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:27,494 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:11:27,494 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25531617] [2020-11-28 03:11:27,494 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:27,494 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:27,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:11:27,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:11:27,496 INFO L87 Difference]: Start difference. First operand 6095 states and 8782 transitions. cyclomatic complexity: 2689 Second operand 5 states. [2020-11-28 03:11:27,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:27,688 INFO L93 Difference]: Finished difference Result 10891 states and 15482 transitions. [2020-11-28 03:11:27,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:11:27,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10891 states and 15482 transitions. [2020-11-28 03:11:27,747 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10800 [2020-11-28 03:11:27,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10891 states to 10891 states and 15482 transitions. [2020-11-28 03:11:27,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10891 [2020-11-28 03:11:27,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10891 [2020-11-28 03:11:27,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10891 states and 15482 transitions. [2020-11-28 03:11:27,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:27,821 INFO L691 BuchiCegarLoop]: Abstraction has 10891 states and 15482 transitions. [2020-11-28 03:11:27,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10891 states and 15482 transitions. [2020-11-28 03:11:27,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10891 to 6143. [2020-11-28 03:11:27,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6143 states. [2020-11-28 03:11:27,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6143 states to 6143 states and 8830 transitions. [2020-11-28 03:11:27,945 INFO L714 BuchiCegarLoop]: Abstraction has 6143 states and 8830 transitions. [2020-11-28 03:11:27,945 INFO L594 BuchiCegarLoop]: Abstraction has 6143 states and 8830 transitions. [2020-11-28 03:11:27,946 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 03:11:27,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6143 states and 8830 transitions. [2020-11-28 03:11:27,971 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6060 [2020-11-28 03:11:27,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:27,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:27,975 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:27,975 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:27,975 INFO L794 eck$LassoCheckResult]: Stem: 111114#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 110993#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 110938#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 110724#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 110725#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110847#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110848#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110726#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110727#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110946#L443-1 assume !(0 == ~M_E~0); 110947#L603-1 assume !(0 == ~T1_E~0); 110953#L608-1 assume !(0 == ~T2_E~0); 110954#L613-1 assume !(0 == ~T3_E~0); 110871#L618-1 assume !(0 == ~T4_E~0); 110872#L623-1 assume !(0 == ~T5_E~0); 110931#L628-1 assume !(0 == ~E_M~0); 110796#L633-1 assume !(0 == ~E_1~0); 110797#L638-1 assume !(0 == ~E_2~0); 110635#L643-1 assume !(0 == ~E_3~0); 110636#L648-1 assume !(0 == ~E_4~0); 110738#L653-1 assume !(0 == ~E_5~0); 110739#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 110990#L296 assume !(1 == ~m_pc~0); 110976#L296-2 is_master_triggered_~__retres1~0 := 0; 110977#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 111000#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 111066#L747 assume !(0 != activate_threads_~tmp~1); 111053#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 111054#L315 assume !(1 == ~t1_pc~0); 111167#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 111168#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 111197#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 111211#L755 assume !(0 != activate_threads_~tmp___0~0); 111212#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110693#L334 assume !(1 == ~t2_pc~0); 110694#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 110691#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110692#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 110748#L763 assume !(0 != activate_threads_~tmp___1~0); 110732#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 110733#L353 assume !(1 == ~t3_pc~0); 110854#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 110855#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 110851#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 110852#L771 assume !(0 != activate_threads_~tmp___2~0); 111094#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 111080#L372 assume !(1 == ~t4_pc~0); 111081#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 111087#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 111047#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 111048#L779 assume !(0 != activate_threads_~tmp___3~0); 111230#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110783#L391 assume !(1 == ~t5_pc~0); 110784#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 110779#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110780#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 110808#L787 assume !(0 != activate_threads_~tmp___4~0); 110809#L787-2 assume !(1 == ~M_E~0); 110812#L671-1 assume !(1 == ~T1_E~0); 110633#L676-1 assume !(1 == ~T2_E~0); 110634#L681-1 assume !(1 == ~T3_E~0); 110736#L686-1 assume !(1 == ~T4_E~0); 110737#L691-1 assume !(1 == ~T5_E~0); 110949#L696-1 assume !(1 == ~E_M~0); 110950#L701-1 assume !(1 == ~E_1~0); 110886#L706-1 assume !(1 == ~E_2~0); 110887#L711-1 assume !(1 == ~E_3~0); 111095#L716-1 assume !(1 == ~E_4~0); 110813#L721-1 assume !(1 == ~E_5~0); 110814#L932-1 [2020-11-28 03:11:27,976 INFO L796 eck$LassoCheckResult]: Loop: 110814#L932-1 assume !false; 115939#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 115660#L578 assume !false; 115496#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 115494#L456 assume !(0 == ~m_st~0); 115492#L460 assume !(0 == ~t1_st~0); 115489#L464 assume !(0 == ~t2_st~0); 115487#L468 assume !(0 == ~t3_st~0); 115484#L472 assume !(0 == ~t4_st~0); 115474#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 115463#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 115458#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 115456#L503 assume !(0 != eval_~tmp~0); 115455#L593 start_simulation_~kernel_st~0 := 2; 115453#L411-1 start_simulation_~kernel_st~0 := 3; 115451#L603-2 assume !(0 == ~M_E~0); 115444#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 115445#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 115431#L613-3 assume !(0 == ~T3_E~0); 115432#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 115419#L623-3 assume !(0 == ~T5_E~0); 115420#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 115404#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 115405#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 115383#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 115384#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 115365#L653-3 assume !(0 == ~E_5~0); 115366#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 115335#L296-21 assume !(1 == ~m_pc~0); 115336#L296-23 is_master_triggered_~__retres1~0 := 0; 110986#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110987#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 111103#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 116074#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 111253#L315-21 assume 1 == ~t1_pc~0; 111243#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 111244#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 116367#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 116366#L755-21 assume !(0 != activate_threads_~tmp___0~0); 111152#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110631#L334-21 assume !(1 == ~t2_pc~0); 110632#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 110637#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110820#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 110687#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 110688#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116062#L353-21 assume 1 == ~t3_pc~0; 116061#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 116059#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 110960#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 110902#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 110903#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110907#L372-21 assume !(1 == ~t4_pc~0); 111067#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 116053#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116051#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 116049#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 116047#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 116045#L391-21 assume 1 == ~t5_pc~0; 116043#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 116039#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 116037#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 116035#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 116033#L787-23 assume !(1 == ~M_E~0); 116031#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116030#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116029#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116028#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116027#L691-3 assume !(1 == ~T5_E~0); 116026#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116025#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116024#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116023#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116022#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116021#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116020#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116019#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 116011#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 116009#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 116007#L951 assume !(0 == start_simulation_~tmp~3); 116004#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116002#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 115996#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 115994#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 115992#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 115983#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 115979#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 115955#L964 assume !(0 != start_simulation_~tmp___0~1); 110814#L932-1 [2020-11-28 03:11:27,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:27,976 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2020-11-28 03:11:27,977 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:27,979 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211478507] [2020-11-28 03:11:27,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:27,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:27,997 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:28,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:28,012 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:28,050 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:28,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:28,050 INFO L82 PathProgramCache]: Analyzing trace with hash 1240601496, now seen corresponding path program 1 times [2020-11-28 03:11:28,051 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:28,051 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907069082] [2020-11-28 03:11:28,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:28,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:28,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:28,110 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907069082] [2020-11-28 03:11:28,110 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:28,110 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:11:28,110 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658155848] [2020-11-28 03:11:28,111 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:28,111 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:28,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:11:28,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:11:28,112 INFO L87 Difference]: Start difference. First operand 6143 states and 8830 transitions. cyclomatic complexity: 2689 Second operand 5 states. [2020-11-28 03:11:28,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:28,477 INFO L93 Difference]: Finished difference Result 11385 states and 16361 transitions. [2020-11-28 03:11:28,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2020-11-28 03:11:28,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11385 states and 16361 transitions. [2020-11-28 03:11:28,541 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11256 [2020-11-28 03:11:28,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11385 states to 11385 states and 16361 transitions. [2020-11-28 03:11:28,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11385 [2020-11-28 03:11:28,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11385 [2020-11-28 03:11:28,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11385 states and 16361 transitions. [2020-11-28 03:11:28,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:28,610 INFO L691 BuchiCegarLoop]: Abstraction has 11385 states and 16361 transitions. [2020-11-28 03:11:28,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11385 states and 16361 transitions. [2020-11-28 03:11:28,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11385 to 6143. [2020-11-28 03:11:28,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6143 states. [2020-11-28 03:11:28,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6143 states to 6143 states and 8733 transitions. [2020-11-28 03:11:28,816 INFO L714 BuchiCegarLoop]: Abstraction has 6143 states and 8733 transitions. [2020-11-28 03:11:28,816 INFO L594 BuchiCegarLoop]: Abstraction has 6143 states and 8733 transitions. [2020-11-28 03:11:28,816 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 03:11:28,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6143 states and 8733 transitions. [2020-11-28 03:11:28,835 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6060 [2020-11-28 03:11:28,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:28,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:28,838 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:28,838 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:28,838 INFO L794 eck$LassoCheckResult]: Stem: 128665#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 128544#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 128484#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 128269#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 128270#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128391#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128392#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128271#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128272#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 128494#L443-1 assume !(0 == ~M_E~0); 128495#L603-1 assume !(0 == ~T1_E~0); 128501#L608-1 assume !(0 == ~T2_E~0); 128502#L613-1 assume !(0 == ~T3_E~0); 128415#L618-1 assume !(0 == ~T4_E~0); 128416#L623-1 assume !(0 == ~T5_E~0); 128477#L628-1 assume !(0 == ~E_M~0); 128344#L633-1 assume !(0 == ~E_1~0); 128345#L638-1 assume !(0 == ~E_2~0); 128177#L643-1 assume !(0 == ~E_3~0); 128178#L648-1 assume !(0 == ~E_4~0); 128284#L653-1 assume !(0 == ~E_5~0); 128285#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128541#L296 assume !(1 == ~m_pc~0); 128526#L296-2 is_master_triggered_~__retres1~0 := 0; 128527#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 128551#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 128618#L747 assume !(0 != activate_threads_~tmp~1); 128605#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128606#L315 assume !(1 == ~t1_pc~0); 128723#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 128724#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 128758#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 128811#L755 assume !(0 != activate_threads_~tmp___0~0); 128772#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128236#L334 assume !(1 == ~t2_pc~0); 128237#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 128234#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 128235#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 128295#L763 assume !(0 != activate_threads_~tmp___1~0); 128278#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128279#L353 assume !(1 == ~t3_pc~0); 128398#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 128399#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128395#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 128396#L771 assume !(0 != activate_threads_~tmp___2~0); 128645#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 128632#L372 assume !(1 == ~t4_pc~0); 128633#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 128638#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128598#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 128599#L779 assume !(0 != activate_threads_~tmp___3~0); 128785#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128331#L391 assume !(1 == ~t5_pc~0); 128332#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 128327#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128328#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 128355#L787 assume !(0 != activate_threads_~tmp___4~0); 128356#L787-2 assume !(1 == ~M_E~0); 128359#L671-1 assume !(1 == ~T1_E~0); 128175#L676-1 assume !(1 == ~T2_E~0); 128176#L681-1 assume !(1 == ~T3_E~0); 128282#L686-1 assume !(1 == ~T4_E~0); 128283#L691-1 assume !(1 == ~T5_E~0); 128497#L696-1 assume !(1 == ~E_M~0); 128498#L701-1 assume !(1 == ~E_1~0); 128430#L706-1 assume !(1 == ~E_2~0); 128431#L711-1 assume !(1 == ~E_3~0); 128646#L716-1 assume !(1 == ~E_4~0); 128360#L721-1 assume !(1 == ~E_5~0); 128361#L932-1 [2020-11-28 03:11:28,838 INFO L796 eck$LassoCheckResult]: Loop: 128361#L932-1 assume !false; 133867#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 133864#L578 assume !false; 133840#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133820#L456 assume !(0 == ~m_st~0); 133822#L460 assume !(0 == ~t1_st~0); 133825#L464 assume !(0 == ~t2_st~0); 133826#L468 assume !(0 == ~t3_st~0); 133823#L472 assume !(0 == ~t4_st~0); 133824#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 133817#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133818#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 134277#L503 assume !(0 != eval_~tmp~0); 134275#L593 start_simulation_~kernel_st~0 := 2; 134274#L411-1 start_simulation_~kernel_st~0 := 3; 134227#L603-2 assume !(0 == ~M_E~0); 134226#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134225#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134224#L613-3 assume !(0 == ~T3_E~0); 134222#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134220#L623-3 assume !(0 == ~T5_E~0); 134218#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134216#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134214#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134212#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134211#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 134210#L653-3 assume !(0 == ~E_5~0); 134209#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134208#L296-21 assume !(1 == ~m_pc~0); 134207#L296-23 is_master_triggered_~__retres1~0 := 0; 134206#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134204#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134202#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 134197#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128825#L315-21 assume !(1 == ~t1_pc~0); 128807#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 128819#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 128804#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 128805#L755-21 assume !(0 != activate_threads_~tmp___0~0); 128704#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128173#L334-21 assume !(1 == ~t2_pc~0); 128174#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 133758#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 133756#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 133754#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 133752#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 133751#L353-21 assume 1 == ~t3_pc~0; 133744#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 133741#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133739#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 128447#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 128448#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 128452#L372-21 assume !(1 == ~t4_pc~0); 128609#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 128610#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128515#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 128516#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 128619#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128620#L391-21 assume !(1 == ~t5_pc~0); 128741#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 128313#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128314#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 128735#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 128780#L787-23 assume !(1 == ~M_E~0); 128781#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133766#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133765#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133764#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133763#L691-3 assume !(1 == ~T5_E~0); 133762#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133761#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133760#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133759#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 133757#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133755#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133753#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133750#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133742#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133740#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 132413#L951 assume !(0 == start_simulation_~tmp~3); 132414#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133898#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133893#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133890#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 133888#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 133887#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 133886#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 133882#L964 assume !(0 != start_simulation_~tmp___0~1); 128361#L932-1 [2020-11-28 03:11:28,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:28,839 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2020-11-28 03:11:28,839 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:28,839 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010017242] [2020-11-28 03:11:28,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:28,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:28,854 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:28,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:28,864 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:28,886 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:28,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:28,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1286258518, now seen corresponding path program 1 times [2020-11-28 03:11:28,887 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:28,888 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642120137] [2020-11-28 03:11:28,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:28,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:28,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:28,971 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642120137] [2020-11-28 03:11:28,971 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:28,972 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:11:28,972 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494102783] [2020-11-28 03:11:28,972 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:28,972 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:28,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:11:28,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:11:28,973 INFO L87 Difference]: Start difference. First operand 6143 states and 8733 transitions. cyclomatic complexity: 2592 Second operand 5 states. [2020-11-28 03:11:29,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:29,250 INFO L93 Difference]: Finished difference Result 12219 states and 17268 transitions. [2020-11-28 03:11:29,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:11:29,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12219 states and 17268 transitions. [2020-11-28 03:11:29,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12136 [2020-11-28 03:11:29,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12219 states to 12219 states and 17268 transitions. [2020-11-28 03:11:29,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12219 [2020-11-28 03:11:29,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12219 [2020-11-28 03:11:29,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12219 states and 17268 transitions. [2020-11-28 03:11:29,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:29,370 INFO L691 BuchiCegarLoop]: Abstraction has 12219 states and 17268 transitions. [2020-11-28 03:11:29,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12219 states and 17268 transitions. [2020-11-28 03:11:29,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12219 to 6299. [2020-11-28 03:11:29,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6299 states. [2020-11-28 03:11:29,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6299 states to 6299 states and 8844 transitions. [2020-11-28 03:11:29,474 INFO L714 BuchiCegarLoop]: Abstraction has 6299 states and 8844 transitions. [2020-11-28 03:11:29,474 INFO L594 BuchiCegarLoop]: Abstraction has 6299 states and 8844 transitions. [2020-11-28 03:11:29,474 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 03:11:29,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6299 states and 8844 transitions. [2020-11-28 03:11:29,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6216 [2020-11-28 03:11:29,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:29,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:29,497 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:29,497 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:29,498 INFO L794 eck$LassoCheckResult]: Stem: 147031#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 146907#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 146852#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 146639#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 146640#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 146763#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 146764#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 146641#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 146642#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 146861#L443-1 assume !(0 == ~M_E~0); 146862#L603-1 assume !(0 == ~T1_E~0); 146868#L608-1 assume !(0 == ~T2_E~0); 146869#L613-1 assume !(0 == ~T3_E~0); 146787#L618-1 assume !(0 == ~T4_E~0); 146788#L623-1 assume !(0 == ~T5_E~0); 146845#L628-1 assume !(0 == ~E_M~0); 146712#L633-1 assume !(0 == ~E_1~0); 146713#L638-1 assume !(0 == ~E_2~0); 146552#L643-1 assume !(0 == ~E_3~0); 146553#L648-1 assume !(0 == ~E_4~0); 146653#L653-1 assume !(0 == ~E_5~0); 146654#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 146904#L296 assume !(1 == ~m_pc~0); 146890#L296-2 is_master_triggered_~__retres1~0 := 0; 146891#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 146915#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 146988#L747 assume !(0 != activate_threads_~tmp~1); 146973#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 146974#L315 assume !(1 == ~t1_pc~0); 147095#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 147096#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 147190#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 147189#L755 assume !(0 != activate_threads_~tmp___0~0); 147144#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 146608#L334 assume !(1 == ~t2_pc~0); 146609#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 146606#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 146607#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 146663#L763 assume !(0 != activate_threads_~tmp___1~0); 146647#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 146648#L353 assume !(1 == ~t3_pc~0); 146770#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 146771#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 146767#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 146768#L771 assume !(0 != activate_threads_~tmp___2~0); 147016#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147002#L372 assume !(1 == ~t4_pc~0); 147003#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 147008#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 146967#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 146968#L779 assume !(0 != activate_threads_~tmp___3~0); 147163#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 146699#L391 assume !(1 == ~t5_pc~0); 146700#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 146695#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 146696#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 146723#L787 assume !(0 != activate_threads_~tmp___4~0); 146724#L787-2 assume !(1 == ~M_E~0); 146727#L671-1 assume !(1 == ~T1_E~0); 146550#L676-1 assume !(1 == ~T2_E~0); 146551#L681-1 assume !(1 == ~T3_E~0); 146651#L686-1 assume !(1 == ~T4_E~0); 146652#L691-1 assume !(1 == ~T5_E~0); 146864#L696-1 assume !(1 == ~E_M~0); 146865#L701-1 assume !(1 == ~E_1~0); 146802#L706-1 assume !(1 == ~E_2~0); 146803#L711-1 assume !(1 == ~E_3~0); 147017#L716-1 assume !(1 == ~E_4~0); 146728#L721-1 assume !(1 == ~E_5~0); 146729#L932-1 [2020-11-28 03:11:29,498 INFO L796 eck$LassoCheckResult]: Loop: 146729#L932-1 assume !false; 149857#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 149856#L578 assume !false; 149855#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149848#L456 assume !(0 == ~m_st~0); 149849#L460 assume !(0 == ~t1_st~0); 149852#L464 assume !(0 == ~t2_st~0); 149854#L468 assume !(0 == ~t3_st~0); 149850#L472 assume !(0 == ~t4_st~0); 149851#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 149853#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 148454#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 148455#L503 assume !(0 != eval_~tmp~0); 152299#L593 start_simulation_~kernel_st~0 := 2; 152298#L411-1 start_simulation_~kernel_st~0 := 3; 152297#L603-2 assume !(0 == ~M_E~0); 152296#L603-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 152295#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 152294#L613-3 assume !(0 == ~T3_E~0); 152293#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152292#L623-3 assume !(0 == ~T5_E~0); 152291#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 152290#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152289#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152288#L643-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152287#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 152286#L653-3 assume !(0 == ~E_5~0); 147165#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 147053#L296-21 assume !(1 == ~m_pc~0); 147054#L296-23 is_master_triggered_~__retres1~0 := 0; 149981#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 149980#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 149979#L747-21 assume !(0 != activate_threads_~tmp~1); 149978#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 149977#L315-21 assume !(1 == ~t1_pc~0); 149975#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 149973#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 149971#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 149969#L755-21 assume !(0 != activate_threads_~tmp___0~0); 149968#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 149967#L334-21 assume !(1 == ~t2_pc~0); 147732#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 149966#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 149965#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 149964#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 149963#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 149962#L353-21 assume !(1 == ~t3_pc~0); 149960#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 149959#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 149958#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 149957#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 149956#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 149955#L372-21 assume !(1 == ~t4_pc~0); 149388#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 149953#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 149951#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 149949#L779-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 149947#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 149945#L391-21 assume 1 == ~t5_pc~0; 149942#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 149938#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 149935#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 149932#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 149930#L787-23 assume !(1 == ~M_E~0); 149110#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149928#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 149926#L681-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149924#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 149922#L691-3 assume !(1 == ~T5_E~0); 149920#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 149918#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149914#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 149911#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 149908#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 149905#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 149902#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149899#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 149892#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 149889#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 149886#L951 assume !(0 == start_simulation_~tmp~3); 149883#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149880#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 149874#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 149871#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 149869#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 149867#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 149865#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 149862#L964 assume !(0 != start_simulation_~tmp___0~1); 146729#L932-1 [2020-11-28 03:11:29,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:29,498 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 4 times [2020-11-28 03:11:29,499 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:29,499 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320023631] [2020-11-28 03:11:29,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:29,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,511 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:29,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,520 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:29,542 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:29,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:29,543 INFO L82 PathProgramCache]: Analyzing trace with hash -771436908, now seen corresponding path program 1 times [2020-11-28 03:11:29,543 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:29,543 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675997156] [2020-11-28 03:11:29,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:29,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:29,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:29,578 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675997156] [2020-11-28 03:11:29,578 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:29,578 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:29,579 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435803128] [2020-11-28 03:11:29,579 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:11:29,579 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:29,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:29,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:29,580 INFO L87 Difference]: Start difference. First operand 6299 states and 8844 transitions. cyclomatic complexity: 2547 Second operand 3 states. [2020-11-28 03:11:29,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:29,667 INFO L93 Difference]: Finished difference Result 10055 states and 13920 transitions. [2020-11-28 03:11:29,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:29,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10055 states and 13920 transitions. [2020-11-28 03:11:29,713 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9974 [2020-11-28 03:11:29,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10055 states to 10055 states and 13920 transitions. [2020-11-28 03:11:29,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10055 [2020-11-28 03:11:29,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10055 [2020-11-28 03:11:29,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10055 states and 13920 transitions. [2020-11-28 03:11:29,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:29,763 INFO L691 BuchiCegarLoop]: Abstraction has 10055 states and 13920 transitions. [2020-11-28 03:11:29,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10055 states and 13920 transitions. [2020-11-28 03:11:29,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10055 to 9751. [2020-11-28 03:11:29,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9751 states. [2020-11-28 03:11:29,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9751 states to 9751 states and 13520 transitions. [2020-11-28 03:11:29,901 INFO L714 BuchiCegarLoop]: Abstraction has 9751 states and 13520 transitions. [2020-11-28 03:11:29,901 INFO L594 BuchiCegarLoop]: Abstraction has 9751 states and 13520 transitions. [2020-11-28 03:11:29,901 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-28 03:11:29,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9751 states and 13520 transitions. [2020-11-28 03:11:29,937 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9670 [2020-11-28 03:11:29,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:29,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:29,938 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:29,938 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:29,939 INFO L794 eck$LassoCheckResult]: Stem: 163414#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 163289#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 163227#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 163002#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 163003#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163129#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163130#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163004#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163005#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163239#L443-1 assume !(0 == ~M_E~0); 163240#L603-1 assume !(0 == ~T1_E~0); 163246#L608-1 assume !(0 == ~T2_E~0); 163247#L613-1 assume !(0 == ~T3_E~0); 163153#L618-1 assume !(0 == ~T4_E~0); 163154#L623-1 assume !(0 == ~T5_E~0); 163218#L628-1 assume !(0 == ~E_M~0); 163077#L633-1 assume !(0 == ~E_1~0); 163078#L638-1 assume !(0 == ~E_2~0); 162912#L643-1 assume !(0 == ~E_3~0); 162913#L648-1 assume !(0 == ~E_4~0); 163017#L653-1 assume !(0 == ~E_5~0); 163018#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 163286#L296 assume !(1 == ~m_pc~0); 163271#L296-2 is_master_triggered_~__retres1~0 := 0; 163272#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 163296#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 163368#L747 assume !(0 != activate_threads_~tmp~1); 163350#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 163351#L315 assume !(1 == ~t1_pc~0); 163470#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 163471#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 163566#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 163565#L755 assume !(0 != activate_threads_~tmp___0~0); 163518#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162971#L334 assume !(1 == ~t2_pc~0); 162972#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 162969#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 162970#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 163028#L763 assume !(0 != activate_threads_~tmp___1~0); 163011#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 163012#L353 assume !(1 == ~t3_pc~0); 163136#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 163137#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 163133#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 163134#L771 assume !(0 != activate_threads_~tmp___2~0); 163394#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 163380#L372 assume !(1 == ~t4_pc~0); 163381#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 163386#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 163344#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 163345#L779 assume !(0 != activate_threads_~tmp___3~0); 163538#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 163063#L391 assume !(1 == ~t5_pc~0); 163064#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 163059#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 163060#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 163089#L787 assume !(0 != activate_threads_~tmp___4~0); 163090#L787-2 assume !(1 == ~M_E~0); 163093#L671-1 assume !(1 == ~T1_E~0); 162910#L676-1 assume !(1 == ~T2_E~0); 162911#L681-1 assume !(1 == ~T3_E~0); 163015#L686-1 assume !(1 == ~T4_E~0); 163016#L691-1 assume !(1 == ~T5_E~0); 163242#L696-1 assume !(1 == ~E_M~0); 163243#L701-1 assume !(1 == ~E_1~0); 163170#L706-1 assume !(1 == ~E_2~0); 163171#L711-1 assume !(1 == ~E_3~0); 163395#L716-1 assume !(1 == ~E_4~0); 163094#L721-1 assume !(1 == ~E_5~0); 163095#L932-1 assume !false; 169574#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 169569#L578 [2020-11-28 03:11:29,939 INFO L796 eck$LassoCheckResult]: Loop: 169569#L578 assume !false; 169564#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 169556#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 169551#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 169545#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 169540#L503 assume 0 != eval_~tmp~0; 169531#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 169523#L511 assume !(0 != eval_~tmp_ndt_1~0); 169517#L508 assume !(0 == ~t1_st~0); 169509#L522 assume !(0 == ~t2_st~0); 169503#L536 assume !(0 == ~t3_st~0); 169585#L550 assume !(0 == ~t4_st~0); 169575#L564 assume !(0 == ~t5_st~0); 169569#L578 [2020-11-28 03:11:29,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:29,940 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2020-11-28 03:11:29,940 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:29,940 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49793755] [2020-11-28 03:11:29,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:29,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,951 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:29,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,965 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:29,991 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:29,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:29,992 INFO L82 PathProgramCache]: Analyzing trace with hash -1515937503, now seen corresponding path program 1 times [2020-11-28 03:11:29,992 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:29,992 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855808787] [2020-11-28 03:11:29,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:29,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,996 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:29,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:29,999 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:30,001 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:30,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:30,002 INFO L82 PathProgramCache]: Analyzing trace with hash -1486889505, now seen corresponding path program 1 times [2020-11-28 03:11:30,002 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:30,002 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248358735] [2020-11-28 03:11:30,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:30,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:30,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:30,059 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248358735] [2020-11-28 03:11:30,059 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:30,059 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:30,059 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548819941] [2020-11-28 03:11:30,229 WARN L193 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 30 [2020-11-28 03:11:30,243 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:30,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:30,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:30,244 INFO L87 Difference]: Start difference. First operand 9751 states and 13520 transitions. cyclomatic complexity: 3772 Second operand 3 states. [2020-11-28 03:11:30,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:30,485 INFO L93 Difference]: Finished difference Result 18069 states and 24926 transitions. [2020-11-28 03:11:30,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:30,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18069 states and 24926 transitions. [2020-11-28 03:11:30,566 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17912 [2020-11-28 03:11:30,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18069 states to 18069 states and 24926 transitions. [2020-11-28 03:11:30,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18069 [2020-11-28 03:11:30,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18069 [2020-11-28 03:11:30,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18069 states and 24926 transitions. [2020-11-28 03:11:30,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:30,656 INFO L691 BuchiCegarLoop]: Abstraction has 18069 states and 24926 transitions. [2020-11-28 03:11:30,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18069 states and 24926 transitions. [2020-11-28 03:11:30,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18069 to 16914. [2020-11-28 03:11:30,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16914 states. [2020-11-28 03:11:30,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16914 states to 16914 states and 23491 transitions. [2020-11-28 03:11:30,849 INFO L714 BuchiCegarLoop]: Abstraction has 16914 states and 23491 transitions. [2020-11-28 03:11:30,849 INFO L594 BuchiCegarLoop]: Abstraction has 16914 states and 23491 transitions. [2020-11-28 03:11:30,849 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-11-28 03:11:30,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16914 states and 23491 transitions. [2020-11-28 03:11:30,906 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16760 [2020-11-28 03:11:30,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:30,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:30,908 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:30,908 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:30,908 INFO L794 eck$LassoCheckResult]: Stem: 191240#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 191108#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 191048#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 190834#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 190835#L418-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 191257#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194606#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194605#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194604#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 194603#L443-1 assume !(0 == ~M_E~0); 194602#L603-1 assume !(0 == ~T1_E~0); 194601#L608-1 assume !(0 == ~T2_E~0); 194600#L613-1 assume !(0 == ~T3_E~0); 194599#L618-1 assume !(0 == ~T4_E~0); 194598#L623-1 assume !(0 == ~T5_E~0); 194597#L628-1 assume !(0 == ~E_M~0); 194596#L633-1 assume !(0 == ~E_1~0); 194595#L638-1 assume !(0 == ~E_2~0); 194594#L643-1 assume !(0 == ~E_3~0); 194593#L648-1 assume !(0 == ~E_4~0); 194592#L653-1 assume !(0 == ~E_5~0); 194591#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 194590#L296 assume !(1 == ~m_pc~0); 194589#L296-2 is_master_triggered_~__retres1~0 := 0; 194588#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 194587#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 194586#L747 assume !(0 != activate_threads_~tmp~1); 194585#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 194584#L315 assume !(1 == ~t1_pc~0); 194582#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 194581#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 194580#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 194579#L755 assume !(0 != activate_threads_~tmp___0~0); 194578#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 194577#L334 assume !(1 == ~t2_pc~0); 194576#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 194575#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 194574#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 194573#L763 assume !(0 != activate_threads_~tmp___1~0); 190842#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 190843#L353 assume !(1 == ~t3_pc~0); 190961#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 190962#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 190958#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 190959#L771 assume !(0 != activate_threads_~tmp___2~0); 191220#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 191206#L372 assume !(1 == ~t4_pc~0); 191207#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 191212#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 191166#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 191167#L779 assume !(0 != activate_threads_~tmp___3~0); 191372#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 190896#L391 assume !(1 == ~t5_pc~0); 190897#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 190891#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 190892#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 190921#L787 assume !(0 != activate_threads_~tmp___4~0); 190922#L787-2 assume !(1 == ~M_E~0); 190925#L671-1 assume !(1 == ~T1_E~0); 190738#L676-1 assume !(1 == ~T2_E~0); 190739#L681-1 assume !(1 == ~T3_E~0); 190846#L686-1 assume !(1 == ~T4_E~0); 190847#L691-1 assume !(1 == ~T5_E~0); 191061#L696-1 assume !(1 == ~E_M~0); 191062#L701-1 assume !(1 == ~E_1~0); 194500#L706-1 assume !(1 == ~E_2~0); 194498#L711-1 assume !(1 == ~E_3~0); 191221#L716-1 assume !(1 == ~E_4~0); 191222#L721-1 assume !(1 == ~E_5~0); 194446#L932-1 assume !false; 194420#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 194411#L578 [2020-11-28 03:11:30,908 INFO L796 eck$LassoCheckResult]: Loop: 194411#L578 assume !false; 194403#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 194395#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 194388#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 194377#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 194350#L503 assume 0 != eval_~tmp~0; 194345#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 194337#L511 assume !(0 != eval_~tmp_ndt_1~0); 194331#L508 assume !(0 == ~t1_st~0); 194246#L522 assume !(0 == ~t2_st~0); 194245#L536 assume !(0 == ~t3_st~0); 194448#L550 assume !(0 == ~t4_st~0); 194421#L564 assume !(0 == ~t5_st~0); 194411#L578 [2020-11-28 03:11:30,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:30,909 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2020-11-28 03:11:30,909 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:30,909 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248526848] [2020-11-28 03:11:30,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:30,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:30,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:30,937 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248526848] [2020-11-28 03:11:30,937 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:30,937 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:30,938 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302580268] [2020-11-28 03:11:30,939 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:11:30,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:30,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1515937503, now seen corresponding path program 2 times [2020-11-28 03:11:30,939 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:30,939 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184457348] [2020-11-28 03:11:30,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:30,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:30,943 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:30,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:30,945 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:30,947 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:31,032 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:31,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:31,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:31,033 INFO L87 Difference]: Start difference. First operand 16914 states and 23491 transitions. cyclomatic complexity: 6580 Second operand 3 states. [2020-11-28 03:11:31,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:31,091 INFO L93 Difference]: Finished difference Result 16845 states and 23393 transitions. [2020-11-28 03:11:31,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:31,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16845 states and 23393 transitions. [2020-11-28 03:11:31,169 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16760 [2020-11-28 03:11:31,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16845 states to 16845 states and 23393 transitions. [2020-11-28 03:11:31,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16845 [2020-11-28 03:11:31,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16845 [2020-11-28 03:11:31,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16845 states and 23393 transitions. [2020-11-28 03:11:31,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:31,254 INFO L691 BuchiCegarLoop]: Abstraction has 16845 states and 23393 transitions. [2020-11-28 03:11:31,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16845 states and 23393 transitions. [2020-11-28 03:11:31,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16845 to 16845. [2020-11-28 03:11:31,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16845 states. [2020-11-28 03:11:31,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16845 states to 16845 states and 23393 transitions. [2020-11-28 03:11:31,564 INFO L714 BuchiCegarLoop]: Abstraction has 16845 states and 23393 transitions. [2020-11-28 03:11:31,564 INFO L594 BuchiCegarLoop]: Abstraction has 16845 states and 23393 transitions. [2020-11-28 03:11:31,564 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2020-11-28 03:11:31,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16845 states and 23393 transitions. [2020-11-28 03:11:31,621 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16760 [2020-11-28 03:11:31,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:31,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:31,622 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:31,622 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:31,622 INFO L794 eck$LassoCheckResult]: Stem: 224986#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 224865#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 224807#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 224595#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 224596#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224717#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224718#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224597#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224598#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224817#L443-1 assume !(0 == ~M_E~0); 224818#L603-1 assume !(0 == ~T1_E~0); 224824#L608-1 assume !(0 == ~T2_E~0); 224825#L613-1 assume !(0 == ~T3_E~0); 224741#L618-1 assume !(0 == ~T4_E~0); 224742#L623-1 assume !(0 == ~T5_E~0); 224800#L628-1 assume !(0 == ~E_M~0); 224669#L633-1 assume !(0 == ~E_1~0); 224670#L638-1 assume !(0 == ~E_2~0); 224505#L643-1 assume !(0 == ~E_3~0); 224506#L648-1 assume !(0 == ~E_4~0); 224609#L653-1 assume !(0 == ~E_5~0); 224610#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 224862#L296 assume !(1 == ~m_pc~0); 224848#L296-2 is_master_triggered_~__retres1~0 := 0; 224849#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 224872#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 224939#L747 assume !(0 != activate_threads_~tmp~1); 224926#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 224927#L315 assume !(1 == ~t1_pc~0); 225039#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 225040#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 225129#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 225128#L755 assume !(0 != activate_threads_~tmp___0~0); 225086#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224563#L334 assume !(1 == ~t2_pc~0); 224564#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 224561#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 224562#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 224619#L763 assume !(0 != activate_threads_~tmp___1~0); 224603#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 224604#L353 assume !(1 == ~t3_pc~0); 224724#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 224725#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224721#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 224722#L771 assume !(0 != activate_threads_~tmp___2~0); 224967#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 224953#L372 assume !(1 == ~t4_pc~0); 224954#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 224959#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 224919#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 224920#L779 assume !(0 != activate_threads_~tmp___3~0); 225102#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 224656#L391 assume !(1 == ~t5_pc~0); 224657#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 224652#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 224653#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 224681#L787 assume !(0 != activate_threads_~tmp___4~0); 224682#L787-2 assume !(1 == ~M_E~0); 224685#L671-1 assume !(1 == ~T1_E~0); 224503#L676-1 assume !(1 == ~T2_E~0); 224504#L681-1 assume !(1 == ~T3_E~0); 224607#L686-1 assume !(1 == ~T4_E~0); 224608#L691-1 assume !(1 == ~T5_E~0); 224820#L696-1 assume !(1 == ~E_M~0); 224821#L701-1 assume !(1 == ~E_1~0); 224756#L706-1 assume !(1 == ~E_2~0); 224757#L711-1 assume !(1 == ~E_3~0); 224968#L716-1 assume !(1 == ~E_4~0); 224686#L721-1 assume !(1 == ~E_5~0); 224687#L932-1 assume !false; 226207#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 226205#L578 [2020-11-28 03:11:31,623 INFO L796 eck$LassoCheckResult]: Loop: 226205#L578 assume !false; 226203#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 226201#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 226199#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 226197#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 226194#L503 assume 0 != eval_~tmp~0; 226192#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 226189#L511 assume !(0 != eval_~tmp_ndt_1~0); 226052#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 226048#L525 assume !(0 != eval_~tmp_ndt_2~0); 226046#L522 assume !(0 == ~t2_st~0); 226042#L536 assume !(0 == ~t3_st~0); 226038#L550 assume !(0 == ~t4_st~0); 226037#L564 assume !(0 == ~t5_st~0); 226205#L578 [2020-11-28 03:11:31,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:31,623 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2020-11-28 03:11:31,623 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:31,623 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370740441] [2020-11-28 03:11:31,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:31,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:31,634 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:31,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:31,642 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:31,661 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:31,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:31,662 INFO L82 PathProgramCache]: Analyzing trace with hash -638145939, now seen corresponding path program 1 times [2020-11-28 03:11:31,662 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:31,662 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223704354] [2020-11-28 03:11:31,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:31,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:31,665 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:31,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:31,667 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:31,670 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:31,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:31,671 INFO L82 PathProgramCache]: Analyzing trace with hash 262341999, now seen corresponding path program 1 times [2020-11-28 03:11:31,671 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:31,671 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647892052] [2020-11-28 03:11:31,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:31,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:31,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:31,713 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647892052] [2020-11-28 03:11:31,713 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:31,713 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:31,713 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306035121] [2020-11-28 03:11:31,838 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:31,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:31,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:31,838 INFO L87 Difference]: Start difference. First operand 16845 states and 23393 transitions. cyclomatic complexity: 6551 Second operand 3 states. [2020-11-28 03:11:31,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:31,994 INFO L93 Difference]: Finished difference Result 31683 states and 43855 transitions. [2020-11-28 03:11:31,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:31,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31683 states and 43855 transitions. [2020-11-28 03:11:32,369 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31590 [2020-11-28 03:11:32,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31683 states to 31683 states and 43855 transitions. [2020-11-28 03:11:32,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31683 [2020-11-28 03:11:32,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31683 [2020-11-28 03:11:32,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31683 states and 43855 transitions. [2020-11-28 03:11:32,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:32,545 INFO L691 BuchiCegarLoop]: Abstraction has 31683 states and 43855 transitions. [2020-11-28 03:11:32,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31683 states and 43855 transitions. [2020-11-28 03:11:32,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31683 to 31025. [2020-11-28 03:11:32,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31025 states. [2020-11-28 03:11:33,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31025 states to 31025 states and 42973 transitions. [2020-11-28 03:11:33,182 INFO L714 BuchiCegarLoop]: Abstraction has 31025 states and 42973 transitions. [2020-11-28 03:11:33,182 INFO L594 BuchiCegarLoop]: Abstraction has 31025 states and 42973 transitions. [2020-11-28 03:11:33,182 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2020-11-28 03:11:33,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31025 states and 42973 transitions. [2020-11-28 03:11:33,248 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30932 [2020-11-28 03:11:33,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:33,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:33,249 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:33,249 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:33,249 INFO L794 eck$LassoCheckResult]: Stem: 273561#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 273433#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 273368#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 273134#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 273135#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 273272#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273273#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 273137#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273138#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273380#L443-1 assume !(0 == ~M_E~0); 273381#L603-1 assume !(0 == ~T1_E~0); 273386#L608-1 assume !(0 == ~T2_E~0); 273387#L613-1 assume !(0 == ~T3_E~0); 273296#L618-1 assume !(0 == ~T4_E~0); 273297#L623-1 assume !(0 == ~T5_E~0); 273361#L628-1 assume !(0 == ~E_M~0); 273212#L633-1 assume !(0 == ~E_1~0); 273213#L638-1 assume !(0 == ~E_2~0); 273041#L643-1 assume !(0 == ~E_3~0); 273042#L648-1 assume !(0 == ~E_4~0); 273149#L653-1 assume !(0 == ~E_5~0); 273150#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273426#L296 assume !(1 == ~m_pc~0); 273413#L296-2 is_master_triggered_~__retres1~0 := 0; 273414#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273441#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 273504#L747 assume !(0 != activate_threads_~tmp~1); 273490#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 273491#L315 assume !(1 == ~t1_pc~0); 273618#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 273619#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273712#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 273711#L755 assume !(0 != activate_threads_~tmp___0~0); 273668#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 273099#L334 assume !(1 == ~t2_pc~0); 273100#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 273097#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 273098#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 273160#L763 assume !(0 != activate_threads_~tmp___1~0); 273143#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273144#L353 assume !(1 == ~t3_pc~0); 273279#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 273280#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 273276#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 273277#L771 assume !(0 != activate_threads_~tmp___2~0); 273537#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 273520#L372 assume !(1 == ~t4_pc~0); 273521#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 273528#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 273485#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 273486#L779 assume !(0 != activate_threads_~tmp___3~0); 273686#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 273199#L391 assume !(1 == ~t5_pc~0); 273200#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 273195#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 273196#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 273225#L787 assume !(0 != activate_threads_~tmp___4~0); 273226#L787-2 assume !(1 == ~M_E~0); 273229#L671-1 assume !(1 == ~T1_E~0); 273039#L676-1 assume !(1 == ~T2_E~0); 273040#L681-1 assume !(1 == ~T3_E~0); 273147#L686-1 assume !(1 == ~T4_E~0); 273148#L691-1 assume !(1 == ~T5_E~0); 273382#L696-1 assume !(1 == ~E_M~0); 273383#L701-1 assume !(1 == ~E_1~0); 273313#L706-1 assume !(1 == ~E_2~0); 273314#L711-1 assume !(1 == ~E_3~0); 273538#L716-1 assume !(1 == ~E_4~0); 273231#L721-1 assume !(1 == ~E_5~0); 273232#L932-1 assume !false; 289749#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 289745#L578 [2020-11-28 03:11:33,250 INFO L796 eck$LassoCheckResult]: Loop: 289745#L578 assume !false; 289743#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 289740#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 289737#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 289735#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 289733#L503 assume 0 != eval_~tmp~0; 289730#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 289726#L511 assume !(0 != eval_~tmp_ndt_1~0); 289723#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 289691#L525 assume !(0 != eval_~tmp_ndt_2~0); 285776#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 285774#L539 assume !(0 != eval_~tmp_ndt_3~0); 285775#L536 assume !(0 == ~t3_st~0); 289757#L550 assume !(0 == ~t4_st~0); 289750#L564 assume !(0 == ~t5_st~0); 289745#L578 [2020-11-28 03:11:33,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:33,250 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2020-11-28 03:11:33,251 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:33,251 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526000472] [2020-11-28 03:11:33,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:33,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:33,260 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:33,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:33,267 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:33,284 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:33,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:33,285 INFO L82 PathProgramCache]: Analyzing trace with hash 1525098172, now seen corresponding path program 1 times [2020-11-28 03:11:33,285 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:33,285 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627608712] [2020-11-28 03:11:33,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:33,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:33,288 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:33,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:33,291 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:33,292 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:33,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:33,293 INFO L82 PathProgramCache]: Analyzing trace with hash -624546822, now seen corresponding path program 1 times [2020-11-28 03:11:33,293 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:33,293 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289520101] [2020-11-28 03:11:33,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:33,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:33,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:33,329 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289520101] [2020-11-28 03:11:33,329 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:33,329 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:33,329 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744268691] [2020-11-28 03:11:33,471 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:33,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:33,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:33,472 INFO L87 Difference]: Start difference. First operand 31025 states and 42973 transitions. cyclomatic complexity: 11951 Second operand 3 states. [2020-11-28 03:11:33,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:33,880 INFO L93 Difference]: Finished difference Result 56525 states and 78217 transitions. [2020-11-28 03:11:33,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:33,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56525 states and 78217 transitions. [2020-11-28 03:11:34,089 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56416 [2020-11-28 03:11:34,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56525 states to 56525 states and 78217 transitions. [2020-11-28 03:11:34,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56525 [2020-11-28 03:11:34,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56525 [2020-11-28 03:11:34,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56525 states and 78217 transitions. [2020-11-28 03:11:34,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:34,477 INFO L691 BuchiCegarLoop]: Abstraction has 56525 states and 78217 transitions. [2020-11-28 03:11:34,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56525 states and 78217 transitions. [2020-11-28 03:11:35,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56525 to 54677. [2020-11-28 03:11:35,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54677 states. [2020-11-28 03:11:35,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54677 states to 54677 states and 75809 transitions. [2020-11-28 03:11:35,133 INFO L714 BuchiCegarLoop]: Abstraction has 54677 states and 75809 transitions. [2020-11-28 03:11:35,133 INFO L594 BuchiCegarLoop]: Abstraction has 54677 states and 75809 transitions. [2020-11-28 03:11:35,133 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2020-11-28 03:11:35,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54677 states and 75809 transitions. [2020-11-28 03:11:35,310 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 54568 [2020-11-28 03:11:35,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:35,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:35,311 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:35,313 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:35,313 INFO L794 eck$LassoCheckResult]: Stem: 361110#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 360982#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 360918#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 360688#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 360689#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 360818#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 360819#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 360690#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 360691#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 360931#L443-1 assume !(0 == ~M_E~0); 360932#L603-1 assume !(0 == ~T1_E~0); 360939#L608-1 assume !(0 == ~T2_E~0); 360940#L613-1 assume !(0 == ~T3_E~0); 360843#L618-1 assume !(0 == ~T4_E~0); 360844#L623-1 assume !(0 == ~T5_E~0); 360909#L628-1 assume !(0 == ~E_M~0); 360763#L633-1 assume !(0 == ~E_1~0); 360764#L638-1 assume !(0 == ~E_2~0); 360599#L643-1 assume !(0 == ~E_3~0); 360600#L648-1 assume !(0 == ~E_4~0); 360703#L653-1 assume !(0 == ~E_5~0); 360704#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 360979#L296 assume !(1 == ~m_pc~0); 360965#L296-2 is_master_triggered_~__retres1~0 := 0; 360966#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 360990#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 361065#L747 assume !(0 != activate_threads_~tmp~1); 361051#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 361052#L315 assume !(1 == ~t1_pc~0); 361170#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 361171#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 361271#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 361270#L755 assume !(0 != activate_threads_~tmp___0~0); 361221#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 360656#L334 assume !(1 == ~t2_pc~0); 360657#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 360654#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 360655#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 360713#L763 assume !(0 != activate_threads_~tmp___1~0); 360697#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 360698#L353 assume !(1 == ~t3_pc~0); 360826#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 360827#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 360823#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 360824#L771 assume !(0 != activate_threads_~tmp___2~0); 361096#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 361081#L372 assume !(1 == ~t4_pc~0); 361082#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 361088#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 361045#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 361046#L779 assume !(0 != activate_threads_~tmp___3~0); 361240#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 360748#L391 assume !(1 == ~t5_pc~0); 360749#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 360744#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 360745#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 360775#L787 assume !(0 != activate_threads_~tmp___4~0); 360776#L787-2 assume !(1 == ~M_E~0); 360779#L671-1 assume !(1 == ~T1_E~0); 360597#L676-1 assume !(1 == ~T2_E~0); 360598#L681-1 assume !(1 == ~T3_E~0); 360701#L686-1 assume !(1 == ~T4_E~0); 360702#L691-1 assume !(1 == ~T5_E~0); 360935#L696-1 assume !(1 == ~E_M~0); 360936#L701-1 assume !(1 == ~E_1~0); 360860#L706-1 assume !(1 == ~E_2~0); 360861#L711-1 assume !(1 == ~E_3~0); 361097#L716-1 assume !(1 == ~E_4~0); 360780#L721-1 assume !(1 == ~E_5~0); 360781#L932-1 assume !false; 373095#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 373096#L578 [2020-11-28 03:11:35,314 INFO L796 eck$LassoCheckResult]: Loop: 373096#L578 assume !false; 373087#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 373088#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 373080#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 373081#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 374524#L503 assume 0 != eval_~tmp~0; 374521#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 373069#L511 assume !(0 != eval_~tmp_ndt_1~0); 373067#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 373051#L525 assume !(0 != eval_~tmp_ndt_2~0); 374432#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 374814#L539 assume !(0 != eval_~tmp_ndt_3~0); 374673#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 373143#L553 assume !(0 != eval_~tmp_ndt_4~0); 373145#L550 assume !(0 == ~t4_st~0); 373097#L564 assume !(0 == ~t5_st~0); 373096#L578 [2020-11-28 03:11:35,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:35,314 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2020-11-28 03:11:35,315 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:35,315 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393159535] [2020-11-28 03:11:35,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:35,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:35,332 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:35,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:35,341 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:35,359 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:35,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:35,360 INFO L82 PathProgramCache]: Analyzing trace with hash 28010706, now seen corresponding path program 1 times [2020-11-28 03:11:35,360 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:35,360 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811849435] [2020-11-28 03:11:35,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:35,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:35,364 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:35,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:35,366 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:35,369 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:35,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:35,369 INFO L82 PathProgramCache]: Analyzing trace with hash 2108492628, now seen corresponding path program 1 times [2020-11-28 03:11:35,370 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:35,370 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964360052] [2020-11-28 03:11:35,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:35,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:35,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:35,674 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964360052] [2020-11-28 03:11:35,674 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:35,674 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:11:35,674 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635388781] [2020-11-28 03:11:35,776 WARN L193 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2020-11-28 03:11:35,828 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:35,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:35,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:35,828 INFO L87 Difference]: Start difference. First operand 54677 states and 75809 transitions. cyclomatic complexity: 21135 Second operand 3 states. [2020-11-28 03:11:36,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:36,159 INFO L93 Difference]: Finished difference Result 101509 states and 140561 transitions. [2020-11-28 03:11:36,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:36,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101509 states and 140561 transitions. [2020-11-28 03:11:36,747 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 101368 [2020-11-28 03:11:37,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101509 states to 101509 states and 140561 transitions. [2020-11-28 03:11:37,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101509 [2020-11-28 03:11:37,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101509 [2020-11-28 03:11:37,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101509 states and 140561 transitions. [2020-11-28 03:11:37,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:37,225 INFO L691 BuchiCegarLoop]: Abstraction has 101509 states and 140561 transitions. [2020-11-28 03:11:37,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101509 states and 140561 transitions. [2020-11-28 03:11:38,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101509 to 100389. [2020-11-28 03:11:38,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100389 states. [2020-11-28 03:11:38,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100389 states to 100389 states and 139105 transitions. [2020-11-28 03:11:38,609 INFO L714 BuchiCegarLoop]: Abstraction has 100389 states and 139105 transitions. [2020-11-28 03:11:38,609 INFO L594 BuchiCegarLoop]: Abstraction has 100389 states and 139105 transitions. [2020-11-28 03:11:38,609 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2020-11-28 03:11:38,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100389 states and 139105 transitions. [2020-11-28 03:11:38,898 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 100248 [2020-11-28 03:11:38,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:38,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:38,899 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:38,899 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:38,900 INFO L794 eck$LassoCheckResult]: Stem: 517304#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 517171#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 517107#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 516883#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 516884#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 517009#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 517010#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 516885#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 516886#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 517120#L443-1 assume !(0 == ~M_E~0); 517121#L603-1 assume !(0 == ~T1_E~0); 517128#L608-1 assume !(0 == ~T2_E~0); 517129#L613-1 assume !(0 == ~T3_E~0); 517034#L618-1 assume !(0 == ~T4_E~0); 517035#L623-1 assume !(0 == ~T5_E~0); 517098#L628-1 assume !(0 == ~E_M~0); 516957#L633-1 assume !(0 == ~E_1~0); 516958#L638-1 assume !(0 == ~E_2~0); 516793#L643-1 assume !(0 == ~E_3~0); 516794#L648-1 assume !(0 == ~E_4~0); 516897#L653-1 assume !(0 == ~E_5~0); 516898#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 517168#L296 assume !(1 == ~m_pc~0); 517153#L296-2 is_master_triggered_~__retres1~0 := 0; 517154#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 517178#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 517255#L747 assume !(0 != activate_threads_~tmp~1); 517237#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 517238#L315 assume !(1 == ~t1_pc~0); 517357#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 517358#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 517464#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 517463#L755 assume !(0 != activate_threads_~tmp___0~0); 517406#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 516851#L334 assume !(1 == ~t2_pc~0); 516852#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 516849#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 516850#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 516908#L763 assume !(0 != activate_threads_~tmp___1~0); 516891#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 516892#L353 assume !(1 == ~t3_pc~0); 517017#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 517018#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 517014#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 517015#L771 assume !(0 != activate_threads_~tmp___2~0); 517284#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 517270#L372 assume !(1 == ~t4_pc~0); 517271#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 517276#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 517231#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 517232#L779 assume !(0 != activate_threads_~tmp___3~0); 517426#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 516942#L391 assume !(1 == ~t5_pc~0); 516943#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 516938#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 516939#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 516969#L787 assume !(0 != activate_threads_~tmp___4~0); 516970#L787-2 assume !(1 == ~M_E~0); 516973#L671-1 assume !(1 == ~T1_E~0); 516791#L676-1 assume !(1 == ~T2_E~0); 516792#L681-1 assume !(1 == ~T3_E~0); 516895#L686-1 assume !(1 == ~T4_E~0); 516896#L691-1 assume !(1 == ~T5_E~0); 517124#L696-1 assume !(1 == ~E_M~0); 517125#L701-1 assume !(1 == ~E_1~0); 517051#L706-1 assume !(1 == ~E_2~0); 517052#L711-1 assume !(1 == ~E_3~0); 517285#L716-1 assume !(1 == ~E_4~0); 516974#L721-1 assume !(1 == ~E_5~0); 516975#L932-1 assume !false; 546905#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 546903#L578 [2020-11-28 03:11:38,900 INFO L796 eck$LassoCheckResult]: Loop: 546903#L578 assume !false; 546901#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 546897#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 546895#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 546893#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 546891#L503 assume 0 != eval_~tmp~0; 546888#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 546884#L511 assume !(0 != eval_~tmp_ndt_1~0); 546883#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 546881#L525 assume !(0 != eval_~tmp_ndt_2~0); 545718#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 541294#L539 assume !(0 != eval_~tmp_ndt_3~0); 541292#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 541209#L553 assume !(0 != eval_~tmp_ndt_4~0); 541290#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 546389#L567 assume !(0 != eval_~tmp_ndt_5~0); 546906#L564 assume !(0 == ~t5_st~0); 546903#L578 [2020-11-28 03:11:38,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:38,901 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2020-11-28 03:11:38,901 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:38,901 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722303015] [2020-11-28 03:11:38,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:38,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:38,911 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:38,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:38,919 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:38,935 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:38,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:38,935 INFO L82 PathProgramCache]: Analyzing trace with hash 868159575, now seen corresponding path program 1 times [2020-11-28 03:11:38,935 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:38,936 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687346899] [2020-11-28 03:11:38,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:38,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:38,939 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:38,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:38,941 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:38,943 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:38,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:38,944 INFO L82 PathProgramCache]: Analyzing trace with hash 938589717, now seen corresponding path program 1 times [2020-11-28 03:11:38,944 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:38,944 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075390471] [2020-11-28 03:11:38,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:38,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:11:38,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:11:38,986 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075390471] [2020-11-28 03:11:38,986 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:11:38,986 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:11:38,986 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923819374] [2020-11-28 03:11:39,617 WARN L193 SmtUtils]: Spent 629.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2020-11-28 03:11:39,681 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:11:39,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:11:39,681 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:11:39,681 INFO L87 Difference]: Start difference. First operand 100389 states and 139105 transitions. cyclomatic complexity: 38719 Second operand 3 states. [2020-11-28 03:11:40,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:11:40,190 INFO L93 Difference]: Finished difference Result 174133 states and 241409 transitions. [2020-11-28 03:11:40,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:11:40,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174133 states and 241409 transitions. [2020-11-28 03:11:41,305 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 173928 [2020-11-28 03:11:42,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174133 states to 174133 states and 241409 transitions. [2020-11-28 03:11:42,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 174133 [2020-11-28 03:11:42,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 174133 [2020-11-28 03:11:42,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174133 states and 241409 transitions. [2020-11-28 03:11:42,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:11:42,152 INFO L691 BuchiCegarLoop]: Abstraction has 174133 states and 241409 transitions. [2020-11-28 03:11:42,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174133 states and 241409 transitions. [2020-11-28 03:11:43,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174133 to 172789. [2020-11-28 03:11:43,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172789 states. [2020-11-28 03:11:44,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172789 states to 172789 states and 240065 transitions. [2020-11-28 03:11:44,471 INFO L714 BuchiCegarLoop]: Abstraction has 172789 states and 240065 transitions. [2020-11-28 03:11:44,471 INFO L594 BuchiCegarLoop]: Abstraction has 172789 states and 240065 transitions. [2020-11-28 03:11:44,471 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2020-11-28 03:11:44,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172789 states and 240065 transitions. [2020-11-28 03:11:45,042 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 172584 [2020-11-28 03:11:45,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:11:45,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:11:45,044 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:45,044 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:11:45,044 INFO L794 eck$LassoCheckResult]: Stem: 791862#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 791718#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 791653#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 791419#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 791420#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 791544#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 791545#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 791421#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 791422#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 791665#L443-1 assume !(0 == ~M_E~0); 791666#L603-1 assume !(0 == ~T1_E~0); 791673#L608-1 assume !(0 == ~T2_E~0); 791674#L613-1 assume !(0 == ~T3_E~0); 791569#L618-1 assume !(0 == ~T4_E~0); 791570#L623-1 assume !(0 == ~T5_E~0); 791643#L628-1 assume !(0 == ~E_M~0); 791494#L633-1 assume !(0 == ~E_1~0); 791495#L638-1 assume !(0 == ~E_2~0); 791323#L643-1 assume !(0 == ~E_3~0); 791324#L648-1 assume !(0 == ~E_4~0); 791435#L653-1 assume !(0 == ~E_5~0); 791436#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 791715#L296 assume !(1 == ~m_pc~0); 791700#L296-2 is_master_triggered_~__retres1~0 := 0; 791701#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 791726#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 791807#L747 assume !(0 != activate_threads_~tmp~1); 791789#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 791790#L315 assume !(1 == ~t1_pc~0); 791929#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 791930#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 792061#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 792060#L755 assume !(0 != activate_threads_~tmp___0~0); 791992#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 791385#L334 assume !(1 == ~t2_pc~0); 791386#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 791383#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 791384#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 791445#L763 assume !(0 != activate_threads_~tmp___1~0); 791429#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 791430#L353 assume !(1 == ~t3_pc~0); 791552#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 791553#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 791549#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 791550#L771 assume !(0 != activate_threads_~tmp___2~0); 791842#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 791826#L372 assume !(1 == ~t4_pc~0); 791827#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 791832#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 791783#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 791784#L779 assume !(0 != activate_threads_~tmp___3~0); 792017#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 791479#L391 assume !(1 == ~t5_pc~0); 791480#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 791476#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 791477#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 791507#L787 assume !(0 != activate_threads_~tmp___4~0); 791508#L787-2 assume !(1 == ~M_E~0); 791511#L671-1 assume !(1 == ~T1_E~0); 791321#L676-1 assume !(1 == ~T2_E~0); 791322#L681-1 assume !(1 == ~T3_E~0); 791433#L686-1 assume !(1 == ~T4_E~0); 791434#L691-1 assume !(1 == ~T5_E~0); 791669#L696-1 assume !(1 == ~E_M~0); 791670#L701-1 assume !(1 == ~E_1~0); 791585#L706-1 assume !(1 == ~E_2~0); 791586#L711-1 assume !(1 == ~E_3~0); 791843#L716-1 assume !(1 == ~E_4~0); 791512#L721-1 assume !(1 == ~E_5~0); 791513#L932-1 assume !false; 846023#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 846021#L578 [2020-11-28 03:11:45,045 INFO L796 eck$LassoCheckResult]: Loop: 846021#L578 assume !false; 846019#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 845954#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 845952#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 845953#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 845944#L503 assume 0 != eval_~tmp~0; 845945#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 847497#L511 assume !(0 != eval_~tmp_ndt_1~0); 837873#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 837868#L525 assume !(0 != eval_~tmp_ndt_2~0); 829656#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 828627#L539 assume !(0 != eval_~tmp_ndt_3~0); 828625#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 826129#L553 assume !(0 != eval_~tmp_ndt_4~0); 828623#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 833465#L567 assume !(0 != eval_~tmp_ndt_5~0); 846025#L564 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet15;havoc eval_#t~nondet15; 842244#L581 assume !(0 != eval_~tmp_ndt_6~0); 846021#L578 [2020-11-28 03:11:45,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:45,045 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2020-11-28 03:11:45,046 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:45,046 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667799324] [2020-11-28 03:11:45,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:45,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,054 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,076 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,095 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:45,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:45,095 INFO L82 PathProgramCache]: Analyzing trace with hash 1143139127, now seen corresponding path program 1 times [2020-11-28 03:11:45,096 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:45,096 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368978019] [2020-11-28 03:11:45,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:45,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,099 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,117 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,119 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:45,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:11:45,120 INFO L82 PathProgramCache]: Analyzing trace with hash -968493767, now seen corresponding path program 1 times [2020-11-28 03:11:45,120 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:11:45,120 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650799852] [2020-11-28 03:11:45,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:11:45,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,128 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:11:45,149 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:11:45,170 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:11:45,324 WARN L193 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2020-11-28 03:11:47,403 WARN L193 SmtUtils]: Spent 2.00 s on a formula simplification. DAG size of input: 251 DAG size of output: 179 [2020-11-28 03:11:47,885 WARN L193 SmtUtils]: Spent 440.00 ms on a formula simplification that was a NOOP. DAG size: 153 [2020-11-28 03:11:47,932 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:11:47 BoogieIcfgContainer [2020-11-28 03:11:47,932 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 03:11:47,932 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 03:11:47,933 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 03:11:47,933 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 03:11:47,933 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:11:21" (3/4) ... [2020-11-28 03:11:47,936 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 03:11:47,989 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_918740ac-6a15-4b4d-a74e-40e77d182540/bin/uautomizer/witness.graphml [2020-11-28 03:11:47,989 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 03:11:47,991 INFO L168 Benchmark]: Toolchain (without parser) took 29102.57 ms. Allocated memory was 88.1 MB in the beginning and 10.6 GB in the end (delta: 10.5 GB). Free memory was 56.9 MB in the beginning and 8.6 GB in the end (delta: -8.6 GB). Peak memory consumption was 1.9 GB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,991 INFO L168 Benchmark]: CDTParser took 0.85 ms. Allocated memory is still 88.1 MB. Free memory was 45.6 MB in the beginning and 45.6 MB in the end (delta: 34.4 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 03:11:47,992 INFO L168 Benchmark]: CACSL2BoogieTranslator took 409.51 ms. Allocated memory is still 88.1 MB. Free memory was 56.8 MB in the beginning and 60.7 MB in the end (delta: -4.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,992 INFO L168 Benchmark]: Boogie Procedure Inliner took 95.57 ms. Allocated memory is still 88.1 MB. Free memory was 60.7 MB in the beginning and 55.5 MB in the end (delta: 5.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,992 INFO L168 Benchmark]: Boogie Preprocessor took 98.04 ms. Allocated memory is still 88.1 MB. Free memory was 55.5 MB in the beginning and 51.0 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,993 INFO L168 Benchmark]: RCFGBuilder took 1854.47 ms. Allocated memory was 88.1 MB in the beginning and 113.2 MB in the end (delta: 25.2 MB). Free memory was 51.0 MB in the beginning and 70.4 MB in the end (delta: -19.4 MB). Peak memory consumption was 34.3 MB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,993 INFO L168 Benchmark]: BuchiAutomizer took 26579.09 ms. Allocated memory was 113.2 MB in the beginning and 10.6 GB in the end (delta: 10.4 GB). Free memory was 70.4 MB in the beginning and 8.7 GB in the end (delta: -8.6 GB). Peak memory consumption was 2.2 GB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,994 INFO L168 Benchmark]: Witness Printer took 57.02 ms. Allocated memory is still 10.6 GB. Free memory was 8.7 GB in the beginning and 8.6 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 03:11:47,996 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.85 ms. Allocated memory is still 88.1 MB. Free memory was 45.6 MB in the beginning and 45.6 MB in the end (delta: 34.4 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 409.51 ms. Allocated memory is still 88.1 MB. Free memory was 56.8 MB in the beginning and 60.7 MB in the end (delta: -4.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 95.57 ms. Allocated memory is still 88.1 MB. Free memory was 60.7 MB in the beginning and 55.5 MB in the end (delta: 5.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 98.04 ms. Allocated memory is still 88.1 MB. Free memory was 55.5 MB in the beginning and 51.0 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1854.47 ms. Allocated memory was 88.1 MB in the beginning and 113.2 MB in the end (delta: 25.2 MB). Free memory was 51.0 MB in the beginning and 70.4 MB in the end (delta: -19.4 MB). Peak memory consumption was 34.3 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 26579.09 ms. Allocated memory was 113.2 MB in the beginning and 10.6 GB in the end (delta: 10.4 GB). Free memory was 70.4 MB in the beginning and 8.7 GB in the end (delta: -8.6 GB). Peak memory consumption was 2.2 GB. Max. memory is 16.1 GB. * Witness Printer took 57.02 ms. Allocated memory is still 10.6 GB. Free memory was 8.7 GB in the beginning and 8.6 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 172789 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 26.5s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 7.2s. Construction of modules took 1.5s. Büchi inclusion checks took 2.6s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 7.2s AutomataMinimizationTime, 23 MinimizatonAttempts, 39974 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 5.2s Buchi closure took 0.2s. Biggest automaton had 172789 states and ocurred in iteration 23. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 20544 SDtfs, 25676 SDslu, 21105 SDs, 0 SdLazy, 851 SolverSat, 340 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 498]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=1, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f987832=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ea3ac5c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52da3b9e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22b14650=0, NULL=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d4adc5c=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34115af=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f84a41d=0, tmp=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c017ab8=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@19236be4=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49f496ba=0, NULL=3, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42d926f=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34e0016f=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5665cd24=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f375da3=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ad8d4cb=0, T1_E=2, NULL=2, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=4, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 498]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L977] int __retres1 ; [L888] m_i = 1 [L889] t1_i = 1 [L890] t2_i = 1 [L891] t3_i = 1 [L892] t4_i = 1 [L893] t5_i = 1 [L918] int kernel_st ; [L919] int tmp ; [L920] int tmp___0 ; [L924] kernel_st = 0 [L418] COND TRUE m_i == 1 [L419] m_st = 0 [L423] COND TRUE t1_i == 1 [L424] t1_st = 0 [L428] COND TRUE t2_i == 1 [L429] t2_st = 0 [L433] COND TRUE t3_i == 1 [L434] t3_st = 0 [L438] COND TRUE t4_i == 1 [L439] t4_st = 0 [L443] COND TRUE t5_i == 1 [L444] t5_st = 0 [L603] COND FALSE !(M_E == 0) [L608] COND FALSE !(T1_E == 0) [L613] COND FALSE !(T2_E == 0) [L618] COND FALSE !(T3_E == 0) [L623] COND FALSE !(T4_E == 0) [L628] COND FALSE !(T5_E == 0) [L633] COND FALSE !(E_M == 0) [L638] COND FALSE !(E_1 == 0) [L643] COND FALSE !(E_2 == 0) [L648] COND FALSE !(E_3 == 0) [L653] COND FALSE !(E_4 == 0) [L658] COND FALSE !(E_5 == 0) [L736] int tmp ; [L737] int tmp___0 ; [L738] int tmp___1 ; [L739] int tmp___2 ; [L740] int tmp___3 ; [L741] int tmp___4 ; [L293] int __retres1 ; [L296] COND FALSE !(m_pc == 1) [L306] __retres1 = 0 [L308] return (__retres1); [L745] tmp = is_master_triggered() [L747] COND FALSE !(\read(tmp)) [L312] int __retres1 ; [L315] COND FALSE !(t1_pc == 1) [L325] __retres1 = 0 [L327] return (__retres1); [L753] tmp___0 = is_transmit1_triggered() [L755] COND FALSE !(\read(tmp___0)) [L331] int __retres1 ; [L334] COND FALSE !(t2_pc == 1) [L344] __retres1 = 0 [L346] return (__retres1); [L761] tmp___1 = is_transmit2_triggered() [L763] COND FALSE !(\read(tmp___1)) [L350] int __retres1 ; [L353] COND FALSE !(t3_pc == 1) [L363] __retres1 = 0 [L365] return (__retres1); [L769] tmp___2 = is_transmit3_triggered() [L771] COND FALSE !(\read(tmp___2)) [L369] int __retres1 ; [L372] COND FALSE !(t4_pc == 1) [L382] __retres1 = 0 [L384] return (__retres1); [L777] tmp___3 = is_transmit4_triggered() [L779] COND FALSE !(\read(tmp___3)) [L388] int __retres1 ; [L391] COND FALSE !(t5_pc == 1) [L401] __retres1 = 0 [L403] return (__retres1); [L785] tmp___4 = is_transmit5_triggered() [L787] COND FALSE !(\read(tmp___4)) [L671] COND FALSE !(M_E == 1) [L676] COND FALSE !(T1_E == 1) [L681] COND FALSE !(T2_E == 1) [L686] COND FALSE !(T3_E == 1) [L691] COND FALSE !(T4_E == 1) [L696] COND FALSE !(T5_E == 1) [L701] COND FALSE !(E_M == 1) [L706] COND FALSE !(E_1 == 1) [L711] COND FALSE !(E_2 == 1) [L716] COND FALSE !(E_3 == 1) [L721] COND FALSE !(E_4 == 1) [L726] COND FALSE !(E_5 == 1) [L932] COND TRUE 1 [L935] kernel_st = 1 [L494] int tmp ; Loop: [L498] COND TRUE 1 [L453] int __retres1 ; [L456] COND TRUE m_st == 0 [L457] __retres1 = 1 [L489] return (__retres1); [L501] tmp = exists_runnable_thread() [L503] COND TRUE \read(tmp) [L508] COND TRUE m_st == 0 [L509] int tmp_ndt_1; [L510] tmp_ndt_1 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_1)) [L522] COND TRUE t1_st == 0 [L523] int tmp_ndt_2; [L524] tmp_ndt_2 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_2)) [L536] COND TRUE t2_st == 0 [L537] int tmp_ndt_3; [L538] tmp_ndt_3 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_3)) [L550] COND TRUE t3_st == 0 [L551] int tmp_ndt_4; [L552] tmp_ndt_4 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_4)) [L564] COND TRUE t4_st == 0 [L565] int tmp_ndt_5; [L566] tmp_ndt_5 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_5)) [L578] COND TRUE t5_st == 0 [L579] int tmp_ndt_6; [L580] tmp_ndt_6 = __VERIFIER_nondet_int() [L581] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...