./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5c6676c90977e408adf03f66d7ae0804453cb34e .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 03:12:12,086 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 03:12:12,089 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 03:12:12,150 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 03:12:12,151 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 03:12:12,153 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 03:12:12,156 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 03:12:12,159 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 03:12:12,162 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 03:12:12,163 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 03:12:12,165 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 03:12:12,167 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 03:12:12,167 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 03:12:12,169 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 03:12:12,171 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 03:12:12,173 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 03:12:12,174 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 03:12:12,176 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 03:12:12,179 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 03:12:12,182 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 03:12:12,184 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 03:12:12,187 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 03:12:12,189 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 03:12:12,190 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 03:12:12,194 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 03:12:12,195 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 03:12:12,196 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 03:12:12,197 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 03:12:12,198 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 03:12:12,200 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 03:12:12,201 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 03:12:12,202 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 03:12:12,203 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 03:12:12,205 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 03:12:12,206 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 03:12:12,207 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 03:12:12,208 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 03:12:12,208 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 03:12:12,209 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 03:12:12,210 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 03:12:12,211 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 03:12:12,213 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 03:12:12,256 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 03:12:12,260 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 03:12:12,262 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 03:12:12,262 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 03:12:12,262 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 03:12:12,263 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 03:12:12,263 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 03:12:12,263 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 03:12:12,263 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 03:12:12,264 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 03:12:12,265 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 03:12:12,265 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 03:12:12,266 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 03:12:12,266 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 03:12:12,266 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 03:12:12,266 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 03:12:12,267 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 03:12:12,267 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 03:12:12,267 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 03:12:12,267 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 03:12:12,276 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 03:12:12,276 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 03:12:12,277 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 03:12:12,277 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 03:12:12,277 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 03:12:12,277 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 03:12:12,278 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 03:12:12,278 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 03:12:12,278 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 03:12:12,280 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 03:12:12,280 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 03:12:12,281 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 03:12:12,284 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 03:12:12,284 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5c6676c90977e408adf03f66d7ae0804453cb34e [2020-11-28 03:12:12,609 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 03:12:12,658 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 03:12:12,664 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 03:12:12,666 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 03:12:12,667 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 03:12:12,668 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2020-11-28 03:12:12,750 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/data/f9b117e0e/06052c8a60b6491d8dbd359c749848c1/FLAGb2b7cfa08 [2020-11-28 03:12:13,280 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 03:12:13,280 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/sv-benchmarks/c/systemc/transmitter.02.cil.c [2020-11-28 03:12:13,312 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/data/f9b117e0e/06052c8a60b6491d8dbd359c749848c1/FLAGb2b7cfa08 [2020-11-28 03:12:13,633 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/data/f9b117e0e/06052c8a60b6491d8dbd359c749848c1 [2020-11-28 03:12:13,636 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 03:12:13,638 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 03:12:13,640 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 03:12:13,640 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 03:12:13,644 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 03:12:13,645 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:12:13" (1/1) ... [2020-11-28 03:12:13,647 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78001495 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:13, skipping insertion in model container [2020-11-28 03:12:13,647 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:12:13" (1/1) ... [2020-11-28 03:12:13,656 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 03:12:13,690 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 03:12:13,906 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:12:13,918 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 03:12:13,973 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 03:12:14,013 INFO L208 MainTranslator]: Completed translation [2020-11-28 03:12:14,015 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14 WrapperNode [2020-11-28 03:12:14,016 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 03:12:14,018 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 03:12:14,019 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 03:12:14,020 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 03:12:14,029 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,051 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,109 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 03:12:14,115 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 03:12:14,116 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 03:12:14,116 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 03:12:14,125 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,126 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,140 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,145 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,154 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,165 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,168 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... [2020-11-28 03:12:14,174 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 03:12:14,175 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 03:12:14,175 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 03:12:14,175 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 03:12:14,176 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 03:12:14,256 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 03:12:14,256 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 03:12:14,256 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 03:12:14,256 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 03:12:15,267 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 03:12:15,269 INFO L298 CfgBuilder]: Removed 96 assume(true) statements. [2020-11-28 03:12:15,273 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:12:15 BoogieIcfgContainer [2020-11-28 03:12:15,273 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 03:12:15,275 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 03:12:15,275 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 03:12:15,279 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 03:12:15,280 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:12:15,280 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:12:13" (1/3) ... [2020-11-28 03:12:15,282 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20a798f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:12:15, skipping insertion in model container [2020-11-28 03:12:15,282 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:12:15,283 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:12:14" (2/3) ... [2020-11-28 03:12:15,283 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20a798f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:12:15, skipping insertion in model container [2020-11-28 03:12:15,283 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 03:12:15,284 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:12:15" (3/3) ... [2020-11-28 03:12:15,286 INFO L373 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2020-11-28 03:12:15,357 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 03:12:15,357 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 03:12:15,358 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 03:12:15,358 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 03:12:15,358 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 03:12:15,358 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 03:12:15,358 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 03:12:15,359 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 03:12:15,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states. [2020-11-28 03:12:15,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2020-11-28 03:12:15,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:15,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:15,438 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,439 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,439 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 03:12:15,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states. [2020-11-28 03:12:15,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2020-11-28 03:12:15,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:15,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:15,454 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,454 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,463 INFO L794 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20#L483true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 162#L206true assume !(1 == ~m_i~0);~m_st~0 := 2; 26#L213-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 82#L218-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 100#L223-1true assume !(0 == ~M_E~0); 29#L326-1true assume !(0 == ~T1_E~0); 67#L331-1true assume !(0 == ~T2_E~0); 116#L336-1true assume !(0 == ~E_1~0); 130#L341-1true assume !(0 == ~E_2~0); 168#L346-1true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 155#L148true assume !(1 == ~m_pc~0); 149#L148-2true is_master_triggered_~__retres1~0 := 0; 183#L159true is_master_triggered_#res := is_master_triggered_~__retres1~0; 106#L160true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53#L397true assume !(0 != activate_threads_~tmp~1); 62#L397-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 176#L167true assume 1 == ~t1_pc~0; 98#L168true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 177#L178true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99#L179true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 101#L405true assume !(0 != activate_threads_~tmp___0~0); 74#L405-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3#L186true assume !(1 == ~t2_pc~0); 14#L186-2true is_transmit2_triggered_~__retres1~2 := 0; 4#L197true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122#L198true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 107#L413true assume !(0 != activate_threads_~tmp___1~0); 110#L413-2true assume !(1 == ~M_E~0); 27#L359-1true assume !(1 == ~T1_E~0); 63#L364-1true assume !(1 == ~T2_E~0); 111#L369-1true assume !(1 == ~E_1~0); 152#L374-1true assume !(1 == ~E_2~0); 134#L520-1true [2020-11-28 03:12:15,464 INFO L796 eck$LassoCheckResult]: Loop: 134#L520-1true assume !false; 39#L521true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 49#L301true assume !true; 159#L316true start_simulation_~kernel_st~0 := 2; 160#L206-1true start_simulation_~kernel_st~0 := 3; 17#L326-2true assume 0 == ~M_E~0;~M_E~0 := 1; 22#L326-4true assume !(0 == ~T1_E~0); 42#L331-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 92#L336-3true assume 0 == ~E_1~0;~E_1~0 := 1; 133#L341-3true assume 0 == ~E_2~0;~E_2~0 := 1; 175#L346-3true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156#L148-9true assume !(1 == ~m_pc~0); 129#L148-11true is_master_triggered_~__retres1~0 := 0; 147#L159-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 61#L160-3true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30#L397-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 31#L397-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154#L167-9true assume !(1 == ~t1_pc~0); 148#L167-11true is_transmit1_triggered_~__retres1~1 := 0; 166#L178-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90#L179-3true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 59#L405-9true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69#L405-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 174#L186-9true assume !(1 == ~t2_pc~0); 167#L186-11true is_transmit2_triggered_~__retres1~2 := 0; 13#L197-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 139#L198-3true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72#L413-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 77#L413-11true assume !(1 == ~M_E~0); 18#L359-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 40#L364-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 88#L369-3true assume 1 == ~E_1~0;~E_1~0 := 2; 132#L374-3true assume 1 == ~E_2~0;~E_2~0 := 2; 172#L379-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 186#L236-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 124#L253-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 34#L254-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 161#L539true assume !(0 == start_simulation_~tmp~3); 164#L539-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 185#L236-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 121#L253-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 32#L254-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 19#L494true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 128#L501true stop_simulation_#res := stop_simulation_~__retres2~0; 35#L502true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 10#L552true assume !(0 != start_simulation_~tmp___0~1); 134#L520-1true [2020-11-28 03:12:15,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:15,471 INFO L82 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2020-11-28 03:12:15,481 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:15,482 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381115674] [2020-11-28 03:12:15,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:15,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:15,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:15,717 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381115674] [2020-11-28 03:12:15,718 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:15,718 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:15,719 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964868076] [2020-11-28 03:12:15,725 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:12:15,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:15,726 INFO L82 PathProgramCache]: Analyzing trace with hash -367765354, now seen corresponding path program 1 times [2020-11-28 03:12:15,726 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:15,726 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807914135] [2020-11-28 03:12:15,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:15,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:15,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:15,748 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807914135] [2020-11-28 03:12:15,749 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:15,749 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:12:15,749 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008799353] [2020-11-28 03:12:15,751 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:15,752 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:15,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:15,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:15,771 INFO L87 Difference]: Start difference. First operand 192 states. Second operand 3 states. [2020-11-28 03:12:15,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:15,818 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2020-11-28 03:12:15,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:15,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2020-11-28 03:12:15,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2020-11-28 03:12:15,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2020-11-28 03:12:15,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2020-11-28 03:12:15,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2020-11-28 03:12:15,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2020-11-28 03:12:15,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:15,854 INFO L691 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2020-11-28 03:12:15,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2020-11-28 03:12:15,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2020-11-28 03:12:15,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2020-11-28 03:12:15,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2020-11-28 03:12:15,919 INFO L714 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2020-11-28 03:12:15,920 INFO L594 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2020-11-28 03:12:15,920 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 03:12:15,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2020-11-28 03:12:15,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2020-11-28 03:12:15,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:15,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:15,930 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,931 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:15,932 INFO L794 eck$LassoCheckResult]: Stem: 563#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 401#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 402#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 424#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 433#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434#L218-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 518#L223-1 assume !(0 == ~M_E~0); 440#L326-1 assume !(0 == ~T1_E~0); 441#L331-1 assume !(0 == ~T2_E~0); 504#L336-1 assume !(0 == ~E_1~0); 559#L341-1 assume !(0 == ~E_2~0); 561#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 573#L148 assume !(1 == ~m_pc~0); 547#L148-2 is_master_triggered_~__retres1~0 := 0; 548#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 549#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 480#L397 assume !(0 != activate_threads_~tmp~1); 481#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 494#L167 assume 1 == ~t1_pc~0; 539#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 540#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 542#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 543#L405 assume !(0 != activate_threads_~tmp___0~0); 510#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 392#L186 assume !(1 == ~t2_pc~0); 393#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 395#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 396#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 551#L413 assume !(0 != activate_threads_~tmp___1~0); 552#L413-2 assume !(1 == ~M_E~0); 435#L359-1 assume !(1 == ~T1_E~0); 436#L364-1 assume !(1 == ~T2_E~0); 495#L369-1 assume !(1 == ~E_1~0); 553#L374-1 assume !(1 == ~E_2~0); 408#L520-1 [2020-11-28 03:12:15,939 INFO L796 eck$LassoCheckResult]: Loop: 408#L520-1 assume !false; 459#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 439#L301 assume !false; 470#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 560#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 476#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 451#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 452#L268 assume !(0 != eval_~tmp~0); 467#L316 start_simulation_~kernel_st~0 := 2; 575#L206-1 start_simulation_~kernel_st~0 := 3; 418#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 419#L326-4 assume !(0 == ~T1_E~0); 426#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 460#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 528#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 564#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 574#L148-9 assume 1 == ~m_pc~0; 490#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 491#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 493#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 442#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 443#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 444#L167-9 assume 1 == ~t1_pc~0; 522#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 523#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 526#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 486#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 487#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 503#L186-9 assume 1 == ~t2_pc~0; 567#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 413#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 414#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 508#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 509#L413-11 assume !(1 == ~M_E~0); 420#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 421#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 456#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 525#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 562#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 577#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 473#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 448#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 449#L539 assume !(0 == start_simulation_~tmp~3); 432#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 576#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 516#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 445#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 422#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 423#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 450#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 407#L552 assume !(0 != start_simulation_~tmp___0~1); 408#L520-1 [2020-11-28 03:12:15,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:15,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2020-11-28 03:12:15,941 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:15,941 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719295826] [2020-11-28 03:12:15,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:15,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:16,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:16,020 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719295826] [2020-11-28 03:12:16,020 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:16,021 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:16,021 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636451498] [2020-11-28 03:12:16,021 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:12:16,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:16,022 INFO L82 PathProgramCache]: Analyzing trace with hash -174617607, now seen corresponding path program 1 times [2020-11-28 03:12:16,022 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:16,023 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554007729] [2020-11-28 03:12:16,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:16,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:16,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:16,133 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554007729] [2020-11-28 03:12:16,134 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:16,134 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:16,135 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028325220] [2020-11-28 03:12:16,137 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:16,139 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:16,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:16,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:16,141 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand 3 states. [2020-11-28 03:12:16,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:16,182 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2020-11-28 03:12:16,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:16,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2020-11-28 03:12:16,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2020-11-28 03:12:16,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2020-11-28 03:12:16,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2020-11-28 03:12:16,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2020-11-28 03:12:16,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2020-11-28 03:12:16,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:16,201 INFO L691 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2020-11-28 03:12:16,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2020-11-28 03:12:16,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2020-11-28 03:12:16,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2020-11-28 03:12:16,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2020-11-28 03:12:16,210 INFO L714 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2020-11-28 03:12:16,210 INFO L594 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2020-11-28 03:12:16,210 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 03:12:16,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2020-11-28 03:12:16,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2020-11-28 03:12:16,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:16,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:16,216 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:16,216 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:16,216 INFO L794 eck$LassoCheckResult]: Stem: 941#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 780#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 781#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 803#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 812#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 813#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 897#L223-1 assume !(0 == ~M_E~0); 819#L326-1 assume !(0 == ~T1_E~0); 820#L331-1 assume !(0 == ~T2_E~0); 881#L336-1 assume !(0 == ~E_1~0); 935#L341-1 assume !(0 == ~E_2~0); 940#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 952#L148 assume !(1 == ~m_pc~0); 926#L148-2 is_master_triggered_~__retres1~0 := 0; 927#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 928#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 857#L397 assume !(0 != activate_threads_~tmp~1); 858#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 873#L167 assume 1 == ~t1_pc~0; 918#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 919#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 921#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 922#L405 assume !(0 != activate_threads_~tmp___0~0); 889#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 771#L186 assume !(1 == ~t2_pc~0); 772#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 774#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 775#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 929#L413 assume !(0 != activate_threads_~tmp___1~0); 930#L413-2 assume !(1 == ~M_E~0); 814#L359-1 assume !(1 == ~T1_E~0); 815#L364-1 assume !(1 == ~T2_E~0); 874#L369-1 assume !(1 == ~E_1~0); 932#L374-1 assume !(1 == ~E_2~0); 787#L520-1 [2020-11-28 03:12:16,216 INFO L796 eck$LassoCheckResult]: Loop: 787#L520-1 assume !false; 835#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 818#L301 assume !false; 849#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 939#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 855#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 830#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 831#L268 assume !(0 != eval_~tmp~0); 843#L316 start_simulation_~kernel_st~0 := 2; 954#L206-1 start_simulation_~kernel_st~0 := 3; 797#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 798#L326-4 assume !(0 == ~T1_E~0); 805#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 840#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 907#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 943#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 953#L148-9 assume 1 == ~m_pc~0; 869#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 870#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 872#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 821#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 822#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 823#L167-9 assume 1 == ~t1_pc~0; 901#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 902#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 905#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 867#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 868#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 883#L186-9 assume 1 == ~t2_pc~0; 946#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 792#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 793#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 887#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 888#L413-11 assume !(1 == ~M_E~0); 799#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 800#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 836#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 904#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 942#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 956#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 852#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 827#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 828#L539 assume !(0 == start_simulation_~tmp~3); 811#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 955#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 895#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 824#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 801#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 802#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 829#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 786#L552 assume !(0 != start_simulation_~tmp___0~1); 787#L520-1 [2020-11-28 03:12:16,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:16,217 INFO L82 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2020-11-28 03:12:16,217 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:16,218 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817482855] [2020-11-28 03:12:16,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:16,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:16,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:16,320 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817482855] [2020-11-28 03:12:16,320 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:16,320 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:16,320 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962543118] [2020-11-28 03:12:16,321 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:12:16,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:16,321 INFO L82 PathProgramCache]: Analyzing trace with hash -174617607, now seen corresponding path program 2 times [2020-11-28 03:12:16,322 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:16,322 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574958375] [2020-11-28 03:12:16,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:16,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:16,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:16,426 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574958375] [2020-11-28 03:12:16,427 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:16,427 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:16,427 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167355391] [2020-11-28 03:12:16,427 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:16,428 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:16,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 03:12:16,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 03:12:16,429 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand 4 states. [2020-11-28 03:12:16,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:16,763 INFO L93 Difference]: Finished difference Result 441 states and 644 transitions. [2020-11-28 03:12:16,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 03:12:16,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 644 transitions. [2020-11-28 03:12:16,769 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 377 [2020-11-28 03:12:16,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 441 states and 644 transitions. [2020-11-28 03:12:16,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 [2020-11-28 03:12:16,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 [2020-11-28 03:12:16,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 441 states and 644 transitions. [2020-11-28 03:12:16,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:16,778 INFO L691 BuchiCegarLoop]: Abstraction has 441 states and 644 transitions. [2020-11-28 03:12:16,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states and 644 transitions. [2020-11-28 03:12:16,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 403. [2020-11-28 03:12:16,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 403 states. [2020-11-28 03:12:16,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 596 transitions. [2020-11-28 03:12:16,799 INFO L714 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2020-11-28 03:12:16,800 INFO L594 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2020-11-28 03:12:16,800 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 03:12:16,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 596 transitions. [2020-11-28 03:12:16,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2020-11-28 03:12:16,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:16,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:16,816 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:16,816 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:16,816 INFO L794 eck$LassoCheckResult]: Stem: 1577#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1417#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1418#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1440#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 1449#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1450#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1538#L223-1 assume !(0 == ~M_E~0); 1456#L326-1 assume !(0 == ~T1_E~0); 1457#L331-1 assume !(0 == ~T2_E~0); 1524#L336-1 assume !(0 == ~E_1~0); 1573#L341-1 assume !(0 == ~E_2~0); 1575#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1593#L148 assume !(1 == ~m_pc~0); 1589#L148-2 is_master_triggered_~__retres1~0 := 0; 1590#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1563#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1499#L397 assume !(0 != activate_threads_~tmp~1); 1500#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1514#L167 assume !(1 == ~t1_pc~0); 1599#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 1600#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1559#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1560#L405 assume !(0 != activate_threads_~tmp___0~0); 1530#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1408#L186 assume !(1 == ~t2_pc~0); 1409#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 1411#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1412#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1565#L413 assume !(0 != activate_threads_~tmp___1~0); 1566#L413-2 assume !(1 == ~M_E~0); 1451#L359-1 assume !(1 == ~T1_E~0); 1452#L364-1 assume !(1 == ~T2_E~0); 1515#L369-1 assume !(1 == ~E_1~0); 1567#L374-1 assume !(1 == ~E_2~0); 1592#L520-1 [2020-11-28 03:12:16,818 INFO L796 eck$LassoCheckResult]: Loop: 1592#L520-1 assume !false; 1716#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1713#L301 assume !false; 1710#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1705#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1701#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1698#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1481#L268 assume !(0 != eval_~tmp~0); 1482#L316 start_simulation_~kernel_st~0 := 2; 1595#L206-1 start_simulation_~kernel_st~0 := 3; 1434#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1435#L326-4 assume !(0 == ~T1_E~0); 1442#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1477#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1548#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1578#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1797#L148-9 assume !(1 == ~m_pc~0); 1796#L148-11 is_master_triggered_~__retres1~0 := 0; 1795#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1794#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1793#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1792#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1790#L167-9 assume !(1 == ~t1_pc~0); 1788#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 1786#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1784#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1782#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1780#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1778#L186-9 assume 1 == ~t2_pc~0; 1776#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1773#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1771#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1769#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1767#L413-11 assume !(1 == ~M_E~0); 1765#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1762#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1760#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1758#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1756#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1754#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1750#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1748#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1745#L539 assume !(0 == start_simulation_~tmp~3); 1743#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1742#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1739#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1737#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1735#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1733#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 1731#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1728#L552 assume !(0 != start_simulation_~tmp___0~1); 1592#L520-1 [2020-11-28 03:12:16,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:16,819 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2020-11-28 03:12:16,819 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:16,819 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794909666] [2020-11-28 03:12:16,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:16,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:16,854 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:16,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:16,888 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:16,930 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:16,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:16,931 INFO L82 PathProgramCache]: Analyzing trace with hash -94843205, now seen corresponding path program 1 times [2020-11-28 03:12:16,931 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:16,931 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731469014] [2020-11-28 03:12:16,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:16,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:16,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:16,968 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731469014] [2020-11-28 03:12:16,969 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:16,969 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:16,969 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080481803] [2020-11-28 03:12:16,969 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:16,970 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:16,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:16,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:16,971 INFO L87 Difference]: Start difference. First operand 403 states and 596 transitions. cyclomatic complexity: 195 Second operand 3 states. [2020-11-28 03:12:17,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:17,059 INFO L93 Difference]: Finished difference Result 625 states and 904 transitions. [2020-11-28 03:12:17,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:17,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 625 states and 904 transitions. [2020-11-28 03:12:17,067 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 561 [2020-11-28 03:12:17,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 625 states to 625 states and 904 transitions. [2020-11-28 03:12:17,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 625 [2020-11-28 03:12:17,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 625 [2020-11-28 03:12:17,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 625 states and 904 transitions. [2020-11-28 03:12:17,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:17,078 INFO L691 BuchiCegarLoop]: Abstraction has 625 states and 904 transitions. [2020-11-28 03:12:17,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 625 states and 904 transitions. [2020-11-28 03:12:17,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 625 to 625. [2020-11-28 03:12:17,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2020-11-28 03:12:17,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 904 transitions. [2020-11-28 03:12:17,101 INFO L714 BuchiCegarLoop]: Abstraction has 625 states and 904 transitions. [2020-11-28 03:12:17,101 INFO L594 BuchiCegarLoop]: Abstraction has 625 states and 904 transitions. [2020-11-28 03:12:17,101 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 03:12:17,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 625 states and 904 transitions. [2020-11-28 03:12:17,107 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 561 [2020-11-28 03:12:17,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:17,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:17,108 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,109 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,109 INFO L794 eck$LassoCheckResult]: Stem: 2616#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2451#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2452#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2474#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 2484#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2485#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2571#L223-1 assume 0 == ~M_E~0;~M_E~0 := 1; 2491#L326-1 assume !(0 == ~T1_E~0); 2492#L331-1 assume !(0 == ~T2_E~0); 2558#L336-1 assume !(0 == ~E_1~0); 2607#L341-1 assume !(0 == ~E_2~0); 2614#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2635#L148 assume !(1 == ~m_pc~0); 2628#L148-2 is_master_triggered_~__retres1~0 := 0; 2629#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2597#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2534#L397 assume !(0 != activate_threads_~tmp~1); 2535#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2549#L167 assume !(1 == ~t1_pc~0); 2646#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 2647#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2592#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2593#L405 assume !(0 != activate_threads_~tmp___0~0); 2563#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2442#L186 assume !(1 == ~t2_pc~0); 2443#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 2445#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2446#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2599#L413 assume !(0 != activate_threads_~tmp___1~0); 2600#L413-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2486#L359-1 assume !(1 == ~T1_E~0); 2487#L364-1 assume !(1 == ~T2_E~0); 2550#L369-1 assume !(1 == ~E_1~0); 2601#L374-1 assume !(1 == ~E_2~0); 2634#L520-1 [2020-11-28 03:12:17,109 INFO L796 eck$LassoCheckResult]: Loop: 2634#L520-1 assume !false; 2961#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2958#L301 assume !false; 2955#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2951#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2947#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2944#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2940#L268 assume !(0 != eval_~tmp~0); 2938#L316 start_simulation_~kernel_st~0 := 2; 2936#L206-1 start_simulation_~kernel_st~0 := 3; 2934#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2933#L326-4 assume !(0 == ~T1_E~0); 2932#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2931#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2927#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2925#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2923#L148-9 assume !(1 == ~m_pc~0); 2919#L148-11 is_master_triggered_~__retres1~0 := 0; 2916#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2912#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2908#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2907#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2906#L167-9 assume !(1 == ~t1_pc~0); 2904#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 2902#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2900#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2899#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2897#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2895#L186-9 assume !(1 == ~t2_pc~0); 2891#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 2890#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2888#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2886#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2884#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2881#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2879#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2871#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2867#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2649#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2650#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2527#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2500#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2501#L539 assume !(0 == start_simulation_~tmp~3); 2483#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3016#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2995#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2496#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2497#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2978#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 2977#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2975#L552 assume !(0 != start_simulation_~tmp___0~1); 2634#L520-1 [2020-11-28 03:12:17,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1361644639, now seen corresponding path program 1 times [2020-11-28 03:12:17,110 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,110 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600091965] [2020-11-28 03:12:17,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:17,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:17,147 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600091965] [2020-11-28 03:12:17,147 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:17,147 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:12:17,148 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016296416] [2020-11-28 03:12:17,148 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:12:17,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1615684866, now seen corresponding path program 1 times [2020-11-28 03:12:17,149 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,149 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742092229] [2020-11-28 03:12:17,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:17,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:17,206 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742092229] [2020-11-28 03:12:17,206 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:17,206 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:12:17,206 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523541653] [2020-11-28 03:12:17,207 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:17,207 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:17,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:17,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:17,208 INFO L87 Difference]: Start difference. First operand 625 states and 904 transitions. cyclomatic complexity: 281 Second operand 3 states. [2020-11-28 03:12:17,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:17,255 INFO L93 Difference]: Finished difference Result 403 states and 578 transitions. [2020-11-28 03:12:17,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:17,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 403 states and 578 transitions. [2020-11-28 03:12:17,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2020-11-28 03:12:17,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 403 states to 403 states and 578 transitions. [2020-11-28 03:12:17,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 403 [2020-11-28 03:12:17,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 403 [2020-11-28 03:12:17,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 403 states and 578 transitions. [2020-11-28 03:12:17,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:17,268 INFO L691 BuchiCegarLoop]: Abstraction has 403 states and 578 transitions. [2020-11-28 03:12:17,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 403 states and 578 transitions. [2020-11-28 03:12:17,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 403 to 403. [2020-11-28 03:12:17,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 403 states. [2020-11-28 03:12:17,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 578 transitions. [2020-11-28 03:12:17,280 INFO L714 BuchiCegarLoop]: Abstraction has 403 states and 578 transitions. [2020-11-28 03:12:17,280 INFO L594 BuchiCegarLoop]: Abstraction has 403 states and 578 transitions. [2020-11-28 03:12:17,280 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 03:12:17,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 578 transitions. [2020-11-28 03:12:17,283 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2020-11-28 03:12:17,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:17,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:17,285 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,285 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,285 INFO L794 eck$LassoCheckResult]: Stem: 3648#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3488#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3489#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3511#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 3520#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3521#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3604#L223-1 assume !(0 == ~M_E~0); 3527#L326-1 assume !(0 == ~T1_E~0); 3528#L331-1 assume !(0 == ~T2_E~0); 3587#L336-1 assume !(0 == ~E_1~0); 3636#L341-1 assume !(0 == ~E_2~0); 3647#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3673#L148 assume !(1 == ~m_pc~0); 3666#L148-2 is_master_triggered_~__retres1~0 := 0; 3667#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3629#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3566#L397 assume !(0 != activate_threads_~tmp~1); 3567#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3580#L167 assume !(1 == ~t1_pc~0); 3678#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 3679#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3625#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3626#L405 assume !(0 != activate_threads_~tmp___0~0); 3596#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3479#L186 assume !(1 == ~t2_pc~0); 3480#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 3482#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3483#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3630#L413 assume !(0 != activate_threads_~tmp___1~0); 3631#L413-2 assume !(1 == ~M_E~0); 3522#L359-1 assume !(1 == ~T1_E~0); 3523#L364-1 assume !(1 == ~T2_E~0); 3581#L369-1 assume !(1 == ~E_1~0); 3633#L374-1 assume !(1 == ~E_2~0); 3672#L520-1 [2020-11-28 03:12:17,286 INFO L796 eck$LassoCheckResult]: Loop: 3672#L520-1 assume !false; 3780#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3778#L301 assume !false; 3776#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3771#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3769#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3767#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3765#L268 assume !(0 != eval_~tmp~0); 3675#L316 start_simulation_~kernel_st~0 := 2; 3676#L206-1 start_simulation_~kernel_st~0 := 3; 3505#L326-2 assume !(0 == ~M_E~0); 3506#L326-4 assume !(0 == ~T1_E~0); 3513#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3548#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3614#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3650#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3674#L148-9 assume !(1 == ~m_pc~0); 3645#L148-11 is_master_triggered_~__retres1~0 := 0; 3646#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3579#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3529#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3530#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3531#L167-9 assume !(1 == ~t1_pc~0); 3664#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 3665#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3612#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3575#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3576#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3589#L186-9 assume 1 == ~t2_pc~0; 3655#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3500#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3501#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3592#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3593#L413-11 assume !(1 == ~M_E~0); 3507#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3508#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3544#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3611#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3649#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3680#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3561#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3642#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3807#L539 assume !(0 == start_simulation_~tmp~3); 3804#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3802#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3798#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3796#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3794#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3792#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 3790#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3788#L552 assume !(0 != start_simulation_~tmp___0~1); 3672#L520-1 [2020-11-28 03:12:17,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,287 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2020-11-28 03:12:17,287 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,287 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650324149] [2020-11-28 03:12:17,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,302 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,319 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,337 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:17,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,340 INFO L82 PathProgramCache]: Analyzing trace with hash 328803517, now seen corresponding path program 1 times [2020-11-28 03:12:17,341 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,341 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272110953] [2020-11-28 03:12:17,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:17,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:17,412 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272110953] [2020-11-28 03:12:17,413 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:17,413 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:12:17,413 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478702308] [2020-11-28 03:12:17,414 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:17,414 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:17,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:12:17,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:12:17,415 INFO L87 Difference]: Start difference. First operand 403 states and 578 transitions. cyclomatic complexity: 177 Second operand 5 states. [2020-11-28 03:12:17,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:17,557 INFO L93 Difference]: Finished difference Result 672 states and 944 transitions. [2020-11-28 03:12:17,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 03:12:17,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 672 states and 944 transitions. [2020-11-28 03:12:17,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 627 [2020-11-28 03:12:17,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 672 states to 672 states and 944 transitions. [2020-11-28 03:12:17,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 672 [2020-11-28 03:12:17,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 672 [2020-11-28 03:12:17,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 672 states and 944 transitions. [2020-11-28 03:12:17,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:17,573 INFO L691 BuchiCegarLoop]: Abstraction has 672 states and 944 transitions. [2020-11-28 03:12:17,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 672 states and 944 transitions. [2020-11-28 03:12:17,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 672 to 412. [2020-11-28 03:12:17,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 412 states. [2020-11-28 03:12:17,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 412 states to 412 states and 587 transitions. [2020-11-28 03:12:17,590 INFO L714 BuchiCegarLoop]: Abstraction has 412 states and 587 transitions. [2020-11-28 03:12:17,601 INFO L594 BuchiCegarLoop]: Abstraction has 412 states and 587 transitions. [2020-11-28 03:12:17,601 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 03:12:17,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 412 states and 587 transitions. [2020-11-28 03:12:17,604 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 372 [2020-11-28 03:12:17,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:17,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:17,605 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,605 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,605 INFO L794 eck$LassoCheckResult]: Stem: 4753#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4579#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4580#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4602#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 4612#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4613#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4703#L223-1 assume !(0 == ~M_E~0); 4619#L326-1 assume !(0 == ~T1_E~0); 4620#L331-1 assume !(0 == ~T2_E~0); 4689#L336-1 assume !(0 == ~E_1~0); 4741#L341-1 assume !(0 == ~E_2~0); 4751#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4778#L148 assume !(1 == ~m_pc~0); 4772#L148-2 is_master_triggered_~__retres1~0 := 0; 4773#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4730#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4664#L397 assume !(0 != activate_threads_~tmp~1); 4665#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4679#L167 assume !(1 == ~t1_pc~0); 4788#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 4789#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4726#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4727#L405 assume !(0 != activate_threads_~tmp___0~0); 4694#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4570#L186 assume !(1 == ~t2_pc~0); 4571#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 4573#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4574#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4732#L413 assume !(0 != activate_threads_~tmp___1~0); 4733#L413-2 assume !(1 == ~M_E~0); 4614#L359-1 assume !(1 == ~T1_E~0); 4615#L364-1 assume !(1 == ~T2_E~0); 4680#L369-1 assume !(1 == ~E_1~0); 4734#L374-1 assume !(1 == ~E_2~0); 4756#L520-1 [2020-11-28 03:12:17,606 INFO L796 eck$LassoCheckResult]: Loop: 4756#L520-1 assume !false; 4640#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4618#L301 assume !false; 4654#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4854#L236 assume !(0 == ~m_st~0); 4848#L240 assume !(0 == ~t1_st~0); 4844#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4841#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4837#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4819#L268 assume !(0 != eval_~tmp~0); 4820#L316 start_simulation_~kernel_st~0 := 2; 4782#L206-1 start_simulation_~kernel_st~0 := 3; 4598#L326-2 assume !(0 == ~M_E~0); 4599#L326-4 assume !(0 == ~T1_E~0); 4643#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4644#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4715#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4795#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4779#L148-9 assume !(1 == ~m_pc~0); 4749#L148-11 is_master_triggered_~__retres1~0 := 0; 4750#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4677#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4678#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4623#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4624#L167-9 assume !(1 == ~t1_pc~0); 4770#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 4771#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4711#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4712#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4686#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4687#L186-9 assume 1 == ~t2_pc~0; 4760#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4591#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4592#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4692#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4693#L413-11 assume !(1 == ~M_E~0); 4596#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4597#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4639#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4710#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4752#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4790#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4657#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4629#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4630#L539 assume !(0 == start_simulation_~tmp~3); 4903#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4797#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4701#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4964#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4600#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4601#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 4748#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4962#L552 assume !(0 != start_simulation_~tmp___0~1); 4756#L520-1 [2020-11-28 03:12:17,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,606 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2020-11-28 03:12:17,606 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,606 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554057659] [2020-11-28 03:12:17,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,615 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,628 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,634 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:17,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,635 INFO L82 PathProgramCache]: Analyzing trace with hash -123149436, now seen corresponding path program 1 times [2020-11-28 03:12:17,635 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,636 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162889509] [2020-11-28 03:12:17,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:17,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:17,729 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162889509] [2020-11-28 03:12:17,729 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:17,731 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 03:12:17,732 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323016518] [2020-11-28 03:12:17,733 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:17,733 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:17,734 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 03:12:17,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 03:12:17,736 INFO L87 Difference]: Start difference. First operand 412 states and 587 transitions. cyclomatic complexity: 177 Second operand 5 states. [2020-11-28 03:12:17,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:17,901 INFO L93 Difference]: Finished difference Result 694 states and 987 transitions. [2020-11-28 03:12:17,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 03:12:17,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 987 transitions. [2020-11-28 03:12:17,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2020-11-28 03:12:17,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 987 transitions. [2020-11-28 03:12:17,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2020-11-28 03:12:17,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2020-11-28 03:12:17,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 987 transitions. [2020-11-28 03:12:17,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:17,921 INFO L691 BuchiCegarLoop]: Abstraction has 694 states and 987 transitions. [2020-11-28 03:12:17,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 987 transitions. [2020-11-28 03:12:17,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 418. [2020-11-28 03:12:17,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2020-11-28 03:12:17,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 585 transitions. [2020-11-28 03:12:17,937 INFO L714 BuchiCegarLoop]: Abstraction has 418 states and 585 transitions. [2020-11-28 03:12:17,938 INFO L594 BuchiCegarLoop]: Abstraction has 418 states and 585 transitions. [2020-11-28 03:12:17,938 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 03:12:17,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 418 states and 585 transitions. [2020-11-28 03:12:17,941 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 378 [2020-11-28 03:12:17,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:17,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:17,945 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,945 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:17,946 INFO L794 eck$LassoCheckResult]: Stem: 5881#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5698#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5699#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5723#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 5732#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5733#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5823#L223-1 assume !(0 == ~M_E~0); 5739#L326-1 assume !(0 == ~T1_E~0); 5740#L331-1 assume !(0 == ~T2_E~0); 5805#L336-1 assume !(0 == ~E_1~0); 5862#L341-1 assume !(0 == ~E_2~0); 5878#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5904#L148 assume !(1 == ~m_pc~0); 5898#L148-2 is_master_triggered_~__retres1~0 := 0; 5899#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5851#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5782#L397 assume !(0 != activate_threads_~tmp~1); 5783#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5795#L167 assume !(1 == ~t1_pc~0); 5913#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 5914#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5847#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5848#L405 assume !(0 != activate_threads_~tmp___0~0); 5811#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5689#L186 assume !(1 == ~t2_pc~0); 5690#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 5692#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5693#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5853#L413 assume !(0 != activate_threads_~tmp___1~0); 5854#L413-2 assume !(1 == ~M_E~0); 5734#L359-1 assume !(1 == ~T1_E~0); 5735#L364-1 assume !(1 == ~T2_E~0); 5796#L369-1 assume !(1 == ~E_1~0); 5855#L374-1 assume !(1 == ~E_2~0); 5903#L520-1 [2020-11-28 03:12:17,946 INFO L796 eck$LassoCheckResult]: Loop: 5903#L520-1 assume !false; 5963#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5962#L301 assume !false; 5961#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5960#L236 assume !(0 == ~m_st~0); 5959#L240 assume !(0 == ~t1_st~0); 5957#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 5956#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5955#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5953#L268 assume !(0 != eval_~tmp~0); 5952#L316 start_simulation_~kernel_st~0 := 2; 5951#L206-1 start_simulation_~kernel_st~0 := 3; 5950#L326-2 assume !(0 == ~M_E~0); 5949#L326-4 assume !(0 == ~T1_E~0); 5947#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5945#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5942#L341-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5940#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5905#L148-9 assume !(1 == ~m_pc~0); 5906#L148-11 is_master_triggered_~__retres1~0 := 0; 6040#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6039#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6038#L397-9 assume !(0 != activate_threads_~tmp~1); 6037#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6035#L167-9 assume !(1 == ~t1_pc~0); 6033#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 6031#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6029#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6027#L405-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6025#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6023#L186-9 assume !(1 == ~t2_pc~0); 6020#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 6018#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6016#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6014#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6012#L413-11 assume !(1 == ~M_E~0); 6010#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6007#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6005#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6003#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6001#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5999#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5995#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5992#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5988#L539 assume !(0 == start_simulation_~tmp~3); 5985#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5984#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5980#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5978#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 5975#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5972#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 5971#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5969#L552 assume !(0 != start_simulation_~tmp___0~1); 5903#L520-1 [2020-11-28 03:12:17,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:17,947 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2020-11-28 03:12:17,947 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:17,947 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583295365] [2020-11-28 03:12:17,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:17,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,965 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:17,975 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:17,998 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,002 INFO L82 PathProgramCache]: Analyzing trace with hash 1358431367, now seen corresponding path program 1 times [2020-11-28 03:12:18,002 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,002 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394380959] [2020-11-28 03:12:18,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:18,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:18,049 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394380959] [2020-11-28 03:12:18,049 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:18,049 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:18,049 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53119597] [2020-11-28 03:12:18,050 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 03:12:18,050 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:18,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:18,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:18,051 INFO L87 Difference]: Start difference. First operand 418 states and 585 transitions. cyclomatic complexity: 169 Second operand 3 states. [2020-11-28 03:12:18,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:18,104 INFO L93 Difference]: Finished difference Result 550 states and 758 transitions. [2020-11-28 03:12:18,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:18,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 550 states and 758 transitions. [2020-11-28 03:12:18,110 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 508 [2020-11-28 03:12:18,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 550 states to 550 states and 758 transitions. [2020-11-28 03:12:18,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 550 [2020-11-28 03:12:18,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 550 [2020-11-28 03:12:18,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 550 states and 758 transitions. [2020-11-28 03:12:18,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:18,119 INFO L691 BuchiCegarLoop]: Abstraction has 550 states and 758 transitions. [2020-11-28 03:12:18,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states and 758 transitions. [2020-11-28 03:12:18,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 550. [2020-11-28 03:12:18,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2020-11-28 03:12:18,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 758 transitions. [2020-11-28 03:12:18,134 INFO L714 BuchiCegarLoop]: Abstraction has 550 states and 758 transitions. [2020-11-28 03:12:18,134 INFO L594 BuchiCegarLoop]: Abstraction has 550 states and 758 transitions. [2020-11-28 03:12:18,135 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 03:12:18,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 550 states and 758 transitions. [2020-11-28 03:12:18,139 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 508 [2020-11-28 03:12:18,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:18,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:18,140 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,140 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,140 INFO L794 eck$LassoCheckResult]: Stem: 6836#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6672#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6673#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6695#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 6705#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6706#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6790#L223-1 assume !(0 == ~M_E~0); 6712#L326-1 assume !(0 == ~T1_E~0); 6713#L331-1 assume !(0 == ~T2_E~0); 6776#L336-1 assume !(0 == ~E_1~0); 6828#L341-1 assume !(0 == ~E_2~0); 6834#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6856#L148 assume !(1 == ~m_pc~0); 6850#L148-2 is_master_triggered_~__retres1~0 := 0; 6851#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6818#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6753#L397 assume !(0 != activate_threads_~tmp~1); 6754#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6766#L167 assume !(1 == ~t1_pc~0); 6863#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 6864#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6813#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6814#L405 assume !(0 != activate_threads_~tmp___0~0); 6781#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6663#L186 assume !(1 == ~t2_pc~0); 6664#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 6666#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6667#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6820#L413 assume !(0 != activate_threads_~tmp___1~0); 6821#L413-2 assume !(1 == ~M_E~0); 6707#L359-1 assume !(1 == ~T1_E~0); 6708#L364-1 assume !(1 == ~T2_E~0); 6765#L369-1 assume !(1 == ~E_1~0); 6822#L374-1 assume !(1 == ~E_2~0); 6854#L520-1 assume !false; 6951#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6949#L301 [2020-11-28 03:12:18,141 INFO L796 eck$LassoCheckResult]: Loop: 6949#L301 assume !false; 6947#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6944#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6942#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6940#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6939#L268 assume 0 != eval_~tmp~0; 6937#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 6725#L276 assume !(0 != eval_~tmp_ndt_1~0); 6727#L273 assume !(0 == ~t1_st~0); 6954#L287 assume !(0 == ~t2_st~0); 6949#L301 [2020-11-28 03:12:18,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,141 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2020-11-28 03:12:18,142 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,142 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637584596] [2020-11-28 03:12:18,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,159 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,176 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,189 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,190 INFO L82 PathProgramCache]: Analyzing trace with hash -1206180397, now seen corresponding path program 1 times [2020-11-28 03:12:18,190 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,190 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446749210] [2020-11-28 03:12:18,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,194 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,213 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,217 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,222 INFO L82 PathProgramCache]: Analyzing trace with hash 202160339, now seen corresponding path program 1 times [2020-11-28 03:12:18,223 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,223 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449698980] [2020-11-28 03:12:18,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:18,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:18,276 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449698980] [2020-11-28 03:12:18,276 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:18,276 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:18,276 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431315671] [2020-11-28 03:12:18,380 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:18,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:18,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:18,380 INFO L87 Difference]: Start difference. First operand 550 states and 758 transitions. cyclomatic complexity: 211 Second operand 3 states. [2020-11-28 03:12:18,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:18,450 INFO L93 Difference]: Finished difference Result 975 states and 1324 transitions. [2020-11-28 03:12:18,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:18,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 975 states and 1324 transitions. [2020-11-28 03:12:18,461 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 843 [2020-11-28 03:12:18,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 975 states to 975 states and 1324 transitions. [2020-11-28 03:12:18,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 975 [2020-11-28 03:12:18,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 975 [2020-11-28 03:12:18,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 975 states and 1324 transitions. [2020-11-28 03:12:18,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:18,475 INFO L691 BuchiCegarLoop]: Abstraction has 975 states and 1324 transitions. [2020-11-28 03:12:18,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 975 states and 1324 transitions. [2020-11-28 03:12:18,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 975 to 906. [2020-11-28 03:12:18,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2020-11-28 03:12:18,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1236 transitions. [2020-11-28 03:12:18,498 INFO L714 BuchiCegarLoop]: Abstraction has 906 states and 1236 transitions. [2020-11-28 03:12:18,498 INFO L594 BuchiCegarLoop]: Abstraction has 906 states and 1236 transitions. [2020-11-28 03:12:18,498 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 03:12:18,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 906 states and 1236 transitions. [2020-11-28 03:12:18,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 807 [2020-11-28 03:12:18,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:18,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:18,506 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,506 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,506 INFO L794 eck$LassoCheckResult]: Stem: 8373#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8205#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8206#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8228#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 8237#L213-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8238#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9013#L223-1 assume !(0 == ~M_E~0); 9012#L326-1 assume !(0 == ~T1_E~0); 9011#L331-1 assume !(0 == ~T2_E~0); 9010#L336-1 assume !(0 == ~E_1~0); 9009#L341-1 assume !(0 == ~E_2~0); 9008#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8395#L148 assume !(1 == ~m_pc~0); 8389#L148-2 is_master_triggered_~__retres1~0 := 0; 8390#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8353#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8283#L397 assume !(0 != activate_threads_~tmp~1); 8284#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8298#L167 assume !(1 == ~t1_pc~0); 8408#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 8409#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8348#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8349#L405 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8350#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8985#L186 assume !(1 == ~t2_pc~0); 8983#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 8982#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8366#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8354#L413 assume !(0 != activate_threads_~tmp___1~0); 8355#L413-2 assume !(1 == ~M_E~0); 8240#L359-1 assume !(1 == ~T1_E~0); 8241#L364-1 assume !(1 == ~T2_E~0); 8299#L369-1 assume !(1 == ~E_1~0); 8358#L374-1 assume !(1 == ~E_2~0); 8394#L520-1 assume !false; 9000#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 8998#L301 [2020-11-28 03:12:18,506 INFO L796 eck$LassoCheckResult]: Loop: 8998#L301 assume !false; 8996#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8994#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 8992#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8990#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8988#L268 assume 0 != eval_~tmp~0; 8942#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 8258#L276 assume !(0 != eval_~tmp_ndt_1~0); 8260#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 8274#L290 assume !(0 != eval_~tmp_ndt_2~0); 8275#L287 assume !(0 == ~t2_st~0); 8998#L301 [2020-11-28 03:12:18,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,507 INFO L82 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2020-11-28 03:12:18,507 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,507 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411536043] [2020-11-28 03:12:18,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:18,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:18,538 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411536043] [2020-11-28 03:12:18,539 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:18,539 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 03:12:18,539 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664001919] [2020-11-28 03:12:18,539 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 03:12:18,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010543, now seen corresponding path program 1 times [2020-11-28 03:12:18,540 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,540 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854966468] [2020-11-28 03:12:18,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,544 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,547 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,550 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,647 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:18,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:18,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:18,648 INFO L87 Difference]: Start difference. First operand 906 states and 1236 transitions. cyclomatic complexity: 334 Second operand 3 states. [2020-11-28 03:12:18,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:18,660 INFO L93 Difference]: Finished difference Result 741 states and 1009 transitions. [2020-11-28 03:12:18,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:18,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 741 states and 1009 transitions. [2020-11-28 03:12:18,667 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 699 [2020-11-28 03:12:18,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 741 states to 741 states and 1009 transitions. [2020-11-28 03:12:18,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 741 [2020-11-28 03:12:18,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 741 [2020-11-28 03:12:18,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 741 states and 1009 transitions. [2020-11-28 03:12:18,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:18,679 INFO L691 BuchiCegarLoop]: Abstraction has 741 states and 1009 transitions. [2020-11-28 03:12:18,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 741 states and 1009 transitions. [2020-11-28 03:12:18,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 741 to 741. [2020-11-28 03:12:18,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 741 states. [2020-11-28 03:12:18,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 741 states to 741 states and 1009 transitions. [2020-11-28 03:12:18,697 INFO L714 BuchiCegarLoop]: Abstraction has 741 states and 1009 transitions. [2020-11-28 03:12:18,697 INFO L594 BuchiCegarLoop]: Abstraction has 741 states and 1009 transitions. [2020-11-28 03:12:18,697 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 03:12:18,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 741 states and 1009 transitions. [2020-11-28 03:12:18,702 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 699 [2020-11-28 03:12:18,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:18,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:18,708 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,708 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:18,708 INFO L794 eck$LassoCheckResult]: Stem: 10029#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 9858#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9859#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9881#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 9891#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9892#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9978#L223-1 assume !(0 == ~M_E~0); 9898#L326-1 assume !(0 == ~T1_E~0); 9899#L331-1 assume !(0 == ~T2_E~0); 9962#L336-1 assume !(0 == ~E_1~0); 10017#L341-1 assume !(0 == ~E_2~0); 10027#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10055#L148 assume !(1 == ~m_pc~0); 10047#L148-2 is_master_triggered_~__retres1~0 := 0; 10048#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10005#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9940#L397 assume !(0 != activate_threads_~tmp~1); 9941#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9953#L167 assume !(1 == ~t1_pc~0); 10065#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 10066#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10001#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10002#L405 assume !(0 != activate_threads_~tmp___0~0); 9970#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9849#L186 assume !(1 == ~t2_pc~0); 9850#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 9852#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9853#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10007#L413 assume !(0 != activate_threads_~tmp___1~0); 10008#L413-2 assume !(1 == ~M_E~0); 9893#L359-1 assume !(1 == ~T1_E~0); 9894#L364-1 assume !(1 == ~T2_E~0); 9954#L369-1 assume !(1 == ~E_1~0); 10009#L374-1 assume !(1 == ~E_2~0); 10054#L520-1 assume !false; 10444#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10443#L301 [2020-11-28 03:12:18,709 INFO L796 eck$LassoCheckResult]: Loop: 10443#L301 assume !false; 10442#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10441#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10440#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10439#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 10438#L268 assume 0 != eval_~tmp~0; 10437#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 10435#L276 assume !(0 != eval_~tmp_ndt_1~0); 10436#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 10449#L290 assume !(0 != eval_~tmp_ndt_2~0); 10447#L287 assume !(0 == ~t2_st~0); 10443#L301 [2020-11-28 03:12:18,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,709 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2020-11-28 03:12:18,709 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,710 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816255216] [2020-11-28 03:12:18,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,722 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,730 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,738 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010543, now seen corresponding path program 2 times [2020-11-28 03:12:18,739 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,740 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259979666] [2020-11-28 03:12:18,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,744 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:18,748 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:18,752 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:18,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:18,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1971900399, now seen corresponding path program 1 times [2020-11-28 03:12:18,753 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:18,757 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605914224] [2020-11-28 03:12:18,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:18,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 03:12:18,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 03:12:18,852 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605914224] [2020-11-28 03:12:18,852 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 03:12:18,852 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 03:12:18,853 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946869432] [2020-11-28 03:12:18,963 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 03:12:18,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 03:12:18,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 03:12:18,964 INFO L87 Difference]: Start difference. First operand 741 states and 1009 transitions. cyclomatic complexity: 270 Second operand 3 states. [2020-11-28 03:12:19,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 03:12:19,035 INFO L93 Difference]: Finished difference Result 1319 states and 1782 transitions. [2020-11-28 03:12:19,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 03:12:19,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1319 states and 1782 transitions. [2020-11-28 03:12:19,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1272 [2020-11-28 03:12:19,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1319 states to 1319 states and 1782 transitions. [2020-11-28 03:12:19,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1319 [2020-11-28 03:12:19,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1319 [2020-11-28 03:12:19,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1319 states and 1782 transitions. [2020-11-28 03:12:19,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 03:12:19,073 INFO L691 BuchiCegarLoop]: Abstraction has 1319 states and 1782 transitions. [2020-11-28 03:12:19,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1319 states and 1782 transitions. [2020-11-28 03:12:19,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1319 to 1319. [2020-11-28 03:12:19,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1319 states. [2020-11-28 03:12:19,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1319 states to 1319 states and 1782 transitions. [2020-11-28 03:12:19,102 INFO L714 BuchiCegarLoop]: Abstraction has 1319 states and 1782 transitions. [2020-11-28 03:12:19,102 INFO L594 BuchiCegarLoop]: Abstraction has 1319 states and 1782 transitions. [2020-11-28 03:12:19,102 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 03:12:19,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1319 states and 1782 transitions. [2020-11-28 03:12:19,111 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1272 [2020-11-28 03:12:19,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 03:12:19,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 03:12:19,112 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:19,112 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 03:12:19,112 INFO L794 eck$LassoCheckResult]: Stem: 12090#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 11926#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11927#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11949#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 11958#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11959#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12043#L223-1 assume !(0 == ~M_E~0); 11965#L326-1 assume !(0 == ~T1_E~0); 11966#L331-1 assume !(0 == ~T2_E~0); 12027#L336-1 assume !(0 == ~E_1~0); 12078#L341-1 assume !(0 == ~E_2~0); 12089#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12112#L148 assume !(1 == ~m_pc~0); 12105#L148-2 is_master_triggered_~__retres1~0 := 0; 12106#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12070#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12004#L397 assume !(0 != activate_threads_~tmp~1); 12005#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12020#L167 assume !(1 == ~t1_pc~0); 12123#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 12124#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12064#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12065#L405 assume !(0 != activate_threads_~tmp___0~0); 12036#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11917#L186 assume !(1 == ~t2_pc~0); 11918#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 11920#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11921#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12071#L413 assume !(0 != activate_threads_~tmp___1~0); 12072#L413-2 assume !(1 == ~M_E~0); 11960#L359-1 assume !(1 == ~T1_E~0); 11961#L364-1 assume !(1 == ~T2_E~0); 12021#L369-1 assume !(1 == ~E_1~0); 12074#L374-1 assume !(1 == ~E_2~0); 12110#L520-1 assume !false; 13167#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13164#L301 [2020-11-28 03:12:19,112 INFO L796 eck$LassoCheckResult]: Loop: 13164#L301 assume !false; 13162#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13160#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12085#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12086#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 13154#L268 assume 0 != eval_~tmp~0; 13150#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 11978#L276 assume !(0 != eval_~tmp_ndt_1~0); 11980#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 13117#L290 assume !(0 != eval_~tmp_ndt_2~0); 13118#L287 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 13165#L304 assume !(0 != eval_~tmp_ndt_3~0); 13164#L301 [2020-11-28 03:12:19,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:19,114 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2020-11-28 03:12:19,114 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:19,115 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45556631] [2020-11-28 03:12:19,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:19,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,135 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,143 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,159 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:19,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:19,166 INFO L82 PathProgramCache]: Analyzing trace with hash 498620435, now seen corresponding path program 1 times [2020-11-28 03:12:19,166 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:19,166 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263025878] [2020-11-28 03:12:19,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:19,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,171 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,175 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,176 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:19,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 03:12:19,177 INFO L82 PathProgramCache]: Analyzing trace with hash 999369491, now seen corresponding path program 1 times [2020-11-28 03:12:19,177 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 03:12:19,178 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908872072] [2020-11-28 03:12:19,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 03:12:19,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,194 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 03:12:19,202 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 03:12:19,210 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 03:12:20,115 WARN L193 SmtUtils]: Spent 773.00 ms on a formula simplification. DAG size of input: 148 DAG size of output: 113 [2020-11-28 03:12:20,356 WARN L193 SmtUtils]: Spent 212.00 ms on a formula simplification that was a NOOP. DAG size: 99 [2020-11-28 03:12:20,430 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:12:20 BoogieIcfgContainer [2020-11-28 03:12:20,431 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 03:12:20,431 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 03:12:20,432 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 03:12:20,432 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 03:12:20,433 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:12:15" (3/4) ... [2020-11-28 03:12:20,436 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 03:12:20,518 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_f0601a29-58b0-4860-8bde-750000025698/bin/uautomizer/witness.graphml [2020-11-28 03:12:20,518 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 03:12:20,520 INFO L168 Benchmark]: Toolchain (without parser) took 6881.11 ms. Allocated memory was 96.5 MB in the beginning and 167.8 MB in the end (delta: 71.3 MB). Free memory was 75.8 MB in the beginning and 88.7 MB in the end (delta: -12.8 MB). Peak memory consumption was 58.7 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,520 INFO L168 Benchmark]: CDTParser took 0.89 ms. Allocated memory is still 79.7 MB. Free memory is still 54.7 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 03:12:20,520 INFO L168 Benchmark]: CACSL2BoogieTranslator took 377.44 ms. Allocated memory is still 96.5 MB. Free memory was 75.5 MB in the beginning and 62.4 MB in the end (delta: 13.1 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,521 INFO L168 Benchmark]: Boogie Procedure Inliner took 96.09 ms. Allocated memory is still 96.5 MB. Free memory was 62.1 MB in the beginning and 59.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,521 INFO L168 Benchmark]: Boogie Preprocessor took 58.51 ms. Allocated memory is still 96.5 MB. Free memory was 59.4 MB in the beginning and 57.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,522 INFO L168 Benchmark]: RCFGBuilder took 1098.61 ms. Allocated memory is still 96.5 MB. Free memory was 57.3 MB in the beginning and 45.2 MB in the end (delta: 12.1 MB). Peak memory consumption was 24.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,522 INFO L168 Benchmark]: BuchiAutomizer took 5156.37 ms. Allocated memory was 96.5 MB in the beginning and 167.8 MB in the end (delta: 71.3 MB). Free memory was 45.2 MB in the beginning and 90.7 MB in the end (delta: -45.5 MB). Peak memory consumption was 57.7 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,523 INFO L168 Benchmark]: Witness Printer took 86.76 ms. Allocated memory is still 167.8 MB. Free memory was 90.7 MB in the beginning and 88.7 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 03:12:20,526 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.89 ms. Allocated memory is still 79.7 MB. Free memory is still 54.7 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 377.44 ms. Allocated memory is still 96.5 MB. Free memory was 75.5 MB in the beginning and 62.4 MB in the end (delta: 13.1 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 96.09 ms. Allocated memory is still 96.5 MB. Free memory was 62.1 MB in the beginning and 59.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 58.51 ms. Allocated memory is still 96.5 MB. Free memory was 59.4 MB in the beginning and 57.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1098.61 ms. Allocated memory is still 96.5 MB. Free memory was 57.3 MB in the beginning and 45.2 MB in the end (delta: 12.1 MB). Peak memory consumption was 24.1 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 5156.37 ms. Allocated memory was 96.5 MB in the beginning and 167.8 MB in the end (delta: 71.3 MB). Free memory was 45.2 MB in the beginning and 90.7 MB in the end (delta: -45.5 MB). Peak memory consumption was 57.7 MB. Max. memory is 16.1 GB. * Witness Printer took 86.76 ms. Allocated memory is still 167.8 MB. Free memory was 90.7 MB in the beginning and 88.7 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1319 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.0s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.5s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 11 MinimizatonAttempts, 643 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1319 states and ocurred in iteration 11. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 3037 SDtfs, 3450 SDslu, 2733 SDs, 0 SdLazy, 215 SolverSat, 104 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 263]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {NULL=0, NULL=1, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4530efce=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@20e4c4b6=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6273f49b=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a502b39=0, NULL=2, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=4, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=3, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@bf8d136=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6b14bd=0, t2_pc=0, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d731678=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79b53f26=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c4f9596=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 263]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L565] int __retres1 ; [L479] m_i = 1 [L480] t1_i = 1 [L481] t2_i = 1 [L506] int kernel_st ; [L507] int tmp ; [L508] int tmp___0 ; [L512] kernel_st = 0 [L213] COND TRUE m_i == 1 [L214] m_st = 0 [L218] COND TRUE t1_i == 1 [L219] t1_st = 0 [L223] COND TRUE t2_i == 1 [L224] t2_st = 0 [L326] COND FALSE !(M_E == 0) [L331] COND FALSE !(T1_E == 0) [L336] COND FALSE !(T2_E == 0) [L341] COND FALSE !(E_1 == 0) [L346] COND FALSE !(E_2 == 0) [L389] int tmp ; [L390] int tmp___0 ; [L391] int tmp___1 ; [L145] int __retres1 ; [L148] COND FALSE !(m_pc == 1) [L158] __retres1 = 0 [L160] return (__retres1); [L395] tmp = is_master_triggered() [L397] COND FALSE !(\read(tmp)) [L164] int __retres1 ; [L167] COND FALSE !(t1_pc == 1) [L177] __retres1 = 0 [L179] return (__retres1); [L403] tmp___0 = is_transmit1_triggered() [L405] COND FALSE !(\read(tmp___0)) [L183] int __retres1 ; [L186] COND FALSE !(t2_pc == 1) [L196] __retres1 = 0 [L198] return (__retres1); [L411] tmp___1 = is_transmit2_triggered() [L413] COND FALSE !(\read(tmp___1)) [L359] COND FALSE !(M_E == 1) [L364] COND FALSE !(T1_E == 1) [L369] COND FALSE !(T2_E == 1) [L374] COND FALSE !(E_1 == 1) [L379] COND FALSE !(E_2 == 1) [L520] COND TRUE 1 [L523] kernel_st = 1 [L259] int tmp ; Loop: [L263] COND TRUE 1 [L233] int __retres1 ; [L236] COND TRUE m_st == 0 [L237] __retres1 = 1 [L254] return (__retres1); [L266] tmp = exists_runnable_thread() [L268] COND TRUE \read(tmp) [L273] COND TRUE m_st == 0 [L274] int tmp_ndt_1; [L275] tmp_ndt_1 = __VERIFIER_nondet_int() [L276] COND FALSE !(\read(tmp_ndt_1)) [L287] COND TRUE t1_st == 0 [L288] int tmp_ndt_2; [L289] tmp_ndt_2 = __VERIFIER_nondet_int() [L290] COND FALSE !(\read(tmp_ndt_2)) [L301] COND TRUE t2_st == 0 [L302] int tmp_ndt_3; [L303] tmp_ndt_3 = __VERIFIER_nondet_int() [L304] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...