./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f6768ec4cb10c0d030986cdc2e459713dbcdaadd ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-28 02:57:50,055 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-28 02:57:50,063 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-28 02:57:50,122 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-28 02:57:50,126 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-28 02:57:50,132 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-28 02:57:50,135 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-28 02:57:50,140 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-28 02:57:50,143 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-28 02:57:50,149 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-28 02:57:50,151 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-28 02:57:50,153 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-28 02:57:50,153 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-28 02:57:50,157 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-28 02:57:50,159 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-28 02:57:50,161 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-28 02:57:50,163 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-28 02:57:50,167 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-28 02:57:50,170 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-28 02:57:50,179 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-28 02:57:50,181 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-28 02:57:50,182 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-28 02:57:50,185 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-28 02:57:50,186 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-28 02:57:50,195 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-28 02:57:50,196 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-28 02:57:50,196 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-28 02:57:50,199 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-28 02:57:50,199 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-28 02:57:50,201 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-28 02:57:50,201 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-28 02:57:50,203 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-28 02:57:50,205 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-28 02:57:50,207 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-28 02:57:50,208 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-28 02:57:50,208 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-28 02:57:50,209 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-28 02:57:50,210 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-28 02:57:50,210 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-28 02:57:50,211 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-28 02:57:50,212 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-28 02:57:50,215 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-28 02:57:50,258 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-28 02:57:50,258 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-28 02:57:50,260 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-28 02:57:50,261 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-28 02:57:50,261 INFO L138 SettingsManager]: * Use SBE=true [2020-11-28 02:57:50,261 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-28 02:57:50,261 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-28 02:57:50,262 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-28 02:57:50,262 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-28 02:57:50,262 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-28 02:57:50,263 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-28 02:57:50,264 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-28 02:57:50,264 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-28 02:57:50,264 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-28 02:57:50,264 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-28 02:57:50,265 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-28 02:57:50,265 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-28 02:57:50,265 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-28 02:57:50,265 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-28 02:57:50,266 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-28 02:57:50,266 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-28 02:57:50,266 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-28 02:57:50,266 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-28 02:57:50,267 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-28 02:57:50,267 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-28 02:57:50,267 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-28 02:57:50,267 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-28 02:57:50,268 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-28 02:57:50,268 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-28 02:57:50,270 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-28 02:57:50,270 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-28 02:57:50,270 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-28 02:57:50,271 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-28 02:57:50,272 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f6768ec4cb10c0d030986cdc2e459713dbcdaadd [2020-11-28 02:57:50,589 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-28 02:57:50,612 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-28 02:57:50,614 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-28 02:57:50,616 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-28 02:57:50,617 INFO L275 PluginConnector]: CDTParser initialized [2020-11-28 02:57:50,619 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2020-11-28 02:57:50,712 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/data/f73567cba/15972ba14583437483b0ca1308200dfc/FLAGf34a0cc82 [2020-11-28 02:57:51,259 INFO L306 CDTParser]: Found 1 translation units. [2020-11-28 02:57:51,260 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/sv-benchmarks/c/systemc/transmitter.03.cil.c [2020-11-28 02:57:51,271 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/data/f73567cba/15972ba14583437483b0ca1308200dfc/FLAGf34a0cc82 [2020-11-28 02:57:51,616 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/data/f73567cba/15972ba14583437483b0ca1308200dfc [2020-11-28 02:57:51,619 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-28 02:57:51,621 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-28 02:57:51,625 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-28 02:57:51,625 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-28 02:57:51,629 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-28 02:57:51,630 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:57:51" (1/1) ... [2020-11-28 02:57:51,632 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45802b16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:51, skipping insertion in model container [2020-11-28 02:57:51,633 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:57:51" (1/1) ... [2020-11-28 02:57:51,641 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-28 02:57:51,707 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-28 02:57:52,070 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 02:57:52,083 INFO L203 MainTranslator]: Completed pre-run [2020-11-28 02:57:52,170 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-28 02:57:52,196 INFO L208 MainTranslator]: Completed translation [2020-11-28 02:57:52,196 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52 WrapperNode [2020-11-28 02:57:52,196 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-28 02:57:52,198 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-28 02:57:52,198 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-28 02:57:52,198 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-28 02:57:52,207 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,217 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,287 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-28 02:57:52,288 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-28 02:57:52,298 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-28 02:57:52,298 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-28 02:57:52,307 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,308 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,312 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,320 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,332 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,366 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,369 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... [2020-11-28 02:57:52,388 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-28 02:57:52,389 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-28 02:57:52,389 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-28 02:57:52,389 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-28 02:57:52,392 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-28 02:57:52,485 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-28 02:57:52,485 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-28 02:57:52,485 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-28 02:57:52,485 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-28 02:57:53,751 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-28 02:57:53,751 INFO L298 CfgBuilder]: Removed 121 assume(true) statements. [2020-11-28 02:57:53,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:53 BoogieIcfgContainer [2020-11-28 02:57:53,754 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-28 02:57:53,755 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-28 02:57:53,755 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-28 02:57:53,762 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-28 02:57:53,763 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:53,764 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 02:57:51" (1/3) ... [2020-11-28 02:57:53,765 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e256999 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 02:57:53, skipping insertion in model container [2020-11-28 02:57:53,765 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:53,766 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:57:52" (2/3) ... [2020-11-28 02:57:53,767 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e256999 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 02:57:53, skipping insertion in model container [2020-11-28 02:57:53,767 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-28 02:57:53,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:53" (3/3) ... [2020-11-28 02:57:53,770 INFO L373 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2020-11-28 02:57:53,844 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-28 02:57:53,844 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-28 02:57:53,844 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-28 02:57:53,845 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-28 02:57:53,845 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-28 02:57:53,845 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-28 02:57:53,845 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-28 02:57:53,845 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-28 02:57:53,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states. [2020-11-28 02:57:53,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 223 [2020-11-28 02:57:53,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:53,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:53,976 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:53,976 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:53,976 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-28 02:57:53,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states. [2020-11-28 02:57:54,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 223 [2020-11-28 02:57:54,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:54,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:54,007 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,008 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,018 INFO L794 eck$LassoCheckResult]: Stem: 85#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 10#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 157#L607true havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 143#L266true assume !(1 == ~m_i~0);~m_st~0 := 2; 62#L273-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 228#L278-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 232#L283-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 142#L288-1true assume !(0 == ~M_E~0); 225#L410-1true assume !(0 == ~T1_E~0); 240#L415-1true assume !(0 == ~T2_E~0); 134#L420-1true assume !(0 == ~T3_E~0); 163#L425-1true assume !(0 == ~E_1~0); 192#L430-1true assume 0 == ~E_2~0;~E_2~0 := 1; 75#L435-1true assume !(0 == ~E_3~0); 96#L440-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 269#L189true assume !(1 == ~m_pc~0); 263#L189-2true is_master_triggered_~__retres1~0 := 0; 270#L200true is_master_triggered_#res := is_master_triggered_~__retres1~0; 216#L201true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 178#L502true assume !(0 != activate_threads_~tmp~1); 158#L502-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6#L208true assume 1 == ~t1_pc~0; 83#L209true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7#L219true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84#L220true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50#L510true assume !(0 != activate_threads_~tmp___0~0); 57#L510-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 171#L227true assume !(1 == ~t2_pc~0); 165#L227-2true is_transmit2_triggered_~__retres1~2 := 0; 173#L238true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 230#L239true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 200#L518true assume !(0 != activate_threads_~tmp___1~0); 189#L518-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53#L246true assume 1 == ~t3_pc~0; 125#L247true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 55#L257true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 126#L258true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 202#L526true assume !(0 != activate_threads_~tmp___2~0); 209#L526-2true assume !(1 == ~M_E~0); 132#L453-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 159#L458-1true assume !(1 == ~T2_E~0); 190#L463-1true assume !(1 == ~T3_E~0); 73#L468-1true assume !(1 == ~E_1~0); 94#L473-1true assume !(1 == ~E_2~0); 121#L478-1true assume !(1 == ~E_3~0); 80#L644-1true [2020-11-28 02:57:54,019 INFO L796 eck$LassoCheckResult]: Loop: 80#L644-1true assume !false; 186#L645true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 97#L385true assume false; 60#L400true start_simulation_~kernel_st~0 := 2; 271#L266-1true start_simulation_~kernel_st~0 := 3; 226#L410-2true assume 0 == ~M_E~0;~M_E~0 := 1; 227#L410-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 249#L415-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 138#L420-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 169#L425-3true assume !(0 == ~E_1~0); 195#L430-3true assume 0 == ~E_2~0;~E_2~0 := 1; 77#L435-3true assume 0 == ~E_3~0;~E_3~0 := 1; 103#L440-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 233#L189-12true assume !(1 == ~m_pc~0); 231#L189-14true is_master_triggered_~__retres1~0 := 0; 278#L200-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 203#L201-4true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 155#L502-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 145#L502-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 131#L208-12true assume 1 == ~t1_pc~0; 88#L209-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15#L219-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89#L220-4true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35#L510-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38#L510-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 149#L227-12true assume !(1 == ~t2_pc~0); 144#L227-14true is_transmit2_triggered_~__retres1~2 := 0; 160#L238-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 244#L239-4true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 188#L518-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 175#L518-14true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32#L246-12true assume 1 == ~t3_pc~0; 102#L247-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 27#L257-4true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104#L258-4true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 64#L526-12true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65#L526-14true assume !(1 == ~M_E~0); 136#L453-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 167#L458-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 193#L463-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 76#L468-3true assume 1 == ~E_1~0;~E_1~0 := 2; 100#L473-3true assume 1 == ~E_2~0;~E_2~0 := 2; 128#L478-3true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L483-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 56#L301-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45#L323-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 109#L324-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 234#L663true assume !(0 == start_simulation_~tmp~3); 236#L663-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 52#L301-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 46#L323-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 111#L324-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 156#L618true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 218#L625true stop_simulation_#res := stop_simulation_~__retres2~0; 36#L626true start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3#L676true assume !(0 != start_simulation_~tmp___0~1); 80#L644-1true [2020-11-28 02:57:54,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1271326673, now seen corresponding path program 1 times [2020-11-28 02:57:54,039 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,039 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114050543] [2020-11-28 02:57:54,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,258 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114050543] [2020-11-28 02:57:54,259 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,259 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:54,260 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116082088] [2020-11-28 02:57:54,268 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:54,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,276 INFO L82 PathProgramCache]: Analyzing trace with hash -1476881754, now seen corresponding path program 1 times [2020-11-28 02:57:54,276 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,277 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658084212] [2020-11-28 02:57:54,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,334 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658084212] [2020-11-28 02:57:54,334 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,335 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:54,335 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036326206] [2020-11-28 02:57:54,336 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:54,337 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:54,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:54,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:54,351 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2020-11-28 02:57:54,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:54,405 INFO L93 Difference]: Finished difference Result 275 states and 415 transitions. [2020-11-28 02:57:54,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:54,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 275 states and 415 transitions. [2020-11-28 02:57:54,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:54,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 275 states to 270 states and 410 transitions. [2020-11-28 02:57:54,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2020-11-28 02:57:54,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2020-11-28 02:57:54,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 410 transitions. [2020-11-28 02:57:54,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:54,429 INFO L691 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2020-11-28 02:57:54,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 410 transitions. [2020-11-28 02:57:54,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2020-11-28 02:57:54,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2020-11-28 02:57:54,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 410 transitions. [2020-11-28 02:57:54,504 INFO L714 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2020-11-28 02:57:54,504 INFO L594 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2020-11-28 02:57:54,504 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-28 02:57:54,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 410 transitions. [2020-11-28 02:57:54,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:54,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:54,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:54,518 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,518 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,519 INFO L794 eck$LassoCheckResult]: Stem: 685#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 575#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 576#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 736#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 661#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 662#L278-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 823#L283-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 734#L288-1 assume !(0 == ~M_E~0); 735#L410-1 assume !(0 == ~T1_E~0); 819#L415-1 assume !(0 == ~T2_E~0); 721#L420-1 assume !(0 == ~T3_E~0); 722#L425-1 assume !(0 == ~E_1~0); 759#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 678#L435-1 assume !(0 == ~E_3~0); 679#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 696#L189 assume !(1 == ~m_pc~0); 811#L189-2 is_master_triggered_~__retres1~0 := 0; 810#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 812#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 774#L502 assume !(0 != activate_threads_~tmp~1); 753#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 566#L208 assume 1 == ~t1_pc~0; 567#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 569#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 570#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 645#L510 assume !(0 != activate_threads_~tmp___0~0); 646#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 656#L227 assume !(1 == ~t2_pc~0); 761#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 762#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 769#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 789#L518 assume !(0 != activate_threads_~tmp___1~0); 782#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 652#L246 assume 1 == ~t3_pc~0; 653#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 616#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 654#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 713#L526 assume !(0 != activate_threads_~tmp___2~0); 794#L526-2 assume !(1 == ~M_E~0); 717#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 718#L458-1 assume !(1 == ~T2_E~0); 754#L463-1 assume !(1 == ~T3_E~0); 676#L468-1 assume !(1 == ~E_1~0); 677#L473-1 assume !(1 == ~E_2~0); 695#L478-1 assume !(1 == ~E_3~0); 561#L644-1 [2020-11-28 02:57:54,520 INFO L796 eck$LassoCheckResult]: Loop: 561#L644-1 assume !false; 684#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 697#L385 assume !false; 632#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 633#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 634#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 635#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 702#L338 assume !(0 != eval_~tmp~0); 659#L400 start_simulation_~kernel_st~0 := 2; 660#L266-1 start_simulation_~kernel_st~0 := 3; 820#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 821#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 822#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 727#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 728#L425-3 assume !(0 == ~E_1~0); 765#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 682#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 683#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 701#L189-12 assume 1 == ~m_pc~0; 790#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 791#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 795#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 752#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 739#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 716#L208-12 assume 1 == ~t1_pc~0; 688#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 585#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 586#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 623#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 624#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 627#L227-12 assume !(1 == ~t2_pc~0); 737#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 738#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 755#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 781#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 770#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 617#L246-12 assume 1 == ~t3_pc~0; 618#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 574#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 608#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 665#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 666#L526-14 assume !(1 == ~M_E~0); 667#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 725#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 764#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 680#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 681#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 700#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 611#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 612#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 638#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 639#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 704#L663 assume !(0 == start_simulation_~tmp~3); 788#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 648#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 640#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 641#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 706#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 751#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 622#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 560#L676 assume !(0 != start_simulation_~tmp___0~1); 561#L644-1 [2020-11-28 02:57:54,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,521 INFO L82 PathProgramCache]: Analyzing trace with hash 1023180179, now seen corresponding path program 1 times [2020-11-28 02:57:54,522 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,522 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677999250] [2020-11-28 02:57:54,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,632 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677999250] [2020-11-28 02:57:54,632 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,632 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:54,632 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285686091] [2020-11-28 02:57:54,633 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:54,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1028109864, now seen corresponding path program 1 times [2020-11-28 02:57:54,634 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,634 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094910762] [2020-11-28 02:57:54,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,734 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094910762] [2020-11-28 02:57:54,735 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,735 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:54,735 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124090140] [2020-11-28 02:57:54,736 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:54,736 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:54,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:54,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:54,738 INFO L87 Difference]: Start difference. First operand 270 states and 410 transitions. cyclomatic complexity: 141 Second operand 3 states. [2020-11-28 02:57:54,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:54,759 INFO L93 Difference]: Finished difference Result 270 states and 409 transitions. [2020-11-28 02:57:54,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:54,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 409 transitions. [2020-11-28 02:57:54,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:54,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 409 transitions. [2020-11-28 02:57:54,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2020-11-28 02:57:54,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2020-11-28 02:57:54,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 409 transitions. [2020-11-28 02:57:54,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:54,784 INFO L691 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2020-11-28 02:57:54,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 409 transitions. [2020-11-28 02:57:54,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2020-11-28 02:57:54,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2020-11-28 02:57:54,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 409 transitions. [2020-11-28 02:57:54,800 INFO L714 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2020-11-28 02:57:54,801 INFO L594 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2020-11-28 02:57:54,801 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-28 02:57:54,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 409 transitions. [2020-11-28 02:57:54,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:54,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:54,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:54,806 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,806 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:54,807 INFO L794 eck$LassoCheckResult]: Stem: 1232#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1122#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1123#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1283#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 1210#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1211#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1370#L283-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1281#L288-1 assume !(0 == ~M_E~0); 1282#L410-1 assume !(0 == ~T1_E~0); 1366#L415-1 assume !(0 == ~T2_E~0); 1268#L420-1 assume !(0 == ~T3_E~0); 1269#L425-1 assume !(0 == ~E_1~0); 1306#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1225#L435-1 assume !(0 == ~E_3~0); 1226#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1243#L189 assume !(1 == ~m_pc~0); 1358#L189-2 is_master_triggered_~__retres1~0 := 0; 1357#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1359#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1321#L502 assume !(0 != activate_threads_~tmp~1); 1300#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1113#L208 assume 1 == ~t1_pc~0; 1114#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1116#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1117#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1192#L510 assume !(0 != activate_threads_~tmp___0~0); 1193#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1203#L227 assume !(1 == ~t2_pc~0); 1308#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 1309#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1316#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1336#L518 assume !(0 != activate_threads_~tmp___1~0); 1329#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1199#L246 assume 1 == ~t3_pc~0; 1200#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1163#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1201#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1260#L526 assume !(0 != activate_threads_~tmp___2~0); 1341#L526-2 assume !(1 == ~M_E~0); 1264#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1265#L458-1 assume !(1 == ~T2_E~0); 1301#L463-1 assume !(1 == ~T3_E~0); 1223#L468-1 assume !(1 == ~E_1~0); 1224#L473-1 assume !(1 == ~E_2~0); 1242#L478-1 assume !(1 == ~E_3~0); 1108#L644-1 [2020-11-28 02:57:54,807 INFO L796 eck$LassoCheckResult]: Loop: 1108#L644-1 assume !false; 1231#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1244#L385 assume !false; 1179#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1180#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1181#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1182#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1249#L338 assume !(0 != eval_~tmp~0); 1206#L400 start_simulation_~kernel_st~0 := 2; 1207#L266-1 start_simulation_~kernel_st~0 := 3; 1367#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1368#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1369#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1274#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1275#L425-3 assume !(0 == ~E_1~0); 1312#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1229#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1230#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1248#L189-12 assume 1 == ~m_pc~0; 1337#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1338#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1342#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1299#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1288#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1263#L208-12 assume 1 == ~t1_pc~0; 1235#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1132#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1133#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1170#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1171#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1174#L227-12 assume !(1 == ~t2_pc~0); 1284#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 1285#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1302#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1327#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1317#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1164#L246-12 assume !(1 == ~t3_pc~0); 1120#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 1121#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1153#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1212#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1213#L526-14 assume !(1 == ~M_E~0); 1214#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1272#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1310#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1227#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1228#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1245#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1156#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1157#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1185#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1186#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1251#L663 assume !(0 == start_simulation_~tmp~3); 1335#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1195#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1187#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1188#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1253#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1298#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 1169#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1107#L676 assume !(0 != start_simulation_~tmp___0~1); 1108#L644-1 [2020-11-28 02:57:54,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,808 INFO L82 PathProgramCache]: Analyzing trace with hash -1899979819, now seen corresponding path program 1 times [2020-11-28 02:57:54,809 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,809 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262396168] [2020-11-28 02:57:54,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,870 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262396168] [2020-11-28 02:57:54,870 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,870 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:54,870 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379788173] [2020-11-28 02:57:54,871 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:54,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:54,874 INFO L82 PathProgramCache]: Analyzing trace with hash -1029494167, now seen corresponding path program 1 times [2020-11-28 02:57:54,874 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:54,875 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020943210] [2020-11-28 02:57:54,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:54,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:54,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:54,959 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020943210] [2020-11-28 02:57:54,960 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:54,960 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:54,960 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781829686] [2020-11-28 02:57:54,961 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:54,961 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:54,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:54,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:54,962 INFO L87 Difference]: Start difference. First operand 270 states and 409 transitions. cyclomatic complexity: 140 Second operand 3 states. [2020-11-28 02:57:54,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:54,976 INFO L93 Difference]: Finished difference Result 270 states and 408 transitions. [2020-11-28 02:57:54,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:54,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 408 transitions. [2020-11-28 02:57:54,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:54,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 408 transitions. [2020-11-28 02:57:54,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2020-11-28 02:57:54,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2020-11-28 02:57:54,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 408 transitions. [2020-11-28 02:57:54,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:54,992 INFO L691 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2020-11-28 02:57:54,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 408 transitions. [2020-11-28 02:57:55,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2020-11-28 02:57:55,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2020-11-28 02:57:55,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 408 transitions. [2020-11-28 02:57:55,009 INFO L714 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2020-11-28 02:57:55,009 INFO L594 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2020-11-28 02:57:55,009 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-28 02:57:55,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 408 transitions. [2020-11-28 02:57:55,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:55,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:55,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:55,016 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,016 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,037 INFO L794 eck$LassoCheckResult]: Stem: 1779#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1669#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1670#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1830#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 1757#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1758#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1917#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1828#L288-1 assume !(0 == ~M_E~0); 1829#L410-1 assume !(0 == ~T1_E~0); 1913#L415-1 assume !(0 == ~T2_E~0); 1815#L420-1 assume !(0 == ~T3_E~0); 1816#L425-1 assume !(0 == ~E_1~0); 1854#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1772#L435-1 assume !(0 == ~E_3~0); 1773#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1790#L189 assume !(1 == ~m_pc~0); 1905#L189-2 is_master_triggered_~__retres1~0 := 0; 1904#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1906#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1868#L502 assume !(0 != activate_threads_~tmp~1); 1847#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1660#L208 assume 1 == ~t1_pc~0; 1661#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1663#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1664#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1739#L510 assume !(0 != activate_threads_~tmp___0~0); 1740#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1750#L227 assume !(1 == ~t2_pc~0); 1855#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 1856#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1863#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1883#L518 assume !(0 != activate_threads_~tmp___1~0); 1876#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1746#L246 assume 1 == ~t3_pc~0; 1747#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1710#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1748#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1807#L526 assume !(0 != activate_threads_~tmp___2~0); 1888#L526-2 assume !(1 == ~M_E~0); 1811#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1812#L458-1 assume !(1 == ~T2_E~0); 1849#L463-1 assume !(1 == ~T3_E~0); 1770#L468-1 assume !(1 == ~E_1~0); 1771#L473-1 assume !(1 == ~E_2~0); 1789#L478-1 assume !(1 == ~E_3~0); 1655#L644-1 [2020-11-28 02:57:55,039 INFO L796 eck$LassoCheckResult]: Loop: 1655#L644-1 assume !false; 1778#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1791#L385 assume !false; 1726#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1727#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1728#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1729#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1796#L338 assume !(0 != eval_~tmp~0); 1753#L400 start_simulation_~kernel_st~0 := 2; 1754#L266-1 start_simulation_~kernel_st~0 := 3; 1914#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1915#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1916#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1821#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1822#L425-3 assume !(0 == ~E_1~0); 1860#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1776#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1777#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1795#L189-12 assume 1 == ~m_pc~0; 1884#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1885#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1889#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1846#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1835#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1810#L208-12 assume 1 == ~t1_pc~0; 1782#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1679#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1680#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1716#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1717#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1721#L227-12 assume 1 == ~t2_pc~0; 1840#L228-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1832#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1848#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1874#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1864#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1711#L246-12 assume 1 == ~t3_pc~0; 1712#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1668#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1700#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1759#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1760#L526-14 assume !(1 == ~M_E~0); 1761#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1819#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1858#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1774#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1775#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1792#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1705#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1706#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1732#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1733#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1798#L663 assume !(0 == start_simulation_~tmp~3); 1882#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1742#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1734#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1735#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1800#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1845#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 1718#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1654#L676 assume !(0 != start_simulation_~tmp___0~1); 1655#L644-1 [2020-11-28 02:57:55,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,039 INFO L82 PathProgramCache]: Analyzing trace with hash -54612653, now seen corresponding path program 1 times [2020-11-28 02:57:55,040 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,040 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333694302] [2020-11-28 02:57:55,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,096 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333694302] [2020-11-28 02:57:55,096 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,097 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:55,097 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348218986] [2020-11-28 02:57:55,097 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:55,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,098 INFO L82 PathProgramCache]: Analyzing trace with hash -1495386457, now seen corresponding path program 1 times [2020-11-28 02:57:55,098 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,098 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048897108] [2020-11-28 02:57:55,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,137 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048897108] [2020-11-28 02:57:55,137 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,137 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:55,137 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281805831] [2020-11-28 02:57:55,138 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:55,138 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:55,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:55,139 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:55,139 INFO L87 Difference]: Start difference. First operand 270 states and 408 transitions. cyclomatic complexity: 139 Second operand 3 states. [2020-11-28 02:57:55,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:55,185 INFO L93 Difference]: Finished difference Result 270 states and 398 transitions. [2020-11-28 02:57:55,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:55,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 398 transitions. [2020-11-28 02:57:55,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:55,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 398 transitions. [2020-11-28 02:57:55,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2020-11-28 02:57:55,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2020-11-28 02:57:55,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 398 transitions. [2020-11-28 02:57:55,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:55,194 INFO L691 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2020-11-28 02:57:55,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 398 transitions. [2020-11-28 02:57:55,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2020-11-28 02:57:55,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2020-11-28 02:57:55,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 398 transitions. [2020-11-28 02:57:55,200 INFO L714 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2020-11-28 02:57:55,201 INFO L594 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2020-11-28 02:57:55,201 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-28 02:57:55,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 398 transitions. [2020-11-28 02:57:55,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2020-11-28 02:57:55,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:55,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:55,205 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,205 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,205 INFO L794 eck$LassoCheckResult]: Stem: 2326#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2216#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2217#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2377#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 2304#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2305#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2464#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2375#L288-1 assume !(0 == ~M_E~0); 2376#L410-1 assume !(0 == ~T1_E~0); 2460#L415-1 assume !(0 == ~T2_E~0); 2362#L420-1 assume !(0 == ~T3_E~0); 2363#L425-1 assume !(0 == ~E_1~0); 2401#L430-1 assume !(0 == ~E_2~0); 2319#L435-1 assume !(0 == ~E_3~0); 2320#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2337#L189 assume !(1 == ~m_pc~0); 2452#L189-2 is_master_triggered_~__retres1~0 := 0; 2451#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2453#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2415#L502 assume !(0 != activate_threads_~tmp~1); 2394#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2207#L208 assume 1 == ~t1_pc~0; 2208#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2210#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2211#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2286#L510 assume !(0 != activate_threads_~tmp___0~0); 2287#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2297#L227 assume !(1 == ~t2_pc~0); 2402#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 2403#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2410#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2430#L518 assume !(0 != activate_threads_~tmp___1~0); 2423#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2293#L246 assume 1 == ~t3_pc~0; 2294#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2257#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2295#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2354#L526 assume !(0 != activate_threads_~tmp___2~0); 2436#L526-2 assume !(1 == ~M_E~0); 2358#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2359#L458-1 assume !(1 == ~T2_E~0); 2396#L463-1 assume !(1 == ~T3_E~0); 2317#L468-1 assume !(1 == ~E_1~0); 2318#L473-1 assume !(1 == ~E_2~0); 2336#L478-1 assume !(1 == ~E_3~0); 2202#L644-1 [2020-11-28 02:57:55,206 INFO L796 eck$LassoCheckResult]: Loop: 2202#L644-1 assume !false; 2325#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2338#L385 assume !false; 2273#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2274#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2275#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2276#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2343#L338 assume !(0 != eval_~tmp~0); 2300#L400 start_simulation_~kernel_st~0 := 2; 2301#L266-1 start_simulation_~kernel_st~0 := 3; 2461#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2462#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2463#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2368#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2369#L425-3 assume !(0 == ~E_1~0); 2407#L430-3 assume !(0 == ~E_2~0); 2323#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2324#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2342#L189-12 assume !(1 == ~m_pc~0); 2433#L189-14 is_master_triggered_~__retres1~0 := 0; 2432#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2434#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2392#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2380#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2357#L208-12 assume 1 == ~t1_pc~0; 2329#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2226#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2227#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2263#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2264#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2268#L227-12 assume !(1 == ~t2_pc~0); 2378#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 2379#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2395#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2421#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2411#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2258#L246-12 assume 1 == ~t3_pc~0; 2259#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2215#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2247#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2306#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2307#L526-14 assume !(1 == ~M_E~0); 2308#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2366#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2405#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2321#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2322#L473-3 assume !(1 == ~E_2~0); 2339#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2252#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2253#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2279#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2280#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2345#L663 assume !(0 == start_simulation_~tmp~3); 2429#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2289#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2281#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2282#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2347#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2393#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 2265#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2201#L676 assume !(0 != start_simulation_~tmp___0~1); 2202#L644-1 [2020-11-28 02:57:55,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,206 INFO L82 PathProgramCache]: Analyzing trace with hash -126999211, now seen corresponding path program 1 times [2020-11-28 02:57:55,207 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,207 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258338244] [2020-11-28 02:57:55,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,250 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258338244] [2020-11-28 02:57:55,250 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,250 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:55,251 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121169402] [2020-11-28 02:57:55,251 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:55,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,251 INFO L82 PathProgramCache]: Analyzing trace with hash -719918103, now seen corresponding path program 1 times [2020-11-28 02:57:55,252 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,252 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790323207] [2020-11-28 02:57:55,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,347 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790323207] [2020-11-28 02:57:55,348 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,348 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:55,349 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146161936] [2020-11-28 02:57:55,349 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:55,350 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:55,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 02:57:55,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 02:57:55,352 INFO L87 Difference]: Start difference. First operand 270 states and 398 transitions. cyclomatic complexity: 129 Second operand 4 states. [2020-11-28 02:57:55,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:55,599 INFO L93 Difference]: Finished difference Result 659 states and 947 transitions. [2020-11-28 02:57:55,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 02:57:55,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 947 transitions. [2020-11-28 02:57:55,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 576 [2020-11-28 02:57:55,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 947 transitions. [2020-11-28 02:57:55,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2020-11-28 02:57:55,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2020-11-28 02:57:55,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 947 transitions. [2020-11-28 02:57:55,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:55,621 INFO L691 BuchiCegarLoop]: Abstraction has 659 states and 947 transitions. [2020-11-28 02:57:55,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 947 transitions. [2020-11-28 02:57:55,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 607. [2020-11-28 02:57:55,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 607 states. [2020-11-28 02:57:55,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 880 transitions. [2020-11-28 02:57:55,642 INFO L714 BuchiCegarLoop]: Abstraction has 607 states and 880 transitions. [2020-11-28 02:57:55,643 INFO L594 BuchiCegarLoop]: Abstraction has 607 states and 880 transitions. [2020-11-28 02:57:55,643 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-28 02:57:55,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 607 states and 880 transitions. [2020-11-28 02:57:55,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 555 [2020-11-28 02:57:55,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:55,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:55,651 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,651 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:55,651 INFO L794 eck$LassoCheckResult]: Stem: 3270#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3154#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3155#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3335#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 3241#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3242#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3425#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3333#L288-1 assume !(0 == ~M_E~0); 3334#L410-1 assume !(0 == ~T1_E~0); 3421#L415-1 assume !(0 == ~T2_E~0); 3319#L420-1 assume !(0 == ~T3_E~0); 3320#L425-1 assume !(0 == ~E_1~0); 3359#L430-1 assume !(0 == ~E_2~0); 3260#L435-1 assume !(0 == ~E_3~0); 3261#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3286#L189 assume !(1 == ~m_pc~0); 3440#L189-2 is_master_triggered_~__retres1~0 := 0; 3441#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3414#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3376#L502 assume !(0 != activate_threads_~tmp~1); 3353#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3146#L208 assume !(1 == ~t1_pc~0); 3147#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 3148#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3149#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3223#L510 assume !(0 != activate_threads_~tmp___0~0); 3224#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3236#L227 assume !(1 == ~t2_pc~0); 3361#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 3362#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3370#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3393#L518 assume !(0 != activate_threads_~tmp___1~0); 3384#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3231#L246 assume 1 == ~t3_pc~0; 3232#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3194#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3233#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3308#L526 assume !(0 != activate_threads_~tmp___2~0); 3398#L526-2 assume !(1 == ~M_E~0); 3315#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3316#L458-1 assume !(1 == ~T2_E~0); 3354#L463-1 assume !(1 == ~T3_E~0); 3258#L468-1 assume !(1 == ~E_1~0); 3259#L473-1 assume !(1 == ~E_2~0); 3284#L478-1 assume !(1 == ~E_3~0); 3141#L644-1 [2020-11-28 02:57:55,652 INFO L796 eck$LassoCheckResult]: Loop: 3141#L644-1 assume !false; 3382#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3287#L385 assume !false; 3210#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3211#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3212#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3213#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3293#L338 assume !(0 != eval_~tmp~0); 3433#L400 start_simulation_~kernel_st~0 := 2; 3442#L266-1 start_simulation_~kernel_st~0 := 3; 3422#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3423#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3424#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3326#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3327#L425-3 assume !(0 == ~E_1~0); 3366#L430-3 assume !(0 == ~E_2~0); 3264#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3265#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3291#L189-12 assume !(1 == ~m_pc~0); 3427#L189-14 is_master_triggered_~__retres1~0 := 0; 3701#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3699#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3698#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3697#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3696#L208-12 assume !(1 == ~t1_pc~0); 3695#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 3694#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3693#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3692#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3691#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3632#L227-12 assume !(1 == ~t2_pc~0); 3630#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 3629#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3628#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3627#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3626#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3625#L246-12 assume !(1 == ~t3_pc~0); 3622#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 3623#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3292#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3245#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3246#L526-14 assume !(1 == ~M_E~0); 3323#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3324#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3387#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3262#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3263#L473-3 assume !(1 == ~E_2~0); 3290#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3189#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3190#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3234#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3648#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3647#L663 assume !(0 == start_simulation_~tmp~3); 3646#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3643#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3641#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3640#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 3351#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3352#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 3202#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3140#L676 assume !(0 != start_simulation_~tmp___0~1); 3141#L644-1 [2020-11-28 02:57:55,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1717394188, now seen corresponding path program 1 times [2020-11-28 02:57:55,654 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,654 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355233118] [2020-11-28 02:57:55,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,724 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355233118] [2020-11-28 02:57:55,724 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,725 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:55,725 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52599066] [2020-11-28 02:57:55,725 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:55,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:55,726 INFO L82 PathProgramCache]: Analyzing trace with hash -1652262165, now seen corresponding path program 1 times [2020-11-28 02:57:55,726 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:55,727 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483593620] [2020-11-28 02:57:55,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:55,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:55,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:55,754 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483593620] [2020-11-28 02:57:55,754 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:55,754 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:55,754 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79684834] [2020-11-28 02:57:55,755 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:55,755 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:55,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-28 02:57:55,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-28 02:57:55,756 INFO L87 Difference]: Start difference. First operand 607 states and 880 transitions. cyclomatic complexity: 275 Second operand 4 states. [2020-11-28 02:57:55,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:55,951 INFO L93 Difference]: Finished difference Result 1687 states and 2396 transitions. [2020-11-28 02:57:55,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-28 02:57:55,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1687 states and 2396 transitions. [2020-11-28 02:57:55,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1551 [2020-11-28 02:57:55,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1687 states to 1687 states and 2396 transitions. [2020-11-28 02:57:55,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1687 [2020-11-28 02:57:55,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1687 [2020-11-28 02:57:55,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1687 states and 2396 transitions. [2020-11-28 02:57:55,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:55,995 INFO L691 BuchiCegarLoop]: Abstraction has 1687 states and 2396 transitions. [2020-11-28 02:57:55,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1687 states and 2396 transitions. [2020-11-28 02:57:56,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1687 to 1606. [2020-11-28 02:57:56,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2020-11-28 02:57:56,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2295 transitions. [2020-11-28 02:57:56,049 INFO L714 BuchiCegarLoop]: Abstraction has 1606 states and 2295 transitions. [2020-11-28 02:57:56,049 INFO L594 BuchiCegarLoop]: Abstraction has 1606 states and 2295 transitions. [2020-11-28 02:57:56,050 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-28 02:57:56,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2295 transitions. [2020-11-28 02:57:56,060 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2020-11-28 02:57:56,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:56,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:56,062 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,062 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,063 INFO L794 eck$LassoCheckResult]: Stem: 5570#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5457#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5458#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5650#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 5541#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5542#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5745#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5648#L288-1 assume !(0 == ~M_E~0); 5649#L410-1 assume !(0 == ~T1_E~0); 5740#L415-1 assume !(0 == ~T2_E~0); 5633#L420-1 assume !(0 == ~T3_E~0); 5634#L425-1 assume !(0 == ~E_1~0); 5678#L430-1 assume !(0 == ~E_2~0); 5559#L435-1 assume !(0 == ~E_3~0); 5560#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5584#L189 assume !(1 == ~m_pc~0); 5765#L189-2 is_master_triggered_~__retres1~0 := 0; 5766#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5732#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5695#L502 assume !(0 != activate_threads_~tmp~1); 5670#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5450#L208 assume !(1 == ~t1_pc~0); 5451#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 5452#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5453#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5523#L510 assume !(0 != activate_threads_~tmp___0~0); 5524#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5534#L227 assume !(1 == ~t2_pc~0); 5679#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 5680#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5688#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5710#L518 assume !(0 != activate_threads_~tmp___1~0); 5703#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5530#L246 assume !(1 == ~t3_pc~0); 5494#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 5495#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5531#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5622#L526 assume !(0 != activate_threads_~tmp___2~0); 5716#L526-2 assume !(1 == ~M_E~0); 5629#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5630#L458-1 assume !(1 == ~T2_E~0); 5672#L463-1 assume !(1 == ~T3_E~0); 5557#L468-1 assume !(1 == ~E_1~0); 5558#L473-1 assume !(1 == ~E_2~0); 5583#L478-1 assume !(1 == ~E_3~0); 5618#L644-1 [2020-11-28 02:57:56,063 INFO L796 eck$LassoCheckResult]: Loop: 5618#L644-1 assume !false; 6945#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5739#L385 assume !false; 6944#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6942#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6939#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6938#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6936#L338 assume !(0 != eval_~tmp~0); 6937#L400 start_simulation_~kernel_st~0 := 2; 7038#L266-1 start_simulation_~kernel_st~0 := 3; 7037#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7036#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7035#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7034#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7033#L425-3 assume !(0 == ~E_1~0); 7032#L430-3 assume !(0 == ~E_2~0); 7031#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5596#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5597#L189-12 assume !(1 == ~m_pc~0); 5749#L189-14 is_master_triggered_~__retres1~0 := 0; 5771#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5714#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5668#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5653#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5628#L208-12 assume !(1 == ~t1_pc~0); 5621#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 5467#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5468#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5500#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5501#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5504#L227-12 assume !(1 == ~t2_pc~0); 6981#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 6980#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6979#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6978#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6977#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6976#L246-12 assume !(1 == ~t3_pc~0); 6975#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 6974#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6973#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6972#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6971#L526-14 assume !(1 == ~M_E~0); 6970#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6969#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6968#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6967#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6966#L473-3 assume !(1 == ~E_2~0); 6965#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5490#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5491#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6961#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6960#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6958#L663 assume !(0 == start_simulation_~tmp~3); 6956#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6953#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6951#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6950#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 6949#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6948#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 6947#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6946#L676 assume !(0 != start_simulation_~tmp___0~1); 5618#L644-1 [2020-11-28 02:57:56,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1289378579, now seen corresponding path program 1 times [2020-11-28 02:57:56,064 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,068 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929143601] [2020-11-28 02:57:56,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,133 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929143601] [2020-11-28 02:57:56,133 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,133 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:56,133 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233489639] [2020-11-28 02:57:56,134 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:56,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,134 INFO L82 PathProgramCache]: Analyzing trace with hash -1652262165, now seen corresponding path program 2 times [2020-11-28 02:57:56,135 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,135 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721564233] [2020-11-28 02:57:56,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,167 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721564233] [2020-11-28 02:57:56,168 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,168 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:56,171 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055226869] [2020-11-28 02:57:56,172 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:56,172 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:56,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:56,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:56,173 INFO L87 Difference]: Start difference. First operand 1606 states and 2295 transitions. cyclomatic complexity: 693 Second operand 3 states. [2020-11-28 02:57:56,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:56,205 INFO L93 Difference]: Finished difference Result 1606 states and 2266 transitions. [2020-11-28 02:57:56,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:56,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1606 states and 2266 transitions. [2020-11-28 02:57:56,221 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2020-11-28 02:57:56,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1606 states to 1606 states and 2266 transitions. [2020-11-28 02:57:56,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1606 [2020-11-28 02:57:56,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1606 [2020-11-28 02:57:56,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1606 states and 2266 transitions. [2020-11-28 02:57:56,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:56,240 INFO L691 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2020-11-28 02:57:56,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states and 2266 transitions. [2020-11-28 02:57:56,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 1606. [2020-11-28 02:57:56,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2020-11-28 02:57:56,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2266 transitions. [2020-11-28 02:57:56,274 INFO L714 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2020-11-28 02:57:56,274 INFO L594 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2020-11-28 02:57:56,274 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-28 02:57:56,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2266 transitions. [2020-11-28 02:57:56,286 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2020-11-28 02:57:56,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:56,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:56,289 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,289 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,290 INFO L794 eck$LassoCheckResult]: Stem: 8792#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8676#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8677#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8871#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 8761#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8762#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8968#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8869#L288-1 assume !(0 == ~M_E~0); 8870#L410-1 assume !(0 == ~T1_E~0); 8964#L415-1 assume !(0 == ~T2_E~0); 8854#L420-1 assume !(0 == ~T3_E~0); 8855#L425-1 assume !(0 == ~E_1~0); 8896#L430-1 assume !(0 == ~E_2~0); 8780#L435-1 assume !(0 == ~E_3~0); 8781#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8806#L189 assume !(1 == ~m_pc~0); 8987#L189-2 is_master_triggered_~__retres1~0 := 0; 8988#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8956#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8913#L502 assume !(0 != activate_threads_~tmp~1); 8888#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8669#L208 assume !(1 == ~t1_pc~0); 8670#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 8671#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8672#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8744#L510 assume !(0 != activate_threads_~tmp___0~0); 8745#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8754#L227 assume !(1 == ~t2_pc~0); 8897#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 8898#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8906#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8934#L518 assume !(0 != activate_threads_~tmp___1~0); 8926#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8751#L246 assume !(1 == ~t3_pc~0); 8714#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 8715#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8752#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8842#L526 assume !(0 != activate_threads_~tmp___2~0); 8941#L526-2 assume !(1 == ~M_E~0); 8850#L453-1 assume !(1 == ~T1_E~0); 8851#L458-1 assume !(1 == ~T2_E~0); 8891#L463-1 assume !(1 == ~T3_E~0); 8778#L468-1 assume !(1 == ~E_1~0); 8779#L473-1 assume !(1 == ~E_2~0); 8805#L478-1 assume !(1 == ~E_3~0); 8837#L644-1 [2020-11-28 02:57:56,290 INFO L796 eck$LassoCheckResult]: Loop: 8837#L644-1 assume !false; 9888#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 9881#L385 assume !false; 9873#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9868#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9862#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9857#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8978#L338 assume !(0 != eval_~tmp~0); 8759#L400 start_simulation_~kernel_st~0 := 2; 8760#L266-1 start_simulation_~kernel_st~0 := 3; 8965#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8966#L410-4 assume !(0 == ~T1_E~0); 8967#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8862#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8863#L425-3 assume !(0 == ~E_1~0); 8902#L430-3 assume !(0 == ~E_2~0); 8929#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10251#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10250#L189-12 assume !(1 == ~m_pc~0); 10249#L189-14 is_master_triggered_~__retres1~0 := 0; 10248#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10247#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10246#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10244#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10243#L208-12 assume !(1 == ~t1_pc~0); 10242#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 10240#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10238#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10236#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8725#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8726#L227-12 assume !(1 == ~t2_pc~0); 8872#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 8873#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10228#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10227#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8907#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8908#L246-12 assume !(1 == ~t3_pc~0); 10220#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 10219#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10176#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8765#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8766#L526-14 assume !(1 == ~M_E~0); 9992#L453-3 assume !(1 == ~T1_E~0); 9989#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9986#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9982#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9978#L473-3 assume !(1 == ~E_2~0); 9975#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9969#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9949#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9943#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9939#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9933#L663 assume !(0 == start_simulation_~tmp~3); 9927#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9919#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9916#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9914#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 9912#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9910#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 9902#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 9896#L676 assume !(0 != start_simulation_~tmp___0~1); 8837#L644-1 [2020-11-28 02:57:56,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 1 times [2020-11-28 02:57:56,291 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,291 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413372955] [2020-11-28 02:57:56,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:56,316 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:56,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:56,330 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:56,372 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:56,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,373 INFO L82 PathProgramCache]: Analyzing trace with hash 472681131, now seen corresponding path program 1 times [2020-11-28 02:57:56,373 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,373 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051059434] [2020-11-28 02:57:56,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,403 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051059434] [2020-11-28 02:57:56,403 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,403 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:56,403 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917445914] [2020-11-28 02:57:56,403 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:56,404 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:56,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:56,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:56,404 INFO L87 Difference]: Start difference. First operand 1606 states and 2266 transitions. cyclomatic complexity: 664 Second operand 3 states. [2020-11-28 02:57:56,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:56,522 INFO L93 Difference]: Finished difference Result 2353 states and 3266 transitions. [2020-11-28 02:57:56,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:56,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2353 states and 3266 transitions. [2020-11-28 02:57:56,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2020-11-28 02:57:56,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2353 states to 2353 states and 3266 transitions. [2020-11-28 02:57:56,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2353 [2020-11-28 02:57:56,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2353 [2020-11-28 02:57:56,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2353 states and 3266 transitions. [2020-11-28 02:57:56,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:56,575 INFO L691 BuchiCegarLoop]: Abstraction has 2353 states and 3266 transitions. [2020-11-28 02:57:56,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2353 states and 3266 transitions. [2020-11-28 02:57:56,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2353 to 2353. [2020-11-28 02:57:56,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2353 states. [2020-11-28 02:57:56,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2353 states to 2353 states and 3266 transitions. [2020-11-28 02:57:56,620 INFO L714 BuchiCegarLoop]: Abstraction has 2353 states and 3266 transitions. [2020-11-28 02:57:56,620 INFO L594 BuchiCegarLoop]: Abstraction has 2353 states and 3266 transitions. [2020-11-28 02:57:56,620 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-28 02:57:56,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2353 states and 3266 transitions. [2020-11-28 02:57:56,635 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2020-11-28 02:57:56,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:56,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:56,636 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,636 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,637 INFO L794 eck$LassoCheckResult]: Stem: 12760#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12641#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12642#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12840#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 12728#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12729#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12941#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12837#L288-1 assume 0 == ~M_E~0;~M_E~0 := 1; 12838#L410-1 assume !(0 == ~T1_E~0); 12936#L415-1 assume !(0 == ~T2_E~0); 12823#L420-1 assume !(0 == ~T3_E~0); 12824#L425-1 assume !(0 == ~E_1~0); 12899#L430-1 assume !(0 == ~E_2~0); 12900#L435-1 assume !(0 == ~E_3~0); 12775#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12776#L189 assume !(1 == ~m_pc~0); 12968#L189-2 is_master_triggered_~__retres1~0 := 0; 12969#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12927#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12928#L502 assume !(0 != activate_threads_~tmp~1); 12859#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12860#L208 assume !(1 == ~t1_pc~0); 12660#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 12661#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12758#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12759#L510 assume !(0 != activate_threads_~tmp___0~0); 12722#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12723#L227 assume !(1 == ~t2_pc~0); 12869#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 12870#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12943#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12944#L518 assume !(0 != activate_threads_~tmp___1~0); 12895#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12896#L246 assume !(1 == ~t3_pc~0); 12681#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 12682#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12719#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12813#L526 assume !(0 != activate_threads_~tmp___2~0); 12913#L526-2 assume 1 == ~M_E~0;~M_E~0 := 2; 12819#L453-1 assume !(1 == ~T1_E~0); 12820#L458-1 assume !(1 == ~T2_E~0); 12862#L463-1 assume !(1 == ~T3_E~0); 12745#L468-1 assume !(1 == ~E_1~0); 12746#L473-1 assume !(1 == ~E_2~0); 12774#L478-1 assume !(1 == ~E_3~0); 12804#L644-1 [2020-11-28 02:57:56,637 INFO L796 eck$LassoCheckResult]: Loop: 12804#L644-1 assume !false; 14667#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 14660#L385 assume !false; 14509#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14506#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14503#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14502#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 14500#L338 assume !(0 != eval_~tmp~0); 14501#L400 start_simulation_~kernel_st~0 := 2; 14875#L266-1 start_simulation_~kernel_st~0 := 3; 14873#L410-2 assume !(0 == ~M_E~0); 14872#L410-4 assume !(0 == ~T1_E~0); 14870#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14868#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14866#L425-3 assume !(0 == ~E_1~0); 14864#L430-3 assume !(0 == ~E_2~0); 14862#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14860#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14858#L189-12 assume !(1 == ~m_pc~0); 14856#L189-14 is_master_triggered_~__retres1~0 := 0; 14854#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14852#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14849#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14846#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14843#L208-12 assume !(1 == ~t1_pc~0); 14840#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 14838#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14835#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14832#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14829#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14825#L227-12 assume !(1 == ~t2_pc~0); 14821#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 14818#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14815#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14810#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14806#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14802#L246-12 assume !(1 == ~t3_pc~0); 14798#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 14794#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14790#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14786#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14782#L526-14 assume !(1 == ~M_E~0); 14779#L453-3 assume !(1 == ~T1_E~0); 14775#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14771#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12749#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12750#L473-3 assume !(1 == ~E_2~0); 12783#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12677#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12678#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14748#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14747#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 14746#L663 assume !(0 == start_simulation_~tmp~3); 14744#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14740#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14737#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14734#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 14732#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14730#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 14672#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 14668#L676 assume !(0 != start_simulation_~tmp___0~1); 12804#L644-1 [2020-11-28 02:57:56,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,638 INFO L82 PathProgramCache]: Analyzing trace with hash 600988817, now seen corresponding path program 1 times [2020-11-28 02:57:56,638 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,639 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251837770] [2020-11-28 02:57:56,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,660 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251837770] [2020-11-28 02:57:56,660 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,660 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:56,660 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955484436] [2020-11-28 02:57:56,660 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:56,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,661 INFO L82 PathProgramCache]: Analyzing trace with hash -1555904979, now seen corresponding path program 1 times [2020-11-28 02:57:56,661 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,661 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976678343] [2020-11-28 02:57:56,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,697 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976678343] [2020-11-28 02:57:56,697 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,697 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:56,697 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089565334] [2020-11-28 02:57:56,698 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:56,698 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:56,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:56,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:56,698 INFO L87 Difference]: Start difference. First operand 2353 states and 3266 transitions. cyclomatic complexity: 917 Second operand 3 states. [2020-11-28 02:57:56,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:56,746 INFO L93 Difference]: Finished difference Result 1606 states and 2219 transitions. [2020-11-28 02:57:56,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:56,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1606 states and 2219 transitions. [2020-11-28 02:57:56,761 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2020-11-28 02:57:56,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1606 states to 1606 states and 2219 transitions. [2020-11-28 02:57:56,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1606 [2020-11-28 02:57:56,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1606 [2020-11-28 02:57:56,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1606 states and 2219 transitions. [2020-11-28 02:57:56,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:56,782 INFO L691 BuchiCegarLoop]: Abstraction has 1606 states and 2219 transitions. [2020-11-28 02:57:56,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states and 2219 transitions. [2020-11-28 02:57:56,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 1606. [2020-11-28 02:57:56,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2020-11-28 02:57:56,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2219 transitions. [2020-11-28 02:57:56,847 INFO L714 BuchiCegarLoop]: Abstraction has 1606 states and 2219 transitions. [2020-11-28 02:57:56,849 INFO L594 BuchiCegarLoop]: Abstraction has 1606 states and 2219 transitions. [2020-11-28 02:57:56,849 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-28 02:57:56,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2219 transitions. [2020-11-28 02:57:56,862 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2020-11-28 02:57:56,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:56,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:56,863 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,863 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:56,864 INFO L794 eck$LassoCheckResult]: Stem: 16719#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16609#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16610#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16793#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 16690#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16691#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16882#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16791#L288-1 assume !(0 == ~M_E~0); 16792#L410-1 assume !(0 == ~T1_E~0); 16878#L415-1 assume !(0 == ~T2_E~0); 16778#L420-1 assume !(0 == ~T3_E~0); 16779#L425-1 assume !(0 == ~E_1~0); 16819#L430-1 assume !(0 == ~E_2~0); 16708#L435-1 assume !(0 == ~E_3~0); 16709#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16732#L189 assume !(1 == ~m_pc~0); 16898#L189-2 is_master_triggered_~__retres1~0 := 0; 16899#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16870#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16836#L502 assume !(0 != activate_threads_~tmp~1); 16812#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16602#L208 assume !(1 == ~t1_pc~0); 16603#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 16604#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16605#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16675#L510 assume !(0 != activate_threads_~tmp___0~0); 16676#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16685#L227 assume !(1 == ~t2_pc~0); 16820#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 16821#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16830#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16851#L518 assume !(0 != activate_threads_~tmp___1~0); 16844#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16682#L246 assume !(1 == ~t3_pc~0); 16647#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 16648#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16683#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16766#L526 assume !(0 != activate_threads_~tmp___2~0); 16855#L526-2 assume !(1 == ~M_E~0); 16773#L453-1 assume !(1 == ~T1_E~0); 16774#L458-1 assume !(1 == ~T2_E~0); 16814#L463-1 assume !(1 == ~T3_E~0); 16706#L468-1 assume !(1 == ~E_1~0); 16707#L473-1 assume !(1 == ~E_2~0); 16731#L478-1 assume !(1 == ~E_3~0); 16761#L644-1 [2020-11-28 02:57:56,864 INFO L796 eck$LassoCheckResult]: Loop: 16761#L644-1 assume !false; 17874#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 17331#L385 assume !false; 17871#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17867#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17863#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17861#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 17859#L338 assume !(0 != eval_~tmp~0); 17860#L400 start_simulation_~kernel_st~0 := 2; 18143#L266-1 start_simulation_~kernel_st~0 := 3; 18141#L410-2 assume !(0 == ~M_E~0); 18139#L410-4 assume !(0 == ~T1_E~0); 18137#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18134#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17966#L425-3 assume !(0 == ~E_1~0); 17965#L430-3 assume !(0 == ~E_2~0); 17964#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17963#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17962#L189-12 assume !(1 == ~m_pc~0); 17961#L189-14 is_master_triggered_~__retres1~0 := 0; 17960#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17959#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17958#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17957#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17955#L208-12 assume !(1 == ~t1_pc~0); 17953#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 17951#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17949#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17947#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17945#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17943#L227-12 assume !(1 == ~t2_pc~0); 17940#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 17938#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17936#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17934#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17932#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17929#L246-12 assume !(1 == ~t3_pc~0); 17927#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 17925#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17923#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17921#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17919#L526-14 assume !(1 == ~M_E~0); 17917#L453-3 assume !(1 == ~T1_E~0); 17915#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17913#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17911#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17909#L473-3 assume !(1 == ~E_2~0); 17907#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17905#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17901#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17897#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17895#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 17893#L663 assume !(0 == start_simulation_~tmp~3); 17891#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17888#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17886#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17885#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 17883#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17881#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 17879#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 17877#L676 assume !(0 != start_simulation_~tmp___0~1); 16761#L644-1 [2020-11-28 02:57:56,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 2 times [2020-11-28 02:57:56,865 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,865 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575714597] [2020-11-28 02:57:56,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:56,884 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:56,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:56,894 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:56,917 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:56,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:56,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1555904979, now seen corresponding path program 2 times [2020-11-28 02:57:56,919 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:56,920 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635741043] [2020-11-28 02:57:56,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:56,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:56,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:56,967 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635741043] [2020-11-28 02:57:56,967 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:56,967 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:56,967 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679429683] [2020-11-28 02:57:56,967 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:56,968 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:56,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:56,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:56,968 INFO L87 Difference]: Start difference. First operand 1606 states and 2219 transitions. cyclomatic complexity: 617 Second operand 5 states. [2020-11-28 02:57:57,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:57,093 INFO L93 Difference]: Finished difference Result 2760 states and 3758 transitions. [2020-11-28 02:57:57,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-28 02:57:57,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2760 states and 3758 transitions. [2020-11-28 02:57:57,112 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2684 [2020-11-28 02:57:57,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2760 states to 2760 states and 3758 transitions. [2020-11-28 02:57:57,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2760 [2020-11-28 02:57:57,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2760 [2020-11-28 02:57:57,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2760 states and 3758 transitions. [2020-11-28 02:57:57,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:57,140 INFO L691 BuchiCegarLoop]: Abstraction has 2760 states and 3758 transitions. [2020-11-28 02:57:57,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states and 3758 transitions. [2020-11-28 02:57:57,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1633. [2020-11-28 02:57:57,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1633 states. [2020-11-28 02:57:57,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1633 states to 1633 states and 2246 transitions. [2020-11-28 02:57:57,185 INFO L714 BuchiCegarLoop]: Abstraction has 1633 states and 2246 transitions. [2020-11-28 02:57:57,185 INFO L594 BuchiCegarLoop]: Abstraction has 1633 states and 2246 transitions. [2020-11-28 02:57:57,185 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-28 02:57:57,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1633 states and 2246 transitions. [2020-11-28 02:57:57,192 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1572 [2020-11-28 02:57:57,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:57,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:57,201 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,201 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,202 INFO L794 eck$LassoCheckResult]: Stem: 21104#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 20991#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20992#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21188#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 21075#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21076#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21287#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21186#L288-1 assume !(0 == ~M_E~0); 21187#L410-1 assume !(0 == ~T1_E~0); 21282#L415-1 assume !(0 == ~T2_E~0); 21172#L420-1 assume !(0 == ~T3_E~0); 21173#L425-1 assume !(0 == ~E_1~0); 21218#L430-1 assume !(0 == ~E_2~0); 21094#L435-1 assume !(0 == ~E_3~0); 21095#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21120#L189 assume !(1 == ~m_pc~0); 21311#L189-2 is_master_triggered_~__retres1~0 := 0; 21312#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21275#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21235#L502 assume !(0 != activate_threads_~tmp~1); 21210#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20984#L208 assume !(1 == ~t1_pc~0); 20985#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 20986#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20987#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21058#L510 assume !(0 != activate_threads_~tmp___0~0); 21059#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21069#L227 assume !(1 == ~t2_pc~0); 21219#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 21220#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21229#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21256#L518 assume !(0 != activate_threads_~tmp___1~0); 21244#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21065#L246 assume !(1 == ~t3_pc~0); 21028#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 21029#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21066#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21159#L526 assume !(0 != activate_threads_~tmp___2~0); 21260#L526-2 assume !(1 == ~M_E~0); 21168#L453-1 assume !(1 == ~T1_E~0); 21169#L458-1 assume !(1 == ~T2_E~0); 21213#L463-1 assume !(1 == ~T3_E~0); 21092#L468-1 assume !(1 == ~E_1~0); 21093#L473-1 assume !(1 == ~E_2~0); 21119#L478-1 assume !(1 == ~E_3~0); 20979#L644-1 [2020-11-28 02:57:57,202 INFO L796 eck$LassoCheckResult]: Loop: 20979#L644-1 assume !false; 21100#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 21121#L385 assume !false; 21045#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21046#L301 assume !(0 == ~m_st~0); 21071#L305 assume !(0 == ~t1_st~0); 21253#L309 assume !(0 == ~t2_st~0); 21141#L313 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 21047#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21048#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 22243#L338 assume !(0 != eval_~tmp~0); 21073#L400 start_simulation_~kernel_st~0 := 2; 21074#L266-1 start_simulation_~kernel_st~0 := 3; 21283#L410-2 assume !(0 == ~M_E~0); 21284#L410-4 assume !(0 == ~T1_E~0); 21306#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21307#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21224#L425-3 assume !(0 == ~E_1~0); 21225#L430-3 assume !(0 == ~E_2~0); 21098#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21099#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21291#L189-12 assume !(1 == ~m_pc~0); 21292#L189-14 is_master_triggered_~__retres1~0 := 0; 21318#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21319#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21208#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21209#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21166#L208-12 assume !(1 == ~t1_pc~0); 21167#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 21001#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21002#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21036#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21037#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21199#L227-12 assume !(1 == ~t2_pc~0); 21201#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 21211#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21212#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21242#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21243#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21030#L246-12 assume !(1 == ~t3_pc~0); 21031#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 22531#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21134#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21135#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21081#L526-14 assume !(1 == ~M_E~0); 21082#L453-3 assume !(1 == ~T1_E~0); 21222#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21223#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21096#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21097#L473-3 assume !(1 == ~E_2~0); 21160#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21161#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21067#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 21051#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21052#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 21143#L663 assume !(0 == start_simulation_~tmp~3); 21255#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21295#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22512#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22510#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 21206#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21207#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 21035#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 20978#L676 assume !(0 != start_simulation_~tmp___0~1); 20979#L644-1 [2020-11-28 02:57:57,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,202 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 3 times [2020-11-28 02:57:57,203 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,203 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805042506] [2020-11-28 02:57:57,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,214 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,224 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,259 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:57,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,260 INFO L82 PathProgramCache]: Analyzing trace with hash 1208288503, now seen corresponding path program 1 times [2020-11-28 02:57:57,261 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,262 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562350776] [2020-11-28 02:57:57,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:57,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:57,338 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562350776] [2020-11-28 02:57:57,339 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:57,339 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-28 02:57:57,339 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455236953] [2020-11-28 02:57:57,339 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:57,340 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:57,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-28 02:57:57,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-28 02:57:57,341 INFO L87 Difference]: Start difference. First operand 1633 states and 2246 transitions. cyclomatic complexity: 617 Second operand 5 states. [2020-11-28 02:57:57,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:57,498 INFO L93 Difference]: Finished difference Result 2337 states and 3223 transitions. [2020-11-28 02:57:57,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-28 02:57:57,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2337 states and 3223 transitions. [2020-11-28 02:57:57,513 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2276 [2020-11-28 02:57:57,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2337 states to 2337 states and 3223 transitions. [2020-11-28 02:57:57,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2337 [2020-11-28 02:57:57,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2337 [2020-11-28 02:57:57,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2337 states and 3223 transitions. [2020-11-28 02:57:57,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:57,539 INFO L691 BuchiCegarLoop]: Abstraction has 2337 states and 3223 transitions. [2020-11-28 02:57:57,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2337 states and 3223 transitions. [2020-11-28 02:57:57,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2337 to 1645. [2020-11-28 02:57:57,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2020-11-28 02:57:57,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 2227 transitions. [2020-11-28 02:57:57,586 INFO L714 BuchiCegarLoop]: Abstraction has 1645 states and 2227 transitions. [2020-11-28 02:57:57,586 INFO L594 BuchiCegarLoop]: Abstraction has 1645 states and 2227 transitions. [2020-11-28 02:57:57,586 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-28 02:57:57,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1645 states and 2227 transitions. [2020-11-28 02:57:57,594 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1584 [2020-11-28 02:57:57,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:57,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:57,595 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,595 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,596 INFO L794 eck$LassoCheckResult]: Stem: 25095#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 24974#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24975#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25177#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 25063#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25064#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25281#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25175#L288-1 assume !(0 == ~M_E~0); 25176#L410-1 assume !(0 == ~T1_E~0); 25277#L415-1 assume !(0 == ~T2_E~0); 25161#L420-1 assume !(0 == ~T3_E~0); 25162#L425-1 assume !(0 == ~E_1~0); 25208#L430-1 assume !(0 == ~E_2~0); 25083#L435-1 assume !(0 == ~E_3~0); 25084#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25112#L189 assume !(1 == ~m_pc~0); 25303#L189-2 is_master_triggered_~__retres1~0 := 0; 25304#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25270#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25227#L502 assume !(0 != activate_threads_~tmp~1); 25200#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24967#L208 assume !(1 == ~t1_pc~0); 24968#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 24969#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24970#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25046#L510 assume !(0 != activate_threads_~tmp___0~0); 25047#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25056#L227 assume !(1 == ~t2_pc~0); 25210#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 25211#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25222#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25251#L518 assume !(0 != activate_threads_~tmp___1~0); 25240#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25051#L246 assume !(1 == ~t3_pc~0); 25014#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 25015#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25054#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25148#L526 assume !(0 != activate_threads_~tmp___2~0); 25254#L526-2 assume !(1 == ~M_E~0); 25157#L453-1 assume !(1 == ~T1_E~0); 25158#L458-1 assume !(1 == ~T2_E~0); 25201#L463-1 assume !(1 == ~T3_E~0); 25081#L468-1 assume !(1 == ~E_1~0); 25082#L473-1 assume !(1 == ~E_2~0); 25111#L478-1 assume !(1 == ~E_3~0); 25143#L644-1 [2020-11-28 02:57:57,596 INFO L796 eck$LassoCheckResult]: Loop: 25143#L644-1 assume !false; 25832#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 25625#L385 assume !false; 25823#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25818#L301 assume !(0 == ~m_st~0); 25819#L305 assume !(0 == ~t1_st~0); 25815#L309 assume !(0 == ~t2_st~0); 25816#L313 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 25817#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25777#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 25778#L338 assume !(0 != eval_~tmp~0); 26048#L400 start_simulation_~kernel_st~0 := 2; 26047#L266-1 start_simulation_~kernel_st~0 := 3; 26046#L410-2 assume !(0 == ~M_E~0); 26045#L410-4 assume !(0 == ~T1_E~0); 26044#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26043#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26042#L425-3 assume !(0 == ~E_1~0); 26041#L430-3 assume !(0 == ~E_2~0); 26040#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26038#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26036#L189-12 assume !(1 == ~m_pc~0); 26034#L189-14 is_master_triggered_~__retres1~0 := 0; 26032#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26030#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26028#L502-12 assume !(0 != activate_threads_~tmp~1); 26026#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26024#L208-12 assume !(1 == ~t1_pc~0); 26022#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 26020#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26018#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26016#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26015#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26014#L227-12 assume !(1 == ~t2_pc~0); 26011#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 26009#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26007#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26005#L518-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26003#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26001#L246-12 assume !(1 == ~t3_pc~0); 25999#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 25997#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25995#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25993#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25991#L526-14 assume !(1 == ~M_E~0); 25989#L453-3 assume !(1 == ~T1_E~0); 25986#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25984#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25982#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25980#L473-3 assume !(1 == ~E_2~0); 25978#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25976#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25895#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25890#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25887#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 25883#L663 assume !(0 == start_simulation_~tmp~3); 25880#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25873#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25870#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25862#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 25857#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25851#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 25845#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 25841#L676 assume !(0 != start_simulation_~tmp___0~1); 25143#L644-1 [2020-11-28 02:57:57,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,597 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 4 times [2020-11-28 02:57:57,597 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,597 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073416842] [2020-11-28 02:57:57,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,612 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,622 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,634 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:57,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,635 INFO L82 PathProgramCache]: Analyzing trace with hash -637078663, now seen corresponding path program 1 times [2020-11-28 02:57:57,635 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,636 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638391780] [2020-11-28 02:57:57,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:57,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:57,672 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638391780] [2020-11-28 02:57:57,672 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:57,672 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:57,674 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426071060] [2020-11-28 02:57:57,674 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-28 02:57:57,674 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:57,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:57,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:57,676 INFO L87 Difference]: Start difference. First operand 1645 states and 2227 transitions. cyclomatic complexity: 586 Second operand 3 states. [2020-11-28 02:57:57,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:57,724 INFO L93 Difference]: Finished difference Result 2306 states and 3079 transitions. [2020-11-28 02:57:57,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:57,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2306 states and 3079 transitions. [2020-11-28 02:57:57,738 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2243 [2020-11-28 02:57:57,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2306 states to 2306 states and 3079 transitions. [2020-11-28 02:57:57,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2306 [2020-11-28 02:57:57,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2306 [2020-11-28 02:57:57,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2306 states and 3079 transitions. [2020-11-28 02:57:57,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:57,768 INFO L691 BuchiCegarLoop]: Abstraction has 2306 states and 3079 transitions. [2020-11-28 02:57:57,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2306 states and 3079 transitions. [2020-11-28 02:57:57,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2306 to 2306. [2020-11-28 02:57:57,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2306 states. [2020-11-28 02:57:57,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2306 states to 2306 states and 3079 transitions. [2020-11-28 02:57:57,825 INFO L714 BuchiCegarLoop]: Abstraction has 2306 states and 3079 transitions. [2020-11-28 02:57:57,825 INFO L594 BuchiCegarLoop]: Abstraction has 2306 states and 3079 transitions. [2020-11-28 02:57:57,825 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-28 02:57:57,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2306 states and 3079 transitions. [2020-11-28 02:57:57,833 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2243 [2020-11-28 02:57:57,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:57,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:57,834 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,834 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:57,834 INFO L794 eck$LassoCheckResult]: Stem: 29048#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 28931#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28932#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29138#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 29019#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29020#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29229#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29136#L288-1 assume !(0 == ~M_E~0); 29137#L410-1 assume !(0 == ~T1_E~0); 29225#L415-1 assume !(0 == ~T2_E~0); 29121#L420-1 assume !(0 == ~T3_E~0); 29122#L425-1 assume !(0 == ~E_1~0); 29164#L430-1 assume !(0 == ~E_2~0); 29039#L435-1 assume !(0 == ~E_3~0); 29040#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29064#L189 assume !(1 == ~m_pc~0); 29250#L189-2 is_master_triggered_~__retres1~0 := 0; 29251#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29218#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29182#L502 assume !(0 != activate_threads_~tmp~1); 29158#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28924#L208 assume !(1 == ~t1_pc~0); 28925#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 28926#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28927#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 29002#L510 assume !(0 != activate_threads_~tmp___0~0); 29003#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29012#L227 assume !(1 == ~t2_pc~0); 29166#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 29167#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29176#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29200#L518 assume !(0 != activate_threads_~tmp___1~0); 29192#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29009#L246 assume !(1 == ~t3_pc~0); 28969#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 28970#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29010#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29108#L526 assume !(0 != activate_threads_~tmp___2~0); 29204#L526-2 assume !(1 == ~M_E~0); 29117#L453-1 assume !(1 == ~T1_E~0); 29118#L458-1 assume !(1 == ~T2_E~0); 29160#L463-1 assume !(1 == ~T3_E~0); 29037#L468-1 assume !(1 == ~E_1~0); 29038#L473-1 assume !(1 == ~E_2~0); 29063#L478-1 assume !(1 == ~E_3~0); 29102#L644-1 assume !false; 30554#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 29851#L385 [2020-11-28 02:57:57,834 INFO L796 eck$LassoCheckResult]: Loop: 29851#L385 assume !false; 30232#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30227#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30225#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30223#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30220#L338 assume 0 != eval_~tmp~0; 30216#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 30213#L346 assume !(0 != eval_~tmp_ndt_1~0); 29399#L343 assume !(0 == ~t1_st~0); 29393#L357 assume !(0 == ~t2_st~0); 30553#L371 assume !(0 == ~t3_st~0); 29851#L385 [2020-11-28 02:57:57,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,835 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 1 times [2020-11-28 02:57:57,835 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,835 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826698476] [2020-11-28 02:57:57,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,846 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,854 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,865 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:57,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1333816930, now seen corresponding path program 1 times [2020-11-28 02:57:57,867 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,867 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479929305] [2020-11-28 02:57:57,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,871 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:57,874 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:57,876 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:57,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:57,877 INFO L82 PathProgramCache]: Analyzing trace with hash 451456976, now seen corresponding path program 1 times [2020-11-28 02:57:57,877 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:57,877 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652122976] [2020-11-28 02:57:57,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:57,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:57,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:57,934 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652122976] [2020-11-28 02:57:57,935 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:57,935 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:57,935 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546922131] [2020-11-28 02:57:58,044 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:58,045 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:58,045 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:58,045 INFO L87 Difference]: Start difference. First operand 2306 states and 3079 transitions. cyclomatic complexity: 780 Second operand 3 states. [2020-11-28 02:57:58,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:58,328 INFO L93 Difference]: Finished difference Result 4206 states and 5530 transitions. [2020-11-28 02:57:58,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:58,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4206 states and 5530 transitions. [2020-11-28 02:57:58,350 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 3876 [2020-11-28 02:57:58,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4206 states to 4206 states and 5530 transitions. [2020-11-28 02:57:58,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4206 [2020-11-28 02:57:58,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4206 [2020-11-28 02:57:58,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4206 states and 5530 transitions. [2020-11-28 02:57:58,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:58,399 INFO L691 BuchiCegarLoop]: Abstraction has 4206 states and 5530 transitions. [2020-11-28 02:57:58,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4206 states and 5530 transitions. [2020-11-28 02:57:58,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4206 to 4108. [2020-11-28 02:57:58,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4108 states. [2020-11-28 02:57:58,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4108 states to 4108 states and 5404 transitions. [2020-11-28 02:57:58,484 INFO L714 BuchiCegarLoop]: Abstraction has 4108 states and 5404 transitions. [2020-11-28 02:57:58,484 INFO L594 BuchiCegarLoop]: Abstraction has 4108 states and 5404 transitions. [2020-11-28 02:57:58,484 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-28 02:57:58,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4108 states and 5404 transitions. [2020-11-28 02:57:58,498 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 3778 [2020-11-28 02:57:58,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:58,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:58,499 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:58,499 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:58,500 INFO L794 eck$LassoCheckResult]: Stem: 35578#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 35451#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 35452#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35666#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 35546#L273-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 35547#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38510#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38509#L288-1 assume !(0 == ~M_E~0); 38508#L410-1 assume !(0 == ~T1_E~0); 38507#L415-1 assume !(0 == ~T2_E~0); 38506#L420-1 assume !(0 == ~T3_E~0); 38505#L425-1 assume !(0 == ~E_1~0); 38504#L430-1 assume !(0 == ~E_2~0); 38503#L435-1 assume !(0 == ~E_3~0); 38502#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38501#L189 assume !(1 == ~m_pc~0); 38500#L189-2 is_master_triggered_~__retres1~0 := 0; 38499#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38498#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 38496#L502 assume !(0 != activate_threads_~tmp~1); 38494#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38493#L208 assume !(1 == ~t1_pc~0); 38492#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 35446#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35447#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35524#L510 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35525#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35709#L227 assume !(1 == ~t2_pc~0); 35699#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 35700#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35711#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35740#L518 assume !(0 != activate_threads_~tmp___1~0); 35727#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35728#L246 assume !(1 == ~t3_pc~0); 38280#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 38278#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35637#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35638#L526 assume !(0 != activate_threads_~tmp___2~0); 38269#L526-2 assume !(1 == ~M_E~0); 38267#L453-1 assume !(1 == ~T1_E~0); 35689#L458-1 assume !(1 == ~T2_E~0); 35690#L463-1 assume !(1 == ~T3_E~0); 35563#L468-1 assume !(1 == ~E_1~0); 35564#L473-1 assume !(1 == ~E_2~0); 35593#L478-1 assume !(1 == ~E_3~0); 35632#L644-1 assume !false; 39294#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 38340#L385 [2020-11-28 02:57:58,500 INFO L796 eck$LassoCheckResult]: Loop: 38340#L385 assume !false; 39290#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 39287#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 39285#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 39270#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 36343#L338 assume 0 != eval_~tmp~0; 36339#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 36341#L346 assume !(0 != eval_~tmp_ndt_1~0); 36290#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 36090#L360 assume !(0 != eval_~tmp_ndt_2~0); 36091#L357 assume !(0 == ~t2_st~0); 38344#L371 assume !(0 == ~t3_st~0); 38340#L385 [2020-11-28 02:57:58,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:58,500 INFO L82 PathProgramCache]: Analyzing trace with hash 216645527, now seen corresponding path program 1 times [2020-11-28 02:57:58,500 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:58,501 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682926002] [2020-11-28 02:57:58,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:58,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:58,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:58,524 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682926002] [2020-11-28 02:57:58,524 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:58,524 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:58,525 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449955040] [2020-11-28 02:57:58,525 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-28 02:57:58,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:58,525 INFO L82 PathProgramCache]: Analyzing trace with hash -1605322483, now seen corresponding path program 1 times [2020-11-28 02:57:58,525 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:58,526 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144014839] [2020-11-28 02:57:58,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:58,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,529 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,530 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,535 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:58,653 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:58,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:58,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:58,654 INFO L87 Difference]: Start difference. First operand 4108 states and 5404 transitions. cyclomatic complexity: 1307 Second operand 3 states. [2020-11-28 02:57:58,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:58,677 INFO L93 Difference]: Finished difference Result 3284 states and 4330 transitions. [2020-11-28 02:57:58,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:58,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3284 states and 4330 transitions. [2020-11-28 02:57:58,694 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3211 [2020-11-28 02:57:58,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3284 states to 3284 states and 4330 transitions. [2020-11-28 02:57:58,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3284 [2020-11-28 02:57:58,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3284 [2020-11-28 02:57:58,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3284 states and 4330 transitions. [2020-11-28 02:57:58,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:58,721 INFO L691 BuchiCegarLoop]: Abstraction has 3284 states and 4330 transitions. [2020-11-28 02:57:58,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3284 states and 4330 transitions. [2020-11-28 02:57:58,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3284 to 3284. [2020-11-28 02:57:58,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3284 states. [2020-11-28 02:57:58,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3284 states to 3284 states and 4330 transitions. [2020-11-28 02:57:58,784 INFO L714 BuchiCegarLoop]: Abstraction has 3284 states and 4330 transitions. [2020-11-28 02:57:58,784 INFO L594 BuchiCegarLoop]: Abstraction has 3284 states and 4330 transitions. [2020-11-28 02:57:58,784 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-28 02:57:58,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3284 states and 4330 transitions. [2020-11-28 02:57:58,796 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3211 [2020-11-28 02:57:58,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:58,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:58,800 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:58,800 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:58,801 INFO L794 eck$LassoCheckResult]: Stem: 42967#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 42849#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42850#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43046#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 42939#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42940#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43137#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43044#L288-1 assume !(0 == ~M_E~0); 43045#L410-1 assume !(0 == ~T1_E~0); 43133#L415-1 assume !(0 == ~T2_E~0); 43031#L420-1 assume !(0 == ~T3_E~0); 43032#L425-1 assume !(0 == ~E_1~0); 43075#L430-1 assume !(0 == ~E_2~0); 42957#L435-1 assume !(0 == ~E_3~0); 42958#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42980#L189 assume !(1 == ~m_pc~0); 43157#L189-2 is_master_triggered_~__retres1~0 := 0; 43158#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43126#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43090#L502 assume !(0 != activate_threads_~tmp~1); 43066#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42842#L208 assume !(1 == ~t1_pc~0); 42843#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 42844#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42845#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 42920#L510 assume !(0 != activate_threads_~tmp___0~0); 42921#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42931#L227 assume !(1 == ~t2_pc~0); 43076#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 43077#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43084#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43106#L518 assume !(0 != activate_threads_~tmp___1~0); 43099#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42928#L246 assume !(1 == ~t3_pc~0); 42886#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 42887#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42929#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 43020#L526 assume !(0 != activate_threads_~tmp___2~0); 43111#L526-2 assume !(1 == ~M_E~0); 43027#L453-1 assume !(1 == ~T1_E~0); 43028#L458-1 assume !(1 == ~T2_E~0); 43069#L463-1 assume !(1 == ~T3_E~0); 42955#L468-1 assume !(1 == ~E_1~0); 42956#L473-1 assume !(1 == ~E_2~0); 42979#L478-1 assume !(1 == ~E_3~0); 43015#L644-1 assume !false; 44271#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 44269#L385 [2020-11-28 02:57:58,801 INFO L796 eck$LassoCheckResult]: Loop: 44269#L385 assume !false; 45352#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45351#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45350#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 45349#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 45348#L338 assume 0 != eval_~tmp~0; 45347#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 45346#L346 assume !(0 != eval_~tmp_ndt_1~0); 45345#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 45344#L360 assume !(0 != eval_~tmp_ndt_2~0); 44323#L357 assume !(0 == ~t2_st~0); 44270#L371 assume !(0 == ~t3_st~0); 44269#L385 [2020-11-28 02:57:58,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:58,802 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 2 times [2020-11-28 02:57:58,802 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:58,803 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102828983] [2020-11-28 02:57:58,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:58,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,814 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,822 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,837 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:58,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:58,839 INFO L82 PathProgramCache]: Analyzing trace with hash -1605322483, now seen corresponding path program 2 times [2020-11-28 02:57:58,839 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:58,839 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34098858] [2020-11-28 02:57:58,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:58,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,843 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:58,845 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:58,848 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:58,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:58,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1106290015, now seen corresponding path program 1 times [2020-11-28 02:57:58,849 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:58,851 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961805496] [2020-11-28 02:57:58,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:58,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:58,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:58,882 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961805496] [2020-11-28 02:57:58,883 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:58,883 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-28 02:57:58,883 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110210860] [2020-11-28 02:57:58,985 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:58,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:58,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:58,986 INFO L87 Difference]: Start difference. First operand 3284 states and 4330 transitions. cyclomatic complexity: 1053 Second operand 3 states. [2020-11-28 02:57:59,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:59,056 INFO L93 Difference]: Finished difference Result 5579 states and 7303 transitions. [2020-11-28 02:57:59,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:59,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5579 states and 7303 transitions. [2020-11-28 02:57:59,082 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 5481 [2020-11-28 02:57:59,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5579 states to 5579 states and 7303 transitions. [2020-11-28 02:57:59,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5579 [2020-11-28 02:57:59,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5579 [2020-11-28 02:57:59,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5579 states and 7303 transitions. [2020-11-28 02:57:59,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:59,128 INFO L691 BuchiCegarLoop]: Abstraction has 5579 states and 7303 transitions. [2020-11-28 02:57:59,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5579 states and 7303 transitions. [2020-11-28 02:57:59,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5579 to 5299. [2020-11-28 02:57:59,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5299 states. [2020-11-28 02:57:59,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5299 states to 5299 states and 6973 transitions. [2020-11-28 02:57:59,269 INFO L714 BuchiCegarLoop]: Abstraction has 5299 states and 6973 transitions. [2020-11-28 02:57:59,269 INFO L594 BuchiCegarLoop]: Abstraction has 5299 states and 6973 transitions. [2020-11-28 02:57:59,269 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-28 02:57:59,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5299 states and 6973 transitions. [2020-11-28 02:57:59,288 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 5201 [2020-11-28 02:57:59,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:59,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:59,289 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:59,289 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:59,289 INFO L794 eck$LassoCheckResult]: Stem: 51838#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 51720#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51721#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 51927#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 51808#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51809#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52045#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51925#L288-1 assume !(0 == ~M_E~0); 51926#L410-1 assume !(0 == ~T1_E~0); 52041#L415-1 assume !(0 == ~T2_E~0); 51911#L420-1 assume !(0 == ~T3_E~0); 51912#L425-1 assume !(0 == ~E_1~0); 51958#L430-1 assume !(0 == ~E_2~0); 51827#L435-1 assume !(0 == ~E_3~0); 51828#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51855#L189 assume !(1 == ~m_pc~0); 52077#L189-2 is_master_triggered_~__retres1~0 := 0; 52078#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52031#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51980#L502 assume !(0 != activate_threads_~tmp~1); 51949#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51713#L208 assume !(1 == ~t1_pc~0); 51714#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 51715#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51716#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51792#L510 assume !(0 != activate_threads_~tmp___0~0); 51793#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51803#L227 assume !(1 == ~t2_pc~0); 51959#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 51960#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51971#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52008#L518 assume !(0 != activate_threads_~tmp___1~0); 51996#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51800#L246 assume !(1 == ~t3_pc~0); 51758#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 51759#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51801#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51898#L526 assume !(0 != activate_threads_~tmp___2~0); 52015#L526-2 assume !(1 == ~M_E~0); 51906#L453-1 assume !(1 == ~T1_E~0); 51907#L458-1 assume !(1 == ~T2_E~0); 51951#L463-1 assume !(1 == ~T3_E~0); 51825#L468-1 assume !(1 == ~E_1~0); 51826#L473-1 assume !(1 == ~E_2~0); 51853#L478-1 assume !(1 == ~E_3~0); 51891#L644-1 assume !false; 52948#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 52945#L385 [2020-11-28 02:57:59,290 INFO L796 eck$LassoCheckResult]: Loop: 52945#L385 assume !false; 56234#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 56232#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 56231#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 56230#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 56229#L338 assume 0 != eval_~tmp~0; 56227#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 56226#L346 assume !(0 != eval_~tmp_ndt_1~0); 56225#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 56224#L360 assume !(0 != eval_~tmp_ndt_2~0); 56096#L357 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 52950#L374 assume !(0 != eval_~tmp_ndt_3~0); 52952#L371 assume !(0 == ~t3_st~0); 52945#L385 [2020-11-28 02:57:59,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 3 times [2020-11-28 02:57:59,291 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,291 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175836643] [2020-11-28 02:57:59,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,303 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,314 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,324 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:59,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,325 INFO L82 PathProgramCache]: Analyzing trace with hash 1774485899, now seen corresponding path program 1 times [2020-11-28 02:57:59,325 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,325 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258738033] [2020-11-28 02:57:59,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,331 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,334 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,336 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:59,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,337 INFO L82 PathProgramCache]: Analyzing trace with hash -64872583, now seen corresponding path program 1 times [2020-11-28 02:57:59,337 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,337 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431325266] [2020-11-28 02:57:59,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-28 02:57:59,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-28 02:57:59,373 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431325266] [2020-11-28 02:57:59,373 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-28 02:57:59,373 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-28 02:57:59,374 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159920891] [2020-11-28 02:57:59,498 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-28 02:57:59,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-28 02:57:59,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-28 02:57:59,499 INFO L87 Difference]: Start difference. First operand 5299 states and 6973 transitions. cyclomatic complexity: 1681 Second operand 3 states. [2020-11-28 02:57:59,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-28 02:57:59,585 INFO L93 Difference]: Finished difference Result 8244 states and 10802 transitions. [2020-11-28 02:57:59,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-28 02:57:59,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8244 states and 10802 transitions. [2020-11-28 02:57:59,629 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8126 [2020-11-28 02:57:59,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8244 states to 8244 states and 10802 transitions. [2020-11-28 02:57:59,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8244 [2020-11-28 02:57:59,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8244 [2020-11-28 02:57:59,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8244 states and 10802 transitions. [2020-11-28 02:57:59,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-28 02:57:59,741 INFO L691 BuchiCegarLoop]: Abstraction has 8244 states and 10802 transitions. [2020-11-28 02:57:59,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8244 states and 10802 transitions. [2020-11-28 02:57:59,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8244 to 8244. [2020-11-28 02:57:59,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8244 states. [2020-11-28 02:57:59,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8244 states to 8244 states and 10802 transitions. [2020-11-28 02:57:59,896 INFO L714 BuchiCegarLoop]: Abstraction has 8244 states and 10802 transitions. [2020-11-28 02:57:59,896 INFO L594 BuchiCegarLoop]: Abstraction has 8244 states and 10802 transitions. [2020-11-28 02:57:59,896 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-28 02:57:59,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8244 states and 10802 transitions. [2020-11-28 02:57:59,927 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8126 [2020-11-28 02:57:59,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-28 02:57:59,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-28 02:57:59,928 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:59,929 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-28 02:57:59,929 INFO L794 eck$LassoCheckResult]: Stem: 65384#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 65271#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65272#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65468#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 65354#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65355#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65570#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65466#L288-1 assume !(0 == ~M_E~0); 65467#L410-1 assume !(0 == ~T1_E~0); 65565#L415-1 assume !(0 == ~T2_E~0); 65452#L420-1 assume !(0 == ~T3_E~0); 65453#L425-1 assume !(0 == ~E_1~0); 65495#L430-1 assume !(0 == ~E_2~0); 65376#L435-1 assume !(0 == ~E_3~0); 65377#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65399#L189 assume !(1 == ~m_pc~0); 65593#L189-2 is_master_triggered_~__retres1~0 := 0; 65594#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65558#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 65513#L502 assume !(0 != activate_threads_~tmp~1); 65488#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65264#L208 assume !(1 == ~t1_pc~0); 65265#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 65266#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65267#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 65339#L510 assume !(0 != activate_threads_~tmp___0~0); 65340#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65349#L227 assume !(1 == ~t2_pc~0); 65497#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 65498#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65506#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 65540#L518 assume !(0 != activate_threads_~tmp___1~0); 65527#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65344#L246 assume !(1 == ~t3_pc~0); 65308#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 65309#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65347#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65441#L526 assume !(0 != activate_threads_~tmp___2~0); 65543#L526-2 assume !(1 == ~M_E~0); 65448#L453-1 assume !(1 == ~T1_E~0); 65449#L458-1 assume !(1 == ~T2_E~0); 65489#L463-1 assume !(1 == ~T3_E~0); 65374#L468-1 assume !(1 == ~E_1~0); 65375#L473-1 assume !(1 == ~E_2~0); 65398#L478-1 assume !(1 == ~E_3~0); 65434#L644-1 assume !false; 71051#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 68257#L385 [2020-11-28 02:57:59,929 INFO L796 eck$LassoCheckResult]: Loop: 68257#L385 assume !false; 71048#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 71045#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 71043#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 71041#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 71039#L338 assume 0 != eval_~tmp~0; 71036#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 71034#L346 assume !(0 != eval_~tmp_ndt_1~0); 71033#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 71031#L360 assume !(0 != eval_~tmp_ndt_2~0); 71032#L357 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 69603#L374 assume !(0 != eval_~tmp_ndt_3~0); 69572#L371 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 68256#L388 assume !(0 != eval_~tmp_ndt_4~0); 68257#L385 [2020-11-28 02:57:59,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,930 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 4 times [2020-11-28 02:57:59,930 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,930 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581999506] [2020-11-28 02:57:59,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,940 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,949 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,959 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:59,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,961 INFO L82 PathProgramCache]: Analyzing trace with hash -825512476, now seen corresponding path program 1 times [2020-11-28 02:57:59,961 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,961 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296775006] [2020-11-28 02:57:59,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,966 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,968 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,971 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:57:59,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-28 02:57:59,972 INFO L82 PathProgramCache]: Analyzing trace with hash -2011050570, now seen corresponding path program 1 times [2020-11-28 02:57:59,973 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-28 02:57:59,973 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846747725] [2020-11-28 02:57:59,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-28 02:57:59,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,983 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:57:59,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-28 02:57:59,996 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-28 02:58:00,011 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-28 02:58:01,294 WARN L193 SmtUtils]: Spent 1.15 s on a formula simplification. DAG size of input: 179 DAG size of output: 133 [2020-11-28 02:58:01,631 WARN L193 SmtUtils]: Spent 308.00 ms on a formula simplification that was a NOOP. DAG size: 115 [2020-11-28 02:58:01,695 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 02:58:01 BoogieIcfgContainer [2020-11-28 02:58:01,695 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-28 02:58:01,697 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-28 02:58:01,697 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-28 02:58:01,698 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-28 02:58:01,698 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:57:53" (3/4) ... [2020-11-28 02:58:01,701 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-28 02:58:01,773 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_dc326d47-e76c-49dc-8a0e-e856ba64d4c9/bin/uautomizer/witness.graphml [2020-11-28 02:58:01,774 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-28 02:58:01,775 INFO L168 Benchmark]: Toolchain (without parser) took 10154.08 ms. Allocated memory was 83.9 MB in the beginning and 274.7 MB in the end (delta: 190.8 MB). Free memory was 54.6 MB in the beginning and 116.7 MB in the end (delta: -62.1 MB). Peak memory consumption was 128.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,776 INFO L168 Benchmark]: CDTParser took 0.34 ms. Allocated memory is still 83.9 MB. Free memory is still 40.7 MB. There was no memory consumed. Max. memory is 16.1 GB. [2020-11-28 02:58:01,776 INFO L168 Benchmark]: CACSL2BoogieTranslator took 572.07 ms. Allocated memory was 83.9 MB in the beginning and 117.4 MB in the end (delta: 33.6 MB). Free memory was 54.4 MB in the beginning and 90.8 MB in the end (delta: -36.4 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,777 INFO L168 Benchmark]: Boogie Procedure Inliner took 89.55 ms. Allocated memory is still 117.4 MB. Free memory was 90.8 MB in the beginning and 87.3 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,777 INFO L168 Benchmark]: Boogie Preprocessor took 99.94 ms. Allocated memory is still 117.4 MB. Free memory was 87.3 MB in the beginning and 84.5 MB in the end (delta: 2.8 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,778 INFO L168 Benchmark]: RCFGBuilder took 1365.10 ms. Allocated memory is still 117.4 MB. Free memory was 84.5 MB in the beginning and 70.9 MB in the end (delta: 13.6 MB). Peak memory consumption was 45.7 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,778 INFO L168 Benchmark]: BuchiAutomizer took 7940.91 ms. Allocated memory was 117.4 MB in the beginning and 274.7 MB in the end (delta: 157.3 MB). Free memory was 70.9 MB in the beginning and 119.9 MB in the end (delta: -48.9 MB). Peak memory consumption was 162.6 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,779 INFO L168 Benchmark]: Witness Printer took 76.58 ms. Allocated memory is still 274.7 MB. Free memory was 119.9 MB in the beginning and 116.7 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2020-11-28 02:58:01,782 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34 ms. Allocated memory is still 83.9 MB. Free memory is still 40.7 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 572.07 ms. Allocated memory was 83.9 MB in the beginning and 117.4 MB in the end (delta: 33.6 MB). Free memory was 54.4 MB in the beginning and 90.8 MB in the end (delta: -36.4 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 89.55 ms. Allocated memory is still 117.4 MB. Free memory was 90.8 MB in the beginning and 87.3 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 99.94 ms. Allocated memory is still 117.4 MB. Free memory was 87.3 MB in the beginning and 84.5 MB in the end (delta: 2.8 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1365.10 ms. Allocated memory is still 117.4 MB. Free memory was 84.5 MB in the beginning and 70.9 MB in the end (delta: 13.6 MB). Peak memory consumption was 45.7 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 7940.91 ms. Allocated memory was 117.4 MB in the beginning and 274.7 MB in the end (delta: 157.3 MB). Free memory was 70.9 MB in the beginning and 119.9 MB in the end (delta: -48.9 MB). Peak memory consumption was 162.6 MB. Max. memory is 16.1 GB. * Witness Printer took 76.58 ms. Allocated memory is still 274.7 MB. Free memory was 119.9 MB in the beginning and 116.7 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8244 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.8s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 0.9s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.9s AutomataMinimizationTime, 16 MinimizatonAttempts, 2330 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had 8244 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 6357 SDtfs, 7416 SDslu, 4971 SDs, 0 SdLazy, 340 SolverSat, 176 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 333]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=23743} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=23743, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6ced23eb=0, E_3=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f2f6637=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79ed0058=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25a3ec44=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21de00f8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@482578bb=0, NULL=23746, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, NULL=23745, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=23744, t2_i=1, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b0ed339=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fd96bba=0, t2_pc=0, tmp___1=0, T3_E=2, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71a0de1d=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d7ddfa3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@179404f8=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 333]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int E_1 = 2; [L34] int E_2 = 2; [L35] int E_3 = 2; [L689] int __retres1 ; [L602] m_i = 1 [L603] t1_i = 1 [L604] t2_i = 1 [L605] t3_i = 1 [L630] int kernel_st ; [L631] int tmp ; [L632] int tmp___0 ; [L636] kernel_st = 0 [L273] COND TRUE m_i == 1 [L274] m_st = 0 [L278] COND TRUE t1_i == 1 [L279] t1_st = 0 [L283] COND TRUE t2_i == 1 [L284] t2_st = 0 [L288] COND TRUE t3_i == 1 [L289] t3_st = 0 [L410] COND FALSE !(M_E == 0) [L415] COND FALSE !(T1_E == 0) [L420] COND FALSE !(T2_E == 0) [L425] COND FALSE !(T3_E == 0) [L430] COND FALSE !(E_1 == 0) [L435] COND FALSE !(E_2 == 0) [L440] COND FALSE !(E_3 == 0) [L493] int tmp ; [L494] int tmp___0 ; [L495] int tmp___1 ; [L496] int tmp___2 ; [L186] int __retres1 ; [L189] COND FALSE !(m_pc == 1) [L199] __retres1 = 0 [L201] return (__retres1); [L500] tmp = is_master_triggered() [L502] COND FALSE !(\read(tmp)) [L205] int __retres1 ; [L208] COND FALSE !(t1_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L508] tmp___0 = is_transmit1_triggered() [L510] COND FALSE !(\read(tmp___0)) [L224] int __retres1 ; [L227] COND FALSE !(t2_pc == 1) [L237] __retres1 = 0 [L239] return (__retres1); [L516] tmp___1 = is_transmit2_triggered() [L518] COND FALSE !(\read(tmp___1)) [L243] int __retres1 ; [L246] COND FALSE !(t3_pc == 1) [L256] __retres1 = 0 [L258] return (__retres1); [L524] tmp___2 = is_transmit3_triggered() [L526] COND FALSE !(\read(tmp___2)) [L453] COND FALSE !(M_E == 1) [L458] COND FALSE !(T1_E == 1) [L463] COND FALSE !(T2_E == 1) [L468] COND FALSE !(T3_E == 1) [L473] COND FALSE !(E_1 == 1) [L478] COND FALSE !(E_2 == 1) [L483] COND FALSE !(E_3 == 1) [L644] COND TRUE 1 [L647] kernel_st = 1 [L329] int tmp ; Loop: [L333] COND TRUE 1 [L298] int __retres1 ; [L301] COND TRUE m_st == 0 [L302] __retres1 = 1 [L324] return (__retres1); [L336] tmp = exists_runnable_thread() [L338] COND TRUE \read(tmp) [L343] COND TRUE m_st == 0 [L344] int tmp_ndt_1; [L345] tmp_ndt_1 = __VERIFIER_nondet_int() [L346] COND FALSE !(\read(tmp_ndt_1)) [L357] COND TRUE t1_st == 0 [L358] int tmp_ndt_2; [L359] tmp_ndt_2 = __VERIFIER_nondet_int() [L360] COND FALSE !(\read(tmp_ndt_2)) [L371] COND TRUE t2_st == 0 [L372] int tmp_ndt_3; [L373] tmp_ndt_3 = __VERIFIER_nondet_int() [L374] COND FALSE !(\read(tmp_ndt_3)) [L385] COND TRUE t3_st == 0 [L386] int tmp_ndt_4; [L387] tmp_ndt_4 = __VERIFIER_nondet_int() [L388] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...