./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a4ecdabc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/data/config -Xmx15G -Xms4m -jar /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c23fa9fd10aa70a52586ccd054da306bf699445a ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-a4ecdab [2020-11-29 18:43:25,795 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-11-29 18:43:25,828 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-11-29 18:43:25,869 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-11-29 18:43:25,870 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-11-29 18:43:25,872 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-11-29 18:43:25,874 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-11-29 18:43:25,876 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-11-29 18:43:25,878 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-11-29 18:43:25,880 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-11-29 18:43:25,881 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-11-29 18:43:25,882 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-11-29 18:43:25,883 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-11-29 18:43:25,884 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-11-29 18:43:25,886 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-11-29 18:43:25,887 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-11-29 18:43:25,888 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-11-29 18:43:25,889 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-11-29 18:43:25,891 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-11-29 18:43:25,894 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-11-29 18:43:25,896 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-11-29 18:43:25,897 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-11-29 18:43:25,899 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-11-29 18:43:25,900 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-11-29 18:43:25,903 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-11-29 18:43:25,904 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-11-29 18:43:25,904 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-11-29 18:43:25,905 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-11-29 18:43:25,906 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-11-29 18:43:25,907 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-11-29 18:43:25,908 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-11-29 18:43:25,909 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-11-29 18:43:25,910 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-11-29 18:43:25,911 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-11-29 18:43:25,912 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-11-29 18:43:25,912 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-11-29 18:43:25,913 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-11-29 18:43:25,914 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-11-29 18:43:25,914 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-11-29 18:43:25,915 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-11-29 18:43:25,916 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-11-29 18:43:25,920 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-11-29 18:43:25,958 INFO L113 SettingsManager]: Loading preferences was successful [2020-11-29 18:43:25,960 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-11-29 18:43:25,962 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-11-29 18:43:25,962 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-11-29 18:43:25,962 INFO L138 SettingsManager]: * Use SBE=true [2020-11-29 18:43:25,963 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-11-29 18:43:25,963 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-11-29 18:43:25,963 INFO L138 SettingsManager]: * Use old map elimination=false [2020-11-29 18:43:25,963 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-11-29 18:43:25,964 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-11-29 18:43:25,965 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-11-29 18:43:25,965 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-11-29 18:43:25,966 INFO L138 SettingsManager]: * sizeof long=4 [2020-11-29 18:43:25,966 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-11-29 18:43:25,966 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-11-29 18:43:25,966 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-11-29 18:43:25,967 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-11-29 18:43:25,967 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-11-29 18:43:25,967 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-11-29 18:43:25,967 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-11-29 18:43:25,967 INFO L138 SettingsManager]: * sizeof long double=12 [2020-11-29 18:43:25,968 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-11-29 18:43:25,968 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-11-29 18:43:25,968 INFO L138 SettingsManager]: * Use constant arrays=true [2020-11-29 18:43:25,968 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-11-29 18:43:25,969 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-11-29 18:43:25,969 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-11-29 18:43:25,969 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-11-29 18:43:25,969 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-11-29 18:43:25,971 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-11-29 18:43:25,971 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-11-29 18:43:25,971 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-11-29 18:43:25,973 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-11-29 18:43:25,973 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c23fa9fd10aa70a52586ccd054da306bf699445a [2020-11-29 18:43:26,246 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-11-29 18:43:26,287 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-11-29 18:43:26,291 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-11-29 18:43:26,293 INFO L271 PluginConnector]: Initializing CDTParser... [2020-11-29 18:43:26,294 INFO L275 PluginConnector]: CDTParser initialized [2020-11-29 18:43:26,294 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2020-11-29 18:43:26,376 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/data/ed908b684/9e2edbe297c149b592f9a5f07ccf8cbf/FLAG018b36b69 [2020-11-29 18:43:26,820 INFO L306 CDTParser]: Found 1 translation units. [2020-11-29 18:43:26,821 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2020-11-29 18:43:26,832 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/data/ed908b684/9e2edbe297c149b592f9a5f07ccf8cbf/FLAG018b36b69 [2020-11-29 18:43:27,187 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/data/ed908b684/9e2edbe297c149b592f9a5f07ccf8cbf [2020-11-29 18:43:27,190 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-11-29 18:43:27,191 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-11-29 18:43:27,197 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-11-29 18:43:27,197 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-11-29 18:43:27,203 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-11-29 18:43:27,204 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,206 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@457c5936 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27, skipping insertion in model container [2020-11-29 18:43:27,206 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,212 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-11-29 18:43:27,257 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-11-29 18:43:27,507 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-29 18:43:27,517 INFO L203 MainTranslator]: Completed pre-run [2020-11-29 18:43:27,572 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-11-29 18:43:27,596 INFO L208 MainTranslator]: Completed translation [2020-11-29 18:43:27,597 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27 WrapperNode [2020-11-29 18:43:27,597 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-11-29 18:43:27,598 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-11-29 18:43:27,598 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-11-29 18:43:27,598 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-11-29 18:43:27,619 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,629 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,691 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-11-29 18:43:27,692 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-11-29 18:43:27,693 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-11-29 18:43:27,693 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-11-29 18:43:27,702 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,702 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,710 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,710 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,729 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,766 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,779 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... [2020-11-29 18:43:27,797 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-11-29 18:43:27,812 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-11-29 18:43:27,812 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-11-29 18:43:27,813 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-11-29 18:43:27,814 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-11-29 18:43:27,886 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-11-29 18:43:27,886 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-11-29 18:43:27,887 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-11-29 18:43:27,887 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-11-29 18:43:29,562 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-11-29 18:43:29,562 INFO L298 CfgBuilder]: Removed 198 assume(true) statements. [2020-11-29 18:43:29,565 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 06:43:29 BoogieIcfgContainer [2020-11-29 18:43:29,569 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-11-29 18:43:29,573 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-11-29 18:43:29,573 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-11-29 18:43:29,576 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-11-29 18:43:29,577 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-29 18:43:29,577 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 06:43:27" (1/3) ... [2020-11-29 18:43:29,578 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2933ed6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 06:43:29, skipping insertion in model container [2020-11-29 18:43:29,578 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-29 18:43:29,579 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 06:43:27" (2/3) ... [2020-11-29 18:43:29,579 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2933ed6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 06:43:29, skipping insertion in model container [2020-11-29 18:43:29,579 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-11-29 18:43:29,579 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 06:43:29" (3/3) ... [2020-11-29 18:43:29,581 INFO L373 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2020-11-29 18:43:29,640 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-11-29 18:43:29,640 INFO L360 BuchiCegarLoop]: Hoare is false [2020-11-29 18:43:29,640 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-11-29 18:43:29,640 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-11-29 18:43:29,640 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-11-29 18:43:29,641 INFO L364 BuchiCegarLoop]: Difference is false [2020-11-29 18:43:29,641 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-11-29 18:43:29,641 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-11-29 18:43:29,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 533 states. [2020-11-29 18:43:29,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 454 [2020-11-29 18:43:29,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:29,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:29,771 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:29,771 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:29,771 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-11-29 18:43:29,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 533 states. [2020-11-29 18:43:29,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 454 [2020-11-29 18:43:29,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:29,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:29,799 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:29,799 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:29,813 INFO L794 eck$LassoCheckResult]: Stem: 367#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 261#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 249#L883true havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 241#L399true assume !(1 == ~m_i~0);~m_st~0 := 2; 275#L406-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 46#L411-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 463#L416-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 220#L421-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 503#L426-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 154#L431-1true assume !(0 == ~M_E~0); 523#L591-1true assume !(0 == ~T1_E~0); 157#L596-1true assume !(0 == ~T2_E~0); 421#L601-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 191#L606-1true assume !(0 == ~T4_E~0); 101#L611-1true assume !(0 == ~T5_E~0); 388#L616-1true assume !(0 == ~E_M~0); 7#L621-1true assume !(0 == ~E_1~0); 278#L626-1true assume !(0 == ~E_2~0); 51#L631-1true assume !(0 == ~E_3~0); 471#L636-1true assume !(0 == ~E_4~0); 245#L641-1true assume 0 == ~E_5~0;~E_5~0 := 1; 534#L646-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 309#L284true assume 1 == ~m_pc~0; 259#L285true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 310#L295true is_master_triggered_#res := is_master_triggered_~__retres1~0; 260#L296true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 482#L735true assume !(0 != activate_threads_~tmp~1); 466#L735-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60#L303true assume !(1 == ~t1_pc~0); 89#L303-2true is_transmit1_triggered_~__retres1~1 := 0; 95#L314true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 414#L315true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 109#L743true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 112#L743-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 225#L322true assume 1 == ~t2_pc~0; 27#L323true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 224#L333true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26#L334true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 251#L751true assume !(0 != activate_threads_~tmp___1~0); 242#L751-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 383#L341true assume !(1 == ~t3_pc~0); 368#L341-2true is_transmit3_triggered_~__retres1~3 := 0; 382#L352true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184#L353true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 393#L759true assume !(0 != activate_threads_~tmp___2~0); 394#L759-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 508#L360true assume 1 == ~t4_pc~0; 318#L361true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 506#L371true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 315#L372true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 399#L767true assume !(0 != activate_threads_~tmp___3~0); 531#L767-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 151#L379true assume !(1 == ~t5_pc~0); 132#L379-2true is_transmit5_triggered_~__retres1~5 := 0; 149#L390true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83#L391true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13#L775true assume !(0 != activate_threads_~tmp___4~0); 15#L775-2true assume !(1 == ~M_E~0); 276#L659-1true assume !(1 == ~T1_E~0); 50#L664-1true assume !(1 == ~T2_E~0); 467#L669-1true assume !(1 == ~T3_E~0); 244#L674-1true assume !(1 == ~T4_E~0); 533#L679-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 163#L684-1true assume !(1 == ~E_M~0); 433#L689-1true assume !(1 == ~E_1~0); 346#L694-1true assume !(1 == ~E_2~0); 113#L699-1true assume !(1 == ~E_3~0); 395#L704-1true assume !(1 == ~E_4~0); 3#L709-1true assume !(1 == ~E_5~0); 438#L920-1true [2020-11-29 18:43:29,816 INFO L796 eck$LassoCheckResult]: Loop: 438#L920-1true assume !false; 397#L921true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9#L566true assume !true; 474#L581true start_simulation_~kernel_st~0 := 2; 222#L399-1true start_simulation_~kernel_st~0 := 3; 525#L591-2true assume 0 == ~M_E~0;~M_E~0 := 1; 528#L591-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 160#L596-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 426#L601-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L606-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 105#L611-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 390#L616-3true assume !(0 == ~E_M~0); 11#L621-3true assume 0 == ~E_1~0;~E_1~0 := 1; 283#L626-3true assume 0 == ~E_2~0;~E_2~0 := 1; 36#L631-3true assume 0 == ~E_3~0;~E_3~0 := 1; 455#L636-3true assume 0 == ~E_4~0;~E_4~0 := 1; 234#L641-3true assume 0 == ~E_5~0;~E_5~0 := 1; 524#L646-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273#L284-21true assume !(1 == ~m_pc~0); 272#L284-23true is_master_triggered_~__retres1~0 := 0; 320#L295-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 265#L296-7true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 314#L735-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 292#L735-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 434#L303-21true assume 1 == ~t1_pc~0; 401#L304-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 447#L314-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 400#L315-7true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 449#L743-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 453#L743-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49#L322-21true assume !(1 == ~t2_pc~0); 52#L322-23true is_transmit2_triggered_~__retres1~2 := 0; 214#L333-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22#L334-7true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 219#L751-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 197#L751-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 345#L341-21true assume 1 == ~t3_pc~0; 180#L342-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 355#L352-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 179#L353-7true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 360#L759-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 362#L759-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 465#L360-21true assume 1 == ~t4_pc~0; 308#L361-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 495#L371-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 307#L372-7true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 499#L767-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 483#L767-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 111#L379-21true assume !(1 == ~t5_pc~0); 98#L379-23true is_transmit5_triggered_~__retres1~5 := 0; 144#L390-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76#L391-7true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 126#L775-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 128#L775-23true assume !(1 == ~M_E~0); 280#L659-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 53#L664-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 476#L669-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 247#L674-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 520#L679-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 156#L684-3true assume 1 == ~E_M~0;~E_M~0 := 2; 420#L689-3true assume 1 == ~E_1~0;~E_1~0 := 2; 190#L694-3true assume !(1 == ~E_2~0); 100#L699-3true assume 1 == ~E_3~0;~E_3~0 := 2; 386#L704-3true assume 1 == ~E_4~0;~E_4~0 := 2; 6#L709-3true assume 1 == ~E_5~0;~E_5~0 := 2; 277#L714-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44#L444-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 239#L476-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43#L477-1true start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 201#L939true assume !(0 == start_simulation_~tmp~3); 205#L939-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47#L444-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 240#L476-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45#L477-2true stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 248#L894true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 296#L901true stop_simulation_#res := stop_simulation_~__retres2~0; 396#L902true start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 114#L952true assume !(0 != start_simulation_~tmp___0~1); 438#L920-1true [2020-11-29 18:43:29,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:29,824 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2020-11-29 18:43:29,832 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:29,833 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704874426] [2020-11-29 18:43:29,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:29,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,093 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1704874426] [2020-11-29 18:43:30,094 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,094 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,095 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950682955] [2020-11-29 18:43:30,102 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:30,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,105 INFO L82 PathProgramCache]: Analyzing trace with hash -462551088, now seen corresponding path program 1 times [2020-11-29 18:43:30,105 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,105 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693848749] [2020-11-29 18:43:30,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,156 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693848749] [2020-11-29 18:43:30,157 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,157 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:30,158 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775368112] [2020-11-29 18:43:30,160 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:30,161 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:30,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:30,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:30,179 INFO L87 Difference]: Start difference. First operand 533 states. Second operand 3 states. [2020-11-29 18:43:30,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:30,238 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2020-11-29 18:43:30,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:30,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2020-11-29 18:43:30,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2020-11-29 18:43:30,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2020-11-29 18:43:30,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2020-11-29 18:43:30,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2020-11-29 18:43:30,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:30,267 INFO L691 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2020-11-29 18:43:30,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2020-11-29 18:43:30,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2020-11-29 18:43:30,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2020-11-29 18:43:30,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2020-11-29 18:43:30,326 INFO L714 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2020-11-29 18:43:30,326 INFO L594 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2020-11-29 18:43:30,326 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-11-29 18:43:30,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2020-11-29 18:43:30,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:30,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:30,333 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,333 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,333 INFO L794 eck$LassoCheckResult]: Stem: 1548#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1443#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1418#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1405#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1406#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1165#L411-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1166#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1393#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1394#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1308#L431-1 assume !(0 == ~M_E~0); 1309#L591-1 assume !(0 == ~T1_E~0); 1313#L596-1 assume !(0 == ~T2_E~0); 1314#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1380#L606-1 assume !(0 == ~T4_E~0); 1263#L611-1 assume !(0 == ~T5_E~0); 1264#L616-1 assume !(0 == ~E_M~0); 1081#L621-1 assume !(0 == ~E_1~0); 1082#L626-1 assume !(0 == ~E_2~0); 1173#L631-1 assume !(0 == ~E_3~0); 1174#L636-1 assume !(0 == ~E_4~0); 1412#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1413#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1494#L284 assume 1 == ~m_pc~0; 1438#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1439#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1441#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1442#L735 assume !(0 != activate_threads_~tmp~1); 1590#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1182#L303 assume !(1 == ~t1_pc~0); 1183#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1243#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1252#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1275#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1276#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1278#L322 assume 1 == ~t2_pc~0; 1122#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1123#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1120#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1121#L751 assume !(0 != activate_threads_~tmp___1~0); 1407#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1408#L341 assume !(1 == ~t3_pc~0); 1369#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1370#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1366#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1367#L759 assume !(0 != activate_threads_~tmp___2~0); 1557#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1558#L360 assume 1 == ~t4_pc~0; 1505#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1506#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1501#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1502#L767 assume !(0 != activate_threads_~tmp___3~0); 1560#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1307#L379 assume !(1 == ~t5_pc~0); 1236#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1235#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1231#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1095#L775 assume !(0 != activate_threads_~tmp___4~0); 1096#L775-2 assume !(1 == ~M_E~0); 1097#L659-1 assume !(1 == ~T1_E~0); 1171#L664-1 assume !(1 == ~T2_E~0); 1172#L669-1 assume !(1 == ~T3_E~0); 1410#L674-1 assume !(1 == ~T4_E~0); 1411#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1323#L684-1 assume !(1 == ~E_M~0); 1324#L689-1 assume !(1 == ~E_1~0); 1537#L694-1 assume !(1 == ~E_2~0); 1279#L699-1 assume !(1 == ~E_3~0); 1280#L704-1 assume !(1 == ~E_4~0); 1074#L709-1 assume !(1 == ~E_5~0); 1075#L920-1 [2020-11-29 18:43:30,334 INFO L796 eck$LassoCheckResult]: Loop: 1075#L920-1 assume !false; 1559#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1085#L566 assume !false; 1086#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1155#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1156#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1153#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1154#L491 assume !(0 != eval_~tmp~0); 1584#L581 start_simulation_~kernel_st~0 := 2; 1397#L399-1 start_simulation_~kernel_st~0 := 3; 1398#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1599#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1319#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1320#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1381#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1269#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1270#L616-3 assume !(0 == ~E_M~0); 1090#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1091#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1145#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1146#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1402#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1403#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1469#L284-21 assume 1 == ~m_pc~0; 1449#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1450#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1452#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1453#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1472#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1473#L303-21 assume 1 == ~t1_pc~0; 1563#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1565#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1561#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1562#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1588#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1170#L322-21 assume 1 == ~t2_pc~0; 1112#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1113#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1110#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1111#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1383#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1384#L341-21 assume 1 == ~t3_pc~0; 1360#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1361#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1358#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1359#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1544#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1545#L360-21 assume 1 == ~t4_pc~0; 1491#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1492#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1489#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1490#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1592#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1277#L379-21 assume 1 == ~t5_pc~0; 1223#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1224#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1217#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1218#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1291#L775-23 assume !(1 == ~M_E~0); 1292#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1175#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1176#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1415#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1416#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1311#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1312#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1378#L694-3 assume !(1 == ~E_2~0); 1261#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1262#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1079#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1080#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1160#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1161#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1158#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1159#L939 assume !(0 == start_simulation_~tmp~3); 1386#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1167#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1168#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1163#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1164#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1417#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 1476#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1281#L952 assume !(0 != start_simulation_~tmp___0~1); 1075#L920-1 [2020-11-29 18:43:30,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,335 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2020-11-29 18:43:30,335 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,335 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73582371] [2020-11-29 18:43:30,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,445 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73582371] [2020-11-29 18:43:30,445 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,446 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,446 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484423423] [2020-11-29 18:43:30,447 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:30,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,447 INFO L82 PathProgramCache]: Analyzing trace with hash 1481781260, now seen corresponding path program 1 times [2020-11-29 18:43:30,448 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,448 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663053805] [2020-11-29 18:43:30,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,555 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663053805] [2020-11-29 18:43:30,556 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,556 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,556 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880819788] [2020-11-29 18:43:30,557 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:30,557 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:30,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:30,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:30,558 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand 3 states. [2020-11-29 18:43:30,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:30,576 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2020-11-29 18:43:30,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:30,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2020-11-29 18:43:30,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2020-11-29 18:43:30,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2020-11-29 18:43:30,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2020-11-29 18:43:30,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2020-11-29 18:43:30,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:30,591 INFO L691 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2020-11-29 18:43:30,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2020-11-29 18:43:30,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2020-11-29 18:43:30,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2020-11-29 18:43:30,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2020-11-29 18:43:30,617 INFO L714 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2020-11-29 18:43:30,617 INFO L594 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2020-11-29 18:43:30,618 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-11-29 18:43:30,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2020-11-29 18:43:30,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:30,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:30,626 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,627 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,628 INFO L794 eck$LassoCheckResult]: Stem: 2609#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2504#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2479#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2466#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 2467#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2229#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2230#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2454#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2455#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2370#L431-1 assume !(0 == ~M_E~0); 2371#L591-1 assume !(0 == ~T1_E~0); 2374#L596-1 assume !(0 == ~T2_E~0); 2375#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2441#L606-1 assume !(0 == ~T4_E~0); 2324#L611-1 assume !(0 == ~T5_E~0); 2325#L616-1 assume !(0 == ~E_M~0); 2142#L621-1 assume !(0 == ~E_1~0); 2143#L626-1 assume !(0 == ~E_2~0); 2234#L631-1 assume !(0 == ~E_3~0); 2235#L636-1 assume !(0 == ~E_4~0); 2473#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2474#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2555#L284 assume 1 == ~m_pc~0; 2499#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2500#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2502#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2503#L735 assume !(0 != activate_threads_~tmp~1); 2651#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2243#L303 assume !(1 == ~t1_pc~0); 2244#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 2304#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2313#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2336#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2337#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2339#L322 assume 1 == ~t2_pc~0; 2183#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2184#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2181#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2182#L751 assume !(0 != activate_threads_~tmp___1~0); 2468#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2469#L341 assume !(1 == ~t3_pc~0); 2430#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 2431#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2427#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2428#L759 assume !(0 != activate_threads_~tmp___2~0); 2618#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2619#L360 assume 1 == ~t4_pc~0; 2566#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2567#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2562#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2563#L767 assume !(0 != activate_threads_~tmp___3~0); 2621#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2368#L379 assume !(1 == ~t5_pc~0); 2297#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 2296#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2292#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2156#L775 assume !(0 != activate_threads_~tmp___4~0); 2157#L775-2 assume !(1 == ~M_E~0); 2158#L659-1 assume !(1 == ~T1_E~0); 2232#L664-1 assume !(1 == ~T2_E~0); 2233#L669-1 assume !(1 == ~T3_E~0); 2471#L674-1 assume !(1 == ~T4_E~0); 2472#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2384#L684-1 assume !(1 == ~E_M~0); 2385#L689-1 assume !(1 == ~E_1~0); 2598#L694-1 assume !(1 == ~E_2~0); 2340#L699-1 assume !(1 == ~E_3~0); 2341#L704-1 assume !(1 == ~E_4~0); 2135#L709-1 assume !(1 == ~E_5~0); 2136#L920-1 [2020-11-29 18:43:30,628 INFO L796 eck$LassoCheckResult]: Loop: 2136#L920-1 assume !false; 2620#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2146#L566 assume !false; 2147#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2218#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2219#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2214#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2215#L491 assume !(0 != eval_~tmp~0); 2645#L581 start_simulation_~kernel_st~0 := 2; 2458#L399-1 start_simulation_~kernel_st~0 := 3; 2459#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2660#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2380#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2381#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2442#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2330#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2331#L616-3 assume !(0 == ~E_M~0); 2151#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2152#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2206#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2207#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2463#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2464#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2530#L284-21 assume !(1 == ~m_pc~0); 2512#L284-23 is_master_triggered_~__retres1~0 := 0; 2511#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2513#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2514#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2533#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2534#L303-21 assume 1 == ~t1_pc~0; 2624#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2626#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2622#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2623#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2649#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2231#L322-21 assume 1 == ~t2_pc~0; 2173#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2174#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2171#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2172#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2444#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2445#L341-21 assume 1 == ~t3_pc~0; 2421#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2422#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2419#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2420#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2605#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2606#L360-21 assume 1 == ~t4_pc~0; 2552#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2553#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2550#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2551#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2653#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2338#L379-21 assume 1 == ~t5_pc~0; 2284#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2285#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2278#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2279#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2352#L775-23 assume !(1 == ~M_E~0); 2353#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2236#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2237#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2476#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2477#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2372#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2373#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2439#L694-3 assume !(1 == ~E_2~0); 2322#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2323#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2139#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2140#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2221#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2222#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2216#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2217#L939 assume !(0 == start_simulation_~tmp~3); 2447#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2226#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2227#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2224#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2225#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2478#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 2537#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2342#L952 assume !(0 != start_simulation_~tmp___0~1); 2136#L920-1 [2020-11-29 18:43:30,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,630 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2020-11-29 18:43:30,630 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,631 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347635183] [2020-11-29 18:43:30,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,670 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347635183] [2020-11-29 18:43:30,671 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,671 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,671 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296074778] [2020-11-29 18:43:30,671 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:30,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,672 INFO L82 PathProgramCache]: Analyzing trace with hash -424702933, now seen corresponding path program 1 times [2020-11-29 18:43:30,672 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,673 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944858817] [2020-11-29 18:43:30,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,747 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944858817] [2020-11-29 18:43:30,747 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,747 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,747 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879704785] [2020-11-29 18:43:30,748 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:30,748 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:30,749 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:30,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:30,759 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand 3 states. [2020-11-29 18:43:30,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:30,775 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2020-11-29 18:43:30,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:30,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2020-11-29 18:43:30,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2020-11-29 18:43:30,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2020-11-29 18:43:30,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2020-11-29 18:43:30,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2020-11-29 18:43:30,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:30,790 INFO L691 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2020-11-29 18:43:30,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2020-11-29 18:43:30,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2020-11-29 18:43:30,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2020-11-29 18:43:30,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2020-11-29 18:43:30,801 INFO L714 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2020-11-29 18:43:30,801 INFO L594 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2020-11-29 18:43:30,801 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-11-29 18:43:30,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2020-11-29 18:43:30,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:30,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:30,809 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,809 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:30,810 INFO L794 eck$LassoCheckResult]: Stem: 3670#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3565#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3540#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3527#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 3528#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3290#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3291#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3515#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3516#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3431#L431-1 assume !(0 == ~M_E~0); 3432#L591-1 assume !(0 == ~T1_E~0); 3435#L596-1 assume !(0 == ~T2_E~0); 3436#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3502#L606-1 assume !(0 == ~T4_E~0); 3385#L611-1 assume !(0 == ~T5_E~0); 3386#L616-1 assume !(0 == ~E_M~0); 3203#L621-1 assume !(0 == ~E_1~0); 3204#L626-1 assume !(0 == ~E_2~0); 3295#L631-1 assume !(0 == ~E_3~0); 3296#L636-1 assume !(0 == ~E_4~0); 3534#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3535#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3616#L284 assume 1 == ~m_pc~0; 3560#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3561#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3563#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3564#L735 assume !(0 != activate_threads_~tmp~1); 3712#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3306#L303 assume !(1 == ~t1_pc~0); 3307#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 3365#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3374#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3397#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3398#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3400#L322 assume 1 == ~t2_pc~0; 3244#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3245#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3242#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3243#L751 assume !(0 != activate_threads_~tmp___1~0); 3529#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3530#L341 assume !(1 == ~t3_pc~0); 3491#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 3492#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3488#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3489#L759 assume !(0 != activate_threads_~tmp___2~0); 3679#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3680#L360 assume 1 == ~t4_pc~0; 3627#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3628#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3623#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3624#L767 assume !(0 != activate_threads_~tmp___3~0); 3682#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3429#L379 assume !(1 == ~t5_pc~0); 3358#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 3357#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3353#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3217#L775 assume !(0 != activate_threads_~tmp___4~0); 3218#L775-2 assume !(1 == ~M_E~0); 3219#L659-1 assume !(1 == ~T1_E~0); 3293#L664-1 assume !(1 == ~T2_E~0); 3294#L669-1 assume !(1 == ~T3_E~0); 3532#L674-1 assume !(1 == ~T4_E~0); 3533#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3445#L684-1 assume !(1 == ~E_M~0); 3446#L689-1 assume !(1 == ~E_1~0); 3659#L694-1 assume !(1 == ~E_2~0); 3401#L699-1 assume !(1 == ~E_3~0); 3402#L704-1 assume !(1 == ~E_4~0); 3196#L709-1 assume !(1 == ~E_5~0); 3197#L920-1 [2020-11-29 18:43:30,811 INFO L796 eck$LassoCheckResult]: Loop: 3197#L920-1 assume !false; 3681#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3207#L566 assume !false; 3208#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3279#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3280#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3275#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3276#L491 assume !(0 != eval_~tmp~0); 3706#L581 start_simulation_~kernel_st~0 := 2; 3519#L399-1 start_simulation_~kernel_st~0 := 3; 3520#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3721#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3441#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3442#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3503#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3391#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3392#L616-3 assume !(0 == ~E_M~0); 3212#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3213#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3267#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3268#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3524#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3525#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3591#L284-21 assume 1 == ~m_pc~0; 3571#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3572#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3574#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3575#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3594#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3595#L303-21 assume 1 == ~t1_pc~0; 3685#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3687#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3683#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3684#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3710#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3292#L322-21 assume 1 == ~t2_pc~0; 3234#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3235#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3232#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3233#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3505#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3506#L341-21 assume 1 == ~t3_pc~0; 3482#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3483#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3480#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3481#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3666#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3667#L360-21 assume 1 == ~t4_pc~0; 3613#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3614#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3610#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3611#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3714#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3399#L379-21 assume 1 == ~t5_pc~0; 3341#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3342#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3339#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3340#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3412#L775-23 assume !(1 == ~M_E~0); 3414#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3297#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3298#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3537#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3538#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3433#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3434#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3500#L694-3 assume !(1 == ~E_2~0); 3383#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3384#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3201#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3202#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3282#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3283#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3277#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3278#L939 assume !(0 == start_simulation_~tmp~3); 3508#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3287#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3288#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3285#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 3286#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3539#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 3598#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3403#L952 assume !(0 != start_simulation_~tmp___0~1); 3197#L920-1 [2020-11-29 18:43:30,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,812 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2020-11-29 18:43:30,813 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,814 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30165955] [2020-11-29 18:43:30,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,882 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30165955] [2020-11-29 18:43:30,882 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,882 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,883 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492361270] [2020-11-29 18:43:30,883 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:30,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:30,885 INFO L82 PathProgramCache]: Analyzing trace with hash 1481781260, now seen corresponding path program 2 times [2020-11-29 18:43:30,886 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:30,886 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811280492] [2020-11-29 18:43:30,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:30,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:30,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:30,956 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811280492] [2020-11-29 18:43:30,956 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:30,957 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:30,957 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445014357] [2020-11-29 18:43:30,957 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:30,958 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:30,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:30,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:30,959 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand 3 states. [2020-11-29 18:43:30,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:30,974 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2020-11-29 18:43:30,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:30,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2020-11-29 18:43:30,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:30,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2020-11-29 18:43:30,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2020-11-29 18:43:30,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2020-11-29 18:43:30,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2020-11-29 18:43:30,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:30,988 INFO L691 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2020-11-29 18:43:30,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2020-11-29 18:43:30,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2020-11-29 18:43:30,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2020-11-29 18:43:31,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2020-11-29 18:43:31,002 INFO L714 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2020-11-29 18:43:31,006 INFO L594 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2020-11-29 18:43:31,006 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-11-29 18:43:31,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2020-11-29 18:43:31,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:31,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:31,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:31,015 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,016 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,016 INFO L794 eck$LassoCheckResult]: Stem: 4731#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4626#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4601#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4588#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 4589#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4351#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4352#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4576#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4577#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4492#L431-1 assume !(0 == ~M_E~0); 4493#L591-1 assume !(0 == ~T1_E~0); 4496#L596-1 assume !(0 == ~T2_E~0); 4497#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L606-1 assume !(0 == ~T4_E~0); 4446#L611-1 assume !(0 == ~T5_E~0); 4447#L616-1 assume !(0 == ~E_M~0); 4264#L621-1 assume !(0 == ~E_1~0); 4265#L626-1 assume !(0 == ~E_2~0); 4356#L631-1 assume !(0 == ~E_3~0); 4357#L636-1 assume !(0 == ~E_4~0); 4595#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4596#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4677#L284 assume 1 == ~m_pc~0; 4621#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4622#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4624#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4625#L735 assume !(0 != activate_threads_~tmp~1); 4773#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4367#L303 assume !(1 == ~t1_pc~0); 4368#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 4427#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4438#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4458#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4459#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4461#L322 assume 1 == ~t2_pc~0; 4305#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4306#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4303#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4304#L751 assume !(0 != activate_threads_~tmp___1~0); 4590#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4591#L341 assume !(1 == ~t3_pc~0); 4552#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 4553#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4549#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4550#L759 assume !(0 != activate_threads_~tmp___2~0); 4740#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4741#L360 assume 1 == ~t4_pc~0; 4688#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4689#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4684#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4685#L767 assume !(0 != activate_threads_~tmp___3~0); 4743#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4490#L379 assume !(1 == ~t5_pc~0); 4419#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 4418#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4414#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4278#L775 assume !(0 != activate_threads_~tmp___4~0); 4279#L775-2 assume !(1 == ~M_E~0); 4280#L659-1 assume !(1 == ~T1_E~0); 4354#L664-1 assume !(1 == ~T2_E~0); 4355#L669-1 assume !(1 == ~T3_E~0); 4593#L674-1 assume !(1 == ~T4_E~0); 4594#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4506#L684-1 assume !(1 == ~E_M~0); 4507#L689-1 assume !(1 == ~E_1~0); 4720#L694-1 assume !(1 == ~E_2~0); 4462#L699-1 assume !(1 == ~E_3~0); 4463#L704-1 assume !(1 == ~E_4~0); 4259#L709-1 assume !(1 == ~E_5~0); 4260#L920-1 [2020-11-29 18:43:31,016 INFO L796 eck$LassoCheckResult]: Loop: 4260#L920-1 assume !false; 4742#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4268#L566 assume !false; 4269#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4340#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4341#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4336#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4337#L491 assume !(0 != eval_~tmp~0); 4767#L581 start_simulation_~kernel_st~0 := 2; 4580#L399-1 start_simulation_~kernel_st~0 := 3; 4581#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4782#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4502#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4503#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4564#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4452#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4453#L616-3 assume !(0 == ~E_M~0); 4273#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4274#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4328#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4329#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4585#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4586#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4652#L284-21 assume 1 == ~m_pc~0; 4632#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4633#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4635#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4636#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4655#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4656#L303-21 assume 1 == ~t1_pc~0; 4746#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4748#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4744#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4745#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4771#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4353#L322-21 assume 1 == ~t2_pc~0; 4295#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4296#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4293#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4294#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4566#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4567#L341-21 assume !(1 == ~t3_pc~0); 4545#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 4544#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4541#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4542#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4727#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4728#L360-21 assume 1 == ~t4_pc~0; 4674#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4675#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4671#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4672#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4775#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4460#L379-21 assume 1 == ~t5_pc~0; 4402#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4403#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4400#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4401#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4474#L775-23 assume !(1 == ~M_E~0); 4475#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4358#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4359#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4598#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4599#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4494#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4495#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4561#L694-3 assume !(1 == ~E_2~0); 4444#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4445#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4262#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4263#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4343#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4344#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4338#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4339#L939 assume !(0 == start_simulation_~tmp~3); 4569#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4348#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4349#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4346#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4347#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4600#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 4659#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4464#L952 assume !(0 != start_simulation_~tmp___0~1); 4260#L920-1 [2020-11-29 18:43:31,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,017 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2020-11-29 18:43:31,023 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,024 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954272049] [2020-11-29 18:43:31,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,057 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954272049] [2020-11-29 18:43:31,057 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,058 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,058 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758743776] [2020-11-29 18:43:31,058 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:31,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,059 INFO L82 PathProgramCache]: Analyzing trace with hash -673733141, now seen corresponding path program 1 times [2020-11-29 18:43:31,059 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,059 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903121266] [2020-11-29 18:43:31,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,113 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903121266] [2020-11-29 18:43:31,114 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,115 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,115 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389365034] [2020-11-29 18:43:31,116 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:31,116 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:31,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:31,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:31,117 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand 3 states. [2020-11-29 18:43:31,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:31,132 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2020-11-29 18:43:31,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:31,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2020-11-29 18:43:31,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:31,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2020-11-29 18:43:31,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2020-11-29 18:43:31,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2020-11-29 18:43:31,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2020-11-29 18:43:31,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:31,146 INFO L691 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2020-11-29 18:43:31,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2020-11-29 18:43:31,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2020-11-29 18:43:31,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2020-11-29 18:43:31,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2020-11-29 18:43:31,157 INFO L714 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2020-11-29 18:43:31,157 INFO L594 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2020-11-29 18:43:31,157 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-11-29 18:43:31,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2020-11-29 18:43:31,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-11-29 18:43:31,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:31,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:31,165 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,165 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,166 INFO L794 eck$LassoCheckResult]: Stem: 5792#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5687#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5662#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5649#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 5650#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5412#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5413#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5637#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5638#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5553#L431-1 assume !(0 == ~M_E~0); 5554#L591-1 assume !(0 == ~T1_E~0); 5557#L596-1 assume !(0 == ~T2_E~0); 5558#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5624#L606-1 assume !(0 == ~T4_E~0); 5507#L611-1 assume !(0 == ~T5_E~0); 5508#L616-1 assume !(0 == ~E_M~0); 5325#L621-1 assume !(0 == ~E_1~0); 5326#L626-1 assume !(0 == ~E_2~0); 5417#L631-1 assume !(0 == ~E_3~0); 5418#L636-1 assume !(0 == ~E_4~0); 5656#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5657#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5738#L284 assume 1 == ~m_pc~0; 5682#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5683#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5685#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5686#L735 assume !(0 != activate_threads_~tmp~1); 5834#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5428#L303 assume !(1 == ~t1_pc~0); 5429#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 5488#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5499#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5519#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5520#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5522#L322 assume 1 == ~t2_pc~0; 5366#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5367#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5364#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5365#L751 assume !(0 != activate_threads_~tmp___1~0); 5651#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5652#L341 assume !(1 == ~t3_pc~0); 5613#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 5614#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5610#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5611#L759 assume !(0 != activate_threads_~tmp___2~0); 5801#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5802#L360 assume 1 == ~t4_pc~0; 5749#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5750#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5745#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5746#L767 assume !(0 != activate_threads_~tmp___3~0); 5804#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5551#L379 assume !(1 == ~t5_pc~0); 5480#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 5479#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5475#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5339#L775 assume !(0 != activate_threads_~tmp___4~0); 5340#L775-2 assume !(1 == ~M_E~0); 5341#L659-1 assume !(1 == ~T1_E~0); 5415#L664-1 assume !(1 == ~T2_E~0); 5416#L669-1 assume !(1 == ~T3_E~0); 5654#L674-1 assume !(1 == ~T4_E~0); 5655#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5567#L684-1 assume !(1 == ~E_M~0); 5568#L689-1 assume !(1 == ~E_1~0); 5781#L694-1 assume !(1 == ~E_2~0); 5523#L699-1 assume !(1 == ~E_3~0); 5524#L704-1 assume !(1 == ~E_4~0); 5320#L709-1 assume !(1 == ~E_5~0); 5321#L920-1 [2020-11-29 18:43:31,166 INFO L796 eck$LassoCheckResult]: Loop: 5321#L920-1 assume !false; 5803#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5329#L566 assume !false; 5330#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5401#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5402#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5397#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5398#L491 assume !(0 != eval_~tmp~0); 5828#L581 start_simulation_~kernel_st~0 := 2; 5641#L399-1 start_simulation_~kernel_st~0 := 3; 5642#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5843#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5563#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5564#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5625#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5513#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5514#L616-3 assume !(0 == ~E_M~0); 5334#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5335#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5389#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5390#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5646#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5647#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5713#L284-21 assume 1 == ~m_pc~0; 5693#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5694#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5696#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5697#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5716#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5717#L303-21 assume !(1 == ~t1_pc~0); 5808#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 5809#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5805#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5806#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5832#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5414#L322-21 assume 1 == ~t2_pc~0; 5356#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5357#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5354#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5355#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5627#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5628#L341-21 assume 1 == ~t3_pc~0; 5604#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5605#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5602#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5603#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5788#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5789#L360-21 assume 1 == ~t4_pc~0; 5735#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5736#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5732#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5733#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5836#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5521#L379-21 assume 1 == ~t5_pc~0; 5463#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5464#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5461#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5462#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5535#L775-23 assume !(1 == ~M_E~0); 5536#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5419#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5420#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5659#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5660#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5555#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5556#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5622#L694-3 assume !(1 == ~E_2~0); 5505#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5506#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5323#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5324#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5404#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5405#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5399#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5400#L939 assume !(0 == start_simulation_~tmp~3); 5630#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5409#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5410#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5407#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5408#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5661#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 5720#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5525#L952 assume !(0 != start_simulation_~tmp___0~1); 5321#L920-1 [2020-11-29 18:43:31,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,166 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2020-11-29 18:43:31,167 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,167 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626047690] [2020-11-29 18:43:31,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,239 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626047690] [2020-11-29 18:43:31,239 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,239 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,239 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918246036] [2020-11-29 18:43:31,240 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:31,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,240 INFO L82 PathProgramCache]: Analyzing trace with hash 1584582507, now seen corresponding path program 1 times [2020-11-29 18:43:31,241 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,241 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753248092] [2020-11-29 18:43:31,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,293 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753248092] [2020-11-29 18:43:31,293 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,293 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,293 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313166008] [2020-11-29 18:43:31,294 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:31,294 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:31,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-29 18:43:31,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-29 18:43:31,295 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand 4 states. [2020-11-29 18:43:31,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:31,393 INFO L93 Difference]: Finished difference Result 936 states and 1405 transitions. [2020-11-29 18:43:31,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-29 18:43:31,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1405 transitions. [2020-11-29 18:43:31,401 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2020-11-29 18:43:31,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1405 transitions. [2020-11-29 18:43:31,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2020-11-29 18:43:31,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2020-11-29 18:43:31,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1405 transitions. [2020-11-29 18:43:31,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:31,414 INFO L691 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2020-11-29 18:43:31,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1405 transitions. [2020-11-29 18:43:31,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2020-11-29 18:43:31,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2020-11-29 18:43:31,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1405 transitions. [2020-11-29 18:43:31,471 INFO L714 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2020-11-29 18:43:31,471 INFO L594 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2020-11-29 18:43:31,471 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-11-29 18:43:31,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1405 transitions. [2020-11-29 18:43:31,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2020-11-29 18:43:31,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:31,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:31,486 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,486 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,487 INFO L794 eck$LassoCheckResult]: Stem: 7279#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7173#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7148#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7135#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 7136#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6886#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6887#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7123#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7124#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7033#L431-1 assume !(0 == ~M_E~0); 7034#L591-1 assume !(0 == ~T1_E~0); 7037#L596-1 assume !(0 == ~T2_E~0); 7038#L601-1 assume !(0 == ~T3_E~0); 7104#L606-1 assume !(0 == ~T4_E~0); 6983#L611-1 assume !(0 == ~T5_E~0); 6984#L616-1 assume !(0 == ~E_M~0); 6798#L621-1 assume !(0 == ~E_1~0); 6799#L626-1 assume !(0 == ~E_2~0); 6891#L631-1 assume !(0 == ~E_3~0); 6892#L636-1 assume !(0 == ~E_4~0); 7142#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 7143#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7225#L284 assume 1 == ~m_pc~0; 7168#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7169#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7171#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7172#L735 assume !(0 != activate_threads_~tmp~1); 7329#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6902#L303 assume !(1 == ~t1_pc~0); 6903#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 6962#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6974#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6994#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6995#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6997#L322 assume 1 == ~t2_pc~0; 6840#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6841#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6838#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6839#L751 assume !(0 != activate_threads_~tmp___1~0); 7137#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7138#L341 assume !(1 == ~t3_pc~0); 7093#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 7094#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7090#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7091#L759 assume !(0 != activate_threads_~tmp___2~0); 7288#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7289#L360 assume 1 == ~t4_pc~0; 7236#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7237#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7234#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7235#L767 assume !(0 != activate_threads_~tmp___3~0); 7294#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7031#L379 assume !(1 == ~t5_pc~0); 6955#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 6954#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6949#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6812#L775 assume !(0 != activate_threads_~tmp___4~0); 6813#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 6814#L659-1 assume !(1 == ~T1_E~0); 7374#L664-1 assume !(1 == ~T2_E~0); 7373#L669-1 assume !(1 == ~T3_E~0); 7330#L674-1 assume !(1 == ~T4_E~0); 7372#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7371#L684-1 assume !(1 == ~E_M~0); 7370#L689-1 assume !(1 == ~E_1~0); 7369#L694-1 assume !(1 == ~E_2~0); 7368#L699-1 assume !(1 == ~E_3~0); 7367#L704-1 assume !(1 == ~E_4~0); 6793#L709-1 assume !(1 == ~E_5~0); 6794#L920-1 [2020-11-29 18:43:31,487 INFO L796 eck$LassoCheckResult]: Loop: 6794#L920-1 assume !false; 7293#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6802#L566 assume !false; 6803#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6875#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6876#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6871#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6872#L491 assume !(0 != eval_~tmp~0); 7319#L581 start_simulation_~kernel_st~0 := 2; 7332#L399-1 start_simulation_~kernel_st~0 := 3; 7348#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7349#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7491#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7490#L601-3 assume !(0 == ~T3_E~0); 7489#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7488#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7487#L616-3 assume !(0 == ~E_M~0); 7486#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7485#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7484#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7483#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7482#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7481#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7480#L284-21 assume 1 == ~m_pc~0; 7478#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7477#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7476#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7475#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7474#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7473#L303-21 assume 1 == ~t1_pc~0; 7472#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7470#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7469#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7468#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7467#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7466#L322-21 assume 1 == ~t2_pc~0; 7464#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7463#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7462#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7461#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7460#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7459#L341-21 assume !(1 == ~t3_pc~0); 7457#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 7456#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7455#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7454#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7453#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7452#L360-21 assume 1 == ~t4_pc~0; 7450#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7449#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7448#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7447#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7446#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7445#L379-21 assume !(1 == ~t5_pc~0); 7443#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 7442#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7441#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7440#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7439#L775-23 assume !(1 == ~M_E~0); 7012#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7438#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7437#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7333#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7436#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7435#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7434#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7433#L694-3 assume !(1 == ~E_2~0); 7432#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7431#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7430#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7429#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7427#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7133#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7134#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7111#L939 assume !(0 == start_simulation_~tmp~3); 7112#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6883#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6884#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6881#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 6882#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7147#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 7206#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7000#L952 assume !(0 != start_simulation_~tmp___0~1); 6794#L920-1 [2020-11-29 18:43:31,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,488 INFO L82 PathProgramCache]: Analyzing trace with hash -515799174, now seen corresponding path program 1 times [2020-11-29 18:43:31,488 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,492 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272468890] [2020-11-29 18:43:31,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,532 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272468890] [2020-11-29 18:43:31,533 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,535 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,536 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163986978] [2020-11-29 18:43:31,536 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:31,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,537 INFO L82 PathProgramCache]: Analyzing trace with hash 1177580424, now seen corresponding path program 1 times [2020-11-29 18:43:31,537 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,537 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137288833] [2020-11-29 18:43:31,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,581 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137288833] [2020-11-29 18:43:31,581 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,582 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,583 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892909824] [2020-11-29 18:43:31,583 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:31,583 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:31,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-29 18:43:31,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-29 18:43:31,584 INFO L87 Difference]: Start difference. First operand 936 states and 1405 transitions. cyclomatic complexity: 471 Second operand 4 states. [2020-11-29 18:43:31,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:31,730 INFO L93 Difference]: Finished difference Result 1656 states and 2478 transitions. [2020-11-29 18:43:31,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-29 18:43:31,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1656 states and 2478 transitions. [2020-11-29 18:43:31,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2020-11-29 18:43:31,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1656 states to 1656 states and 2478 transitions. [2020-11-29 18:43:31,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1656 [2020-11-29 18:43:31,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1656 [2020-11-29 18:43:31,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1656 states and 2478 transitions. [2020-11-29 18:43:31,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:31,763 INFO L691 BuchiCegarLoop]: Abstraction has 1656 states and 2478 transitions. [2020-11-29 18:43:31,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states and 2478 transitions. [2020-11-29 18:43:31,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1654. [2020-11-29 18:43:31,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1654 states. [2020-11-29 18:43:31,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 2476 transitions. [2020-11-29 18:43:31,836 INFO L714 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2020-11-29 18:43:31,836 INFO L594 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2020-11-29 18:43:31,837 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-11-29 18:43:31,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1654 states and 2476 transitions. [2020-11-29 18:43:31,850 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2020-11-29 18:43:31,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:31,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:31,851 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,852 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:31,852 INFO L794 eck$LassoCheckResult]: Stem: 9901#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9780#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9755#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9742#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 9743#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9491#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9492#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9731#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9732#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9640#L431-1 assume !(0 == ~M_E~0); 9641#L591-1 assume !(0 == ~T1_E~0); 9644#L596-1 assume !(0 == ~T2_E~0); 9645#L601-1 assume !(0 == ~T3_E~0); 9711#L606-1 assume !(0 == ~T4_E~0); 9588#L611-1 assume !(0 == ~T5_E~0); 9589#L616-1 assume !(0 == ~E_M~0); 9402#L621-1 assume !(0 == ~E_1~0); 9403#L626-1 assume !(0 == ~E_2~0); 9496#L631-1 assume !(0 == ~E_3~0); 9497#L636-1 assume !(0 == ~E_4~0); 9749#L641-1 assume !(0 == ~E_5~0); 9750#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9834#L284 assume 1 == ~m_pc~0; 9775#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9776#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9778#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9779#L735 assume !(0 != activate_threads_~tmp~1); 9959#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9507#L303 assume !(1 == ~t1_pc~0); 9508#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 9568#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9579#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9600#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9601#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9603#L322 assume 1 == ~t2_pc~0; 9445#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9446#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9443#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9444#L751 assume !(0 != activate_threads_~tmp___1~0); 9744#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9745#L341 assume !(1 == ~t3_pc~0); 9700#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 9701#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9697#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9698#L759 assume !(0 != activate_threads_~tmp___2~0); 9918#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9919#L360 assume 1 == ~t4_pc~0; 9846#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9847#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9844#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9845#L767 assume !(0 != activate_threads_~tmp___3~0); 9922#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9638#L379 assume !(1 == ~t5_pc~0); 9561#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 9560#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9557#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9417#L775 assume !(0 != activate_threads_~tmp___4~0); 9418#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 9419#L659-1 assume !(1 == ~T1_E~0); 9807#L664-1 assume !(1 == ~T2_E~0); 9960#L669-1 assume !(1 == ~T3_E~0); 9961#L674-1 assume !(1 == ~T4_E~0); 9983#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9984#L684-1 assume !(1 == ~E_M~0); 9953#L689-1 assume !(1 == ~E_1~0); 9882#L694-1 assume !(1 == ~E_2~0); 9604#L699-1 assume !(1 == ~E_3~0); 9605#L704-1 assume !(1 == ~E_4~0); 9920#L709-1 assume !(1 == ~E_5~0); 10010#L920-1 [2020-11-29 18:43:31,852 INFO L796 eck$LassoCheckResult]: Loop: 10010#L920-1 assume !false; 10003#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10000#L566 assume !false; 9999#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9993#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9992#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9991#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9989#L491 assume !(0 != eval_~tmp~0); 9988#L581 start_simulation_~kernel_st~0 := 2; 9987#L399-1 start_simulation_~kernel_st~0 := 3; 9985#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9986#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10753#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10749#L601-3 assume !(0 == ~T3_E~0); 10745#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10740#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10735#L616-3 assume !(0 == ~E_M~0); 10731#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10726#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10721#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10691#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10689#L641-3 assume !(0 == ~E_5~0); 10687#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10686#L284-21 assume 1 == ~m_pc~0; 10684#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10633#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10631#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10629#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10627#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10626#L303-21 assume !(1 == ~t1_pc~0); 10624#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 10623#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10620#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10618#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10616#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10614#L322-21 assume !(1 == ~t2_pc~0); 10560#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 10557#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9433#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9434#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10468#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10466#L341-21 assume !(1 == ~t3_pc~0); 10462#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 10460#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9689#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9690#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9896#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9897#L360-21 assume 1 == ~t4_pc~0; 9831#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9832#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10251#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10242#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10237#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10225#L379-21 assume !(1 == ~t5_pc~0); 10221#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 10219#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10218#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10216#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10200#L775-23 assume !(1 == ~M_E~0); 9620#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10185#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10183#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9964#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10180#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10175#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10159#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10158#L694-3 assume !(1 == ~E_2~0); 10122#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10088#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10087#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10085#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10083#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10078#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10077#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 10076#L939 assume !(0 == start_simulation_~tmp~3); 9917#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10073#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10067#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10065#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 10063#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10061#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 10031#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 10019#L952 assume !(0 != start_simulation_~tmp___0~1); 10010#L920-1 [2020-11-29 18:43:31,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,853 INFO L82 PathProgramCache]: Analyzing trace with hash -531317892, now seen corresponding path program 1 times [2020-11-29 18:43:31,853 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,853 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651291282] [2020-11-29 18:43:31,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,894 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651291282] [2020-11-29 18:43:31,894 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,894 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:31,894 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519946293] [2020-11-29 18:43:31,895 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:31,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:31,895 INFO L82 PathProgramCache]: Analyzing trace with hash -902478652, now seen corresponding path program 1 times [2020-11-29 18:43:31,896 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:31,896 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149578595] [2020-11-29 18:43:31,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:31,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:31,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:31,941 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149578595] [2020-11-29 18:43:31,944 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:31,944 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:31,944 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503445218] [2020-11-29 18:43:31,945 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:31,945 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:31,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:31,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:31,946 INFO L87 Difference]: Start difference. First operand 1654 states and 2476 transitions. cyclomatic complexity: 826 Second operand 3 states. [2020-11-29 18:43:32,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:32,038 INFO L93 Difference]: Finished difference Result 3178 states and 4699 transitions. [2020-11-29 18:43:32,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:32,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3178 states and 4699 transitions. [2020-11-29 18:43:32,068 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3081 [2020-11-29 18:43:32,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3178 states to 3178 states and 4699 transitions. [2020-11-29 18:43:32,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3178 [2020-11-29 18:43:32,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3178 [2020-11-29 18:43:32,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3178 states and 4699 transitions. [2020-11-29 18:43:32,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:32,103 INFO L691 BuchiCegarLoop]: Abstraction has 3178 states and 4699 transitions. [2020-11-29 18:43:32,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3178 states and 4699 transitions. [2020-11-29 18:43:32,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3178 to 3018. [2020-11-29 18:43:32,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3018 states. [2020-11-29 18:43:32,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3018 states to 3018 states and 4475 transitions. [2020-11-29 18:43:32,170 INFO L714 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2020-11-29 18:43:32,170 INFO L594 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2020-11-29 18:43:32,170 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-11-29 18:43:32,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3018 states and 4475 transitions. [2020-11-29 18:43:32,188 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2921 [2020-11-29 18:43:32,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:32,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:32,190 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:32,190 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:32,190 INFO L794 eck$LassoCheckResult]: Stem: 14740#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 14613#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14591#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14578#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 14579#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14326#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14327#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14565#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14566#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14475#L431-1 assume !(0 == ~M_E~0); 14476#L591-1 assume !(0 == ~T1_E~0); 14480#L596-1 assume !(0 == ~T2_E~0); 14481#L601-1 assume !(0 == ~T3_E~0); 14547#L606-1 assume !(0 == ~T4_E~0); 14426#L611-1 assume !(0 == ~T5_E~0); 14427#L616-1 assume !(0 == ~E_M~0); 14240#L621-1 assume !(0 == ~E_1~0); 14241#L626-1 assume !(0 == ~E_2~0); 14334#L631-1 assume !(0 == ~E_3~0); 14335#L636-1 assume !(0 == ~E_4~0); 14585#L641-1 assume !(0 == ~E_5~0); 14586#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14683#L284 assume !(1 == ~m_pc~0); 14668#L284-2 is_master_triggered_~__retres1~0 := 0; 14669#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14611#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14612#L735 assume !(0 != activate_threads_~tmp~1); 14800#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14343#L303 assume !(1 == ~t1_pc~0); 14344#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 14404#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14415#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14438#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14439#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14441#L322 assume 1 == ~t2_pc~0; 14282#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14283#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14280#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14281#L751 assume !(0 != activate_threads_~tmp___1~0); 14580#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14581#L341 assume !(1 == ~t3_pc~0); 14537#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 14538#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14534#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14535#L759 assume !(0 != activate_threads_~tmp___2~0); 14754#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14755#L360 assume 1 == ~t4_pc~0; 14694#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14695#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14690#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14691#L767 assume !(0 != activate_threads_~tmp___3~0); 14761#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14474#L379 assume !(1 == ~t5_pc~0); 14397#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 14396#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14392#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14252#L775 assume !(0 != activate_threads_~tmp___4~0); 14253#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 14256#L659-1 assume !(1 == ~T1_E~0); 14644#L664-1 assume !(1 == ~T2_E~0); 14801#L669-1 assume !(1 == ~T3_E~0); 14802#L674-1 assume !(1 == ~T4_E~0); 16585#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14491#L684-1 assume !(1 == ~E_M~0); 14492#L689-1 assume !(1 == ~E_1~0); 14728#L694-1 assume !(1 == ~E_2~0); 14442#L699-1 assume !(1 == ~E_3~0); 14443#L704-1 assume !(1 == ~E_4~0); 14232#L709-1 assume !(1 == ~E_5~0); 14233#L920-1 [2020-11-29 18:43:32,191 INFO L796 eck$LassoCheckResult]: Loop: 14233#L920-1 assume !false; 16807#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 14482#L566 assume !false; 14924#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14925#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16812#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16811#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16810#L491 assume !(0 != eval_~tmp~0); 14804#L581 start_simulation_~kernel_st~0 := 2; 14805#L399-1 start_simulation_~kernel_st~0 := 3; 16809#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14824#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14487#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14488#L601-3 assume !(0 == ~T3_E~0); 14549#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14432#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14433#L616-3 assume !(0 == ~E_M~0); 14249#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14250#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14305#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14306#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14574#L641-3 assume !(0 == ~E_5~0); 14575#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14641#L284-21 assume !(1 == ~m_pc~0); 14639#L284-23 is_master_triggered_~__retres1~0 := 0; 14640#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14622#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14623#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14658#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14659#L303-21 assume 1 == ~t1_pc~0; 14764#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14766#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14762#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14763#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14798#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14331#L322-21 assume 1 == ~t2_pc~0; 14272#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14273#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14270#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14271#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14551#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14552#L341-21 assume 1 == ~t3_pc~0; 14528#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14529#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14526#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14527#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14736#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14737#L360-21 assume 1 == ~t4_pc~0; 14680#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14681#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14678#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14679#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14808#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14440#L379-21 assume 1 == ~t5_pc~0; 14384#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14385#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14378#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14379#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14456#L775-23 assume !(1 == ~M_E~0); 14457#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14336#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14337#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14588#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14589#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14478#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14479#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14546#L694-3 assume !(1 == ~E_2~0); 14424#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14425#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14238#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14239#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14321#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 14322#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14319#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 14320#L939 assume !(0 == start_simulation_~tmp~3); 14554#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17186#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17181#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17180#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 17179#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17178#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 17177#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 17176#L952 assume !(0 != start_simulation_~tmp___0~1); 14233#L920-1 [2020-11-29 18:43:32,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:32,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1870207229, now seen corresponding path program 1 times [2020-11-29 18:43:32,192 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:32,192 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921157873] [2020-11-29 18:43:32,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:32,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:32,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:32,251 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921157873] [2020-11-29 18:43:32,251 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:32,251 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-29 18:43:32,252 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594501838] [2020-11-29 18:43:32,252 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:32,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:32,253 INFO L82 PathProgramCache]: Analyzing trace with hash -2131940185, now seen corresponding path program 1 times [2020-11-29 18:43:32,253 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:32,253 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767789643] [2020-11-29 18:43:32,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:32,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:32,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:32,286 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767789643] [2020-11-29 18:43:32,287 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:32,287 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:32,287 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93561870] [2020-11-29 18:43:32,287 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:32,288 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:32,289 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-29 18:43:32,289 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-29 18:43:32,289 INFO L87 Difference]: Start difference. First operand 3018 states and 4475 transitions. cyclomatic complexity: 1465 Second operand 5 states. [2020-11-29 18:43:32,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:32,561 INFO L93 Difference]: Finished difference Result 8208 states and 12147 transitions. [2020-11-29 18:43:32,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-29 18:43:32,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8208 states and 12147 transitions. [2020-11-29 18:43:32,630 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7982 [2020-11-29 18:43:32,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8208 states to 8208 states and 12147 transitions. [2020-11-29 18:43:32,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8208 [2020-11-29 18:43:32,712 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8208 [2020-11-29 18:43:32,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8208 states and 12147 transitions. [2020-11-29 18:43:32,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:32,725 INFO L691 BuchiCegarLoop]: Abstraction has 8208 states and 12147 transitions. [2020-11-29 18:43:32,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8208 states and 12147 transitions. [2020-11-29 18:43:32,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8208 to 3171. [2020-11-29 18:43:32,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3171 states. [2020-11-29 18:43:32,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3171 states to 3171 states and 4628 transitions. [2020-11-29 18:43:32,883 INFO L714 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2020-11-29 18:43:32,883 INFO L594 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2020-11-29 18:43:32,883 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-11-29 18:43:32,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3171 states and 4628 transitions. [2020-11-29 18:43:32,899 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3071 [2020-11-29 18:43:32,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:32,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:32,900 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:32,900 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:32,901 INFO L794 eck$LassoCheckResult]: Stem: 25993#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 25859#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25837#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25824#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 25825#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25565#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25566#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25810#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25811#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25717#L431-1 assume !(0 == ~M_E~0); 25718#L591-1 assume !(0 == ~T1_E~0); 25722#L596-1 assume !(0 == ~T2_E~0); 25723#L601-1 assume !(0 == ~T3_E~0); 25788#L606-1 assume !(0 == ~T4_E~0); 25665#L611-1 assume !(0 == ~T5_E~0); 25666#L616-1 assume !(0 == ~E_M~0); 25479#L621-1 assume !(0 == ~E_1~0); 25480#L626-1 assume !(0 == ~E_2~0); 25573#L631-1 assume !(0 == ~E_3~0); 25574#L636-1 assume !(0 == ~E_4~0); 25831#L641-1 assume !(0 == ~E_5~0); 25832#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25930#L284 assume !(1 == ~m_pc~0); 25915#L284-2 is_master_triggered_~__retres1~0 := 0; 25916#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25857#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25858#L735 assume !(0 != activate_threads_~tmp~1); 26093#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25582#L303 assume !(1 == ~t1_pc~0); 25583#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 25645#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25654#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25678#L743 assume !(0 != activate_threads_~tmp___0~0); 25679#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25681#L322 assume 1 == ~t2_pc~0; 25521#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25522#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25519#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 25520#L751 assume !(0 != activate_threads_~tmp___1~0); 25826#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25827#L341 assume !(1 == ~t3_pc~0); 25778#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 25779#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25775#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25776#L759 assume !(0 != activate_threads_~tmp___2~0); 26004#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26005#L360 assume 1 == ~t4_pc~0; 25943#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25944#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25938#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25939#L767 assume !(0 != activate_threads_~tmp___3~0); 26010#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25716#L379 assume !(1 == ~t5_pc~0); 25638#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 25637#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25632#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25491#L775 assume !(0 != activate_threads_~tmp___4~0); 25492#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 25495#L659-1 assume !(1 == ~T1_E~0); 25571#L664-1 assume !(1 == ~T2_E~0); 25572#L669-1 assume !(1 == ~T3_E~0); 25829#L674-1 assume !(1 == ~T4_E~0); 25830#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25732#L684-1 assume !(1 == ~E_M~0); 25733#L689-1 assume !(1 == ~E_1~0); 25978#L694-1 assume !(1 == ~E_2~0); 25682#L699-1 assume !(1 == ~E_3~0); 25683#L704-1 assume !(1 == ~E_4~0); 27227#L709-1 assume !(1 == ~E_5~0); 27213#L920-1 [2020-11-29 18:43:32,901 INFO L796 eck$LassoCheckResult]: Loop: 27213#L920-1 assume !false; 27203#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 27180#L566 assume !false; 27094#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27000#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26996#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26995#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 26982#L491 assume !(0 != eval_~tmp~0); 26983#L581 start_simulation_~kernel_st~0 := 2; 28349#L399-1 start_simulation_~kernel_st~0 := 3; 28346#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28344#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28048#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28045#L601-3 assume !(0 == ~T3_E~0); 28043#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28041#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28039#L616-3 assume !(0 == ~E_M~0); 28037#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28035#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28032#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28031#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28020#L641-3 assume !(0 == ~E_5~0); 28013#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28012#L284-21 assume !(1 == ~m_pc~0); 28011#L284-23 is_master_triggered_~__retres1~0 := 0; 28010#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28009#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28008#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28007#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28006#L303-21 assume 1 == ~t1_pc~0; 28004#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 28002#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28000#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27998#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27991#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27986#L322-21 assume 1 == ~t2_pc~0; 27981#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 27976#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27965#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27943#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27937#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27930#L341-21 assume !(1 == ~t3_pc~0); 27921#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 27915#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27910#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27905#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27904#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27903#L360-21 assume 1 == ~t4_pc~0; 27864#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27861#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27859#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27857#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27855#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27853#L379-21 assume !(1 == ~t5_pc~0); 27849#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 27846#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27844#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27842#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 27840#L775-23 assume !(1 == ~M_E~0); 25697#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27836#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27834#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26096#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27831#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27829#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27814#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27808#L694-3 assume !(1 == ~E_2~0); 27799#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27793#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27786#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27624#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27598#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27592#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27590#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 27588#L939 assume !(0 == start_simulation_~tmp~3); 26003#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27319#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27311#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27309#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 27308#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27306#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 27304#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 27226#L952 assume !(0 != start_simulation_~tmp___0~1); 27213#L920-1 [2020-11-29 18:43:32,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:32,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1765228545, now seen corresponding path program 1 times [2020-11-29 18:43:32,902 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:32,902 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690217700] [2020-11-29 18:43:32,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:32,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:32,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:32,942 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690217700] [2020-11-29 18:43:32,942 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:32,943 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:32,943 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592723429] [2020-11-29 18:43:32,944 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:32,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:32,945 INFO L82 PathProgramCache]: Analyzing trace with hash -49631515, now seen corresponding path program 1 times [2020-11-29 18:43:32,949 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:32,950 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015795253] [2020-11-29 18:43:32,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:32,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:32,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:32,981 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015795253] [2020-11-29 18:43:32,981 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:32,981 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:32,981 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928783796] [2020-11-29 18:43:32,982 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:32,982 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:32,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-29 18:43:32,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-29 18:43:32,983 INFO L87 Difference]: Start difference. First operand 3171 states and 4628 transitions. cyclomatic complexity: 1465 Second operand 4 states. [2020-11-29 18:43:33,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:33,243 INFO L93 Difference]: Finished difference Result 7450 states and 10744 transitions. [2020-11-29 18:43:33,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-29 18:43:33,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7450 states and 10744 transitions. [2020-11-29 18:43:33,288 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7147 [2020-11-29 18:43:33,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7450 states to 7450 states and 10744 transitions. [2020-11-29 18:43:33,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7450 [2020-11-29 18:43:33,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7450 [2020-11-29 18:43:33,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7450 states and 10744 transitions. [2020-11-29 18:43:33,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:33,360 INFO L691 BuchiCegarLoop]: Abstraction has 7450 states and 10744 transitions. [2020-11-29 18:43:33,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7450 states and 10744 transitions. [2020-11-29 18:43:33,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7450 to 5823. [2020-11-29 18:43:33,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5823 states. [2020-11-29 18:43:33,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5823 states to 5823 states and 8450 transitions. [2020-11-29 18:43:33,566 INFO L714 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2020-11-29 18:43:33,566 INFO L594 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2020-11-29 18:43:33,566 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-11-29 18:43:33,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5823 states and 8450 transitions. [2020-11-29 18:43:33,594 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5720 [2020-11-29 18:43:33,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:33,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:33,596 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:33,596 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:33,597 INFO L794 eck$LassoCheckResult]: Stem: 36641#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36510#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36488#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36475#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 36476#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36198#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36199#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36462#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36463#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36360#L431-1 assume !(0 == ~M_E~0); 36361#L591-1 assume !(0 == ~T1_E~0); 36364#L596-1 assume !(0 == ~T2_E~0); 36365#L601-1 assume !(0 == ~T3_E~0); 36433#L606-1 assume !(0 == ~T4_E~0); 36305#L611-1 assume !(0 == ~T5_E~0); 36306#L616-1 assume !(0 == ~E_M~0); 36111#L621-1 assume !(0 == ~E_1~0); 36112#L626-1 assume !(0 == ~E_2~0); 36204#L631-1 assume !(0 == ~E_3~0); 36205#L636-1 assume !(0 == ~E_4~0); 36482#L641-1 assume !(0 == ~E_5~0); 36483#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36573#L284 assume !(1 == ~m_pc~0); 36557#L284-2 is_master_triggered_~__retres1~0 := 0; 36558#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36508#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36509#L735 assume !(0 != activate_threads_~tmp~1); 36727#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36222#L303 assume !(1 == ~t1_pc~0); 36223#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 36283#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36296#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36317#L743 assume !(0 != activate_threads_~tmp___0~0); 36318#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36320#L322 assume !(1 == ~t2_pc~0); 36468#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 36467#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36151#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36152#L751 assume !(0 != activate_threads_~tmp___1~0); 36477#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36478#L341 assume !(1 == ~t3_pc~0); 36420#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 36421#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36417#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36418#L759 assume !(0 != activate_threads_~tmp___2~0); 36655#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36656#L360 assume 1 == ~t4_pc~0; 36584#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36585#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36582#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36583#L767 assume !(0 != activate_threads_~tmp___3~0); 36662#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36358#L379 assume !(1 == ~t5_pc~0); 36277#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 36276#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36273#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36125#L775 assume !(0 != activate_threads_~tmp___4~0); 36126#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 36127#L659-1 assume !(1 == ~T1_E~0); 36537#L664-1 assume !(1 == ~T2_E~0); 36729#L669-1 assume !(1 == ~T3_E~0); 36730#L674-1 assume !(1 == ~T4_E~0); 36755#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36756#L684-1 assume !(1 == ~E_M~0); 36705#L689-1 assume !(1 == ~E_1~0); 36706#L694-1 assume !(1 == ~E_2~0); 36321#L699-1 assume !(1 == ~E_3~0); 36322#L704-1 assume !(1 == ~E_4~0); 36102#L709-1 assume !(1 == ~E_5~0); 36103#L920-1 [2020-11-29 18:43:33,597 INFO L796 eck$LassoCheckResult]: Loop: 36103#L920-1 assume !false; 39377#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 39375#L566 assume !false; 36474#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36187#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36188#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36183#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 36184#L491 assume !(0 != eval_~tmp~0); 36701#L581 start_simulation_~kernel_st~0 := 2; 39316#L399-1 start_simulation_~kernel_st~0 := 3; 39315#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 39314#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39313#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39312#L601-3 assume !(0 == ~T3_E~0); 39311#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39310#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39309#L616-3 assume !(0 == ~E_M~0); 39308#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39307#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39306#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39305#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39304#L641-3 assume !(0 == ~E_5~0); 39303#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39302#L284-21 assume !(1 == ~m_pc~0); 39301#L284-23 is_master_triggered_~__retres1~0 := 0; 39300#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39299#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 39298#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 39297#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39296#L303-21 assume 1 == ~t1_pc~0; 39294#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 39292#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39290#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 39288#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39287#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39286#L322-21 assume !(1 == ~t2_pc~0); 37820#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 39285#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39284#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 39283#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39282#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39281#L341-21 assume 1 == ~t3_pc~0; 39280#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 39278#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39277#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 39276#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 39275#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39274#L360-21 assume 1 == ~t4_pc~0; 39272#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 39271#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39270#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 39269#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 39268#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39267#L379-21 assume !(1 == ~t5_pc~0); 39265#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 39264#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39263#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 39262#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39261#L775-23 assume !(1 == ~M_E~0); 38670#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39260#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39259#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38831#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39258#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39257#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39256#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39255#L694-3 assume !(1 == ~E_2~0); 39254#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39253#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39252#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38368#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39250#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39245#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39244#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 36442#L939 assume !(0 == start_simulation_~tmp~3); 36443#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39402#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39396#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39393#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 39391#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39389#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 39387#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 39382#L952 assume !(0 != start_simulation_~tmp___0~1); 36103#L920-1 [2020-11-29 18:43:33,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:33,598 INFO L82 PathProgramCache]: Analyzing trace with hash -713779456, now seen corresponding path program 1 times [2020-11-29 18:43:33,598 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:33,598 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138366858] [2020-11-29 18:43:33,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:33,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:33,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:33,657 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138366858] [2020-11-29 18:43:33,657 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:33,657 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:33,657 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439842812] [2020-11-29 18:43:33,658 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:33,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:33,658 INFO L82 PathProgramCache]: Analyzing trace with hash -756249691, now seen corresponding path program 1 times [2020-11-29 18:43:33,658 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:33,659 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702840359] [2020-11-29 18:43:33,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:33,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:33,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:33,694 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702840359] [2020-11-29 18:43:33,695 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:33,695 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:33,695 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634897377] [2020-11-29 18:43:33,695 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:33,696 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:33,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-11-29 18:43:33,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-11-29 18:43:33,697 INFO L87 Difference]: Start difference. First operand 5823 states and 8450 transitions. cyclomatic complexity: 2635 Second operand 4 states. [2020-11-29 18:43:33,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:33,982 INFO L93 Difference]: Finished difference Result 13963 states and 20008 transitions. [2020-11-29 18:43:33,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-11-29 18:43:33,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13963 states and 20008 transitions. [2020-11-29 18:43:34,076 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13457 [2020-11-29 18:43:34,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13963 states to 13963 states and 20008 transitions. [2020-11-29 18:43:34,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13963 [2020-11-29 18:43:34,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13963 [2020-11-29 18:43:34,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13963 states and 20008 transitions. [2020-11-29 18:43:34,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:34,255 INFO L691 BuchiCegarLoop]: Abstraction has 13963 states and 20008 transitions. [2020-11-29 18:43:34,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13963 states and 20008 transitions. [2020-11-29 18:43:34,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13963 to 11074. [2020-11-29 18:43:34,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11074 states. [2020-11-29 18:43:34,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11074 states to 11074 states and 15959 transitions. [2020-11-29 18:43:34,483 INFO L714 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2020-11-29 18:43:34,483 INFO L594 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2020-11-29 18:43:34,483 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-11-29 18:43:34,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11074 states and 15959 transitions. [2020-11-29 18:43:34,616 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10964 [2020-11-29 18:43:34,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:34,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:34,618 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:34,618 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:34,618 INFO L794 eck$LassoCheckResult]: Stem: 56420#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56291#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56269#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56255#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 56256#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55993#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55994#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56238#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56239#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56147#L431-1 assume !(0 == ~M_E~0); 56148#L591-1 assume !(0 == ~T1_E~0); 56152#L596-1 assume !(0 == ~T2_E~0); 56153#L601-1 assume !(0 == ~T3_E~0); 56218#L606-1 assume !(0 == ~T4_E~0); 56097#L611-1 assume !(0 == ~T5_E~0); 56098#L616-1 assume !(0 == ~E_M~0); 55906#L621-1 assume !(0 == ~E_1~0); 55907#L626-1 assume !(0 == ~E_2~0); 56002#L631-1 assume !(0 == ~E_3~0); 56003#L636-1 assume !(0 == ~E_4~0); 56262#L641-1 assume !(0 == ~E_5~0); 56263#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56360#L284 assume !(1 == ~m_pc~0); 56344#L284-2 is_master_triggered_~__retres1~0 := 0; 56345#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56289#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56290#L735 assume !(0 != activate_threads_~tmp~1); 56496#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56014#L303 assume !(1 == ~t1_pc~0); 56015#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 56076#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56086#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56109#L743 assume !(0 != activate_threads_~tmp___0~0); 56110#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56112#L322 assume !(1 == ~t2_pc~0); 56246#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 56245#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55947#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55948#L751 assume !(0 != activate_threads_~tmp___1~0); 56257#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56258#L341 assume !(1 == ~t3_pc~0); 56208#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 56209#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56205#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56206#L759 assume !(0 != activate_threads_~tmp___2~0); 56434#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56435#L360 assume !(1 == ~t4_pc~0); 56522#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 56520#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56367#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56368#L767 assume !(0 != activate_threads_~tmp___3~0); 56440#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56145#L379 assume !(1 == ~t5_pc~0); 56070#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 56069#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56065#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55919#L775 assume !(0 != activate_threads_~tmp___4~0); 55920#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 55923#L659-1 assume !(1 == ~T1_E~0); 56322#L664-1 assume !(1 == ~T2_E~0); 56497#L669-1 assume !(1 == ~T3_E~0); 56498#L674-1 assume !(1 == ~T4_E~0); 56533#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56534#L684-1 assume !(1 == ~E_M~0); 56481#L689-1 assume !(1 == ~E_1~0); 56482#L694-1 assume !(1 == ~E_2~0); 56113#L699-1 assume !(1 == ~E_3~0); 56114#L704-1 assume !(1 == ~E_4~0); 55898#L709-1 assume !(1 == ~E_5~0); 55899#L920-1 [2020-11-29 18:43:34,619 INFO L796 eck$LassoCheckResult]: Loop: 55899#L920-1 assume !false; 65442#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 65047#L566 assume !false; 65000#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 64930#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 64920#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 64910#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 64894#L491 assume !(0 != eval_~tmp~0); 64895#L581 start_simulation_~kernel_st~0 := 2; 66876#L399-1 start_simulation_~kernel_st~0 := 3; 66875#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 66873#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66871#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66869#L601-3 assume !(0 == ~T3_E~0); 66867#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66865#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66863#L616-3 assume !(0 == ~E_M~0); 66859#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66857#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66855#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66853#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66850#L641-3 assume !(0 == ~E_5~0); 66849#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66848#L284-21 assume !(1 == ~m_pc~0); 66847#L284-23 is_master_triggered_~__retres1~0 := 0; 66846#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66845#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 66844#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 66843#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56483#L303-21 assume 1 == ~t1_pc~0; 56443#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56445#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66828#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66827#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56489#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55998#L322-21 assume !(1 == ~t2_pc~0); 55999#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 56004#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55937#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55938#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56223#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56224#L341-21 assume 1 == ~t3_pc~0; 56199#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56200#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56197#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56198#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56416#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56417#L360-21 assume !(1 == ~t4_pc~0); 56495#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 66194#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 66192#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 66190#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 66188#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 66186#L379-21 assume !(1 == ~t5_pc~0); 66183#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 66181#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66179#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 66177#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 66108#L775-23 assume !(1 == ~M_E~0); 64001#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66105#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66103#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66099#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66098#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66097#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66096#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66095#L694-3 assume !(1 == ~E_2~0); 66094#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66093#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66092#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63983#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 66090#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 66085#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 66083#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 65879#L939 assume !(0 == start_simulation_~tmp~3); 65876#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 65773#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 65767#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 65765#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 65762#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 65760#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 65758#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 65756#L952 assume !(0 != start_simulation_~tmp___0~1); 55899#L920-1 [2020-11-29 18:43:34,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:34,619 INFO L82 PathProgramCache]: Analyzing trace with hash 66201473, now seen corresponding path program 1 times [2020-11-29 18:43:34,619 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:34,619 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841093342] [2020-11-29 18:43:34,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:34,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:34,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:34,661 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841093342] [2020-11-29 18:43:34,661 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:34,661 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:34,663 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661395945] [2020-11-29 18:43:34,663 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:34,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:34,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1773900996, now seen corresponding path program 1 times [2020-11-29 18:43:34,664 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:34,664 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683226005] [2020-11-29 18:43:34,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:34,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:34,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:34,699 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683226005] [2020-11-29 18:43:34,699 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:34,699 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:34,699 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30793544] [2020-11-29 18:43:34,700 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:34,700 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:34,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:34,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:34,701 INFO L87 Difference]: Start difference. First operand 11074 states and 15959 transitions. cyclomatic complexity: 4893 Second operand 3 states. [2020-11-29 18:43:34,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:34,793 INFO L93 Difference]: Finished difference Result 13875 states and 19988 transitions. [2020-11-29 18:43:34,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:34,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13875 states and 19988 transitions. [2020-11-29 18:43:34,870 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13772 [2020-11-29 18:43:34,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13875 states to 13875 states and 19988 transitions. [2020-11-29 18:43:35,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13875 [2020-11-29 18:43:35,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13875 [2020-11-29 18:43:35,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13875 states and 19988 transitions. [2020-11-29 18:43:35,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:35,035 INFO L691 BuchiCegarLoop]: Abstraction has 13875 states and 19988 transitions. [2020-11-29 18:43:35,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13875 states and 19988 transitions. [2020-11-29 18:43:35,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13875 to 6055. [2020-11-29 18:43:35,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6055 states. [2020-11-29 18:43:35,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8760 transitions. [2020-11-29 18:43:35,166 INFO L714 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2020-11-29 18:43:35,166 INFO L594 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2020-11-29 18:43:35,167 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-11-29 18:43:35,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8760 transitions. [2020-11-29 18:43:35,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2020-11-29 18:43:35,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:35,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:35,193 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:35,194 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:35,194 INFO L794 eck$LassoCheckResult]: Stem: 81388#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81254#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81232#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81219#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 81220#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80946#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80947#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81204#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81205#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81103#L431-1 assume !(0 == ~M_E~0); 81104#L591-1 assume !(0 == ~T1_E~0); 81108#L596-1 assume !(0 == ~T2_E~0); 81109#L601-1 assume !(0 == ~T3_E~0); 81174#L606-1 assume !(0 == ~T4_E~0); 81054#L611-1 assume !(0 == ~T5_E~0); 81055#L616-1 assume !(0 == ~E_M~0); 80861#L621-1 assume !(0 == ~E_1~0); 80862#L626-1 assume !(0 == ~E_2~0); 80957#L631-1 assume !(0 == ~E_3~0); 80958#L636-1 assume !(0 == ~E_4~0); 81226#L641-1 assume !(0 == ~E_5~0); 81227#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81320#L284 assume !(1 == ~m_pc~0); 81304#L284-2 is_master_triggered_~__retres1~0 := 0; 81305#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81252#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81253#L735 assume !(0 != activate_threads_~tmp~1); 81464#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80971#L303 assume !(1 == ~t1_pc~0); 80972#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 81032#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81496#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81066#L743 assume !(0 != activate_threads_~tmp___0~0); 81067#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81069#L322 assume !(1 == ~t2_pc~0); 81212#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 81211#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80900#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 80901#L751 assume !(0 != activate_threads_~tmp___1~0); 81221#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81222#L341 assume !(1 == ~t3_pc~0); 81164#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 81165#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81161#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81162#L759 assume !(0 != activate_threads_~tmp___2~0); 81399#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81400#L360 assume !(1 == ~t4_pc~0); 81489#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 81487#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81327#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81328#L767 assume !(0 != activate_threads_~tmp___3~0); 81403#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81102#L379 assume !(1 == ~t5_pc~0); 81026#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 81025#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81021#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 80873#L775 assume !(0 != activate_threads_~tmp___4~0); 80874#L775-2 assume !(1 == ~M_E~0); 80877#L659-1 assume !(1 == ~T1_E~0); 80955#L664-1 assume !(1 == ~T2_E~0); 80956#L669-1 assume !(1 == ~T3_E~0); 81224#L674-1 assume !(1 == ~T4_E~0); 81225#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81118#L684-1 assume !(1 == ~E_M~0); 81119#L689-1 assume !(1 == ~E_1~0); 81368#L694-1 assume !(1 == ~E_2~0); 81070#L699-1 assume !(1 == ~E_3~0); 81071#L704-1 assume !(1 == ~E_4~0); 80854#L709-1 assume !(1 == ~E_5~0); 80855#L920-1 [2020-11-29 18:43:35,194 INFO L796 eck$LassoCheckResult]: Loop: 80855#L920-1 assume !false; 81401#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 80865#L566 assume !false; 80866#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 80936#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 80937#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 80934#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 80935#L491 assume !(0 != eval_~tmp~0); 81441#L581 start_simulation_~kernel_st~0 := 2; 81208#L399-1 start_simulation_~kernel_st~0 := 3; 81209#L591-2 assume !(0 == ~M_E~0); 81494#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81114#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81115#L601-3 assume !(0 == ~T3_E~0); 81178#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81060#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81061#L616-3 assume !(0 == ~E_M~0); 80870#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80871#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 80922#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80923#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81216#L641-3 assume !(0 == ~E_5~0); 81217#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81493#L284-21 assume !(1 == ~m_pc~0); 86881#L284-23 is_master_triggered_~__retres1~0 := 0; 86879#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86877#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 86875#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86872#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86871#L303-21 assume 1 == ~t1_pc~0; 86869#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 86866#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86863#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 86860#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86856#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86784#L322-21 assume !(1 == ~t2_pc~0); 86779#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 86775#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86772#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 86769#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86767#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86764#L341-21 assume !(1 == ~t3_pc~0); 86759#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 86757#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86754#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 86752#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86748#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86746#L360-21 assume !(1 == ~t4_pc~0); 86529#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 86743#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86741#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 86739#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 81469#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81068#L379-21 assume 1 == ~t5_pc~0; 81013#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 81014#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81007#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 81008#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 81082#L775-23 assume !(1 == ~M_E~0); 81988#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81986#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81984#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81980#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81979#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81976#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81974#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81972#L694-3 assume !(1 == ~E_2~0); 81969#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81967#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81962#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81707#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81663#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81647#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81639#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 81637#L939 assume !(0 == start_simulation_~tmp~3); 81191#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 80948#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 80949#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 80944#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 80945#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 81231#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 81298#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 81072#L952 assume !(0 != start_simulation_~tmp___0~1); 80855#L920-1 [2020-11-29 18:43:35,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:35,195 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2020-11-29 18:43:35,195 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:35,195 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528851989] [2020-11-29 18:43:35,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:35,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:35,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:35,285 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528851989] [2020-11-29 18:43:35,285 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:35,285 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:35,285 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94407489] [2020-11-29 18:43:35,286 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:35,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:35,287 INFO L82 PathProgramCache]: Analyzing trace with hash 2059455558, now seen corresponding path program 1 times [2020-11-29 18:43:35,288 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:35,288 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865406869] [2020-11-29 18:43:35,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:35,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:35,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:35,367 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865406869] [2020-11-29 18:43:35,368 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:35,368 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:35,368 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559122725] [2020-11-29 18:43:35,369 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:35,369 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:35,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:35,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:35,370 INFO L87 Difference]: Start difference. First operand 6055 states and 8760 transitions. cyclomatic complexity: 2707 Second operand 3 states. [2020-11-29 18:43:35,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:35,489 INFO L93 Difference]: Finished difference Result 6055 states and 8710 transitions. [2020-11-29 18:43:35,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:35,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6055 states and 8710 transitions. [2020-11-29 18:43:35,523 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2020-11-29 18:43:35,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6055 states to 6055 states and 8710 transitions. [2020-11-29 18:43:35,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6055 [2020-11-29 18:43:35,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6055 [2020-11-29 18:43:35,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6055 states and 8710 transitions. [2020-11-29 18:43:35,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:35,559 INFO L691 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2020-11-29 18:43:35,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6055 states and 8710 transitions. [2020-11-29 18:43:35,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6055 to 6055. [2020-11-29 18:43:35,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6055 states. [2020-11-29 18:43:35,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8710 transitions. [2020-11-29 18:43:35,676 INFO L714 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2020-11-29 18:43:35,676 INFO L594 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2020-11-29 18:43:35,676 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-11-29 18:43:35,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8710 transitions. [2020-11-29 18:43:35,703 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2020-11-29 18:43:35,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:35,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:35,706 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:35,706 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:35,707 INFO L794 eck$LassoCheckResult]: Stem: 93487#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 93363#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 93341#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 93328#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 93329#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93064#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93065#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93312#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93313#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93218#L431-1 assume !(0 == ~M_E~0); 93219#L591-1 assume !(0 == ~T1_E~0); 93222#L596-1 assume !(0 == ~T2_E~0); 93223#L601-1 assume !(0 == ~T3_E~0); 93289#L606-1 assume !(0 == ~T4_E~0); 93166#L611-1 assume !(0 == ~T5_E~0); 93167#L616-1 assume !(0 == ~E_M~0); 92978#L621-1 assume !(0 == ~E_1~0); 92979#L626-1 assume !(0 == ~E_2~0); 93070#L631-1 assume !(0 == ~E_3~0); 93071#L636-1 assume !(0 == ~E_4~0); 93335#L641-1 assume !(0 == ~E_5~0); 93336#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93427#L284 assume !(1 == ~m_pc~0); 93411#L284-2 is_master_triggered_~__retres1~0 := 0; 93412#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93361#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 93362#L735 assume !(0 != activate_threads_~tmp~1); 93553#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93087#L303 assume !(1 == ~t1_pc~0); 93088#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 93146#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93157#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 93178#L743 assume !(0 != activate_threads_~tmp___0~0); 93179#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93181#L322 assume !(1 == ~t2_pc~0); 93318#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 93317#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93017#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 93018#L751 assume !(0 != activate_threads_~tmp___1~0); 93330#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93331#L341 assume !(1 == ~t3_pc~0); 93278#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 93279#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93275#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 93276#L759 assume !(0 != activate_threads_~tmp___2~0); 93500#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93501#L360 assume !(1 == ~t4_pc~0); 93576#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 93574#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93436#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 93437#L767 assume !(0 != activate_threads_~tmp___3~0); 93503#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 93216#L379 assume !(1 == ~t5_pc~0); 93142#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 93141#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93136#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 92992#L775 assume !(0 != activate_threads_~tmp___4~0); 92993#L775-2 assume !(1 == ~M_E~0); 92994#L659-1 assume !(1 == ~T1_E~0); 93068#L664-1 assume !(1 == ~T2_E~0); 93069#L669-1 assume !(1 == ~T3_E~0); 93333#L674-1 assume !(1 == ~T4_E~0); 93334#L679-1 assume !(1 == ~T5_E~0); 93232#L684-1 assume !(1 == ~E_M~0); 93233#L689-1 assume !(1 == ~E_1~0); 93475#L694-1 assume !(1 == ~E_2~0); 93182#L699-1 assume !(1 == ~E_3~0); 93183#L704-1 assume !(1 == ~E_4~0); 92973#L709-1 assume !(1 == ~E_5~0); 92974#L920-1 [2020-11-29 18:43:35,707 INFO L796 eck$LassoCheckResult]: Loop: 92974#L920-1 assume !false; 97181#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 97178#L566 assume !false; 97177#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97171#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 97170#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97169#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 97167#L491 assume !(0 != eval_~tmp~0); 97168#L581 start_simulation_~kernel_st~0 := 2; 98812#L399-1 start_simulation_~kernel_st~0 := 3; 98811#L591-2 assume !(0 == ~M_E~0); 98810#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98809#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98808#L601-3 assume !(0 == ~T3_E~0); 98807#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98805#L611-3 assume !(0 == ~T5_E~0); 98804#L616-3 assume !(0 == ~E_M~0); 98803#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 98802#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98801#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98799#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98797#L641-3 assume !(0 == ~E_5~0); 98795#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98793#L284-21 assume !(1 == ~m_pc~0); 98792#L284-23 is_master_triggered_~__retres1~0 := 0; 98789#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98787#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 98421#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 98420#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98419#L303-21 assume !(1 == ~t1_pc~0); 98417#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 98415#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98413#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 98412#L743-21 assume !(0 != activate_threads_~tmp___0~0); 98410#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93066#L322-21 assume !(1 == ~t2_pc~0); 93067#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 98062#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98052#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 98049#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 98047#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98045#L341-21 assume 1 == ~t3_pc~0; 98043#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 98040#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98038#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 98035#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 98033#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93551#L360-21 assume !(1 == ~t4_pc~0); 93552#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 97303#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97301#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 97299#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 97297#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97295#L379-21 assume 1 == ~t5_pc~0; 97293#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 97289#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97287#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97285#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 97281#L775-23 assume !(1 == ~M_E~0); 97280#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97279#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97277#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97275#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97273#L679-3 assume !(1 == ~T5_E~0); 97271#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97269#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97266#L694-3 assume !(1 == ~E_2~0); 97264#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97262#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97260#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97258#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97254#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 97248#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97246#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 97211#L939 assume !(0 == start_simulation_~tmp~3); 97209#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97204#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 97198#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97195#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 97193#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 97191#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 97189#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 97188#L952 assume !(0 != start_simulation_~tmp___0~1); 92974#L920-1 [2020-11-29 18:43:35,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:35,709 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2020-11-29 18:43:35,709 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:35,710 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313013496] [2020-11-29 18:43:35,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:35,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:35,730 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:35,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:35,741 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:35,792 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:35,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:35,793 INFO L82 PathProgramCache]: Analyzing trace with hash -321984640, now seen corresponding path program 1 times [2020-11-29 18:43:35,793 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:35,793 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475292703] [2020-11-29 18:43:35,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:35,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:35,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:35,838 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475292703] [2020-11-29 18:43:35,838 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:35,839 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:35,839 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579409051] [2020-11-29 18:43:35,839 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:35,840 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:35,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:35,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:35,842 INFO L87 Difference]: Start difference. First operand 6055 states and 8710 transitions. cyclomatic complexity: 2657 Second operand 3 states. [2020-11-29 18:43:35,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:35,983 INFO L93 Difference]: Finished difference Result 10535 states and 15042 transitions. [2020-11-29 18:43:35,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:35,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10535 states and 15042 transitions. [2020-11-29 18:43:36,101 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10390 [2020-11-29 18:43:36,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10535 states to 10535 states and 15042 transitions. [2020-11-29 18:43:36,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10535 [2020-11-29 18:43:36,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10535 [2020-11-29 18:43:36,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10535 states and 15042 transitions. [2020-11-29 18:43:36,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:36,167 INFO L691 BuchiCegarLoop]: Abstraction has 10535 states and 15042 transitions. [2020-11-29 18:43:36,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10535 states and 15042 transitions. [2020-11-29 18:43:36,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10535 to 10519. [2020-11-29 18:43:36,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10519 states. [2020-11-29 18:43:36,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10519 states to 10519 states and 15026 transitions. [2020-11-29 18:43:36,296 INFO L714 BuchiCegarLoop]: Abstraction has 10519 states and 15026 transitions. [2020-11-29 18:43:36,296 INFO L594 BuchiCegarLoop]: Abstraction has 10519 states and 15026 transitions. [2020-11-29 18:43:36,296 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-11-29 18:43:36,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10519 states and 15026 transitions. [2020-11-29 18:43:36,334 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10374 [2020-11-29 18:43:36,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:36,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:36,338 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:36,338 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:36,338 INFO L794 eck$LassoCheckResult]: Stem: 110087#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 109965#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 109942#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 109928#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 109929#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109651#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109652#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109908#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109909#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109811#L431-1 assume !(0 == ~M_E~0); 109812#L591-1 assume !(0 == ~T1_E~0); 109816#L596-1 assume !(0 == ~T2_E~0); 109817#L601-1 assume !(0 == ~T3_E~0); 109882#L606-1 assume !(0 == ~T4_E~0); 109760#L611-1 assume !(0 == ~T5_E~0); 109761#L616-1 assume !(0 == ~E_M~0); 109574#L621-1 assume !(0 == ~E_1~0); 109575#L626-1 assume 0 == ~E_2~0;~E_2~0 := 1; 109994#L631-1 assume !(0 == ~E_3~0); 110172#L636-1 assume !(0 == ~E_4~0); 110173#L641-1 assume !(0 == ~E_5~0); 110209#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 110210#L284 assume !(1 == ~m_pc~0); 110009#L284-2 is_master_triggered_~__retres1~0 := 0; 110010#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110235#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 110177#L735 assume !(0 != activate_threads_~tmp~1); 110170#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 109677#L303 assume !(1 == ~t1_pc~0); 109678#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 110230#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 110231#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 109773#L743 assume !(0 != activate_threads_~tmp___0~0); 109774#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 109917#L322 assume !(1 == ~t2_pc~0); 109918#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 109915#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109916#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 110228#L751 assume !(0 != activate_threads_~tmp___1~0); 109930#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 109931#L341 assume !(1 == ~t3_pc~0); 109872#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 109873#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 109869#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 109870#L759 assume !(0 != activate_threads_~tmp___2~0); 110102#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110226#L360 assume !(1 == ~t4_pc~0); 110200#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 110192#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 110193#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 110224#L767 assume !(0 != activate_threads_~tmp___3~0); 110205#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110206#L379 assume !(1 == ~t5_pc~0); 110220#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 109807#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 109726#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 109586#L775 assume !(0 != activate_threads_~tmp___4~0); 109587#L775-2 assume !(1 == ~M_E~0); 109590#L659-1 assume !(1 == ~T1_E~0); 110216#L664-1 assume !(1 == ~T2_E~0); 110215#L669-1 assume !(1 == ~T3_E~0); 110214#L674-1 assume !(1 == ~T4_E~0); 110208#L679-1 assume !(1 == ~T5_E~0); 109826#L684-1 assume !(1 == ~E_M~0); 109827#L689-1 assume !(1 == ~E_1~0); 110074#L694-1 assume 1 == ~E_2~0;~E_2~0 := 2; 109778#L699-1 assume !(1 == ~E_3~0); 109779#L704-1 assume !(1 == ~E_4~0); 109567#L709-1 assume !(1 == ~E_5~0); 109568#L920-1 [2020-11-29 18:43:36,338 INFO L796 eck$LassoCheckResult]: Loop: 109568#L920-1 assume !false; 114413#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 114409#L566 assume !false; 114407#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 114396#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 114394#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 114392#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 114388#L491 assume !(0 != eval_~tmp~0); 114389#L581 start_simulation_~kernel_st~0 := 2; 119773#L399-1 start_simulation_~kernel_st~0 := 3; 119771#L591-2 assume !(0 == ~M_E~0); 119770#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119768#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 119767#L601-3 assume !(0 == ~T3_E~0); 119766#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119764#L611-3 assume !(0 == ~T5_E~0); 119763#L616-3 assume !(0 == ~E_M~0); 119760#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119757#L626-3 assume !(0 == ~E_2~0); 119758#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119994#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119993#L641-3 assume !(0 == ~E_5~0); 119992#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119991#L284-21 assume !(1 == ~m_pc~0); 119990#L284-23 is_master_triggered_~__retres1~0 := 0; 119989#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 119988#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 119987#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 119986#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 119985#L303-21 assume 1 == ~t1_pc~0; 119983#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 119984#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119995#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 119978#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 119977#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 119976#L322-21 assume !(1 == ~t2_pc~0); 119160#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 119975#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 119974#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 119973#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 119972#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 119971#L341-21 assume !(1 == ~t3_pc~0); 119969#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 119968#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119966#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 119963#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 119961#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119959#L360-21 assume !(1 == ~t4_pc~0); 113841#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 119956#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 119955#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 119954#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 119950#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 119948#L379-21 assume !(1 == ~t5_pc~0); 119945#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 119943#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 119940#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 119938#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 119936#L775-23 assume !(1 == ~M_E~0); 114238#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119933#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119931#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119929#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119927#L679-3 assume !(1 == ~T5_E~0); 119925#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119922#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119920#L694-3 assume !(1 == ~E_2~0); 109758#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109759#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109572#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 109573#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 109646#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 109647#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 109644#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 109645#L939 assume !(0 == start_simulation_~tmp~3); 109895#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 114474#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 114469#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 114465#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 114463#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 114462#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 114461#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 114457#L952 assume !(0 != start_simulation_~tmp___0~1); 109568#L920-1 [2020-11-29 18:43:36,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:36,339 INFO L82 PathProgramCache]: Analyzing trace with hash 560974661, now seen corresponding path program 1 times [2020-11-29 18:43:36,339 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:36,342 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010682742] [2020-11-29 18:43:36,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:36,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:36,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:36,383 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010682742] [2020-11-29 18:43:36,383 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:36,383 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:36,383 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778037802] [2020-11-29 18:43:36,384 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:36,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:36,387 INFO L82 PathProgramCache]: Analyzing trace with hash 452423203, now seen corresponding path program 1 times [2020-11-29 18:43:36,387 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:36,388 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539756984] [2020-11-29 18:43:36,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:36,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:36,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:36,426 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539756984] [2020-11-29 18:43:36,426 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:36,426 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-29 18:43:36,426 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051304802] [2020-11-29 18:43:36,427 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:36,427 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:36,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:36,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:36,428 INFO L87 Difference]: Start difference. First operand 10519 states and 15026 transitions. cyclomatic complexity: 4509 Second operand 3 states. [2020-11-29 18:43:36,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:36,505 INFO L93 Difference]: Finished difference Result 6047 states and 8600 transitions. [2020-11-29 18:43:36,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:36,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6047 states and 8600 transitions. [2020-11-29 18:43:36,533 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5964 [2020-11-29 18:43:36,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6047 states to 6047 states and 8600 transitions. [2020-11-29 18:43:36,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6047 [2020-11-29 18:43:36,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6047 [2020-11-29 18:43:36,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6047 states and 8600 transitions. [2020-11-29 18:43:36,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:36,561 INFO L691 BuchiCegarLoop]: Abstraction has 6047 states and 8600 transitions. [2020-11-29 18:43:36,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6047 states and 8600 transitions. [2020-11-29 18:43:36,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6047 to 6047. [2020-11-29 18:43:36,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6047 states. [2020-11-29 18:43:36,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6047 states to 6047 states and 8600 transitions. [2020-11-29 18:43:36,659 INFO L714 BuchiCegarLoop]: Abstraction has 6047 states and 8600 transitions. [2020-11-29 18:43:36,659 INFO L594 BuchiCegarLoop]: Abstraction has 6047 states and 8600 transitions. [2020-11-29 18:43:36,659 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-11-29 18:43:36,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6047 states and 8600 transitions. [2020-11-29 18:43:36,683 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5964 [2020-11-29 18:43:36,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:36,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:36,686 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:36,686 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:36,687 INFO L794 eck$LassoCheckResult]: Stem: 126668#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 126547#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 126525#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 126511#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 126512#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126230#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126231#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126493#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126494#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126391#L431-1 assume !(0 == ~M_E~0); 126392#L591-1 assume !(0 == ~T1_E~0); 126395#L596-1 assume !(0 == ~T2_E~0); 126396#L601-1 assume !(0 == ~T3_E~0); 126462#L606-1 assume !(0 == ~T4_E~0); 126333#L611-1 assume !(0 == ~T5_E~0); 126334#L616-1 assume !(0 == ~E_M~0); 126150#L621-1 assume !(0 == ~E_1~0); 126151#L626-1 assume !(0 == ~E_2~0); 126237#L631-1 assume !(0 == ~E_3~0); 126238#L636-1 assume !(0 == ~E_4~0); 126518#L641-1 assume !(0 == ~E_5~0); 126519#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 126610#L284 assume !(1 == ~m_pc~0); 126594#L284-2 is_master_triggered_~__retres1~0 := 0; 126595#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 126545#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 126546#L735 assume !(0 != activate_threads_~tmp~1); 126751#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 126253#L303 assume !(1 == ~t1_pc~0); 126254#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 126312#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 126324#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 126346#L743 assume !(0 != activate_threads_~tmp___0~0); 126347#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 126349#L322 assume !(1 == ~t2_pc~0); 126499#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 126498#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 126185#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 126186#L751 assume !(0 != activate_threads_~tmp___1~0); 126513#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 126514#L341 assume !(1 == ~t3_pc~0); 126451#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 126452#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 126448#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 126449#L759 assume !(0 != activate_threads_~tmp___2~0); 126685#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 126686#L360 assume !(1 == ~t4_pc~0); 126775#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 126773#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 126619#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 126620#L767 assume !(0 != activate_threads_~tmp___3~0); 126690#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 126389#L379 assume !(1 == ~t5_pc~0); 126308#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 126307#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 126302#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 126164#L775 assume !(0 != activate_threads_~tmp___4~0); 126165#L775-2 assume !(1 == ~M_E~0); 126166#L659-1 assume !(1 == ~T1_E~0); 126235#L664-1 assume !(1 == ~T2_E~0); 126236#L669-1 assume !(1 == ~T3_E~0); 126516#L674-1 assume !(1 == ~T4_E~0); 126517#L679-1 assume !(1 == ~T5_E~0); 126405#L684-1 assume !(1 == ~E_M~0); 126406#L689-1 assume !(1 == ~E_1~0); 126656#L694-1 assume !(1 == ~E_2~0); 126350#L699-1 assume !(1 == ~E_3~0); 126351#L704-1 assume !(1 == ~E_4~0); 126144#L709-1 assume !(1 == ~E_5~0); 126145#L920-1 [2020-11-29 18:43:36,687 INFO L796 eck$LassoCheckResult]: Loop: 126145#L920-1 assume !false; 128872#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 128869#L566 assume !false; 128867#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 128856#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 128854#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 128852#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 128848#L491 assume !(0 != eval_~tmp~0); 128849#L581 start_simulation_~kernel_st~0 := 2; 129622#L399-1 start_simulation_~kernel_st~0 := 3; 129620#L591-2 assume !(0 == ~M_E~0); 129618#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 129614#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129610#L601-3 assume !(0 == ~T3_E~0); 129606#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129602#L611-3 assume !(0 == ~T5_E~0); 129598#L616-3 assume !(0 == ~E_M~0); 129594#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129590#L626-3 assume !(0 == ~E_2~0); 129586#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129582#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129579#L641-3 assume !(0 == ~E_5~0); 129544#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129534#L284-21 assume !(1 == ~m_pc~0); 129525#L284-23 is_master_triggered_~__retres1~0 := 0; 129517#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129509#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129502#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 129493#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129481#L303-21 assume 1 == ~t1_pc~0; 129469#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 129429#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129430#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129180#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 129181#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128783#L322-21 assume !(1 == ~t2_pc~0); 128780#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 128779#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 128777#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 128775#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 128773#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128771#L341-21 assume 1 == ~t3_pc~0; 128769#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 128766#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128764#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 128762#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 128760#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 128758#L360-21 assume !(1 == ~t4_pc~0); 128528#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 128755#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128753#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 128751#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 128749#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128747#L379-21 assume 1 == ~t5_pc~0; 128745#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 128741#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128739#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 128737#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 128733#L775-23 assume !(1 == ~M_E~0); 128732#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128731#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128730#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128729#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128728#L679-3 assume !(1 == ~T5_E~0); 128727#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 128726#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128725#L694-3 assume !(1 == ~E_2~0); 128724#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128723#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128722#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 128720#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 128717#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 128712#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 128710#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 128708#L939 assume !(0 == start_simulation_~tmp~3); 128709#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 128916#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 128909#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 128907#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 128905#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 128903#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 128901#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 128899#L952 assume !(0 != start_simulation_~tmp___0~1); 126145#L920-1 [2020-11-29 18:43:36,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:36,688 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2020-11-29 18:43:36,688 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:36,688 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811734668] [2020-11-29 18:43:36,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:36,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:36,702 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:36,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:36,716 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:36,816 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:36,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:36,817 INFO L82 PathProgramCache]: Analyzing trace with hash -1629885467, now seen corresponding path program 1 times [2020-11-29 18:43:36,817 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:36,817 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459577031] [2020-11-29 18:43:36,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:36,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:36,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:36,858 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459577031] [2020-11-29 18:43:36,858 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:36,858 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-29 18:43:36,859 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897552972] [2020-11-29 18:43:36,859 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:36,859 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:36,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-29 18:43:36,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-29 18:43:36,860 INFO L87 Difference]: Start difference. First operand 6047 states and 8600 transitions. cyclomatic complexity: 2555 Second operand 5 states. [2020-11-29 18:43:37,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:37,049 INFO L93 Difference]: Finished difference Result 10795 states and 15160 transitions. [2020-11-29 18:43:37,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-11-29 18:43:37,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10795 states and 15160 transitions. [2020-11-29 18:43:37,102 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10704 [2020-11-29 18:43:37,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10795 states to 10795 states and 15160 transitions. [2020-11-29 18:43:37,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10795 [2020-11-29 18:43:37,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10795 [2020-11-29 18:43:37,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10795 states and 15160 transitions. [2020-11-29 18:43:37,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:37,154 INFO L691 BuchiCegarLoop]: Abstraction has 10795 states and 15160 transitions. [2020-11-29 18:43:37,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10795 states and 15160 transitions. [2020-11-29 18:43:37,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10795 to 6095. [2020-11-29 18:43:37,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6095 states. [2020-11-29 18:43:37,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6095 states to 6095 states and 8648 transitions. [2020-11-29 18:43:37,251 INFO L714 BuchiCegarLoop]: Abstraction has 6095 states and 8648 transitions. [2020-11-29 18:43:37,251 INFO L594 BuchiCegarLoop]: Abstraction has 6095 states and 8648 transitions. [2020-11-29 18:43:37,251 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-11-29 18:43:37,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6095 states and 8648 transitions. [2020-11-29 18:43:37,273 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2020-11-29 18:43:37,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:37,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:37,276 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:37,276 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:37,276 INFO L794 eck$LassoCheckResult]: Stem: 143518#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 143391#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 143369#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 143356#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 143357#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143083#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143084#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143335#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143336#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 143239#L431-1 assume !(0 == ~M_E~0); 143240#L591-1 assume !(0 == ~T1_E~0); 143244#L596-1 assume !(0 == ~T2_E~0); 143245#L601-1 assume !(0 == ~T3_E~0); 143313#L606-1 assume !(0 == ~T4_E~0); 143190#L611-1 assume !(0 == ~T5_E~0); 143191#L616-1 assume !(0 == ~E_M~0); 143007#L621-1 assume !(0 == ~E_1~0); 143008#L626-1 assume !(0 == ~E_2~0); 143093#L631-1 assume !(0 == ~E_3~0); 143094#L636-1 assume !(0 == ~E_4~0); 143363#L641-1 assume !(0 == ~E_5~0); 143364#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 143456#L284 assume !(1 == ~m_pc~0); 143440#L284-2 is_master_triggered_~__retres1~0 := 0; 143441#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 143389#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 143390#L735 assume !(0 != activate_threads_~tmp~1); 143589#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 143109#L303 assume !(1 == ~t1_pc~0); 143110#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 143170#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143179#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 143202#L743 assume !(0 != activate_threads_~tmp___0~0); 143203#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143205#L322 assume !(1 == ~t2_pc~0); 143344#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 143343#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 143042#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 143043#L751 assume !(0 != activate_threads_~tmp___1~0); 143358#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 143359#L341 assume !(1 == ~t3_pc~0); 143303#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 143304#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 143300#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 143301#L759 assume !(0 != activate_threads_~tmp___2~0); 143529#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 143530#L360 assume !(1 == ~t4_pc~0); 143609#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 143606#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 143464#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 143465#L767 assume !(0 != activate_threads_~tmp___3~0); 143532#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 143238#L379 assume !(1 == ~t5_pc~0); 143164#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 143163#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 143159#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 143019#L775 assume !(0 != activate_threads_~tmp___4~0); 143020#L775-2 assume !(1 == ~M_E~0); 143023#L659-1 assume !(1 == ~T1_E~0); 143091#L664-1 assume !(1 == ~T2_E~0); 143092#L669-1 assume !(1 == ~T3_E~0); 143361#L674-1 assume !(1 == ~T4_E~0); 143362#L679-1 assume !(1 == ~T5_E~0); 143257#L684-1 assume !(1 == ~E_M~0); 143258#L689-1 assume !(1 == ~E_1~0); 143504#L694-1 assume !(1 == ~E_2~0); 143206#L699-1 assume !(1 == ~E_3~0); 143207#L704-1 assume !(1 == ~E_4~0); 143000#L709-1 assume !(1 == ~E_5~0); 143001#L920-1 [2020-11-29 18:43:37,277 INFO L796 eck$LassoCheckResult]: Loop: 143001#L920-1 assume !false; 143531#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 143247#L566 assume !false; 143352#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 143073#L444 assume !(0 == ~m_st~0); 143075#L448 assume !(0 == ~t1_st~0); 143297#L452 assume !(0 == ~t2_st~0); 143231#L456 assume !(0 == ~t3_st~0); 143232#L460 assume !(0 == ~t4_st~0); 143254#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 143255#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 148763#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 148762#L491 assume !(0 != eval_~tmp~0); 143592#L581 start_simulation_~kernel_st~0 := 2; 143339#L399-1 start_simulation_~kernel_st~0 := 3; 143340#L591-2 assume !(0 == ~M_E~0); 143618#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143252#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143253#L601-3 assume !(0 == ~T3_E~0); 143315#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143196#L611-3 assume !(0 == ~T5_E~0); 143197#L616-3 assume !(0 == ~E_M~0); 143016#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 143017#L626-3 assume !(0 == ~E_2~0); 148208#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 148207#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 148206#L641-3 assume !(0 == ~E_5~0); 147378#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 147379#L284-21 assume !(1 == ~m_pc~0); 148205#L284-23 is_master_triggered_~__retres1~0 := 0; 148204#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 143799#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 143800#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 148203#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 143789#L303-21 assume !(1 == ~t1_pc~0); 143790#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 143796#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143754#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 143733#L743-21 assume !(0 != activate_threads_~tmp___0~0); 143724#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143725#L322-21 assume !(1 == ~t2_pc~0); 147911#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 148197#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 148196#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 148195#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 148194#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 148193#L341-21 assume 1 == ~t3_pc~0; 148192#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 148190#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 148189#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 148188#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 148187#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 148186#L360-21 assume !(1 == ~t4_pc~0); 146159#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 148185#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148184#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 148183#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 148182#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 148181#L379-21 assume !(1 == ~t5_pc~0); 148179#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 143229#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 143145#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 143146#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 143220#L775-23 assume !(1 == ~M_E~0); 143221#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143096#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143097#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143366#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143367#L679-3 assume !(1 == ~T5_E~0); 143242#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143243#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143312#L694-3 assume !(1 == ~E_2~0); 143188#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 143189#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143005#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143006#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 143078#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 143079#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 143076#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 143077#L939 assume !(0 == start_simulation_~tmp~3); 143322#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 143085#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 143086#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 143081#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 143082#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 143368#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 143435#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 143208#L952 assume !(0 != start_simulation_~tmp___0~1); 143001#L920-1 [2020-11-29 18:43:37,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:37,277 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2020-11-29 18:43:37,278 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:37,278 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318300988] [2020-11-29 18:43:37,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:37,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:37,294 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:37,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:37,303 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:37,325 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:37,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:37,325 INFO L82 PathProgramCache]: Analyzing trace with hash 1551874042, now seen corresponding path program 1 times [2020-11-29 18:43:37,325 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:37,326 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406233880] [2020-11-29 18:43:37,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:37,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:37,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:37,400 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406233880] [2020-11-29 18:43:37,400 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:37,401 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-11-29 18:43:37,401 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689958676] [2020-11-29 18:43:37,401 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:37,401 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:37,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-11-29 18:43:37,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-11-29 18:43:37,402 INFO L87 Difference]: Start difference. First operand 6095 states and 8648 transitions. cyclomatic complexity: 2555 Second operand 5 states. [2020-11-29 18:43:37,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:37,703 INFO L93 Difference]: Finished difference Result 12083 states and 17031 transitions. [2020-11-29 18:43:37,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-11-29 18:43:37,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12083 states and 17031 transitions. [2020-11-29 18:43:37,761 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12000 [2020-11-29 18:43:37,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12083 states to 12083 states and 17031 transitions. [2020-11-29 18:43:37,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12083 [2020-11-29 18:43:37,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12083 [2020-11-29 18:43:37,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12083 states and 17031 transitions. [2020-11-29 18:43:37,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:37,827 INFO L691 BuchiCegarLoop]: Abstraction has 12083 states and 17031 transitions. [2020-11-29 18:43:37,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12083 states and 17031 transitions. [2020-11-29 18:43:38,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12083 to 6251. [2020-11-29 18:43:38,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6251 states. [2020-11-29 18:43:38,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6251 states to 6251 states and 8759 transitions. [2020-11-29 18:43:38,034 INFO L714 BuchiCegarLoop]: Abstraction has 6251 states and 8759 transitions. [2020-11-29 18:43:38,034 INFO L594 BuchiCegarLoop]: Abstraction has 6251 states and 8759 transitions. [2020-11-29 18:43:38,034 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-11-29 18:43:38,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6251 states and 8759 transitions. [2020-11-29 18:43:38,058 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6168 [2020-11-29 18:43:38,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:38,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:38,060 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:38,060 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:38,061 INFO L794 eck$LassoCheckResult]: Stem: 161725#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 161586#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 161564#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 161551#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 161552#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161274#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161275#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161532#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161533#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161435#L431-1 assume !(0 == ~M_E~0); 161436#L591-1 assume !(0 == ~T1_E~0); 161440#L596-1 assume !(0 == ~T2_E~0); 161441#L601-1 assume !(0 == ~T3_E~0); 161509#L606-1 assume !(0 == ~T4_E~0); 161382#L611-1 assume !(0 == ~T5_E~0); 161383#L616-1 assume !(0 == ~E_M~0); 161198#L621-1 assume !(0 == ~E_1~0); 161199#L626-1 assume !(0 == ~E_2~0); 161284#L631-1 assume !(0 == ~E_3~0); 161285#L636-1 assume !(0 == ~E_4~0); 161558#L641-1 assume !(0 == ~E_5~0); 161559#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161660#L284 assume !(1 == ~m_pc~0); 161642#L284-2 is_master_triggered_~__retres1~0 := 0; 161643#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 161584#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 161585#L735 assume !(0 != activate_threads_~tmp~1); 161796#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 161299#L303 assume !(1 == ~t1_pc~0); 161300#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 161361#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 161371#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 161395#L743 assume !(0 != activate_threads_~tmp___0~0); 161396#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 161398#L322 assume !(1 == ~t2_pc~0); 161540#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 161539#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 161233#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 161234#L751 assume !(0 != activate_threads_~tmp___1~0); 161553#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 161554#L341 assume !(1 == ~t3_pc~0); 161499#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 161500#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161496#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 161497#L759 assume !(0 != activate_threads_~tmp___2~0); 161736#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 161737#L360 assume !(1 == ~t4_pc~0); 161821#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 161819#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161667#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 161668#L767 assume !(0 != activate_threads_~tmp___3~0); 161740#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 161434#L379 assume !(1 == ~t5_pc~0); 161355#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 161354#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161350#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 161210#L775 assume !(0 != activate_threads_~tmp___4~0); 161211#L775-2 assume !(1 == ~M_E~0); 161214#L659-1 assume !(1 == ~T1_E~0); 161282#L664-1 assume !(1 == ~T2_E~0); 161283#L669-1 assume !(1 == ~T3_E~0); 161556#L674-1 assume !(1 == ~T4_E~0); 161557#L679-1 assume !(1 == ~T5_E~0); 161453#L684-1 assume !(1 == ~E_M~0); 161454#L689-1 assume !(1 == ~E_1~0); 161714#L694-1 assume !(1 == ~E_2~0); 161399#L699-1 assume !(1 == ~E_3~0); 161400#L704-1 assume !(1 == ~E_4~0); 161191#L709-1 assume !(1 == ~E_5~0); 161192#L920-1 [2020-11-29 18:43:38,061 INFO L796 eck$LassoCheckResult]: Loop: 161192#L920-1 assume !false; 164562#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 164462#L566 assume !false; 164560#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 164547#L444 assume !(0 == ~m_st~0); 164548#L448 assume !(0 == ~t1_st~0); 164551#L452 assume !(0 == ~t2_st~0); 164553#L456 assume !(0 == ~t3_st~0); 164549#L460 assume !(0 == ~t4_st~0); 164550#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 164552#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 164469#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 164470#L491 assume !(0 != eval_~tmp~0); 166535#L581 start_simulation_~kernel_st~0 := 2; 166534#L399-1 start_simulation_~kernel_st~0 := 3; 166533#L591-2 assume !(0 == ~M_E~0); 166532#L591-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 166531#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 166530#L601-3 assume !(0 == ~T3_E~0); 166529#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 166528#L611-3 assume !(0 == ~T5_E~0); 166527#L616-3 assume !(0 == ~E_M~0); 166526#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 166525#L626-3 assume !(0 == ~E_2~0); 166524#L631-3 assume 0 == ~E_3~0;~E_3~0 := 1; 166523#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 166522#L641-3 assume !(0 == ~E_5~0); 166521#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161613#L284-21 assume !(1 == ~m_pc~0); 161614#L284-23 is_master_triggered_~__retres1~0 := 0; 162331#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 162332#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 162323#L735-21 assume !(0 != activate_threads_~tmp~1); 162324#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 162151#L303-21 assume !(1 == ~t1_pc~0); 162152#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 162135#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 162136#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 162111#L743-21 assume !(0 != activate_threads_~tmp___0~0); 162110#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162084#L322-21 assume !(1 == ~t2_pc~0); 162083#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 162082#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 162081#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 162080#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 162079#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 162078#L341-21 assume !(1 == ~t3_pc~0); 162076#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 162075#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 162074#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 162073#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 162072#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 162071#L360-21 assume !(1 == ~t4_pc~0); 162009#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 162004#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 162001#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 161999#L767-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 161997#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 161993#L379-21 assume !(1 == ~t5_pc~0); 161988#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 161985#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161981#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 161982#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 161974#L775-23 assume !(1 == ~M_E~0); 161975#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164237#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 164235#L669-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 164233#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164230#L679-3 assume !(1 == ~T5_E~0); 164228#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 164226#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 164224#L694-3 assume !(1 == ~E_2~0); 164222#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 164202#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 164196#L709-3 assume 1 == ~E_5~0;~E_5~0 := 2; 161961#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161959#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161954#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161953#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 161950#L939 assume !(0 == start_simulation_~tmp~3); 161951#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 164582#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 164576#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 164574#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 164571#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 164569#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 164567#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 164565#L952 assume !(0 != start_simulation_~tmp___0~1); 161192#L920-1 [2020-11-29 18:43:38,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:38,062 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 4 times [2020-11-29 18:43:38,062 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:38,062 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40753972] [2020-11-29 18:43:38,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:38,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,073 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,083 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,105 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:38,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:38,106 INFO L82 PathProgramCache]: Analyzing trace with hash -562965609, now seen corresponding path program 1 times [2020-11-29 18:43:38,106 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:38,107 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001386141] [2020-11-29 18:43:38,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:38,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:38,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:38,143 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001386141] [2020-11-29 18:43:38,143 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:38,143 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:38,144 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522167484] [2020-11-29 18:43:38,144 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-11-29 18:43:38,144 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:38,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:38,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:38,145 INFO L87 Difference]: Start difference. First operand 6251 states and 8759 transitions. cyclomatic complexity: 2510 Second operand 3 states. [2020-11-29 18:43:38,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:38,266 INFO L93 Difference]: Finished difference Result 10001 states and 13844 transitions. [2020-11-29 18:43:38,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:38,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10001 states and 13844 transitions. [2020-11-29 18:43:38,315 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9920 [2020-11-29 18:43:38,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10001 states to 10001 states and 13844 transitions. [2020-11-29 18:43:38,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10001 [2020-11-29 18:43:38,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10001 [2020-11-29 18:43:38,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10001 states and 13844 transitions. [2020-11-29 18:43:38,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:38,363 INFO L691 BuchiCegarLoop]: Abstraction has 10001 states and 13844 transitions. [2020-11-29 18:43:38,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10001 states and 13844 transitions. [2020-11-29 18:43:38,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10001 to 9697. [2020-11-29 18:43:38,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9697 states. [2020-11-29 18:43:38,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9697 states to 9697 states and 13440 transitions. [2020-11-29 18:43:38,487 INFO L714 BuchiCegarLoop]: Abstraction has 9697 states and 13440 transitions. [2020-11-29 18:43:38,487 INFO L594 BuchiCegarLoop]: Abstraction has 9697 states and 13440 transitions. [2020-11-29 18:43:38,487 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-11-29 18:43:38,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9697 states and 13440 transitions. [2020-11-29 18:43:38,523 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9616 [2020-11-29 18:43:38,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:38,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:38,525 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:38,525 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:38,525 INFO L794 eck$LassoCheckResult]: Stem: 177973#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 177847#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 177825#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 177812#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 177813#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 177533#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 177534#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 177794#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 177795#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 177699#L431-1 assume !(0 == ~M_E~0); 177700#L591-1 assume !(0 == ~T1_E~0); 177704#L596-1 assume !(0 == ~T2_E~0); 177705#L601-1 assume !(0 == ~T3_E~0); 177771#L606-1 assume !(0 == ~T4_E~0); 177639#L611-1 assume !(0 == ~T5_E~0); 177640#L616-1 assume !(0 == ~E_M~0); 177457#L621-1 assume !(0 == ~E_1~0); 177458#L626-1 assume !(0 == ~E_2~0); 177543#L631-1 assume !(0 == ~E_3~0); 177544#L636-1 assume !(0 == ~E_4~0); 177819#L641-1 assume !(0 == ~E_5~0); 177820#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 177916#L284 assume !(1 == ~m_pc~0); 177899#L284-2 is_master_triggered_~__retres1~0 := 0; 177900#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 177845#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 177846#L735 assume !(0 != activate_threads_~tmp~1); 178053#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 177557#L303 assume !(1 == ~t1_pc~0); 177558#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 177618#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 177628#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 177654#L743 assume !(0 != activate_threads_~tmp___0~0); 177655#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 177657#L322 assume !(1 == ~t2_pc~0); 177802#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 177801#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 177493#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 177494#L751 assume !(0 != activate_threads_~tmp___1~0); 177814#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 177815#L341 assume !(1 == ~t3_pc~0); 177761#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 177762#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 177758#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 177759#L759 assume !(0 != activate_threads_~tmp___2~0); 177991#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 177992#L360 assume !(1 == ~t4_pc~0); 178077#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 178075#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 177924#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 177925#L767 assume !(0 != activate_threads_~tmp___3~0); 177994#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 177697#L379 assume !(1 == ~t5_pc~0); 177612#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 177611#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 177607#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 177470#L775 assume !(0 != activate_threads_~tmp___4~0); 177471#L775-2 assume !(1 == ~M_E~0); 177474#L659-1 assume !(1 == ~T1_E~0); 177541#L664-1 assume !(1 == ~T2_E~0); 177542#L669-1 assume !(1 == ~T3_E~0); 177817#L674-1 assume !(1 == ~T4_E~0); 177818#L679-1 assume !(1 == ~T5_E~0); 177715#L684-1 assume !(1 == ~E_M~0); 177716#L689-1 assume !(1 == ~E_1~0); 177962#L694-1 assume !(1 == ~E_2~0); 177658#L699-1 assume !(1 == ~E_3~0); 177659#L704-1 assume !(1 == ~E_4~0); 177449#L709-1 assume !(1 == ~E_5~0); 177450#L920-1 assume !false; 178949#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 178945#L566 [2020-11-29 18:43:38,525 INFO L796 eck$LassoCheckResult]: Loop: 178945#L566 assume !false; 178942#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 178937#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 178934#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 178931#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 178927#L491 assume 0 != eval_~tmp~0; 178921#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 178918#L499 assume !(0 != eval_~tmp_ndt_1~0); 178915#L496 assume !(0 == ~t1_st~0); 178909#L510 assume !(0 == ~t2_st~0); 178906#L524 assume !(0 == ~t3_st~0); 178902#L538 assume !(0 == ~t4_st~0); 178901#L552 assume !(0 == ~t5_st~0); 178945#L566 [2020-11-29 18:43:38,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:38,526 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2020-11-29 18:43:38,526 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:38,526 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729318106] [2020-11-29 18:43:38,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:38,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,540 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,553 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,577 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:38,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:38,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1773192289, now seen corresponding path program 1 times [2020-11-29 18:43:38,579 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:38,579 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681569133] [2020-11-29 18:43:38,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:38,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,583 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:38,585 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:38,587 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:38,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:38,589 INFO L82 PathProgramCache]: Analyzing trace with hash 1802240287, now seen corresponding path program 1 times [2020-11-29 18:43:38,589 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:38,589 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117216821] [2020-11-29 18:43:38,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:38,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:38,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:38,625 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117216821] [2020-11-29 18:43:38,625 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:38,625 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:38,626 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099024865] [2020-11-29 18:43:38,722 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:38,722 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:38,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:38,722 INFO L87 Difference]: Start difference. First operand 9697 states and 13440 transitions. cyclomatic complexity: 3746 Second operand 3 states. [2020-11-29 18:43:39,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:39,010 INFO L93 Difference]: Finished difference Result 17961 states and 24730 transitions. [2020-11-29 18:43:39,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:39,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17961 states and 24730 transitions. [2020-11-29 18:43:39,097 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17804 [2020-11-29 18:43:39,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17961 states to 17961 states and 24730 transitions. [2020-11-29 18:43:39,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17961 [2020-11-29 18:43:39,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17961 [2020-11-29 18:43:39,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17961 states and 24730 transitions. [2020-11-29 18:43:39,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:39,370 INFO L691 BuchiCegarLoop]: Abstraction has 17961 states and 24730 transitions. [2020-11-29 18:43:39,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17961 states and 24730 transitions. [2020-11-29 18:43:39,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17961 to 17135. [2020-11-29 18:43:39,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17135 states. [2020-11-29 18:43:39,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17135 states to 17135 states and 23638 transitions. [2020-11-29 18:43:39,627 INFO L714 BuchiCegarLoop]: Abstraction has 17135 states and 23638 transitions. [2020-11-29 18:43:39,627 INFO L594 BuchiCegarLoop]: Abstraction has 17135 states and 23638 transitions. [2020-11-29 18:43:39,627 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2020-11-29 18:43:39,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17135 states and 23638 transitions. [2020-11-29 18:43:39,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16978 [2020-11-29 18:43:39,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:39,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:39,702 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:39,702 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:39,703 INFO L794 eck$LassoCheckResult]: Stem: 205641#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 205506#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 205484#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 205471#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 205472#L406-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 205537#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 207718#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 207717#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 207716#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 207715#L431-1 assume !(0 == ~M_E~0); 207714#L591-1 assume !(0 == ~T1_E~0); 207713#L596-1 assume !(0 == ~T2_E~0); 207712#L601-1 assume !(0 == ~T3_E~0); 207711#L606-1 assume !(0 == ~T4_E~0); 207710#L611-1 assume !(0 == ~T5_E~0); 207709#L616-1 assume !(0 == ~E_M~0); 207708#L621-1 assume !(0 == ~E_1~0); 207707#L626-1 assume !(0 == ~E_2~0); 207706#L631-1 assume !(0 == ~E_3~0); 207705#L636-1 assume !(0 == ~E_4~0); 207704#L641-1 assume !(0 == ~E_5~0); 207703#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 207702#L284 assume !(1 == ~m_pc~0); 207701#L284-2 is_master_triggered_~__retres1~0 := 0; 207700#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 207699#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 207698#L735 assume !(0 != activate_threads_~tmp~1); 207697#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 207696#L303 assume !(1 == ~t1_pc~0); 207695#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 205293#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 205294#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 205316#L743 assume !(0 != activate_threads_~tmp___0~0); 205317#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 205319#L322 assume !(1 == ~t2_pc~0); 205462#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 205461#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 205157#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 205158#L751 assume !(0 != activate_threads_~tmp___1~0); 205473#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 205474#L341 assume !(1 == ~t3_pc~0); 205646#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 207362#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 207361#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 207360#L759 assume !(0 != activate_threads_~tmp___2~0); 207359#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 207358#L360 assume !(1 == ~t4_pc~0); 207357#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 207356#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 207355#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 207354#L767 assume !(0 != activate_threads_~tmp___3~0); 207353#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 207352#L379 assume !(1 == ~t5_pc~0); 207350#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 207349#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 207348#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 207347#L775 assume !(0 != activate_threads_~tmp___4~0); 207346#L775-2 assume !(1 == ~M_E~0); 207345#L659-1 assume !(1 == ~T1_E~0); 207344#L664-1 assume !(1 == ~T2_E~0); 207343#L669-1 assume !(1 == ~T3_E~0); 207342#L674-1 assume !(1 == ~T4_E~0); 207341#L679-1 assume !(1 == ~T5_E~0); 207340#L684-1 assume !(1 == ~E_M~0); 207339#L689-1 assume !(1 == ~E_1~0); 207338#L694-1 assume !(1 == ~E_2~0); 207337#L699-1 assume !(1 == ~E_3~0); 207334#L704-1 assume !(1 == ~E_4~0); 207332#L709-1 assume !(1 == ~E_5~0); 207330#L920-1 assume !false; 207247#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 207243#L566 [2020-11-29 18:43:39,703 INFO L796 eck$LassoCheckResult]: Loop: 207243#L566 assume !false; 207241#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 207238#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 207236#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 207234#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 207231#L491 assume 0 != eval_~tmp~0; 207228#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 207225#L499 assume !(0 != eval_~tmp_ndt_1~0); 207226#L496 assume !(0 == ~t1_st~0); 207483#L510 assume !(0 == ~t2_st~0); 207479#L524 assume !(0 == ~t3_st~0); 207474#L538 assume !(0 == ~t4_st~0); 207245#L552 assume !(0 == ~t5_st~0); 207243#L566 [2020-11-29 18:43:39,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:39,704 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2020-11-29 18:43:39,704 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:39,704 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412935295] [2020-11-29 18:43:39,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:39,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:39,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:39,731 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412935295] [2020-11-29 18:43:39,731 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:39,731 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:39,731 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104394288] [2020-11-29 18:43:39,732 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-11-29 18:43:39,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:39,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1773192289, now seen corresponding path program 2 times [2020-11-29 18:43:39,732 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:39,733 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816673880] [2020-11-29 18:43:39,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:39,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:39,736 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:39,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:39,739 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:39,741 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:39,838 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:39,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:39,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:39,839 INFO L87 Difference]: Start difference. First operand 17135 states and 23638 transitions. cyclomatic complexity: 6506 Second operand 3 states. [2020-11-29 18:43:39,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:39,942 INFO L93 Difference]: Finished difference Result 17063 states and 23538 transitions. [2020-11-29 18:43:39,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:39,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17063 states and 23538 transitions. [2020-11-29 18:43:40,038 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16978 [2020-11-29 18:43:40,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17063 states to 17063 states and 23538 transitions. [2020-11-29 18:43:40,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17063 [2020-11-29 18:43:40,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17063 [2020-11-29 18:43:40,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17063 states and 23538 transitions. [2020-11-29 18:43:40,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:40,131 INFO L691 BuchiCegarLoop]: Abstraction has 17063 states and 23538 transitions. [2020-11-29 18:43:40,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17063 states and 23538 transitions. [2020-11-29 18:43:40,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17063 to 17063. [2020-11-29 18:43:40,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17063 states. [2020-11-29 18:43:40,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17063 states to 17063 states and 23538 transitions. [2020-11-29 18:43:40,570 INFO L714 BuchiCegarLoop]: Abstraction has 17063 states and 23538 transitions. [2020-11-29 18:43:40,570 INFO L594 BuchiCegarLoop]: Abstraction has 17063 states and 23538 transitions. [2020-11-29 18:43:40,570 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2020-11-29 18:43:40,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17063 states and 23538 transitions. [2020-11-29 18:43:40,634 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16978 [2020-11-29 18:43:40,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:40,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:40,636 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:40,636 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:40,636 INFO L794 eck$LassoCheckResult]: Stem: 239847#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 239717#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 239695#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 239682#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 239683#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 239402#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 239403#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239666#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239667#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 239563#L431-1 assume !(0 == ~M_E~0); 239564#L591-1 assume !(0 == ~T1_E~0); 239567#L596-1 assume !(0 == ~T2_E~0); 239568#L601-1 assume !(0 == ~T3_E~0); 239638#L606-1 assume !(0 == ~T4_E~0); 239509#L611-1 assume !(0 == ~T5_E~0); 239510#L616-1 assume !(0 == ~E_M~0); 239326#L621-1 assume !(0 == ~E_1~0); 239327#L626-1 assume !(0 == ~E_2~0); 239410#L631-1 assume !(0 == ~E_3~0); 239411#L636-1 assume !(0 == ~E_4~0); 239689#L641-1 assume !(0 == ~E_5~0); 239690#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 239790#L284 assume !(1 == ~m_pc~0); 239773#L284-2 is_master_triggered_~__retres1~0 := 0; 239774#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 239715#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 239716#L735 assume !(0 != activate_threads_~tmp~1); 239931#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 239427#L303 assume !(1 == ~t1_pc~0); 239428#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 239488#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 239500#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 239520#L743 assume !(0 != activate_threads_~tmp___0~0); 239521#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 239523#L322 assume !(1 == ~t2_pc~0); 239672#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 239671#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 239361#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 239362#L751 assume !(0 != activate_threads_~tmp___1~0); 239684#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 239685#L341 assume !(1 == ~t3_pc~0); 239625#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 239626#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 239622#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 239623#L759 assume !(0 != activate_threads_~tmp___2~0); 239857#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 239858#L360 assume !(1 == ~t4_pc~0); 239953#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 239952#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 239800#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 239801#L767 assume !(0 != activate_threads_~tmp___3~0); 239860#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 239561#L379 assume !(1 == ~t5_pc~0); 239484#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 239483#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 239478#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 239340#L775 assume !(0 != activate_threads_~tmp___4~0); 239341#L775-2 assume !(1 == ~M_E~0); 239342#L659-1 assume !(1 == ~T1_E~0); 239408#L664-1 assume !(1 == ~T2_E~0); 239409#L669-1 assume !(1 == ~T3_E~0); 239687#L674-1 assume !(1 == ~T4_E~0); 239688#L679-1 assume !(1 == ~T5_E~0); 239578#L684-1 assume !(1 == ~E_M~0); 239579#L689-1 assume !(1 == ~E_1~0); 239836#L694-1 assume !(1 == ~E_2~0); 239524#L699-1 assume !(1 == ~E_3~0); 239525#L704-1 assume !(1 == ~E_4~0); 239321#L709-1 assume !(1 == ~E_5~0); 239322#L920-1 assume !false; 241385#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 241380#L566 [2020-11-29 18:43:40,637 INFO L796 eck$LassoCheckResult]: Loop: 241380#L566 assume !false; 241375#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 241366#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 241362#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 241355#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 241350#L491 assume 0 != eval_~tmp~0; 241341#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 241334#L499 assume !(0 != eval_~tmp_ndt_1~0); 241326#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 241303#L513 assume !(0 != eval_~tmp_ndt_2~0); 241320#L510 assume !(0 == ~t2_st~0); 241331#L524 assume !(0 == ~t3_st~0); 241322#L538 assume !(0 == ~t4_st~0); 241317#L552 assume !(0 == ~t5_st~0); 241380#L566 [2020-11-29 18:43:40,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:40,637 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2020-11-29 18:43:40,637 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:40,638 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311040405] [2020-11-29 18:43:40,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:40,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:40,647 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:40,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:40,659 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:40,678 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:40,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:40,678 INFO L82 PathProgramCache]: Analyzing trace with hash -1754337525, now seen corresponding path program 1 times [2020-11-29 18:43:40,679 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:40,679 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460399503] [2020-11-29 18:43:40,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:40,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:40,683 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:40,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:40,685 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:40,688 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:40,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:40,689 INFO L82 PathProgramCache]: Analyzing trace with hash -853849587, now seen corresponding path program 1 times [2020-11-29 18:43:40,689 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:40,689 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798198658] [2020-11-29 18:43:40,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:40,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:40,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:40,726 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798198658] [2020-11-29 18:43:40,726 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:40,726 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:40,728 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512522470] [2020-11-29 18:43:40,953 WARN L193 SmtUtils]: Spent 153.00 ms on a formula simplification that was a NOOP. DAG size: 33 [2020-11-29 18:43:40,955 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:40,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:40,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:40,956 INFO L87 Difference]: Start difference. First operand 17063 states and 23538 transitions. cyclomatic complexity: 6478 Second operand 3 states. [2020-11-29 18:43:41,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:41,167 INFO L93 Difference]: Finished difference Result 32077 states and 44120 transitions. [2020-11-29 18:43:41,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:41,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32077 states and 44120 transitions. [2020-11-29 18:43:41,319 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31984 [2020-11-29 18:43:41,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32077 states to 32077 states and 44120 transitions. [2020-11-29 18:43:41,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32077 [2020-11-29 18:43:41,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32077 [2020-11-29 18:43:41,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32077 states and 44120 transitions. [2020-11-29 18:43:41,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:41,472 INFO L691 BuchiCegarLoop]: Abstraction has 32077 states and 44120 transitions. [2020-11-29 18:43:41,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32077 states and 44120 transitions. [2020-11-29 18:43:41,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32077 to 31419. [2020-11-29 18:43:41,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31419 states. [2020-11-29 18:43:41,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31419 states to 31419 states and 43238 transitions. [2020-11-29 18:43:41,989 INFO L714 BuchiCegarLoop]: Abstraction has 31419 states and 43238 transitions. [2020-11-29 18:43:41,989 INFO L594 BuchiCegarLoop]: Abstraction has 31419 states and 43238 transitions. [2020-11-29 18:43:41,990 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2020-11-29 18:43:41,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31419 states and 43238 transitions. [2020-11-29 18:43:42,270 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31326 [2020-11-29 18:43:42,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:42,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:42,273 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:42,273 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:42,273 INFO L794 eck$LassoCheckResult]: Stem: 289012#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 288880#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 288858#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 288843#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 288844#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 288549#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 288550#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 288826#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 288827#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 288718#L431-1 assume !(0 == ~M_E~0); 288719#L591-1 assume !(0 == ~T1_E~0); 288722#L596-1 assume !(0 == ~T2_E~0); 288723#L601-1 assume !(0 == ~T3_E~0); 288796#L606-1 assume !(0 == ~T4_E~0); 288656#L611-1 assume !(0 == ~T5_E~0); 288657#L616-1 assume !(0 == ~E_M~0); 288474#L621-1 assume !(0 == ~E_1~0); 288475#L626-1 assume !(0 == ~E_2~0); 288556#L631-1 assume !(0 == ~E_3~0); 288557#L636-1 assume !(0 == ~E_4~0); 288851#L641-1 assume !(0 == ~E_5~0); 288852#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 288951#L284 assume !(1 == ~m_pc~0); 288934#L284-2 is_master_triggered_~__retres1~0 := 0; 288935#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 288878#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 288879#L735 assume !(0 != activate_threads_~tmp~1); 289102#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 288574#L303 assume !(1 == ~t1_pc~0); 288575#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 288635#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 288647#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 288668#L743 assume !(0 != activate_threads_~tmp___0~0); 288669#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 288671#L322 assume !(1 == ~t2_pc~0); 288832#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 288831#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 288509#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 288510#L751 assume !(0 != activate_threads_~tmp___1~0); 288845#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 288846#L341 assume !(1 == ~t3_pc~0); 288785#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 288786#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 288782#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 288783#L759 assume !(0 != activate_threads_~tmp___2~0); 289027#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 289028#L360 assume !(1 == ~t4_pc~0); 289129#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 289127#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 288961#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 288962#L767 assume !(0 != activate_threads_~tmp___3~0); 289030#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 288716#L379 assume !(1 == ~t5_pc~0); 288631#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 288630#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 288625#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 288488#L775 assume !(0 != activate_threads_~tmp___4~0); 288489#L775-2 assume !(1 == ~M_E~0); 288490#L659-1 assume !(1 == ~T1_E~0); 288554#L664-1 assume !(1 == ~T2_E~0); 288555#L669-1 assume !(1 == ~T3_E~0); 288849#L674-1 assume !(1 == ~T4_E~0); 288850#L679-1 assume !(1 == ~T5_E~0); 288735#L684-1 assume !(1 == ~E_M~0); 288736#L689-1 assume !(1 == ~E_1~0); 288997#L694-1 assume !(1 == ~E_2~0); 288672#L699-1 assume !(1 == ~E_3~0); 288673#L704-1 assume !(1 == ~E_4~0); 288469#L709-1 assume !(1 == ~E_5~0); 288470#L920-1 assume !false; 296539#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 296535#L566 [2020-11-29 18:43:42,274 INFO L796 eck$LassoCheckResult]: Loop: 296535#L566 assume !false; 296533#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 296529#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 296527#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 296525#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 296522#L491 assume 0 != eval_~tmp~0; 296518#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 296513#L499 assume !(0 != eval_~tmp_ndt_1~0); 296301#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 295802#L513 assume !(0 != eval_~tmp_ndt_2~0); 296288#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 294312#L527 assume !(0 != eval_~tmp_ndt_3~0); 296465#L524 assume !(0 == ~t3_st~0); 296931#L538 assume !(0 == ~t4_st~0); 296537#L552 assume !(0 == ~t5_st~0); 296535#L566 [2020-11-29 18:43:42,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:42,274 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2020-11-29 18:43:42,275 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:42,275 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914927193] [2020-11-29 18:43:42,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:42,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:42,287 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:42,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:42,301 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:42,320 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:42,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:42,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1282897340, now seen corresponding path program 1 times [2020-11-29 18:43:42,321 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:42,321 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138099301] [2020-11-29 18:43:42,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:42,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:42,324 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:42,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:42,327 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:42,330 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:42,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:42,331 INFO L82 PathProgramCache]: Analyzing trace with hash -866747654, now seen corresponding path program 1 times [2020-11-29 18:43:42,331 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:42,331 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742402865] [2020-11-29 18:43:42,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:42,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:42,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:42,381 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742402865] [2020-11-29 18:43:42,382 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:42,382 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:42,382 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017689322] [2020-11-29 18:43:42,496 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:42,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:42,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:42,497 INFO L87 Difference]: Start difference. First operand 31419 states and 43238 transitions. cyclomatic complexity: 11822 Second operand 3 states. [2020-11-29 18:43:42,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:42,869 INFO L93 Difference]: Finished difference Result 57145 states and 78540 transitions. [2020-11-29 18:43:42,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:42,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57145 states and 78540 transitions. [2020-11-29 18:43:43,156 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 57036 [2020-11-29 18:43:43,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57145 states to 57145 states and 78540 transitions. [2020-11-29 18:43:43,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57145 [2020-11-29 18:43:43,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57145 [2020-11-29 18:43:43,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57145 states and 78540 transitions. [2020-11-29 18:43:43,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:43,689 INFO L691 BuchiCegarLoop]: Abstraction has 57145 states and 78540 transitions. [2020-11-29 18:43:43,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57145 states and 78540 transitions. [2020-11-29 18:43:44,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57145 to 55297. [2020-11-29 18:43:44,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55297 states. [2020-11-29 18:43:44,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55297 states to 55297 states and 76132 transitions. [2020-11-29 18:43:44,357 INFO L714 BuchiCegarLoop]: Abstraction has 55297 states and 76132 transitions. [2020-11-29 18:43:44,357 INFO L594 BuchiCegarLoop]: Abstraction has 55297 states and 76132 transitions. [2020-11-29 18:43:44,357 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2020-11-29 18:43:44,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55297 states and 76132 transitions. [2020-11-29 18:43:44,769 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 55188 [2020-11-29 18:43:44,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:44,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:44,771 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:44,772 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:44,772 INFO L794 eck$LassoCheckResult]: Stem: 377608#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 377458#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 377436#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 377422#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 377423#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 377121#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 377122#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 377401#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 377402#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 377288#L431-1 assume !(0 == ~M_E~0); 377289#L591-1 assume !(0 == ~T1_E~0); 377294#L596-1 assume !(0 == ~T2_E~0); 377295#L601-1 assume !(0 == ~T3_E~0); 377367#L606-1 assume !(0 == ~T4_E~0); 377229#L611-1 assume !(0 == ~T5_E~0); 377230#L616-1 assume !(0 == ~E_M~0); 377047#L621-1 assume !(0 == ~E_1~0); 377048#L626-1 assume !(0 == ~E_2~0); 377131#L631-1 assume !(0 == ~E_3~0); 377132#L636-1 assume !(0 == ~E_4~0); 377429#L641-1 assume !(0 == ~E_5~0); 377430#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 377535#L284 assume !(1 == ~m_pc~0); 377515#L284-2 is_master_triggered_~__retres1~0 := 0; 377516#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 377456#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 377457#L735 assume !(0 != activate_threads_~tmp~1); 377716#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 377144#L303 assume !(1 == ~t1_pc~0); 377145#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 377207#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 377218#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 377241#L743 assume !(0 != activate_threads_~tmp___0~0); 377242#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 377244#L322 assume !(1 == ~t2_pc~0); 377409#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 377408#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 377082#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 377083#L751 assume !(0 != activate_threads_~tmp___1~0); 377424#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 377425#L341 assume !(1 == ~t3_pc~0); 377357#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 377358#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 377354#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 377355#L759 assume !(0 != activate_threads_~tmp___2~0); 377625#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 377626#L360 assume !(1 == ~t4_pc~0); 377744#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 377742#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 377543#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 377544#L767 assume !(0 != activate_threads_~tmp___3~0); 377630#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 377287#L379 assume !(1 == ~t5_pc~0); 377200#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 377199#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 377194#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 377059#L775 assume !(0 != activate_threads_~tmp___4~0); 377060#L775-2 assume !(1 == ~M_E~0); 377063#L659-1 assume !(1 == ~T1_E~0); 377129#L664-1 assume !(1 == ~T2_E~0); 377130#L669-1 assume !(1 == ~T3_E~0); 377427#L674-1 assume !(1 == ~T4_E~0); 377428#L679-1 assume !(1 == ~T5_E~0); 377307#L684-1 assume !(1 == ~E_M~0); 377308#L689-1 assume !(1 == ~E_1~0); 377587#L694-1 assume !(1 == ~E_2~0); 377245#L699-1 assume !(1 == ~E_3~0); 377246#L704-1 assume !(1 == ~E_4~0); 377039#L709-1 assume !(1 == ~E_5~0); 377040#L920-1 assume !false; 391536#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 391530#L566 [2020-11-29 18:43:44,773 INFO L796 eck$LassoCheckResult]: Loop: 391530#L566 assume !false; 391531#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 391523#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 391524#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 391518#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 391519#L491 assume 0 != eval_~tmp~0; 391824#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 391821#L499 assume !(0 != eval_~tmp_ndt_1~0); 389151#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 388459#L513 assume !(0 != eval_~tmp_ndt_2~0); 388458#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 388456#L527 assume !(0 != eval_~tmp_ndt_3~0); 388457#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 386846#L541 assume !(0 != eval_~tmp_ndt_4~0); 390768#L538 assume !(0 == ~t4_st~0); 391560#L552 assume !(0 == ~t5_st~0); 391530#L566 [2020-11-29 18:43:44,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:44,773 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2020-11-29 18:43:44,773 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:44,774 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103598430] [2020-11-29 18:43:44,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:44,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:44,784 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:44,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:44,794 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:44,811 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:44,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:44,812 INFO L82 PathProgramCache]: Analyzing trace with hash 1109719472, now seen corresponding path program 1 times [2020-11-29 18:43:44,812 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:44,812 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099769270] [2020-11-29 18:43:44,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:44,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:44,816 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:44,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:44,819 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:44,822 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:44,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:44,824 INFO L82 PathProgramCache]: Analyzing trace with hash -1104765902, now seen corresponding path program 1 times [2020-11-29 18:43:44,824 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:44,825 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335032821] [2020-11-29 18:43:44,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:44,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:44,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:44,873 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335032821] [2020-11-29 18:43:44,874 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:44,874 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-11-29 18:43:44,874 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835652732] [2020-11-29 18:43:44,982 WARN L193 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2020-11-29 18:43:45,037 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:45,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:45,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:45,038 INFO L87 Difference]: Start difference. First operand 55297 states and 76132 transitions. cyclomatic complexity: 20838 Second operand 3 states. [2020-11-29 18:43:45,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:45,414 INFO L93 Difference]: Finished difference Result 102581 states and 141000 transitions. [2020-11-29 18:43:45,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:45,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102581 states and 141000 transitions. [2020-11-29 18:43:46,105 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 102440 [2020-11-29 18:43:46,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102581 states to 102581 states and 141000 transitions. [2020-11-29 18:43:46,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102581 [2020-11-29 18:43:46,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102581 [2020-11-29 18:43:46,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102581 states and 141000 transitions. [2020-11-29 18:43:46,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:46,524 INFO L691 BuchiCegarLoop]: Abstraction has 102581 states and 141000 transitions. [2020-11-29 18:43:46,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102581 states and 141000 transitions. [2020-11-29 18:43:47,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102581 to 101461. [2020-11-29 18:43:47,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101461 states. [2020-11-29 18:43:47,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101461 states to 101461 states and 139544 transitions. [2020-11-29 18:43:47,940 INFO L714 BuchiCegarLoop]: Abstraction has 101461 states and 139544 transitions. [2020-11-29 18:43:47,940 INFO L594 BuchiCegarLoop]: Abstraction has 101461 states and 139544 transitions. [2020-11-29 18:43:47,940 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2020-11-29 18:43:47,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101461 states and 139544 transitions. [2020-11-29 18:43:48,573 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 101320 [2020-11-29 18:43:48,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:48,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:48,575 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:48,575 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:48,575 INFO L794 eck$LassoCheckResult]: Stem: 535482#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 535344#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 535322#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 535308#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 535309#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 535006#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 535007#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 535287#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 535288#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 535177#L431-1 assume !(0 == ~M_E~0); 535178#L591-1 assume !(0 == ~T1_E~0); 535183#L596-1 assume !(0 == ~T2_E~0); 535184#L601-1 assume !(0 == ~T3_E~0); 535258#L606-1 assume !(0 == ~T4_E~0); 535115#L611-1 assume !(0 == ~T5_E~0); 535116#L616-1 assume !(0 == ~E_M~0); 534932#L621-1 assume !(0 == ~E_1~0); 534933#L626-1 assume !(0 == ~E_2~0); 535016#L631-1 assume !(0 == ~E_3~0); 535017#L636-1 assume !(0 == ~E_4~0); 535316#L641-1 assume !(0 == ~E_5~0); 535317#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 535419#L284 assume !(1 == ~m_pc~0); 535401#L284-2 is_master_triggered_~__retres1~0 := 0; 535402#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 535342#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 535343#L735 assume !(0 != activate_threads_~tmp~1); 535586#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 535034#L303 assume !(1 == ~t1_pc~0); 535035#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 535094#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 535107#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 535129#L743 assume !(0 != activate_threads_~tmp___0~0); 535130#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 535132#L322 assume !(1 == ~t2_pc~0); 535295#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 535294#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 534968#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 534969#L751 assume !(0 != activate_threads_~tmp___1~0); 535310#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 535311#L341 assume !(1 == ~t3_pc~0); 535248#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 535249#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 535245#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 535246#L759 assume !(0 != activate_threads_~tmp___2~0); 535501#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 535502#L360 assume !(1 == ~t4_pc~0); 535617#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 535616#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 535426#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 535427#L767 assume !(0 != activate_threads_~tmp___3~0); 535506#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 535175#L379 assume !(1 == ~t5_pc~0); 535087#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 535086#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 535081#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 534945#L775 assume !(0 != activate_threads_~tmp___4~0); 534946#L775-2 assume !(1 == ~M_E~0); 534949#L659-1 assume !(1 == ~T1_E~0); 535014#L664-1 assume !(1 == ~T2_E~0); 535015#L669-1 assume !(1 == ~T3_E~0); 535314#L674-1 assume !(1 == ~T4_E~0); 535315#L679-1 assume !(1 == ~T5_E~0); 535198#L684-1 assume !(1 == ~E_M~0); 535199#L689-1 assume !(1 == ~E_1~0); 535468#L694-1 assume !(1 == ~E_2~0); 535133#L699-1 assume !(1 == ~E_3~0); 535134#L704-1 assume !(1 == ~E_4~0); 534927#L709-1 assume !(1 == ~E_5~0); 534928#L920-1 assume !false; 563451#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 563447#L566 [2020-11-29 18:43:48,576 INFO L796 eck$LassoCheckResult]: Loop: 563447#L566 assume !false; 563445#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 563442#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 563441#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 563440#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 563439#L491 assume 0 != eval_~tmp~0; 563437#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 563435#L499 assume !(0 != eval_~tmp_ndt_1~0); 563434#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 562438#L513 assume !(0 != eval_~tmp_ndt_2~0); 563433#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 558938#L527 assume !(0 != eval_~tmp_ndt_3~0); 563544#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 563542#L541 assume !(0 != eval_~tmp_ndt_4~0); 563541#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 560895#L555 assume !(0 != eval_~tmp_ndt_5~0); 563449#L552 assume !(0 == ~t5_st~0); 563447#L566 [2020-11-29 18:43:48,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:48,576 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2020-11-29 18:43:48,576 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:48,576 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038736293] [2020-11-29 18:43:48,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:48,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:48,593 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:48,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:48,611 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:48,636 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:48,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:48,637 INFO L82 PathProgramCache]: Analyzing trace with hash 41392919, now seen corresponding path program 1 times [2020-11-29 18:43:48,638 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:48,638 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125431939] [2020-11-29 18:43:48,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:48,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:48,647 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:48,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:48,649 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:48,651 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:48,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:48,652 INFO L82 PathProgramCache]: Analyzing trace with hash 111823061, now seen corresponding path program 1 times [2020-11-29 18:43:48,653 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:48,653 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648755526] [2020-11-29 18:43:48,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:48,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-11-29 18:43:48,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-11-29 18:43:48,700 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648755526] [2020-11-29 18:43:48,701 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-11-29 18:43:48,701 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-11-29 18:43:48,701 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739232769] [2020-11-29 18:43:48,819 WARN L193 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2020-11-29 18:43:48,881 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-11-29 18:43:48,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-11-29 18:43:48,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-11-29 18:43:48,882 INFO L87 Difference]: Start difference. First operand 101461 states and 139544 transitions. cyclomatic complexity: 38086 Second operand 3 states. [2020-11-29 18:43:49,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-11-29 18:43:49,485 INFO L93 Difference]: Finished difference Result 175605 states and 241408 transitions. [2020-11-29 18:43:49,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-11-29 18:43:49,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175605 states and 241408 transitions. [2020-11-29 18:43:50,646 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 175400 [2020-11-29 18:43:50,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175605 states to 175605 states and 241408 transitions. [2020-11-29 18:43:50,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 175605 [2020-11-29 18:43:51,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 175605 [2020-11-29 18:43:51,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175605 states and 241408 transitions. [2020-11-29 18:43:51,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-11-29 18:43:51,096 INFO L691 BuchiCegarLoop]: Abstraction has 175605 states and 241408 transitions. [2020-11-29 18:43:51,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175605 states and 241408 transitions. [2020-11-29 18:43:52,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175605 to 174261. [2020-11-29 18:43:52,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174261 states. [2020-11-29 18:43:53,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174261 states to 174261 states and 240064 transitions. [2020-11-29 18:43:53,219 INFO L714 BuchiCegarLoop]: Abstraction has 174261 states and 240064 transitions. [2020-11-29 18:43:53,219 INFO L594 BuchiCegarLoop]: Abstraction has 174261 states and 240064 transitions. [2020-11-29 18:43:53,219 INFO L427 BuchiCegarLoop]: ======== Iteration 25============ [2020-11-29 18:43:53,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 174261 states and 240064 transitions. [2020-11-29 18:43:54,449 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 174056 [2020-11-29 18:43:54,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-11-29 18:43:54,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-11-29 18:43:54,451 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:54,451 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-11-29 18:43:54,451 INFO L794 eck$LassoCheckResult]: Stem: 812569#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 812431#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 812409#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 812396#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 812397#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 812082#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 812083#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 812375#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 812376#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 812255#L431-1 assume !(0 == ~M_E~0); 812256#L591-1 assume !(0 == ~T1_E~0); 812261#L596-1 assume !(0 == ~T2_E~0); 812262#L601-1 assume !(0 == ~T3_E~0); 812333#L606-1 assume !(0 == ~T4_E~0); 812190#L611-1 assume !(0 == ~T5_E~0); 812191#L616-1 assume !(0 == ~E_M~0); 812007#L621-1 assume !(0 == ~E_1~0); 812008#L626-1 assume !(0 == ~E_2~0); 812092#L631-1 assume !(0 == ~E_3~0); 812093#L636-1 assume !(0 == ~E_4~0); 812403#L641-1 assume !(0 == ~E_5~0); 812404#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812506#L284 assume !(1 == ~m_pc~0); 812489#L284-2 is_master_triggered_~__retres1~0 := 0; 812490#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 812429#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 812430#L735 assume !(0 != activate_threads_~tmp~1); 812667#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 812107#L303 assume !(1 == ~t1_pc~0); 812108#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 812169#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 812182#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 812204#L743 assume !(0 != activate_threads_~tmp___0~0); 812205#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 812209#L322 assume !(1 == ~t2_pc~0); 812382#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 812381#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 812043#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 812044#L751 assume !(0 != activate_threads_~tmp___1~0); 812398#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 812399#L341 assume !(1 == ~t3_pc~0); 812323#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 812324#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 812320#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 812321#L759 assume !(0 != activate_threads_~tmp___2~0); 812586#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 812587#L360 assume !(1 == ~t4_pc~0); 812696#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 812695#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 812515#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 812516#L767 assume !(0 != activate_threads_~tmp___3~0); 812589#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 812253#L379 assume !(1 == ~t5_pc~0); 812161#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 812160#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 812155#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 812020#L775 assume !(0 != activate_threads_~tmp___4~0); 812021#L775-2 assume !(1 == ~M_E~0); 812024#L659-1 assume !(1 == ~T1_E~0); 812090#L664-1 assume !(1 == ~T2_E~0); 812091#L669-1 assume !(1 == ~T3_E~0); 812401#L674-1 assume !(1 == ~T4_E~0); 812402#L679-1 assume !(1 == ~T5_E~0); 812273#L684-1 assume !(1 == ~E_M~0); 812274#L689-1 assume !(1 == ~E_1~0); 812553#L694-1 assume !(1 == ~E_2~0); 812210#L699-1 assume !(1 == ~E_3~0); 812211#L704-1 assume !(1 == ~E_4~0); 812001#L709-1 assume !(1 == ~E_5~0); 812002#L920-1 assume !false; 862925#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 862923#L566 [2020-11-29 18:43:54,451 INFO L796 eck$LassoCheckResult]: Loop: 862923#L566 assume !false; 862921#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 862877#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 862878#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 873759#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 873758#L491 assume 0 != eval_~tmp~0; 873756#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 873753#L499 assume !(0 != eval_~tmp_ndt_1~0); 873751#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 872985#L513 assume !(0 != eval_~tmp_ndt_2~0); 872024#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 848697#L527 assume !(0 != eval_~tmp_ndt_3~0); 859472#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 859466#L541 assume !(0 != eval_~tmp_ndt_4~0); 859461#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 852647#L555 assume !(0 != eval_~tmp_ndt_5~0); 859456#L552 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 862926#L569 assume !(0 != eval_~tmp_ndt_6~0); 862923#L566 [2020-11-29 18:43:54,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:54,452 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2020-11-29 18:43:54,452 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:54,452 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765255625] [2020-11-29 18:43:54,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:54,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,461 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,469 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,487 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:54,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:54,488 INFO L82 PathProgramCache]: Analyzing trace with hash 1283176533, now seen corresponding path program 1 times [2020-11-29 18:43:54,488 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:54,488 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304058836] [2020-11-29 18:43:54,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:54,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,492 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,495 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,497 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:54,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-11-29 18:43:54,498 INFO L82 PathProgramCache]: Analyzing trace with hash -828456361, now seen corresponding path program 1 times [2020-11-29 18:43:54,498 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-11-29 18:43:54,498 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428428621] [2020-11-29 18:43:54,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-11-29 18:43:54,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,508 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-11-29 18:43:54,517 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-11-29 18:43:54,542 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-11-29 18:43:54,677 WARN L193 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2020-11-29 18:43:54,888 WARN L193 SmtUtils]: Spent 210.00 ms on a formula simplification that was a NOOP. DAG size: 45 [2020-11-29 18:43:56,541 WARN L193 SmtUtils]: Spent 1.64 s on a formula simplification. DAG size of input: 251 DAG size of output: 179 [2020-11-29 18:43:56,987 WARN L193 SmtUtils]: Spent 411.00 ms on a formula simplification that was a NOOP. DAG size: 153 [2020-11-29 18:43:57,047 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 06:43:57 BoogieIcfgContainer [2020-11-29 18:43:57,047 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-11-29 18:43:57,048 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-11-29 18:43:57,048 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-11-29 18:43:57,048 INFO L275 PluginConnector]: Witness Printer initialized [2020-11-29 18:43:57,049 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 06:43:29" (3/4) ... [2020-11-29 18:43:57,051 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-11-29 18:43:57,146 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_aabf048a-5f32-4da3-972a-05cbb3951551/bin/uautomizer/witness.graphml [2020-11-29 18:43:57,146 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-11-29 18:43:57,148 INFO L168 Benchmark]: Toolchain (without parser) took 29956.28 ms. Allocated memory was 90.2 MB in the beginning and 12.1 GB in the end (delta: 12.1 GB). Free memory was 56.2 MB in the beginning and 9.9 GB in the end (delta: -9.9 GB). Peak memory consumption was 2.2 GB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,148 INFO L168 Benchmark]: CDTParser took 0.82 ms. Allocated memory is still 73.4 MB. Free memory was 47.8 MB in the beginning and 47.7 MB in the end (delta: 31.5 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-11-29 18:43:57,149 INFO L168 Benchmark]: CACSL2BoogieTranslator took 400.40 ms. Allocated memory is still 90.2 MB. Free memory was 56.0 MB in the beginning and 61.2 MB in the end (delta: -5.1 MB). Peak memory consumption was 10.1 MB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,149 INFO L168 Benchmark]: Boogie Procedure Inliner took 93.86 ms. Allocated memory is still 90.2 MB. Free memory was 61.2 MB in the beginning and 56.0 MB in the end (delta: 5.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,150 INFO L168 Benchmark]: Boogie Preprocessor took 118.90 ms. Allocated memory is still 90.2 MB. Free memory was 56.0 MB in the beginning and 51.5 MB in the end (delta: 4.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,150 INFO L168 Benchmark]: RCFGBuilder took 1757.58 ms. Allocated memory was 90.2 MB in the beginning and 109.1 MB in the end (delta: 18.9 MB). Free memory was 51.3 MB in the beginning and 51.5 MB in the end (delta: -191.5 kB). Peak memory consumption was 32.6 MB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,150 INFO L168 Benchmark]: BuchiAutomizer took 27474.52 ms. Allocated memory was 109.1 MB in the beginning and 12.1 GB in the end (delta: 12.0 GB). Free memory was 51.5 MB in the beginning and 9.9 GB in the end (delta: -9.9 GB). Peak memory consumption was 2.1 GB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,151 INFO L168 Benchmark]: Witness Printer took 98.43 ms. Allocated memory is still 12.1 GB. Free memory was 9.9 GB in the beginning and 9.9 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-11-29 18:43:57,153 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.82 ms. Allocated memory is still 73.4 MB. Free memory was 47.8 MB in the beginning and 47.7 MB in the end (delta: 31.5 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 400.40 ms. Allocated memory is still 90.2 MB. Free memory was 56.0 MB in the beginning and 61.2 MB in the end (delta: -5.1 MB). Peak memory consumption was 10.1 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 93.86 ms. Allocated memory is still 90.2 MB. Free memory was 61.2 MB in the beginning and 56.0 MB in the end (delta: 5.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 118.90 ms. Allocated memory is still 90.2 MB. Free memory was 56.0 MB in the beginning and 51.5 MB in the end (delta: 4.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1757.58 ms. Allocated memory was 90.2 MB in the beginning and 109.1 MB in the end (delta: 18.9 MB). Free memory was 51.3 MB in the beginning and 51.5 MB in the end (delta: -191.5 kB). Peak memory consumption was 32.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 27474.52 ms. Allocated memory was 109.1 MB in the beginning and 12.1 GB in the end (delta: 12.0 GB). Free memory was 51.5 MB in the beginning and 9.9 GB in the end (delta: -9.9 GB). Peak memory consumption was 2.1 GB. Max. memory is 16.1 GB. * Witness Printer took 98.43 ms. Allocated memory is still 12.1 GB. Free memory was 9.9 GB in the beginning and 9.9 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 174261 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 27.3s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 6.4s. Construction of modules took 1.4s. Büchi inclusion checks took 2.9s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 7.2s AutomataMinimizationTime, 24 MinimizatonAttempts, 34183 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 5.1s Buchi closure took 0.3s. Biggest automaton had 174261 states and ocurred in iteration 24. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 20883 SDtfs, 24567 SDslu, 19083 SDs, 0 SdLazy, 753 SolverSat, 339 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 486]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=12973} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=12973, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b0feddb=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@58bb5a6=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3faa5f71=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3043c48f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@755e0d06=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@75fc7d8d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d02c011=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55f05a75=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@775b507a=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17b78d2f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@331fdee7=0, NULL=12976, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3ba66ceb=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@780519b3=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@62a05a19=0, T1_E=2, NULL=12975, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=12974, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dc1bc7c=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 486]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L965] int __retres1 ; [L876] m_i = 1 [L877] t1_i = 1 [L878] t2_i = 1 [L879] t3_i = 1 [L880] t4_i = 1 [L881] t5_i = 1 [L906] int kernel_st ; [L907] int tmp ; [L908] int tmp___0 ; [L912] kernel_st = 0 [L406] COND TRUE m_i == 1 [L407] m_st = 0 [L411] COND TRUE t1_i == 1 [L412] t1_st = 0 [L416] COND TRUE t2_i == 1 [L417] t2_st = 0 [L421] COND TRUE t3_i == 1 [L422] t3_st = 0 [L426] COND TRUE t4_i == 1 [L427] t4_st = 0 [L431] COND TRUE t5_i == 1 [L432] t5_st = 0 [L591] COND FALSE !(M_E == 0) [L596] COND FALSE !(T1_E == 0) [L601] COND FALSE !(T2_E == 0) [L606] COND FALSE !(T3_E == 0) [L611] COND FALSE !(T4_E == 0) [L616] COND FALSE !(T5_E == 0) [L621] COND FALSE !(E_M == 0) [L626] COND FALSE !(E_1 == 0) [L631] COND FALSE !(E_2 == 0) [L636] COND FALSE !(E_3 == 0) [L641] COND FALSE !(E_4 == 0) [L646] COND FALSE !(E_5 == 0) [L724] int tmp ; [L725] int tmp___0 ; [L726] int tmp___1 ; [L727] int tmp___2 ; [L728] int tmp___3 ; [L729] int tmp___4 ; [L281] int __retres1 ; [L284] COND FALSE !(m_pc == 1) [L294] __retres1 = 0 [L296] return (__retres1); [L733] tmp = is_master_triggered() [L735] COND FALSE !(\read(tmp)) [L300] int __retres1 ; [L303] COND FALSE !(t1_pc == 1) [L313] __retres1 = 0 [L315] return (__retres1); [L741] tmp___0 = is_transmit1_triggered() [L743] COND FALSE !(\read(tmp___0)) [L319] int __retres1 ; [L322] COND FALSE !(t2_pc == 1) [L332] __retres1 = 0 [L334] return (__retres1); [L749] tmp___1 = is_transmit2_triggered() [L751] COND FALSE !(\read(tmp___1)) [L338] int __retres1 ; [L341] COND FALSE !(t3_pc == 1) [L351] __retres1 = 0 [L353] return (__retres1); [L757] tmp___2 = is_transmit3_triggered() [L759] COND FALSE !(\read(tmp___2)) [L357] int __retres1 ; [L360] COND FALSE !(t4_pc == 1) [L370] __retres1 = 0 [L372] return (__retres1); [L765] tmp___3 = is_transmit4_triggered() [L767] COND FALSE !(\read(tmp___3)) [L376] int __retres1 ; [L379] COND FALSE !(t5_pc == 1) [L389] __retres1 = 0 [L391] return (__retres1); [L773] tmp___4 = is_transmit5_triggered() [L775] COND FALSE !(\read(tmp___4)) [L659] COND FALSE !(M_E == 1) [L664] COND FALSE !(T1_E == 1) [L669] COND FALSE !(T2_E == 1) [L674] COND FALSE !(T3_E == 1) [L679] COND FALSE !(T4_E == 1) [L684] COND FALSE !(T5_E == 1) [L689] COND FALSE !(E_M == 1) [L694] COND FALSE !(E_1 == 1) [L699] COND FALSE !(E_2 == 1) [L704] COND FALSE !(E_3 == 1) [L709] COND FALSE !(E_4 == 1) [L714] COND FALSE !(E_5 == 1) [L920] COND TRUE 1 [L923] kernel_st = 1 [L482] int tmp ; Loop: [L486] COND TRUE 1 [L441] int __retres1 ; [L444] COND TRUE m_st == 0 [L445] __retres1 = 1 [L477] return (__retres1); [L489] tmp = exists_runnable_thread() [L491] COND TRUE \read(tmp) [L496] COND TRUE m_st == 0 [L497] int tmp_ndt_1; [L498] tmp_ndt_1 = __VERIFIER_nondet_int() [L499] COND FALSE !(\read(tmp_ndt_1)) [L510] COND TRUE t1_st == 0 [L511] int tmp_ndt_2; [L512] tmp_ndt_2 = __VERIFIER_nondet_int() [L513] COND FALSE !(\read(tmp_ndt_2)) [L524] COND TRUE t2_st == 0 [L525] int tmp_ndt_3; [L526] tmp_ndt_3 = __VERIFIER_nondet_int() [L527] COND FALSE !(\read(tmp_ndt_3)) [L538] COND TRUE t3_st == 0 [L539] int tmp_ndt_4; [L540] tmp_ndt_4 = __VERIFIER_nondet_int() [L541] COND FALSE !(\read(tmp_ndt_4)) [L552] COND TRUE t4_st == 0 [L553] int tmp_ndt_5; [L554] tmp_ndt_5 = __VERIFIER_nondet_int() [L555] COND FALSE !(\read(tmp_ndt_5)) [L566] COND TRUE t5_st == 0 [L567] int tmp_ndt_6; [L568] tmp_ndt_6 = __VERIFIER_nondet_int() [L569] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...