./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 7b2dab56 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c23fa9fd10aa70a52586ccd054da306bf699445a ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-7b2dab5 [2021-10-11 00:29:23,563 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-11 00:29:23,566 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-11 00:29:23,604 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-11 00:29:23,604 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-11 00:29:23,606 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-11 00:29:23,608 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-11 00:29:23,610 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-11 00:29:23,612 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-11 00:29:23,614 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-11 00:29:23,615 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-11 00:29:23,616 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-11 00:29:23,617 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-11 00:29:23,619 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-11 00:29:23,620 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-11 00:29:23,622 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-11 00:29:23,623 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-11 00:29:23,624 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-11 00:29:23,626 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-11 00:29:23,629 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-11 00:29:23,631 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-11 00:29:23,632 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-11 00:29:23,634 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-11 00:29:23,635 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-11 00:29:23,638 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-11 00:29:23,638 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-11 00:29:23,639 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-11 00:29:23,640 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-11 00:29:23,641 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-11 00:29:23,642 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-11 00:29:23,642 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-11 00:29:23,643 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-11 00:29:23,644 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-11 00:29:23,650 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-11 00:29:23,654 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-11 00:29:23,655 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-11 00:29:23,656 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-11 00:29:23,656 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-11 00:29:23,656 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-11 00:29:23,658 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-11 00:29:23,659 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-11 00:29:23,660 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-11 00:29:23,686 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-11 00:29:23,686 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-11 00:29:23,688 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-11 00:29:23,688 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-11 00:29:23,688 INFO L138 SettingsManager]: * Use SBE=true [2021-10-11 00:29:23,689 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-11 00:29:23,689 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-11 00:29:23,689 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-11 00:29:23,689 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-11 00:29:23,689 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-11 00:29:23,690 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-11 00:29:23,690 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-11 00:29:23,690 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-11 00:29:23,690 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-11 00:29:23,691 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-11 00:29:23,691 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-11 00:29:23,691 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-11 00:29:23,691 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-11 00:29:23,691 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-11 00:29:23,692 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-11 00:29:23,692 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-11 00:29:23,692 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-11 00:29:23,692 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-11 00:29:23,692 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-11 00:29:23,693 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-11 00:29:23,693 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-11 00:29:23,693 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-11 00:29:23,693 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-11 00:29:23,694 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-11 00:29:23,694 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-11 00:29:23,695 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-11 00:29:23,695 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c23fa9fd10aa70a52586ccd054da306bf699445a [2021-10-11 00:29:23,968 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-11 00:29:23,988 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-11 00:29:23,991 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-11 00:29:23,992 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-11 00:29:23,993 INFO L275 PluginConnector]: CDTParser initialized [2021-10-11 00:29:23,994 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-10-11 00:29:24,058 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/data/f4a5f1f7c/aa47aaa205364bb59c526d274750174c/FLAGca4e9bad1 [2021-10-11 00:29:24,514 INFO L306 CDTParser]: Found 1 translation units. [2021-10-11 00:29:24,515 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-10-11 00:29:24,545 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/data/f4a5f1f7c/aa47aaa205364bb59c526d274750174c/FLAGca4e9bad1 [2021-10-11 00:29:24,887 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/data/f4a5f1f7c/aa47aaa205364bb59c526d274750174c [2021-10-11 00:29:24,892 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-11 00:29:24,895 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-11 00:29:24,898 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-11 00:29:24,899 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-11 00:29:24,902 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-11 00:29:24,904 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.10 12:29:24" (1/1) ... [2021-10-11 00:29:24,905 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77db9a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:24, skipping insertion in model container [2021-10-11 00:29:24,906 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.10 12:29:24" (1/1) ... [2021-10-11 00:29:24,912 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-11 00:29:24,972 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-11 00:29:25,202 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-10-11 00:29:25,307 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-11 00:29:25,324 INFO L203 MainTranslator]: Completed pre-run [2021-10-11 00:29:25,334 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-10-11 00:29:25,387 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-11 00:29:25,411 INFO L208 MainTranslator]: Completed translation [2021-10-11 00:29:25,412 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25 WrapperNode [2021-10-11 00:29:25,412 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-11 00:29:25,413 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-11 00:29:25,413 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-11 00:29:25,414 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-11 00:29:25,421 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,433 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,501 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-11 00:29:25,502 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-11 00:29:25,502 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-11 00:29:25,502 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-11 00:29:25,511 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,511 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,519 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,520 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,543 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,563 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,568 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... [2021-10-11 00:29:25,577 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-11 00:29:25,578 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-11 00:29:25,578 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-11 00:29:25,578 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-11 00:29:25,579 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (1/1) ... No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-11 00:29:25,672 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-11 00:29:25,673 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-11 00:29:25,673 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-11 00:29:25,674 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-11 00:29:26,932 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-11 00:29:26,933 INFO L299 CfgBuilder]: Removed 196 assume(true) statements. [2021-10-11 00:29:26,937 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.10 12:29:26 BoogieIcfgContainer [2021-10-11 00:29:26,937 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-11 00:29:26,938 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-11 00:29:26,938 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-11 00:29:26,941 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-11 00:29:26,942 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-11 00:29:26,942 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 11.10 12:29:24" (1/3) ... [2021-10-11 00:29:26,944 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38c5bcdc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 11.10 12:29:26, skipping insertion in model container [2021-10-11 00:29:26,944 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-11 00:29:26,944 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.10 12:29:25" (2/3) ... [2021-10-11 00:29:26,944 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38c5bcdc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 11.10 12:29:26, skipping insertion in model container [2021-10-11 00:29:26,944 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-11 00:29:26,945 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.10 12:29:26" (3/3) ... [2021-10-11 00:29:26,946 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2021-10-11 00:29:27,004 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-11 00:29:27,004 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-11 00:29:27,004 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-11 00:29:27,004 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-11 00:29:27,004 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-11 00:29:27,005 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-11 00:29:27,005 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-11 00:29:27,005 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-11 00:29:27,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2021-10-11 00:29:27,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-10-11 00:29:27,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:27,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:27,121 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,121 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,121 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-11 00:29:27,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2021-10-11 00:29:27,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-10-11 00:29:27,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:27,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:27,136 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,136 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,144 INFO L794 eck$LassoCheckResult]: Stem: 366#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 260#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 248#L883true havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 240#L399true assume !(1 == ~m_i~0);~m_st~0 := 2; 274#L406-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 46#L411-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 462#L416-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 219#L421-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 502#L426-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 154#L431-1true assume !(0 == ~M_E~0); 522#L591-1true assume !(0 == ~T1_E~0); 157#L596-1true assume !(0 == ~T2_E~0); 420#L601-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 191#L606-1true assume !(0 == ~T4_E~0); 101#L611-1true assume !(0 == ~T5_E~0); 387#L616-1true assume !(0 == ~E_M~0); 7#L621-1true assume !(0 == ~E_1~0); 277#L626-1true assume !(0 == ~E_2~0); 51#L631-1true assume !(0 == ~E_3~0); 470#L636-1true assume !(0 == ~E_4~0); 244#L641-1true assume 0 == ~E_5~0;~E_5~0 := 1; 533#L646-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 308#L284true assume 1 == ~m_pc~0; 258#L285true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 309#L295true is_master_triggered_#res := is_master_triggered_~__retres1~0; 259#L296true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 481#L735true assume !(0 != activate_threads_~tmp~1); 465#L735-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60#L303true assume !(1 == ~t1_pc~0); 89#L303-2true is_transmit1_triggered_~__retres1~1 := 0; 95#L314true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 413#L315true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 109#L743true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 112#L743-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224#L322true assume 1 == ~t2_pc~0; 27#L323true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 223#L333true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26#L334true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 250#L751true assume !(0 != activate_threads_~tmp___1~0); 241#L751-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 382#L341true assume !(1 == ~t3_pc~0); 367#L341-2true is_transmit3_triggered_~__retres1~3 := 0; 381#L352true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184#L353true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 392#L759true assume !(0 != activate_threads_~tmp___2~0); 393#L759-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 507#L360true assume 1 == ~t4_pc~0; 317#L361true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 505#L371true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 314#L372true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 398#L767true assume !(0 != activate_threads_~tmp___3~0); 530#L767-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 151#L379true assume !(1 == ~t5_pc~0); 132#L379-2true is_transmit5_triggered_~__retres1~5 := 0; 149#L390true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83#L391true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13#L775true assume !(0 != activate_threads_~tmp___4~0); 15#L775-2true assume !(1 == ~M_E~0); 275#L659-1true assume !(1 == ~T1_E~0); 50#L664-1true assume !(1 == ~T2_E~0); 466#L669-1true assume !(1 == ~T3_E~0); 243#L674-1true assume !(1 == ~T4_E~0); 532#L679-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 163#L684-1true assume !(1 == ~E_M~0); 432#L689-1true assume !(1 == ~E_1~0); 345#L694-1true assume !(1 == ~E_2~0); 113#L699-1true assume !(1 == ~E_3~0); 394#L704-1true assume !(1 == ~E_4~0); 3#L709-1true assume !(1 == ~E_5~0); 437#L920-1true [2021-10-11 00:29:27,146 INFO L796 eck$LassoCheckResult]: Loop: 437#L920-1true assume !false; 396#L921true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9#L566true assume !true; 473#L581true start_simulation_~kernel_st~0 := 2; 221#L399-1true start_simulation_~kernel_st~0 := 3; 524#L591-2true assume 0 == ~M_E~0;~M_E~0 := 1; 527#L591-4true assume !(0 == ~T1_E~0); 160#L596-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 425#L601-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L606-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 105#L611-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 389#L616-3true assume 0 == ~E_M~0;~E_M~0 := 1; 11#L621-3true assume 0 == ~E_1~0;~E_1~0 := 1; 282#L626-3true assume 0 == ~E_2~0;~E_2~0 := 1; 36#L631-3true assume !(0 == ~E_3~0); 454#L636-3true assume 0 == ~E_4~0;~E_4~0 := 1; 233#L641-3true assume 0 == ~E_5~0;~E_5~0 := 1; 523#L646-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 272#L284-21true assume 1 == ~m_pc~0; 263#L285-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 319#L295-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 264#L296-7true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 313#L735-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 291#L735-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 433#L303-21true assume 1 == ~t1_pc~0; 400#L304-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 446#L314-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 399#L315-7true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 448#L743-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 452#L743-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49#L322-21true assume !(1 == ~t2_pc~0); 52#L322-23true is_transmit2_triggered_~__retres1~2 := 0; 214#L333-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22#L334-7true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 218#L751-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 197#L751-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 344#L341-21true assume 1 == ~t3_pc~0; 180#L342-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 354#L352-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 179#L353-7true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 359#L759-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 361#L759-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 464#L360-21true assume 1 == ~t4_pc~0; 307#L361-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 494#L371-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 306#L372-7true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 498#L767-21true assume !(0 != activate_threads_~tmp___3~0); 482#L767-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 111#L379-21true assume !(1 == ~t5_pc~0); 98#L379-23true is_transmit5_triggered_~__retres1~5 := 0; 144#L390-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76#L391-7true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 126#L775-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 128#L775-23true assume 1 == ~M_E~0;~M_E~0 := 2; 279#L659-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 53#L664-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 475#L669-3true assume !(1 == ~T3_E~0); 246#L674-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 519#L679-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 156#L684-3true assume 1 == ~E_M~0;~E_M~0 := 2; 419#L689-3true assume 1 == ~E_1~0;~E_1~0 := 2; 190#L694-3true assume 1 == ~E_2~0;~E_2~0 := 2; 100#L699-3true assume 1 == ~E_3~0;~E_3~0 := 2; 385#L704-3true assume 1 == ~E_4~0;~E_4~0 := 2; 6#L709-3true assume !(1 == ~E_5~0); 276#L714-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44#L444-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 238#L476-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43#L477-1true start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 201#L939true assume !(0 == start_simulation_~tmp~3); 205#L939-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47#L444-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 239#L476-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45#L477-2true stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 247#L894true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 295#L901true stop_simulation_#res := stop_simulation_~__retres2~0; 395#L902true start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 114#L952true assume !(0 != start_simulation_~tmp___0~1); 437#L920-1true [2021-10-11 00:29:27,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:27,152 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-10-11 00:29:27,161 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:27,161 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933534458] [2021-10-11 00:29:27,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:27,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:27,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:27,397 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933534458] [2021-10-11 00:29:27,398 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:27,398 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:27,399 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017796584] [2021-10-11 00:29:27,403 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:27,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:27,405 INFO L82 PathProgramCache]: Analyzing trace with hash -2114634143, now seen corresponding path program 1 times [2021-10-11 00:29:27,406 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:27,406 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019212393] [2021-10-11 00:29:27,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:27,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:27,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:27,476 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019212393] [2021-10-11 00:29:27,476 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:27,476 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-11 00:29:27,476 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428313396] [2021-10-11 00:29:27,480 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:27,481 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:27,495 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:27,495 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:27,497 INFO L87 Difference]: Start difference. First operand 532 states. Second operand 3 states. [2021-10-11 00:29:27,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:27,571 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-10-11 00:29:27,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:27,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-10-11 00:29:27,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:27,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2021-10-11 00:29:27,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-10-11 00:29:27,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-10-11 00:29:27,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2021-10-11 00:29:27,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:27,616 INFO L692 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-10-11 00:29:27,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2021-10-11 00:29:27,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-10-11 00:29:27,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2021-10-11 00:29:27,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2021-10-11 00:29:27,696 INFO L715 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-10-11 00:29:27,696 INFO L595 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-10-11 00:29:27,696 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-11 00:29:27,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2021-10-11 00:29:27,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:27,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:27,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:27,711 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,711 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,712 INFO L794 eck$LassoCheckResult]: Stem: 1547#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1442#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1417#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1404#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1405#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1164#L411-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1165#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1392#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1393#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1307#L431-1 assume !(0 == ~M_E~0); 1308#L591-1 assume !(0 == ~T1_E~0); 1312#L596-1 assume !(0 == ~T2_E~0); 1313#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1379#L606-1 assume !(0 == ~T4_E~0); 1262#L611-1 assume !(0 == ~T5_E~0); 1263#L616-1 assume !(0 == ~E_M~0); 1080#L621-1 assume !(0 == ~E_1~0); 1081#L626-1 assume !(0 == ~E_2~0); 1172#L631-1 assume !(0 == ~E_3~0); 1173#L636-1 assume !(0 == ~E_4~0); 1411#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1412#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1493#L284 assume 1 == ~m_pc~0; 1437#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1438#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1440#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1441#L735 assume !(0 != activate_threads_~tmp~1); 1589#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1181#L303 assume !(1 == ~t1_pc~0); 1182#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1242#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1251#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1274#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1275#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1277#L322 assume 1 == ~t2_pc~0; 1121#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1122#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1119#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1120#L751 assume !(0 != activate_threads_~tmp___1~0); 1406#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1407#L341 assume !(1 == ~t3_pc~0); 1368#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1369#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1365#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1366#L759 assume !(0 != activate_threads_~tmp___2~0); 1556#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1557#L360 assume 1 == ~t4_pc~0; 1504#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1505#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1500#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1501#L767 assume !(0 != activate_threads_~tmp___3~0); 1559#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1306#L379 assume !(1 == ~t5_pc~0); 1235#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1234#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1230#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1094#L775 assume !(0 != activate_threads_~tmp___4~0); 1095#L775-2 assume !(1 == ~M_E~0); 1096#L659-1 assume !(1 == ~T1_E~0); 1170#L664-1 assume !(1 == ~T2_E~0); 1171#L669-1 assume !(1 == ~T3_E~0); 1409#L674-1 assume !(1 == ~T4_E~0); 1410#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1322#L684-1 assume !(1 == ~E_M~0); 1323#L689-1 assume !(1 == ~E_1~0); 1536#L694-1 assume !(1 == ~E_2~0); 1278#L699-1 assume !(1 == ~E_3~0); 1279#L704-1 assume !(1 == ~E_4~0); 1073#L709-1 assume !(1 == ~E_5~0); 1074#L920-1 [2021-10-11 00:29:27,713 INFO L796 eck$LassoCheckResult]: Loop: 1074#L920-1 assume !false; 1558#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1084#L566 assume !false; 1085#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1154#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1155#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1152#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1153#L491 assume !(0 != eval_~tmp~0); 1583#L581 start_simulation_~kernel_st~0 := 2; 1396#L399-1 start_simulation_~kernel_st~0 := 3; 1397#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1598#L591-4 assume !(0 == ~T1_E~0); 1318#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1319#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1380#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1268#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1269#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1089#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1090#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1144#L631-3 assume !(0 == ~E_3~0); 1145#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1401#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1402#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1468#L284-21 assume 1 == ~m_pc~0; 1448#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1449#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1451#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1452#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1471#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1472#L303-21 assume 1 == ~t1_pc~0; 1562#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1563#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1560#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1561#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1587#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1169#L322-21 assume 1 == ~t2_pc~0; 1111#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1112#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1109#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1110#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1382#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1383#L341-21 assume !(1 == ~t3_pc~0); 1361#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 1360#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1357#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1358#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1543#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1544#L360-21 assume 1 == ~t4_pc~0; 1490#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1491#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1488#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1489#L767-21 assume !(0 != activate_threads_~tmp___3~0); 1591#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1276#L379-21 assume 1 == ~t5_pc~0; 1222#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1223#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1216#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1217#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1290#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1291#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1174#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1175#L669-3 assume !(1 == ~T3_E~0); 1414#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1415#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1310#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1311#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1377#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1260#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1261#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1078#L709-3 assume !(1 == ~E_5~0); 1079#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1159#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1160#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1157#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1158#L939 assume !(0 == start_simulation_~tmp~3); 1385#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1166#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1167#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1162#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1163#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1416#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 1475#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1280#L952 assume !(0 != start_simulation_~tmp___0~1); 1074#L920-1 [2021-10-11 00:29:27,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:27,714 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-10-11 00:29:27,715 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:27,715 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217675669] [2021-10-11 00:29:27,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:27,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:27,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:27,803 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217675669] [2021-10-11 00:29:27,804 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:27,804 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:27,804 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281599897] [2021-10-11 00:29:27,804 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:27,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:27,805 INFO L82 PathProgramCache]: Analyzing trace with hash -2014669991, now seen corresponding path program 1 times [2021-10-11 00:29:27,805 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:27,806 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933575852] [2021-10-11 00:29:27,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:27,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:27,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:27,921 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933575852] [2021-10-11 00:29:27,921 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:27,921 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:27,922 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478719388] [2021-10-11 00:29:27,922 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:27,922 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:27,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:27,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:27,923 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand 3 states. [2021-10-11 00:29:27,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:27,938 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2021-10-11 00:29:27,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:27,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2021-10-11 00:29:27,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:27,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2021-10-11 00:29:27,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-10-11 00:29:27,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-10-11 00:29:27,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2021-10-11 00:29:27,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:27,952 INFO L692 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-10-11 00:29:27,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2021-10-11 00:29:27,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-10-11 00:29:27,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2021-10-11 00:29:27,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2021-10-11 00:29:27,966 INFO L715 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-10-11 00:29:27,967 INFO L595 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-10-11 00:29:27,967 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-11 00:29:27,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2021-10-11 00:29:27,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:27,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:27,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:27,973 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,973 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:27,973 INFO L794 eck$LassoCheckResult]: Stem: 2608#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2503#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2478#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2465#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 2466#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2228#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2229#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2453#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2454#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2369#L431-1 assume !(0 == ~M_E~0); 2370#L591-1 assume !(0 == ~T1_E~0); 2373#L596-1 assume !(0 == ~T2_E~0); 2374#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2440#L606-1 assume !(0 == ~T4_E~0); 2323#L611-1 assume !(0 == ~T5_E~0); 2324#L616-1 assume !(0 == ~E_M~0); 2141#L621-1 assume !(0 == ~E_1~0); 2142#L626-1 assume !(0 == ~E_2~0); 2233#L631-1 assume !(0 == ~E_3~0); 2234#L636-1 assume !(0 == ~E_4~0); 2472#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2473#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2554#L284 assume 1 == ~m_pc~0; 2498#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2499#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2501#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2502#L735 assume !(0 != activate_threads_~tmp~1); 2650#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2242#L303 assume !(1 == ~t1_pc~0); 2243#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 2303#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2312#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2335#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2336#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2338#L322 assume 1 == ~t2_pc~0; 2182#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2183#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2180#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2181#L751 assume !(0 != activate_threads_~tmp___1~0); 2467#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2468#L341 assume !(1 == ~t3_pc~0); 2429#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 2430#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2426#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2427#L759 assume !(0 != activate_threads_~tmp___2~0); 2617#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2618#L360 assume 1 == ~t4_pc~0; 2565#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2566#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2561#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2562#L767 assume !(0 != activate_threads_~tmp___3~0); 2620#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2367#L379 assume !(1 == ~t5_pc~0); 2296#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 2295#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2291#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2155#L775 assume !(0 != activate_threads_~tmp___4~0); 2156#L775-2 assume !(1 == ~M_E~0); 2157#L659-1 assume !(1 == ~T1_E~0); 2231#L664-1 assume !(1 == ~T2_E~0); 2232#L669-1 assume !(1 == ~T3_E~0); 2470#L674-1 assume !(1 == ~T4_E~0); 2471#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2383#L684-1 assume !(1 == ~E_M~0); 2384#L689-1 assume !(1 == ~E_1~0); 2597#L694-1 assume !(1 == ~E_2~0); 2339#L699-1 assume !(1 == ~E_3~0); 2340#L704-1 assume !(1 == ~E_4~0); 2134#L709-1 assume !(1 == ~E_5~0); 2135#L920-1 [2021-10-11 00:29:27,974 INFO L796 eck$LassoCheckResult]: Loop: 2135#L920-1 assume !false; 2619#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2145#L566 assume !false; 2146#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2217#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2218#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2213#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2214#L491 assume !(0 != eval_~tmp~0); 2644#L581 start_simulation_~kernel_st~0 := 2; 2457#L399-1 start_simulation_~kernel_st~0 := 3; 2458#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2659#L591-4 assume !(0 == ~T1_E~0); 2379#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2380#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2441#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2329#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2330#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2150#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2151#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2205#L631-3 assume !(0 == ~E_3~0); 2206#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2462#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2463#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2529#L284-21 assume 1 == ~m_pc~0; 2509#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2510#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2512#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2513#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2532#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2533#L303-21 assume !(1 == ~t1_pc~0); 2625#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 2624#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2621#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2622#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2648#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2230#L322-21 assume 1 == ~t2_pc~0; 2172#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2173#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2170#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2171#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2443#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2444#L341-21 assume 1 == ~t3_pc~0; 2420#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2421#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2418#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2419#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2604#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2605#L360-21 assume 1 == ~t4_pc~0; 2551#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2552#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2549#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2550#L767-21 assume !(0 != activate_threads_~tmp___3~0); 2652#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2337#L379-21 assume 1 == ~t5_pc~0; 2283#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2284#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2277#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2278#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2351#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2352#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2235#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2236#L669-3 assume !(1 == ~T3_E~0); 2475#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2476#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2371#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2372#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2438#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2321#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2322#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2138#L709-3 assume !(1 == ~E_5~0); 2139#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2220#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2221#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2215#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2216#L939 assume !(0 == start_simulation_~tmp~3); 2446#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2225#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2226#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2223#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2224#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2477#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 2536#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2341#L952 assume !(0 != start_simulation_~tmp___0~1); 2135#L920-1 [2021-10-11 00:29:27,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:27,974 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-10-11 00:29:27,975 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:27,975 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59784446] [2021-10-11 00:29:27,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:27,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,025 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59784446] [2021-10-11 00:29:28,026 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,028 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,028 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489911674] [2021-10-11 00:29:28,029 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:28,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,029 INFO L82 PathProgramCache]: Analyzing trace with hash 243645657, now seen corresponding path program 1 times [2021-10-11 00:29:28,029 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,031 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62734105] [2021-10-11 00:29:28,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,111 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62734105] [2021-10-11 00:29:28,111 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,111 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,111 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777097099] [2021-10-11 00:29:28,112 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:28,112 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:28,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:28,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:28,113 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand 3 states. [2021-10-11 00:29:28,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:28,126 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2021-10-11 00:29:28,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:28,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2021-10-11 00:29:28,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2021-10-11 00:29:28,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-10-11 00:29:28,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-10-11 00:29:28,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2021-10-11 00:29:28,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:28,139 INFO L692 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-10-11 00:29:28,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2021-10-11 00:29:28,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-10-11 00:29:28,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2021-10-11 00:29:28,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2021-10-11 00:29:28,151 INFO L715 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-10-11 00:29:28,151 INFO L595 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-10-11 00:29:28,151 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-11 00:29:28,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2021-10-11 00:29:28,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:28,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:28,157 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,157 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,158 INFO L794 eck$LassoCheckResult]: Stem: 3669#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3564#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3539#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3526#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 3527#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3289#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3290#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3514#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3515#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3430#L431-1 assume !(0 == ~M_E~0); 3431#L591-1 assume !(0 == ~T1_E~0); 3434#L596-1 assume !(0 == ~T2_E~0); 3435#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3501#L606-1 assume !(0 == ~T4_E~0); 3384#L611-1 assume !(0 == ~T5_E~0); 3385#L616-1 assume !(0 == ~E_M~0); 3202#L621-1 assume !(0 == ~E_1~0); 3203#L626-1 assume !(0 == ~E_2~0); 3294#L631-1 assume !(0 == ~E_3~0); 3295#L636-1 assume !(0 == ~E_4~0); 3533#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3534#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3615#L284 assume 1 == ~m_pc~0; 3559#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3560#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3562#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3563#L735 assume !(0 != activate_threads_~tmp~1); 3711#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3305#L303 assume !(1 == ~t1_pc~0); 3306#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 3364#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3373#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3396#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3397#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3399#L322 assume 1 == ~t2_pc~0; 3243#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3244#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3241#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3242#L751 assume !(0 != activate_threads_~tmp___1~0); 3528#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3529#L341 assume !(1 == ~t3_pc~0); 3490#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 3491#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3487#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3488#L759 assume !(0 != activate_threads_~tmp___2~0); 3678#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3679#L360 assume 1 == ~t4_pc~0; 3626#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3627#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3622#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3623#L767 assume !(0 != activate_threads_~tmp___3~0); 3681#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3428#L379 assume !(1 == ~t5_pc~0); 3357#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 3356#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3352#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3216#L775 assume !(0 != activate_threads_~tmp___4~0); 3217#L775-2 assume !(1 == ~M_E~0); 3218#L659-1 assume !(1 == ~T1_E~0); 3292#L664-1 assume !(1 == ~T2_E~0); 3293#L669-1 assume !(1 == ~T3_E~0); 3531#L674-1 assume !(1 == ~T4_E~0); 3532#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3444#L684-1 assume !(1 == ~E_M~0); 3445#L689-1 assume !(1 == ~E_1~0); 3658#L694-1 assume !(1 == ~E_2~0); 3400#L699-1 assume !(1 == ~E_3~0); 3401#L704-1 assume !(1 == ~E_4~0); 3195#L709-1 assume !(1 == ~E_5~0); 3196#L920-1 [2021-10-11 00:29:28,158 INFO L796 eck$LassoCheckResult]: Loop: 3196#L920-1 assume !false; 3680#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3206#L566 assume !false; 3207#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3278#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3279#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3274#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3275#L491 assume !(0 != eval_~tmp~0); 3705#L581 start_simulation_~kernel_st~0 := 2; 3518#L399-1 start_simulation_~kernel_st~0 := 3; 3519#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3720#L591-4 assume !(0 == ~T1_E~0); 3440#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3441#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3502#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3390#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3391#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3211#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3212#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3266#L631-3 assume !(0 == ~E_3~0); 3267#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3523#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3524#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3590#L284-21 assume 1 == ~m_pc~0; 3570#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3571#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3573#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3574#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3593#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3594#L303-21 assume 1 == ~t1_pc~0; 3684#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3685#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3682#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3683#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3709#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3291#L322-21 assume 1 == ~t2_pc~0; 3233#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3234#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3231#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3232#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3504#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3505#L341-21 assume 1 == ~t3_pc~0; 3481#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3482#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3479#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3480#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3665#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3666#L360-21 assume 1 == ~t4_pc~0; 3612#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3613#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3609#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3610#L767-21 assume !(0 != activate_threads_~tmp___3~0); 3713#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3398#L379-21 assume 1 == ~t5_pc~0; 3340#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3341#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3338#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3339#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3411#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3413#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3296#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3297#L669-3 assume !(1 == ~T3_E~0); 3536#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3537#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3432#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3433#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3499#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3382#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3383#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3199#L709-3 assume !(1 == ~E_5~0); 3200#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3281#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3282#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3276#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3277#L939 assume !(0 == start_simulation_~tmp~3); 3507#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3286#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3287#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3284#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 3285#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3538#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 3597#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3402#L952 assume !(0 != start_simulation_~tmp___0~1); 3196#L920-1 [2021-10-11 00:29:28,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,159 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-10-11 00:29:28,159 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,159 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314299929] [2021-10-11 00:29:28,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,194 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314299929] [2021-10-11 00:29:28,194 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,194 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,195 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372972658] [2021-10-11 00:29:28,195 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:28,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,196 INFO L82 PathProgramCache]: Analyzing trace with hash 140844410, now seen corresponding path program 1 times [2021-10-11 00:29:28,196 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,196 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343591689] [2021-10-11 00:29:28,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,295 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343591689] [2021-10-11 00:29:28,295 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,295 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,296 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827260977] [2021-10-11 00:29:28,296 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:28,296 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:28,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:28,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:28,298 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand 3 states. [2021-10-11 00:29:28,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:28,311 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2021-10-11 00:29:28,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:28,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2021-10-11 00:29:28,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2021-10-11 00:29:28,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-10-11 00:29:28,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-10-11 00:29:28,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2021-10-11 00:29:28,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:28,324 INFO L692 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-10-11 00:29:28,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2021-10-11 00:29:28,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-10-11 00:29:28,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2021-10-11 00:29:28,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2021-10-11 00:29:28,337 INFO L715 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-10-11 00:29:28,340 INFO L595 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-10-11 00:29:28,340 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-11 00:29:28,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2021-10-11 00:29:28,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:28,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:28,349 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,349 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,350 INFO L794 eck$LassoCheckResult]: Stem: 4730#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4625#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4600#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4587#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 4588#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4350#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4351#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4575#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4576#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4491#L431-1 assume !(0 == ~M_E~0); 4492#L591-1 assume !(0 == ~T1_E~0); 4495#L596-1 assume !(0 == ~T2_E~0); 4496#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4562#L606-1 assume !(0 == ~T4_E~0); 4445#L611-1 assume !(0 == ~T5_E~0); 4446#L616-1 assume !(0 == ~E_M~0); 4263#L621-1 assume !(0 == ~E_1~0); 4264#L626-1 assume !(0 == ~E_2~0); 4355#L631-1 assume !(0 == ~E_3~0); 4356#L636-1 assume !(0 == ~E_4~0); 4594#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4595#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4676#L284 assume 1 == ~m_pc~0; 4620#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4621#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4623#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4624#L735 assume !(0 != activate_threads_~tmp~1); 4772#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4366#L303 assume !(1 == ~t1_pc~0); 4367#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 4426#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4437#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4457#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4458#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4460#L322 assume 1 == ~t2_pc~0; 4304#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4305#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4302#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4303#L751 assume !(0 != activate_threads_~tmp___1~0); 4589#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4590#L341 assume !(1 == ~t3_pc~0); 4551#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 4552#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4548#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4549#L759 assume !(0 != activate_threads_~tmp___2~0); 4739#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4740#L360 assume 1 == ~t4_pc~0; 4687#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4688#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4683#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4684#L767 assume !(0 != activate_threads_~tmp___3~0); 4742#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4489#L379 assume !(1 == ~t5_pc~0); 4418#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 4417#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4413#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4277#L775 assume !(0 != activate_threads_~tmp___4~0); 4278#L775-2 assume !(1 == ~M_E~0); 4279#L659-1 assume !(1 == ~T1_E~0); 4353#L664-1 assume !(1 == ~T2_E~0); 4354#L669-1 assume !(1 == ~T3_E~0); 4592#L674-1 assume !(1 == ~T4_E~0); 4593#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4505#L684-1 assume !(1 == ~E_M~0); 4506#L689-1 assume !(1 == ~E_1~0); 4719#L694-1 assume !(1 == ~E_2~0); 4461#L699-1 assume !(1 == ~E_3~0); 4462#L704-1 assume !(1 == ~E_4~0); 4258#L709-1 assume !(1 == ~E_5~0); 4259#L920-1 [2021-10-11 00:29:28,350 INFO L796 eck$LassoCheckResult]: Loop: 4259#L920-1 assume !false; 4741#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4267#L566 assume !false; 4268#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4339#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4340#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4335#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4336#L491 assume !(0 != eval_~tmp~0); 4766#L581 start_simulation_~kernel_st~0 := 2; 4579#L399-1 start_simulation_~kernel_st~0 := 3; 4580#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4781#L591-4 assume !(0 == ~T1_E~0); 4501#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4502#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4451#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4452#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4272#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4273#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4327#L631-3 assume !(0 == ~E_3~0); 4328#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4584#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4585#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4651#L284-21 assume 1 == ~m_pc~0; 4631#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4632#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4634#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4635#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4654#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4655#L303-21 assume 1 == ~t1_pc~0; 4745#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4746#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4743#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4744#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4770#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4352#L322-21 assume 1 == ~t2_pc~0; 4294#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4295#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4292#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4293#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4565#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4566#L341-21 assume !(1 == ~t3_pc~0); 4544#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 4543#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4540#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4541#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4726#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4727#L360-21 assume 1 == ~t4_pc~0; 4673#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4674#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4670#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4671#L767-21 assume !(0 != activate_threads_~tmp___3~0); 4774#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4459#L379-21 assume 1 == ~t5_pc~0; 4401#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4402#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4399#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4400#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4473#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4474#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4358#L669-3 assume !(1 == ~T3_E~0); 4597#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4598#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4493#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4494#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4560#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4443#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4444#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4261#L709-3 assume !(1 == ~E_5~0); 4262#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4342#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4343#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4337#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4338#L939 assume !(0 == start_simulation_~tmp~3); 4568#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4347#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4348#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4345#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4346#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4599#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 4658#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4463#L952 assume !(0 != start_simulation_~tmp___0~1); 4259#L920-1 [2021-10-11 00:29:28,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,351 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-10-11 00:29:28,358 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,359 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847799921] [2021-10-11 00:29:28,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,419 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847799921] [2021-10-11 00:29:28,419 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,419 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,419 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733846226] [2021-10-11 00:29:28,420 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:28,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,420 INFO L82 PathProgramCache]: Analyzing trace with hash -2014669991, now seen corresponding path program 2 times [2021-10-11 00:29:28,420 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,421 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319774480] [2021-10-11 00:29:28,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,459 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319774480] [2021-10-11 00:29:28,459 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,460 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,460 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257153343] [2021-10-11 00:29:28,460 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:28,460 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:28,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:28,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:28,461 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand 3 states. [2021-10-11 00:29:28,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:28,473 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2021-10-11 00:29:28,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:28,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2021-10-11 00:29:28,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2021-10-11 00:29:28,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-10-11 00:29:28,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-10-11 00:29:28,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2021-10-11 00:29:28,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:28,485 INFO L692 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-10-11 00:29:28,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2021-10-11 00:29:28,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-10-11 00:29:28,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2021-10-11 00:29:28,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2021-10-11 00:29:28,497 INFO L715 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-10-11 00:29:28,497 INFO L595 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-10-11 00:29:28,497 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-11 00:29:28,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2021-10-11 00:29:28,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-10-11 00:29:28,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:28,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:28,502 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,503 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,503 INFO L794 eck$LassoCheckResult]: Stem: 5791#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5686#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5661#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5648#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 5649#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5411#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5412#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5636#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5637#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5552#L431-1 assume !(0 == ~M_E~0); 5553#L591-1 assume !(0 == ~T1_E~0); 5556#L596-1 assume !(0 == ~T2_E~0); 5557#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5623#L606-1 assume !(0 == ~T4_E~0); 5506#L611-1 assume !(0 == ~T5_E~0); 5507#L616-1 assume !(0 == ~E_M~0); 5324#L621-1 assume !(0 == ~E_1~0); 5325#L626-1 assume !(0 == ~E_2~0); 5416#L631-1 assume !(0 == ~E_3~0); 5417#L636-1 assume !(0 == ~E_4~0); 5655#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5656#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5737#L284 assume 1 == ~m_pc~0; 5681#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5682#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5684#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5685#L735 assume !(0 != activate_threads_~tmp~1); 5833#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5427#L303 assume !(1 == ~t1_pc~0); 5428#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 5487#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5498#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5518#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5519#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5521#L322 assume 1 == ~t2_pc~0; 5365#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5366#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5363#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5364#L751 assume !(0 != activate_threads_~tmp___1~0); 5650#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5651#L341 assume !(1 == ~t3_pc~0); 5612#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 5613#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5609#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5610#L759 assume !(0 != activate_threads_~tmp___2~0); 5800#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5801#L360 assume 1 == ~t4_pc~0; 5748#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5749#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5744#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5745#L767 assume !(0 != activate_threads_~tmp___3~0); 5803#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5550#L379 assume !(1 == ~t5_pc~0); 5479#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 5478#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5474#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5338#L775 assume !(0 != activate_threads_~tmp___4~0); 5339#L775-2 assume !(1 == ~M_E~0); 5340#L659-1 assume !(1 == ~T1_E~0); 5414#L664-1 assume !(1 == ~T2_E~0); 5415#L669-1 assume !(1 == ~T3_E~0); 5653#L674-1 assume !(1 == ~T4_E~0); 5654#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5566#L684-1 assume !(1 == ~E_M~0); 5567#L689-1 assume !(1 == ~E_1~0); 5780#L694-1 assume !(1 == ~E_2~0); 5522#L699-1 assume !(1 == ~E_3~0); 5523#L704-1 assume !(1 == ~E_4~0); 5319#L709-1 assume !(1 == ~E_5~0); 5320#L920-1 [2021-10-11 00:29:28,503 INFO L796 eck$LassoCheckResult]: Loop: 5320#L920-1 assume !false; 5802#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5328#L566 assume !false; 5329#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5400#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5401#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5396#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5397#L491 assume !(0 != eval_~tmp~0); 5827#L581 start_simulation_~kernel_st~0 := 2; 5640#L399-1 start_simulation_~kernel_st~0 := 3; 5641#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5842#L591-4 assume !(0 == ~T1_E~0); 5562#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5563#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5624#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5512#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5513#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5333#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5334#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5388#L631-3 assume !(0 == ~E_3~0); 5389#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5645#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5646#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5712#L284-21 assume 1 == ~m_pc~0; 5692#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5693#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5695#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5696#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5715#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5716#L303-21 assume !(1 == ~t1_pc~0); 5808#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 5807#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5804#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5805#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5831#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5413#L322-21 assume 1 == ~t2_pc~0; 5355#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5356#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5353#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5354#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5626#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5627#L341-21 assume 1 == ~t3_pc~0; 5603#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5604#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5601#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5602#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5787#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5788#L360-21 assume 1 == ~t4_pc~0; 5734#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5735#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5731#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5732#L767-21 assume !(0 != activate_threads_~tmp___3~0); 5835#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5520#L379-21 assume 1 == ~t5_pc~0; 5462#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5463#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5460#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5461#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5534#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5535#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5418#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5419#L669-3 assume !(1 == ~T3_E~0); 5658#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5659#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5554#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5555#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5621#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5504#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5505#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5322#L709-3 assume !(1 == ~E_5~0); 5323#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5403#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5404#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5398#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5399#L939 assume !(0 == start_simulation_~tmp~3); 5629#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5408#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5409#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5406#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5407#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5660#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 5719#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5524#L952 assume !(0 != start_simulation_~tmp___0~1); 5320#L920-1 [2021-10-11 00:29:28,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,504 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-10-11 00:29:28,504 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,504 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789797427] [2021-10-11 00:29:28,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,541 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789797427] [2021-10-11 00:29:28,541 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,541 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,542 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438379508] [2021-10-11 00:29:28,542 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:28,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,542 INFO L82 PathProgramCache]: Analyzing trace with hash 243645657, now seen corresponding path program 2 times [2021-10-11 00:29:28,543 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,543 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624356432] [2021-10-11 00:29:28,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,592 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624356432] [2021-10-11 00:29:28,592 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,593 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,593 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844971686] [2021-10-11 00:29:28,593 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:28,594 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:28,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-11 00:29:28,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-11 00:29:28,596 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand 4 states. [2021-10-11 00:29:28,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:28,693 INFO L93 Difference]: Finished difference Result 936 states and 1405 transitions. [2021-10-11 00:29:28,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-11 00:29:28,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1405 transitions. [2021-10-11 00:29:28,703 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-10-11 00:29:28,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1405 transitions. [2021-10-11 00:29:28,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2021-10-11 00:29:28,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2021-10-11 00:29:28,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1405 transitions. [2021-10-11 00:29:28,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:28,716 INFO L692 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-10-11 00:29:28,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1405 transitions. [2021-10-11 00:29:28,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2021-10-11 00:29:28,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2021-10-11 00:29:28,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1405 transitions. [2021-10-11 00:29:28,743 INFO L715 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-10-11 00:29:28,744 INFO L595 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-10-11 00:29:28,744 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-11 00:29:28,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1405 transitions. [2021-10-11 00:29:28,749 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-10-11 00:29:28,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:28,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:28,756 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,756 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:28,757 INFO L794 eck$LassoCheckResult]: Stem: 7319#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7196#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7171#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7158#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 7159#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6885#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6886#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7148#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7149#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7050#L431-1 assume !(0 == ~M_E~0); 7051#L591-1 assume !(0 == ~T1_E~0); 7054#L596-1 assume !(0 == ~T2_E~0); 7055#L601-1 assume !(0 == ~T3_E~0); 7123#L606-1 assume !(0 == ~T4_E~0); 6985#L611-1 assume !(0 == ~T5_E~0); 6986#L616-1 assume !(0 == ~E_M~0); 6797#L621-1 assume !(0 == ~E_1~0); 6798#L626-1 assume !(0 == ~E_2~0); 6892#L631-1 assume !(0 == ~E_3~0); 6893#L636-1 assume !(0 == ~E_4~0); 7165#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 7166#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7251#L284 assume 1 == ~m_pc~0; 7191#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7192#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7194#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7195#L735 assume !(0 != activate_threads_~tmp~1); 7386#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6903#L303 assume !(1 == ~t1_pc~0); 6904#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 6964#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6976#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6998#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6999#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7003#L322 assume 1 == ~t2_pc~0; 6839#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6840#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6837#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6838#L751 assume !(0 != activate_threads_~tmp___1~0); 7160#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7161#L341 assume !(1 == ~t3_pc~0); 7111#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 7112#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7108#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7109#L759 assume !(0 != activate_threads_~tmp___2~0); 7334#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7335#L360 assume 1 == ~t4_pc~0; 7264#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7265#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7262#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7263#L767 assume !(0 != activate_threads_~tmp___3~0); 7339#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7048#L379 assume !(1 == ~t5_pc~0); 6957#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 6956#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6951#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6811#L775 assume !(0 != activate_threads_~tmp___4~0); 6812#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 6813#L659-1 assume !(1 == ~T1_E~0); 6890#L664-1 assume !(1 == ~T2_E~0); 6891#L669-1 assume !(1 == ~T3_E~0); 7163#L674-1 assume !(1 == ~T4_E~0); 7164#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7065#L684-1 assume !(1 == ~E_M~0); 7066#L689-1 assume !(1 == ~E_1~0); 7301#L694-1 assume !(1 == ~E_2~0); 7302#L699-1 assume !(1 == ~E_3~0); 7336#L704-1 assume !(1 == ~E_4~0); 7337#L709-1 assume !(1 == ~E_5~0); 7476#L920-1 [2021-10-11 00:29:28,757 INFO L796 eck$LassoCheckResult]: Loop: 7476#L920-1 assume !false; 7338#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6801#L566 assume !false; 6802#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6874#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6875#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6870#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6871#L491 assume !(0 != eval_~tmp~0); 7364#L581 start_simulation_~kernel_st~0 := 2; 7390#L399-1 start_simulation_~kernel_st~0 := 3; 7419#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7415#L591-4 assume !(0 == ~T1_E~0); 7061#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7062#L601-3 assume !(0 == ~T3_E~0); 7124#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6991#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6806#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6807#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6862#L631-3 assume !(0 == ~E_3~0); 6863#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7542#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7541#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7540#L284-21 assume 1 == ~m_pc~0; 7538#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7268#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7269#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7258#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7259#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7367#L303-21 assume !(1 == ~t1_pc~0); 7368#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 7535#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7340#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7341#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7379#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7380#L322-21 assume 1 == ~t2_pc~0; 6829#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6830#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6827#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6828#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7127#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7128#L341-21 assume !(1 == ~t3_pc~0); 7104#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 7103#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7100#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7101#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7315#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7316#L360-21 assume 1 == ~t4_pc~0; 7248#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7249#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7246#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7247#L767-21 assume !(0 != activate_threads_~tmp___3~0); 7534#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7000#L379-21 assume 1 == ~t5_pc~0; 7001#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7035#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7036#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7016#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7017#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7019#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7226#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7391#L669-3 assume !(1 == ~T3_E~0); 7392#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7410#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7411#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7533#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7120#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7121#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7328#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7329#L709-3 assume !(1 == ~E_5~0); 7224#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7225#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7499#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7498#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7497#L939 assume !(0 == start_simulation_~tmp~3); 7333#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7486#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7482#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7481#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 7480#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7479#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 7478#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7477#L952 assume !(0 != start_simulation_~tmp___0~1); 7476#L920-1 [2021-10-11 00:29:28,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,758 INFO L82 PathProgramCache]: Analyzing trace with hash -515799174, now seen corresponding path program 1 times [2021-10-11 00:29:28,758 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,763 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598541082] [2021-10-11 00:29:28,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,801 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598541082] [2021-10-11 00:29:28,804 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,807 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,807 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41503424] [2021-10-11 00:29:28,808 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:28,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:28,808 INFO L82 PathProgramCache]: Analyzing trace with hash -3410954, now seen corresponding path program 1 times [2021-10-11 00:29:28,808 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:28,808 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673969718] [2021-10-11 00:29:28,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:28,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:28,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:28,852 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673969718] [2021-10-11 00:29:28,852 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:28,853 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:28,853 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053783342] [2021-10-11 00:29:28,853 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:28,853 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:28,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-11 00:29:28,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-11 00:29:28,854 INFO L87 Difference]: Start difference. First operand 936 states and 1405 transitions. cyclomatic complexity: 471 Second operand 4 states. [2021-10-11 00:29:28,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:28,971 INFO L93 Difference]: Finished difference Result 1656 states and 2478 transitions. [2021-10-11 00:29:28,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-11 00:29:28,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1656 states and 2478 transitions. [2021-10-11 00:29:29,019 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2021-10-11 00:29:29,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1656 states to 1656 states and 2478 transitions. [2021-10-11 00:29:29,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1656 [2021-10-11 00:29:29,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1656 [2021-10-11 00:29:29,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1656 states and 2478 transitions. [2021-10-11 00:29:29,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:29,039 INFO L692 BuchiCegarLoop]: Abstraction has 1656 states and 2478 transitions. [2021-10-11 00:29:29,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states and 2478 transitions. [2021-10-11 00:29:29,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1654. [2021-10-11 00:29:29,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1654 states. [2021-10-11 00:29:29,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 2476 transitions. [2021-10-11 00:29:29,085 INFO L715 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2021-10-11 00:29:29,086 INFO L595 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2021-10-11 00:29:29,086 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-11 00:29:29,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1654 states and 2476 transitions. [2021-10-11 00:29:29,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2021-10-11 00:29:29,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:29,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:29,105 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:29,105 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:29,106 INFO L794 eck$LassoCheckResult]: Stem: 9885#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9773#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9748#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9735#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 9736#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9488#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9489#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9725#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9726#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9636#L431-1 assume !(0 == ~M_E~0); 9637#L591-1 assume !(0 == ~T1_E~0); 9640#L596-1 assume !(0 == ~T2_E~0); 9641#L601-1 assume !(0 == ~T3_E~0); 9707#L606-1 assume !(0 == ~T4_E~0); 9587#L611-1 assume !(0 == ~T5_E~0); 9588#L616-1 assume !(0 == ~E_M~0); 9400#L621-1 assume !(0 == ~E_1~0); 9401#L626-1 assume !(0 == ~E_2~0); 9493#L631-1 assume !(0 == ~E_3~0); 9494#L636-1 assume !(0 == ~E_4~0); 9742#L641-1 assume !(0 == ~E_5~0); 9743#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9829#L284 assume 1 == ~m_pc~0; 9768#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9769#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9771#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9772#L735 assume !(0 != activate_threads_~tmp~1); 9935#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9506#L303 assume !(1 == ~t1_pc~0); 9507#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 9567#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9578#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9598#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9599#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9601#L322 assume 1 == ~t2_pc~0; 9442#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9443#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9440#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9441#L751 assume !(0 != activate_threads_~tmp___1~0); 9737#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9738#L341 assume !(1 == ~t3_pc~0); 9696#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 9697#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9693#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9694#L759 assume !(0 != activate_threads_~tmp___2~0); 9895#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9896#L360 assume 1 == ~t4_pc~0; 9840#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9841#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9838#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9839#L767 assume !(0 != activate_threads_~tmp___3~0); 9900#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9634#L379 assume !(1 == ~t5_pc~0); 9560#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 9559#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9556#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9414#L775 assume !(0 != activate_threads_~tmp___4~0); 9415#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 9416#L659-1 assume !(1 == ~T1_E~0); 9491#L664-1 assume !(1 == ~T2_E~0); 9492#L669-1 assume !(1 == ~T3_E~0); 10042#L674-1 assume !(1 == ~T4_E~0); 10038#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10005#L684-1 assume !(1 == ~E_M~0); 10003#L689-1 assume !(1 == ~E_1~0); 10002#L694-1 assume !(1 == ~E_2~0); 10000#L699-1 assume !(1 == ~E_3~0); 9897#L704-1 assume !(1 == ~E_4~0); 9898#L709-1 assume !(1 == ~E_5~0); 9979#L920-1 [2021-10-11 00:29:29,106 INFO L796 eck$LassoCheckResult]: Loop: 9979#L920-1 assume !false; 9974#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9973#L566 assume !false; 9972#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9966#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9965#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9964#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9962#L491 assume !(0 != eval_~tmp~0); 9961#L581 start_simulation_~kernel_st~0 := 2; 9960#L399-1 start_simulation_~kernel_st~0 := 3; 9958#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9959#L591-4 assume !(0 == ~T1_E~0); 10467#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10464#L601-3 assume !(0 == ~T3_E~0); 10461#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10457#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10452#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10448#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10445#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10442#L631-3 assume !(0 == ~E_3~0); 10440#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10438#L641-3 assume !(0 == ~E_5~0); 10431#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10430#L284-21 assume 1 == ~m_pc~0; 10425#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10420#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10416#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10412#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10408#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10405#L303-21 assume !(1 == ~t1_pc~0); 10398#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 10393#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10389#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10385#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10381#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10378#L322-21 assume 1 == ~t2_pc~0; 10371#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10365#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10363#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10361#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10359#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10351#L341-21 assume !(1 == ~t3_pc~0); 10347#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 10342#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10338#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9880#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9881#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9882#L360-21 assume 1 == ~t4_pc~0; 10311#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10309#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10297#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10286#L767-21 assume !(0 != activate_threads_~tmp___3~0); 10284#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10281#L379-21 assume 1 == ~t5_pc~0; 10275#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10272#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10268#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10263#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10259#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9616#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10252#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10248#L669-3 assume !(1 == ~T3_E~0); 10246#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10242#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10239#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10236#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10233#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10230#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10227#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10222#L709-3 assume !(1 == ~E_5~0); 10220#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10217#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10211#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10209#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 10207#L939 assume !(0 == start_simulation_~tmp~3); 9894#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10183#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10175#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10014#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 10012#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9998#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 9996#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9985#L952 assume !(0 != start_simulation_~tmp___0~1); 9979#L920-1 [2021-10-11 00:29:29,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:29,107 INFO L82 PathProgramCache]: Analyzing trace with hash -531317892, now seen corresponding path program 1 times [2021-10-11 00:29:29,107 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:29,107 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854677794] [2021-10-11 00:29:29,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:29,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:29,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:29,153 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854677794] [2021-10-11 00:29:29,153 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:29,153 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-11 00:29:29,154 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543227745] [2021-10-11 00:29:29,154 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:29,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:29,155 INFO L82 PathProgramCache]: Analyzing trace with hash 675861300, now seen corresponding path program 1 times [2021-10-11 00:29:29,155 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:29,155 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481096286] [2021-10-11 00:29:29,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:29,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:29,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:29,190 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481096286] [2021-10-11 00:29:29,190 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:29,191 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:29,191 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574674501] [2021-10-11 00:29:29,191 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:29,191 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:29,192 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:29,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:29,192 INFO L87 Difference]: Start difference. First operand 1654 states and 2476 transitions. cyclomatic complexity: 826 Second operand 3 states. [2021-10-11 00:29:29,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:29,265 INFO L93 Difference]: Finished difference Result 3178 states and 4699 transitions. [2021-10-11 00:29:29,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:29,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3178 states and 4699 transitions. [2021-10-11 00:29:29,294 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3081 [2021-10-11 00:29:29,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3178 states to 3178 states and 4699 transitions. [2021-10-11 00:29:29,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3178 [2021-10-11 00:29:29,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3178 [2021-10-11 00:29:29,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3178 states and 4699 transitions. [2021-10-11 00:29:29,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:29,333 INFO L692 BuchiCegarLoop]: Abstraction has 3178 states and 4699 transitions. [2021-10-11 00:29:29,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3178 states and 4699 transitions. [2021-10-11 00:29:29,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3178 to 3018. [2021-10-11 00:29:29,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3018 states. [2021-10-11 00:29:29,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3018 states to 3018 states and 4475 transitions. [2021-10-11 00:29:29,404 INFO L715 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2021-10-11 00:29:29,404 INFO L595 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2021-10-11 00:29:29,404 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-11 00:29:29,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3018 states and 4475 transitions. [2021-10-11 00:29:29,422 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2921 [2021-10-11 00:29:29,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:29,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:29,424 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:29,424 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:29,424 INFO L794 eck$LassoCheckResult]: Stem: 14772#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 14630#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14608#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14595#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 14596#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14325#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14326#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14581#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14582#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14484#L431-1 assume !(0 == ~M_E~0); 14485#L591-1 assume !(0 == ~T1_E~0); 14489#L596-1 assume !(0 == ~T2_E~0); 14490#L601-1 assume !(0 == ~T3_E~0); 14555#L606-1 assume !(0 == ~T4_E~0); 14426#L611-1 assume !(0 == ~T5_E~0); 14427#L616-1 assume !(0 == ~E_M~0); 14240#L621-1 assume !(0 == ~E_1~0); 14241#L626-1 assume !(0 == ~E_2~0); 14333#L631-1 assume !(0 == ~E_3~0); 14334#L636-1 assume !(0 == ~E_4~0); 14602#L641-1 assume !(0 == ~E_5~0); 14603#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14701#L284 assume !(1 == ~m_pc~0); 14685#L284-2 is_master_triggered_~__retres1~0 := 0; 14686#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14628#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14629#L735 assume !(0 != activate_threads_~tmp~1); 14842#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14344#L303 assume !(1 == ~t1_pc~0); 14345#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 14406#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14415#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14439#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14440#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14442#L322 assume 1 == ~t2_pc~0; 14282#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14283#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14280#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14281#L751 assume !(0 != activate_threads_~tmp___1~0); 14597#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14598#L341 assume !(1 == ~t3_pc~0); 14545#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 14546#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14542#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14543#L759 assume !(0 != activate_threads_~tmp___2~0); 14787#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14788#L360 assume 1 == ~t4_pc~0; 14714#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14715#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14709#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14710#L767 assume !(0 != activate_threads_~tmp___3~0); 14793#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14483#L379 assume !(1 == ~t5_pc~0); 14399#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 14398#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14394#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14252#L775 assume !(0 != activate_threads_~tmp___4~0); 14253#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 14256#L659-1 assume !(1 == ~T1_E~0); 14331#L664-1 assume !(1 == ~T2_E~0); 14332#L669-1 assume !(1 == ~T3_E~0); 14843#L674-1 assume !(1 == ~T4_E~0); 16657#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16656#L684-1 assume !(1 == ~E_M~0); 16655#L689-1 assume !(1 == ~E_1~0); 16651#L694-1 assume !(1 == ~E_2~0); 16649#L699-1 assume !(1 == ~E_3~0); 16644#L704-1 assume !(1 == ~E_4~0); 14231#L709-1 assume !(1 == ~E_5~0); 14232#L920-1 [2021-10-11 00:29:29,424 INFO L796 eck$LassoCheckResult]: Loop: 14232#L920-1 assume !false; 14968#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 14963#L566 assume !false; 14958#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14949#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 14945#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14929#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 14923#L491 assume !(0 != eval_~tmp~0); 14848#L581 start_simulation_~kernel_st~0 := 2; 14585#L399-1 start_simulation_~kernel_st~0 := 3; 14586#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14871#L591-4 assume !(0 == ~T1_E~0); 14495#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14496#L601-3 assume !(0 == ~T3_E~0); 14559#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14433#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14434#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14249#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14250#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14305#L631-3 assume !(0 == ~E_3~0); 14306#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14592#L641-3 assume !(0 == ~E_5~0); 14593#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14658#L284-21 assume !(1 == ~m_pc~0); 14656#L284-23 is_master_triggered_~__retres1~0 := 0; 14657#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14639#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14640#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14673#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14674#L303-21 assume 1 == ~t1_pc~0; 14796#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14797#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14794#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14795#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14836#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14330#L322-21 assume 1 == ~t2_pc~0; 14272#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14273#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14270#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14271#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14561#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14562#L341-21 assume 1 == ~t3_pc~0; 14536#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14537#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14534#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14535#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14765#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14766#L360-21 assume 1 == ~t4_pc~0; 14698#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14699#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14696#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14697#L767-21 assume !(0 != activate_threads_~tmp___3~0); 14853#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14854#L379-21 assume !(1 == ~t5_pc~0); 17024#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 17021#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17019#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 17017#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17014#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 14460#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17011#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17009#L669-3 assume !(1 == ~T3_E~0); 16600#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17006#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17005#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17002#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17000#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16706#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16704#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16702#L709-3 assume !(1 == ~E_5~0); 14239#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16694#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16686#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16684#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 16683#L939 assume !(0 == start_simulation_~tmp~3); 15062#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16680#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16676#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16675#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 16674#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16673#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 16672#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 14975#L952 assume !(0 != start_simulation_~tmp___0~1); 14232#L920-1 [2021-10-11 00:29:29,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:29,425 INFO L82 PathProgramCache]: Analyzing trace with hash 1870207229, now seen corresponding path program 1 times [2021-10-11 00:29:29,425 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:29,425 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519555981] [2021-10-11 00:29:29,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:29,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:29,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:29,493 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519555981] [2021-10-11 00:29:29,493 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:29,494 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-11 00:29:29,494 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693465844] [2021-10-11 00:29:29,494 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:29,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:29,495 INFO L82 PathProgramCache]: Analyzing trace with hash 764946036, now seen corresponding path program 1 times [2021-10-11 00:29:29,495 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:29,495 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745178767] [2021-10-11 00:29:29,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:29,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:29,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:29,529 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745178767] [2021-10-11 00:29:29,529 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:29,529 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-11 00:29:29,529 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035685055] [2021-10-11 00:29:29,530 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:29,530 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:29,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-11 00:29:29,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-11 00:29:29,531 INFO L87 Difference]: Start difference. First operand 3018 states and 4475 transitions. cyclomatic complexity: 1465 Second operand 5 states. [2021-10-11 00:29:29,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:29,740 INFO L93 Difference]: Finished difference Result 8208 states and 12147 transitions. [2021-10-11 00:29:29,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-11 00:29:29,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8208 states and 12147 transitions. [2021-10-11 00:29:29,795 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7982 [2021-10-11 00:29:29,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8208 states to 8208 states and 12147 transitions. [2021-10-11 00:29:29,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8208 [2021-10-11 00:29:29,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8208 [2021-10-11 00:29:29,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8208 states and 12147 transitions. [2021-10-11 00:29:29,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:29,886 INFO L692 BuchiCegarLoop]: Abstraction has 8208 states and 12147 transitions. [2021-10-11 00:29:29,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8208 states and 12147 transitions. [2021-10-11 00:29:30,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8208 to 3171. [2021-10-11 00:29:30,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3171 states. [2021-10-11 00:29:30,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3171 states to 3171 states and 4628 transitions. [2021-10-11 00:29:30,065 INFO L715 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2021-10-11 00:29:30,065 INFO L595 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2021-10-11 00:29:30,065 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-11 00:29:30,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3171 states and 4628 transitions. [2021-10-11 00:29:30,079 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3071 [2021-10-11 00:29:30,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:30,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:30,081 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:30,081 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:30,081 INFO L794 eck$LassoCheckResult]: Stem: 26009#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 25872#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25850#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25837#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 25838#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25568#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25569#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25821#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25822#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25726#L431-1 assume !(0 == ~M_E~0); 25727#L591-1 assume !(0 == ~T1_E~0); 25731#L596-1 assume !(0 == ~T2_E~0); 25732#L601-1 assume !(0 == ~T3_E~0); 25800#L606-1 assume !(0 == ~T4_E~0); 25671#L611-1 assume !(0 == ~T5_E~0); 25672#L616-1 assume !(0 == ~E_M~0); 25481#L621-1 assume !(0 == ~E_1~0); 25482#L626-1 assume !(0 == ~E_2~0); 25576#L631-1 assume !(0 == ~E_3~0); 25577#L636-1 assume !(0 == ~E_4~0); 25844#L641-1 assume !(0 == ~E_5~0); 25845#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25940#L284 assume !(1 == ~m_pc~0); 25925#L284-2 is_master_triggered_~__retres1~0 := 0; 25926#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25870#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25871#L735 assume !(0 != activate_threads_~tmp~1); 26118#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25585#L303 assume !(1 == ~t1_pc~0); 25586#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 25650#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25660#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25684#L743 assume !(0 != activate_threads_~tmp___0~0); 25685#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25687#L322 assume 1 == ~t2_pc~0; 25523#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25524#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25521#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 25522#L751 assume !(0 != activate_threads_~tmp___1~0); 25839#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25840#L341 assume !(1 == ~t3_pc~0); 25789#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 25790#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25786#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25787#L759 assume !(0 != activate_threads_~tmp___2~0); 26028#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26029#L360 assume 1 == ~t4_pc~0; 25953#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25954#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25947#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25948#L767 assume !(0 != activate_threads_~tmp___3~0); 26033#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25724#L379 assume !(1 == ~t5_pc~0); 25643#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 25642#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25637#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25493#L775 assume !(0 != activate_threads_~tmp___4~0); 25494#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 25497#L659-1 assume !(1 == ~T1_E~0); 27363#L664-1 assume !(1 == ~T2_E~0); 26119#L669-1 assume !(1 == ~T3_E~0); 26120#L674-1 assume !(1 == ~T4_E~0); 27780#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27753#L684-1 assume !(1 == ~E_M~0); 27746#L689-1 assume !(1 == ~E_1~0); 27738#L694-1 assume !(1 == ~E_2~0); 27729#L699-1 assume !(1 == ~E_3~0); 27722#L704-1 assume !(1 == ~E_4~0); 27714#L709-1 assume !(1 == ~E_5~0); 27148#L920-1 [2021-10-11 00:29:30,081 INFO L796 eck$LassoCheckResult]: Loop: 27148#L920-1 assume !false; 27326#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 27325#L566 assume !false; 27144#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27115#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27105#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27101#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 27098#L491 assume !(0 != eval_~tmp~0); 27099#L581 start_simulation_~kernel_st~0 := 2; 28468#L399-1 start_simulation_~kernel_st~0 := 3; 28466#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 26144#L591-4 assume !(0 == ~T1_E~0); 25738#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25739#L601-3 assume !(0 == ~T3_E~0); 25802#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25678#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25679#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25490#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25491#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25546#L631-3 assume !(0 == ~E_3~0); 25547#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25831#L641-3 assume !(0 == ~E_5~0); 25832#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25900#L284-21 assume !(1 == ~m_pc~0); 25898#L284-23 is_master_triggered_~__retres1~0 := 0; 25899#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25881#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25882#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25912#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25913#L303-21 assume 1 == ~t1_pc~0; 26036#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26037#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26105#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28482#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26106#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28163#L322-21 assume 1 == ~t2_pc~0; 28161#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28159#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28156#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28036#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28035#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28034#L341-21 assume !(1 == ~t3_pc~0); 28032#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 28030#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28029#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 28027#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28024#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28021#L360-21 assume 1 == ~t4_pc~0; 28017#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27982#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27977#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27972#L767-21 assume !(0 != activate_threads_~tmp___3~0); 27965#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27960#L379-21 assume 1 == ~t5_pc~0; 27954#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 27947#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27942#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27937#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 27930#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 25703#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27921#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27916#L669-3 assume !(1 == ~T3_E~0); 26128#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27908#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27902#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27898#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27894#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27891#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27872#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27867#L709-3 assume !(1 == ~E_5~0); 27849#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27840#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27831#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27827#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 27823#L939 assume !(0 == start_simulation_~tmp~3); 26027#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27777#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27752#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27745#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 27737#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27728#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 27721#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 27713#L952 assume !(0 != start_simulation_~tmp___0~1); 27148#L920-1 [2021-10-11 00:29:30,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:30,082 INFO L82 PathProgramCache]: Analyzing trace with hash -1765228545, now seen corresponding path program 1 times [2021-10-11 00:29:30,082 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:30,082 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100294688] [2021-10-11 00:29:30,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:30,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:30,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:30,121 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100294688] [2021-10-11 00:29:30,126 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:30,126 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:30,126 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934821257] [2021-10-11 00:29:30,127 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:30,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:30,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1333424140, now seen corresponding path program 1 times [2021-10-11 00:29:30,128 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:30,128 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406918589] [2021-10-11 00:29:30,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:30,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:30,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:30,169 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406918589] [2021-10-11 00:29:30,169 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:30,170 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:30,170 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724559902] [2021-10-11 00:29:30,170 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:30,170 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:30,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-11 00:29:30,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-11 00:29:30,172 INFO L87 Difference]: Start difference. First operand 3171 states and 4628 transitions. cyclomatic complexity: 1465 Second operand 4 states. [2021-10-11 00:29:30,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:30,380 INFO L93 Difference]: Finished difference Result 7450 states and 10744 transitions. [2021-10-11 00:29:30,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-11 00:29:30,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7450 states and 10744 transitions. [2021-10-11 00:29:30,501 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7147 [2021-10-11 00:29:30,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7450 states to 7450 states and 10744 transitions. [2021-10-11 00:29:30,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7450 [2021-10-11 00:29:30,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7450 [2021-10-11 00:29:30,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7450 states and 10744 transitions. [2021-10-11 00:29:30,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:30,570 INFO L692 BuchiCegarLoop]: Abstraction has 7450 states and 10744 transitions. [2021-10-11 00:29:30,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7450 states and 10744 transitions. [2021-10-11 00:29:30,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7450 to 5823. [2021-10-11 00:29:30,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5823 states. [2021-10-11 00:29:30,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5823 states to 5823 states and 8450 transitions. [2021-10-11 00:29:30,695 INFO L715 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2021-10-11 00:29:30,696 INFO L595 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2021-10-11 00:29:30,696 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-11 00:29:30,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5823 states and 8450 transitions. [2021-10-11 00:29:30,721 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5720 [2021-10-11 00:29:30,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:30,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:30,723 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:30,723 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:30,723 INFO L794 eck$LassoCheckResult]: Stem: 36621#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36492#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36470#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36457#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 36458#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36199#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36200#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36445#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36446#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36351#L431-1 assume !(0 == ~M_E~0); 36352#L591-1 assume !(0 == ~T1_E~0); 36355#L596-1 assume !(0 == ~T2_E~0); 36356#L601-1 assume !(0 == ~T3_E~0); 36422#L606-1 assume !(0 == ~T4_E~0); 36305#L611-1 assume !(0 == ~T5_E~0); 36306#L616-1 assume !(0 == ~E_M~0); 36111#L621-1 assume !(0 == ~E_1~0); 36112#L626-1 assume !(0 == ~E_2~0); 36207#L631-1 assume !(0 == ~E_3~0); 36208#L636-1 assume !(0 == ~E_4~0); 36464#L641-1 assume !(0 == ~E_5~0); 36465#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36562#L284 assume !(1 == ~m_pc~0); 36547#L284-2 is_master_triggered_~__retres1~0 := 0; 36548#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36490#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36491#L735 assume !(0 != activate_threads_~tmp~1); 36691#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36223#L303 assume !(1 == ~t1_pc~0); 36224#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 36284#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36296#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36316#L743 assume !(0 != activate_threads_~tmp___0~0); 36317#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36319#L322 assume !(1 == ~t2_pc~0); 36451#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 36450#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36151#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36152#L751 assume !(0 != activate_threads_~tmp___1~0); 36459#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36460#L341 assume !(1 == ~t3_pc~0); 36411#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 36412#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36408#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36409#L759 assume !(0 != activate_threads_~tmp___2~0); 36631#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36632#L360 assume 1 == ~t4_pc~0; 36573#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36574#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36571#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36572#L767 assume !(0 != activate_threads_~tmp___3~0); 36636#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36348#L379 assume !(1 == ~t5_pc~0); 36278#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 36277#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36273#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36125#L775 assume !(0 != activate_threads_~tmp___4~0); 36126#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 36127#L659-1 assume !(1 == ~T1_E~0); 36523#L664-1 assume !(1 == ~T2_E~0); 36693#L669-1 assume !(1 == ~T3_E~0); 36694#L674-1 assume !(1 == ~T4_E~0); 36708#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36709#L684-1 assume !(1 == ~E_M~0); 36675#L689-1 assume !(1 == ~E_1~0); 36676#L694-1 assume !(1 == ~E_2~0); 36320#L699-1 assume !(1 == ~E_3~0); 36321#L704-1 assume !(1 == ~E_4~0); 36103#L709-1 assume !(1 == ~E_5~0); 36104#L920-1 [2021-10-11 00:29:30,723 INFO L796 eck$LassoCheckResult]: Loop: 36104#L920-1 assume !false; 36635#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 36115#L566 assume !false; 36116#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36188#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36189#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36184#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 36185#L491 assume !(0 != eval_~tmp~0); 36671#L581 start_simulation_~kernel_st~0 := 2; 36447#L399-1 start_simulation_~kernel_st~0 := 3; 36448#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36706#L591-4 assume !(0 == ~T1_E~0); 36361#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36362#L601-3 assume !(0 == ~T3_E~0); 36423#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36310#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36311#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36120#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36121#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36173#L631-3 assume !(0 == ~E_3~0); 36174#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36454#L641-3 assume !(0 == ~E_5~0); 36455#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36520#L284-21 assume !(1 == ~m_pc~0); 36518#L284-23 is_master_triggered_~__retres1~0 := 0; 36519#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36501#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36502#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 36535#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36536#L303-21 assume !(1 == ~t1_pc~0); 36641#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 36669#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36637#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36638#L743-21 assume !(0 != activate_threads_~tmp___0~0); 36686#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36203#L322-21 assume !(1 == ~t2_pc~0); 36204#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 36209#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36141#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36142#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36428#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36429#L341-21 assume 1 == ~t3_pc~0; 36402#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 36403#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36400#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36401#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36617#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36618#L360-21 assume !(1 == ~t4_pc~0); 36561#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 36560#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36557#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36558#L767-21 assume !(0 != activate_threads_~tmp___3~0); 36695#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36318#L379-21 assume 1 == ~t5_pc~0; 36263#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36264#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36257#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36258#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36330#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 36332#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36210#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36211#L669-3 assume !(1 == ~T3_E~0); 36467#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36468#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36353#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36354#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36420#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36302#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36303#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36107#L709-3 assume !(1 == ~E_5~0); 36108#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36191#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36192#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36186#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 36187#L939 assume !(0 == start_simulation_~tmp~3); 36431#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36196#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36197#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36194#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 36195#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 36469#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 36542#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 36322#L952 assume !(0 != start_simulation_~tmp___0~1); 36104#L920-1 [2021-10-11 00:29:30,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:30,724 INFO L82 PathProgramCache]: Analyzing trace with hash -713779456, now seen corresponding path program 1 times [2021-10-11 00:29:30,724 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:30,724 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731143237] [2021-10-11 00:29:30,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:30,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:30,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:30,758 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731143237] [2021-10-11 00:29:30,758 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:30,758 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:30,758 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765106766] [2021-10-11 00:29:30,758 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:30,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:30,759 INFO L82 PathProgramCache]: Analyzing trace with hash 111829360, now seen corresponding path program 1 times [2021-10-11 00:29:30,759 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:30,759 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209573528] [2021-10-11 00:29:30,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:30,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:30,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:30,862 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209573528] [2021-10-11 00:29:30,862 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:30,862 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:30,862 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524082398] [2021-10-11 00:29:30,862 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:30,863 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:30,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-11 00:29:30,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-11 00:29:30,863 INFO L87 Difference]: Start difference. First operand 5823 states and 8450 transitions. cyclomatic complexity: 2635 Second operand 4 states. [2021-10-11 00:29:31,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:31,116 INFO L93 Difference]: Finished difference Result 13963 states and 20008 transitions. [2021-10-11 00:29:31,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-11 00:29:31,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13963 states and 20008 transitions. [2021-10-11 00:29:31,209 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13457 [2021-10-11 00:29:31,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13963 states to 13963 states and 20008 transitions. [2021-10-11 00:29:31,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13963 [2021-10-11 00:29:31,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13963 [2021-10-11 00:29:31,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13963 states and 20008 transitions. [2021-10-11 00:29:31,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:31,321 INFO L692 BuchiCegarLoop]: Abstraction has 13963 states and 20008 transitions. [2021-10-11 00:29:31,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13963 states and 20008 transitions. [2021-10-11 00:29:31,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13963 to 11074. [2021-10-11 00:29:31,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11074 states. [2021-10-11 00:29:31,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11074 states to 11074 states and 15959 transitions. [2021-10-11 00:29:31,622 INFO L715 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2021-10-11 00:29:31,622 INFO L595 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2021-10-11 00:29:31,622 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-11 00:29:31,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11074 states and 15959 transitions. [2021-10-11 00:29:31,663 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10964 [2021-10-11 00:29:31,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:31,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:31,665 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:31,665 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:31,665 INFO L794 eck$LassoCheckResult]: Stem: 56425#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56293#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56271#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56258#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 56259#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55993#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55994#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56243#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56244#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56150#L431-1 assume !(0 == ~M_E~0); 56151#L591-1 assume !(0 == ~T1_E~0); 56155#L596-1 assume !(0 == ~T2_E~0); 56156#L601-1 assume !(0 == ~T3_E~0); 56221#L606-1 assume !(0 == ~T4_E~0); 56101#L611-1 assume !(0 == ~T5_E~0); 56102#L616-1 assume !(0 == ~E_M~0); 55907#L621-1 assume !(0 == ~E_1~0); 55908#L626-1 assume !(0 == ~E_2~0); 56004#L631-1 assume !(0 == ~E_3~0); 56005#L636-1 assume !(0 == ~E_4~0); 56265#L641-1 assume !(0 == ~E_5~0); 56266#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56364#L284 assume !(1 == ~m_pc~0); 56347#L284-2 is_master_triggered_~__retres1~0 := 0; 56348#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56291#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56292#L735 assume !(0 != activate_threads_~tmp~1); 56498#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56018#L303 assume !(1 == ~t1_pc~0); 56019#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 56080#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56090#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56114#L743 assume !(0 != activate_threads_~tmp___0~0); 56115#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56117#L322 assume !(1 == ~t2_pc~0); 56251#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 56250#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55947#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55948#L751 assume !(0 != activate_threads_~tmp___1~0); 56260#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56261#L341 assume !(1 == ~t3_pc~0); 56211#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 56212#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56208#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56209#L759 assume !(0 != activate_threads_~tmp___2~0); 56434#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56435#L360 assume !(1 == ~t4_pc~0); 56518#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 56516#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56371#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56372#L767 assume !(0 != activate_threads_~tmp___3~0); 56438#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56148#L379 assume !(1 == ~t5_pc~0); 56074#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 56073#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56069#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55919#L775 assume !(0 != activate_threads_~tmp___4~0); 55920#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 55923#L659-1 assume !(1 == ~T1_E~0); 56324#L664-1 assume !(1 == ~T2_E~0); 56499#L669-1 assume !(1 == ~T3_E~0); 56263#L674-1 assume !(1 == ~T4_E~0); 56264#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56165#L684-1 assume !(1 == ~E_M~0); 56166#L689-1 assume !(1 == ~E_1~0); 64092#L694-1 assume !(1 == ~E_2~0); 64090#L699-1 assume !(1 == ~E_3~0); 64088#L704-1 assume !(1 == ~E_4~0); 55899#L709-1 assume !(1 == ~E_5~0); 55900#L920-1 [2021-10-11 00:29:31,666 INFO L796 eck$LassoCheckResult]: Loop: 55900#L920-1 assume !false; 56437#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 55911#L566 assume !false; 55912#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55983#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55984#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55981#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 55982#L491 assume !(0 != eval_~tmp~0); 56477#L581 start_simulation_~kernel_st~0 := 2; 56247#L399-1 start_simulation_~kernel_st~0 := 3; 56248#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56522#L591-4 assume !(0 == ~T1_E~0); 56161#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56162#L601-3 assume !(0 == ~T3_E~0); 56223#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56108#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56109#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55916#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55917#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55969#L631-3 assume !(0 == ~E_3~0); 55970#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56255#L641-3 assume !(0 == ~E_5~0); 56256#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56321#L284-21 assume !(1 == ~m_pc~0); 56319#L284-23 is_master_triggered_~__retres1~0 := 0; 56320#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56302#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56303#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 56334#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56335#L303-21 assume 1 == ~t1_pc~0; 56441#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56442#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66956#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66852#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56490#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56000#L322-21 assume !(1 == ~t2_pc~0); 56001#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 56006#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55937#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55938#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56225#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56226#L341-21 assume 1 == ~t3_pc~0; 56202#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56203#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56200#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56201#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56421#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56422#L360-21 assume !(1 == ~t4_pc~0); 56497#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 56501#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56359#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56360#L767-21 assume !(0 != activate_threads_~tmp___3~0); 56502#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56116#L379-21 assume 1 == ~t5_pc~0; 56061#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56062#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56055#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56056#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 56129#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 56131#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56007#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56008#L669-3 assume !(1 == ~T3_E~0); 56268#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56269#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56153#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56154#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56220#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56099#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56100#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55905#L709-3 assume !(1 == ~E_5~0); 55906#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55988#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55989#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55986#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 55987#L939 assume !(0 == start_simulation_~tmp~3); 56228#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55995#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55996#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55991#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 55992#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56270#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 56342#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 56120#L952 assume !(0 != start_simulation_~tmp___0~1); 55900#L920-1 [2021-10-11 00:29:31,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:31,666 INFO L82 PathProgramCache]: Analyzing trace with hash 66201473, now seen corresponding path program 1 times [2021-10-11 00:29:31,666 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:31,666 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564415525] [2021-10-11 00:29:31,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:31,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:31,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:31,699 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564415525] [2021-10-11 00:29:31,700 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:31,700 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-11 00:29:31,700 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404116466] [2021-10-11 00:29:31,700 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:31,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:31,701 INFO L82 PathProgramCache]: Analyzing trace with hash 490108371, now seen corresponding path program 1 times [2021-10-11 00:29:31,701 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:31,701 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621975448] [2021-10-11 00:29:31,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:31,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:31,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:31,727 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621975448] [2021-10-11 00:29:31,727 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:31,727 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:31,727 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172831566] [2021-10-11 00:29:31,728 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:31,728 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:31,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:31,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:31,729 INFO L87 Difference]: Start difference. First operand 11074 states and 15959 transitions. cyclomatic complexity: 4893 Second operand 3 states. [2021-10-11 00:29:31,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:31,807 INFO L93 Difference]: Finished difference Result 13875 states and 19988 transitions. [2021-10-11 00:29:31,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:31,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13875 states and 19988 transitions. [2021-10-11 00:29:31,876 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13772 [2021-10-11 00:29:32,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13875 states to 13875 states and 19988 transitions. [2021-10-11 00:29:32,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13875 [2021-10-11 00:29:32,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13875 [2021-10-11 00:29:32,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13875 states and 19988 transitions. [2021-10-11 00:29:32,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:32,094 INFO L692 BuchiCegarLoop]: Abstraction has 13875 states and 19988 transitions. [2021-10-11 00:29:32,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13875 states and 19988 transitions. [2021-10-11 00:29:32,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13875 to 6055. [2021-10-11 00:29:32,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6055 states. [2021-10-11 00:29:32,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8760 transitions. [2021-10-11 00:29:32,232 INFO L715 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2021-10-11 00:29:32,232 INFO L595 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2021-10-11 00:29:32,232 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-11 00:29:32,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8760 transitions. [2021-10-11 00:29:32,254 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2021-10-11 00:29:32,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:32,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:32,256 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:32,257 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:32,257 INFO L794 eck$LassoCheckResult]: Stem: 81403#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81261#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81239#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81226#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 81227#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80947#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80948#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81209#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81210#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81108#L431-1 assume !(0 == ~M_E~0); 81109#L591-1 assume !(0 == ~T1_E~0); 81113#L596-1 assume !(0 == ~T2_E~0); 81114#L601-1 assume !(0 == ~T3_E~0); 81179#L606-1 assume !(0 == ~T4_E~0); 81055#L611-1 assume !(0 == ~T5_E~0); 81056#L616-1 assume !(0 == ~E_M~0); 80862#L621-1 assume !(0 == ~E_1~0); 80863#L626-1 assume !(0 == ~E_2~0); 80956#L631-1 assume !(0 == ~E_3~0); 80957#L636-1 assume !(0 == ~E_4~0); 81233#L641-1 assume !(0 == ~E_5~0); 81234#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81335#L284 assume !(1 == ~m_pc~0); 81318#L284-2 is_master_triggered_~__retres1~0 := 0; 81319#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81259#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81260#L735 assume !(0 != activate_threads_~tmp~1); 81482#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80970#L303 assume !(1 == ~t1_pc~0); 80971#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 81033#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81519#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81067#L743 assume !(0 != activate_threads_~tmp___0~0); 81068#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81070#L322 assume !(1 == ~t2_pc~0); 81217#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 81216#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80901#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 80902#L751 assume !(0 != activate_threads_~tmp___1~0); 81228#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81229#L341 assume !(1 == ~t3_pc~0); 81169#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 81170#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81166#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81167#L759 assume !(0 != activate_threads_~tmp___2~0); 81420#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81421#L360 assume !(1 == ~t4_pc~0); 81510#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 81508#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81342#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81343#L767 assume !(0 != activate_threads_~tmp___3~0); 81425#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81107#L379 assume !(1 == ~t5_pc~0); 81027#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 81026#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81021#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 80874#L775 assume !(0 != activate_threads_~tmp___4~0); 80875#L775-2 assume !(1 == ~M_E~0); 80878#L659-1 assume !(1 == ~T1_E~0); 80954#L664-1 assume !(1 == ~T2_E~0); 80955#L669-1 assume !(1 == ~T3_E~0); 81231#L674-1 assume !(1 == ~T4_E~0); 81232#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81123#L684-1 assume !(1 == ~E_M~0); 81124#L689-1 assume !(1 == ~E_1~0); 81382#L694-1 assume !(1 == ~E_2~0); 81071#L699-1 assume !(1 == ~E_3~0); 81072#L704-1 assume !(1 == ~E_4~0); 80855#L709-1 assume !(1 == ~E_5~0); 80856#L920-1 [2021-10-11 00:29:32,257 INFO L796 eck$LassoCheckResult]: Loop: 80856#L920-1 assume !false; 86311#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 86310#L566 assume !false; 86309#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86301#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86277#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86273#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 86268#L491 assume !(0 != eval_~tmp~0); 86269#L581 start_simulation_~kernel_st~0 := 2; 86818#L399-1 start_simulation_~kernel_st~0 := 3; 86816#L591-2 assume !(0 == ~M_E~0); 86813#L591-4 assume !(0 == ~T1_E~0); 86811#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86809#L601-3 assume !(0 == ~T3_E~0); 86807#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86805#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86804#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86800#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86798#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86796#L631-3 assume !(0 == ~E_3~0); 86794#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86791#L641-3 assume !(0 == ~E_5~0); 86789#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86787#L284-21 assume !(1 == ~m_pc~0); 86786#L284-23 is_master_triggered_~__retres1~0 := 0; 86785#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86784#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 86782#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86781#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86778#L303-21 assume !(1 == ~t1_pc~0); 86776#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 86774#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86772#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 86770#L743-21 assume !(0 != activate_threads_~tmp___0~0); 86766#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80952#L322-21 assume !(1 == ~t2_pc~0); 80953#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 86868#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86866#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 86864#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 81185#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81186#L341-21 assume !(1 == ~t3_pc~0); 86583#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 86581#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86579#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 86576#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86575#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86573#L360-21 assume !(1 == ~t4_pc~0); 82020#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 86569#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86570#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 86574#L767-21 assume !(0 != activate_threads_~tmp___3~0); 86572#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86571#L379-21 assume 1 == ~t5_pc~0; 86567#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 86564#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86562#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 86560#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 86558#L775-23 assume !(1 == ~M_E~0); 82868#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86555#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86547#L669-3 assume !(1 == ~T3_E~0); 86542#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86539#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81111#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81112#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81178#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81053#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81054#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81414#L709-3 assume !(1 == ~E_5~0); 81730#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81686#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81670#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81662#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 81659#L939 assume !(0 == start_simulation_~tmp~3); 81660#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86391#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86385#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86370#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 86367#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86366#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 86365#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 86353#L952 assume !(0 != start_simulation_~tmp___0~1); 80856#L920-1 [2021-10-11 00:29:32,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:32,258 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-10-11 00:29:32,258 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:32,258 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656522455] [2021-10-11 00:29:32,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:32,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:32,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:32,298 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656522455] [2021-10-11 00:29:32,298 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:32,298 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-11 00:29:32,299 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299032939] [2021-10-11 00:29:32,299 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:32,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:32,299 INFO L82 PathProgramCache]: Analyzing trace with hash 480788307, now seen corresponding path program 1 times [2021-10-11 00:29:32,300 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:32,300 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443605213] [2021-10-11 00:29:32,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:32,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:32,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:32,328 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443605213] [2021-10-11 00:29:32,328 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:32,328 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:32,328 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299144323] [2021-10-11 00:29:32,329 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:32,329 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:32,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:32,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:32,330 INFO L87 Difference]: Start difference. First operand 6055 states and 8760 transitions. cyclomatic complexity: 2707 Second operand 3 states. [2021-10-11 00:29:32,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:32,427 INFO L93 Difference]: Finished difference Result 6055 states and 8710 transitions. [2021-10-11 00:29:32,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:32,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6055 states and 8710 transitions. [2021-10-11 00:29:32,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2021-10-11 00:29:32,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6055 states to 6055 states and 8710 transitions. [2021-10-11 00:29:32,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6055 [2021-10-11 00:29:32,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6055 [2021-10-11 00:29:32,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6055 states and 8710 transitions. [2021-10-11 00:29:32,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:32,484 INFO L692 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2021-10-11 00:29:32,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6055 states and 8710 transitions. [2021-10-11 00:29:32,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6055 to 6055. [2021-10-11 00:29:32,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6055 states. [2021-10-11 00:29:32,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8710 transitions. [2021-10-11 00:29:32,568 INFO L715 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2021-10-11 00:29:32,568 INFO L595 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2021-10-11 00:29:32,568 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-11 00:29:32,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8710 transitions. [2021-10-11 00:29:32,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2021-10-11 00:29:32,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:32,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:32,592 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:32,592 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:32,593 INFO L794 eck$LassoCheckResult]: Stem: 93482#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 93357#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 93335#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 93321#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 93322#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93067#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93068#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93308#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93309#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93216#L431-1 assume !(0 == ~M_E~0); 93217#L591-1 assume !(0 == ~T1_E~0); 93220#L596-1 assume !(0 == ~T2_E~0); 93221#L601-1 assume !(0 == ~T3_E~0); 93288#L606-1 assume !(0 == ~T4_E~0); 93170#L611-1 assume !(0 == ~T5_E~0); 93171#L616-1 assume !(0 == ~E_M~0); 92979#L621-1 assume !(0 == ~E_1~0); 92980#L626-1 assume !(0 == ~E_2~0); 93075#L631-1 assume !(0 == ~E_3~0); 93076#L636-1 assume !(0 == ~E_4~0); 93329#L641-1 assume !(0 == ~E_5~0); 93330#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93426#L284 assume !(1 == ~m_pc~0); 93411#L284-2 is_master_triggered_~__retres1~0 := 0; 93412#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93355#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 93356#L735 assume !(0 != activate_threads_~tmp~1); 93544#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93091#L303 assume !(1 == ~t1_pc~0); 93092#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 93150#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93161#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 93181#L743 assume !(0 != activate_threads_~tmp___0~0); 93182#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93184#L322 assume !(1 == ~t2_pc~0); 93314#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 93313#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93018#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 93019#L751 assume !(0 != activate_threads_~tmp___1~0); 93323#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93324#L341 assume !(1 == ~t3_pc~0); 93276#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 93277#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93273#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 93274#L759 assume !(0 != activate_threads_~tmp___2~0); 93492#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93493#L360 assume !(1 == ~t4_pc~0); 93566#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 93565#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93435#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 93436#L767 assume !(0 != activate_threads_~tmp___3~0); 93495#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 93214#L379 assume !(1 == ~t5_pc~0); 93146#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 93145#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93140#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 92993#L775 assume !(0 != activate_threads_~tmp___4~0); 92994#L775-2 assume !(1 == ~M_E~0); 92995#L659-1 assume !(1 == ~T1_E~0); 93073#L664-1 assume !(1 == ~T2_E~0); 93074#L669-1 assume !(1 == ~T3_E~0); 93327#L674-1 assume !(1 == ~T4_E~0); 93328#L679-1 assume !(1 == ~T5_E~0); 93230#L684-1 assume !(1 == ~E_M~0); 93231#L689-1 assume !(1 == ~E_1~0); 93469#L694-1 assume !(1 == ~E_2~0); 93185#L699-1 assume !(1 == ~E_3~0); 93186#L704-1 assume !(1 == ~E_4~0); 92974#L709-1 assume !(1 == ~E_5~0); 92975#L920-1 [2021-10-11 00:29:32,593 INFO L796 eck$LassoCheckResult]: Loop: 92975#L920-1 assume !false; 93494#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 92983#L566 assume !false; 92984#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 93054#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 93055#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 93052#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 93053#L491 assume !(0 != eval_~tmp~0); 93530#L581 start_simulation_~kernel_st~0 := 2; 93310#L399-1 start_simulation_~kernel_st~0 := 3; 93311#L591-2 assume !(0 == ~M_E~0); 93570#L591-4 assume !(0 == ~T1_E~0); 93226#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93227#L601-3 assume !(0 == ~T3_E~0); 93289#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93175#L611-3 assume !(0 == ~T5_E~0); 93176#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92988#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92989#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93040#L631-3 assume !(0 == ~E_3~0); 93041#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 93318#L641-3 assume !(0 == ~E_5~0); 93319#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93385#L284-21 assume !(1 == ~m_pc~0); 93383#L284-23 is_master_triggered_~__retres1~0 := 0; 93384#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93366#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 93367#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 93400#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93401#L303-21 assume 1 == ~t1_pc~0; 93498#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 93499#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99024#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 99023#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 93537#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93071#L322-21 assume !(1 == ~t2_pc~0); 93072#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 93077#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93008#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 93009#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 93305#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98361#L341-21 assume !(1 == ~t3_pc~0); 98355#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 98350#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98345#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 98337#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 98332#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98322#L360-21 assume !(1 == ~t4_pc~0); 98266#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 98314#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98312#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 98310#L767-21 assume !(0 != activate_threads_~tmp___3~0); 98308#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98306#L379-21 assume !(1 == ~t5_pc~0); 98303#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 98300#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98298#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 98296#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 98294#L775-23 assume !(1 == ~M_E~0); 98290#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98289#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98287#L669-3 assume !(1 == ~T3_E~0); 98285#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98283#L679-3 assume !(1 == ~T5_E~0); 98281#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98279#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98276#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98274#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98273#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98268#L709-3 assume !(1 == ~E_5~0); 93388#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 93061#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 93062#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 93057#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 93058#L939 assume !(0 == start_simulation_~tmp~3); 93294#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 93064#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 93065#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 93059#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 93060#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 93334#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 93405#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 93187#L952 assume !(0 != start_simulation_~tmp___0~1); 92975#L920-1 [2021-10-11 00:29:32,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:32,594 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-10-11 00:29:32,595 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:32,595 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207903267] [2021-10-11 00:29:32,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:32,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:32,612 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:32,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:32,624 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:32,673 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:32,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:32,673 INFO L82 PathProgramCache]: Analyzing trace with hash 938214801, now seen corresponding path program 1 times [2021-10-11 00:29:32,674 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:32,674 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023248570] [2021-10-11 00:29:32,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:32,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:32,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:32,712 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023248570] [2021-10-11 00:29:32,712 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:32,713 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-11 00:29:32,713 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187580142] [2021-10-11 00:29:32,713 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:32,713 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:32,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-11 00:29:32,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-11 00:29:32,715 INFO L87 Difference]: Start difference. First operand 6055 states and 8710 transitions. cyclomatic complexity: 2657 Second operand 5 states. [2021-10-11 00:29:32,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:32,923 INFO L93 Difference]: Finished difference Result 10811 states and 15338 transitions. [2021-10-11 00:29:32,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-11 00:29:32,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10811 states and 15338 transitions. [2021-10-11 00:29:32,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10720 [2021-10-11 00:29:33,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10811 states to 10811 states and 15338 transitions. [2021-10-11 00:29:33,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10811 [2021-10-11 00:29:33,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10811 [2021-10-11 00:29:33,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10811 states and 15338 transitions. [2021-10-11 00:29:33,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:33,049 INFO L692 BuchiCegarLoop]: Abstraction has 10811 states and 15338 transitions. [2021-10-11 00:29:33,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10811 states and 15338 transitions. [2021-10-11 00:29:33,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10811 to 6103. [2021-10-11 00:29:33,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6103 states. [2021-10-11 00:29:33,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6103 states to 6103 states and 8758 transitions. [2021-10-11 00:29:33,164 INFO L715 BuchiCegarLoop]: Abstraction has 6103 states and 8758 transitions. [2021-10-11 00:29:33,164 INFO L595 BuchiCegarLoop]: Abstraction has 6103 states and 8758 transitions. [2021-10-11 00:29:33,164 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-11 00:29:33,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6103 states and 8758 transitions. [2021-10-11 00:29:33,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6020 [2021-10-11 00:29:33,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:33,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:33,193 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:33,193 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:33,193 INFO L794 eck$LassoCheckResult]: Stem: 110377#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 110252#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 110230#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 110217#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 110218#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109944#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109945#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110198#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110199#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110100#L431-1 assume !(0 == ~M_E~0); 110101#L591-1 assume !(0 == ~T1_E~0); 110105#L596-1 assume !(0 == ~T2_E~0); 110106#L601-1 assume !(0 == ~T3_E~0); 110174#L606-1 assume !(0 == ~T4_E~0); 110049#L611-1 assume !(0 == ~T5_E~0); 110050#L616-1 assume !(0 == ~E_M~0); 109861#L621-1 assume !(0 == ~E_1~0); 109862#L626-1 assume !(0 == ~E_2~0); 109955#L631-1 assume !(0 == ~E_3~0); 109956#L636-1 assume !(0 == ~E_4~0); 110224#L641-1 assume !(0 == ~E_5~0); 110225#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 110323#L284 assume !(1 == ~m_pc~0); 110307#L284-2 is_master_triggered_~__retres1~0 := 0; 110308#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110250#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 110251#L735 assume !(0 != activate_threads_~tmp~1); 110443#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 109967#L303 assume !(1 == ~t1_pc~0); 109968#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 110027#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 110038#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 110061#L743 assume !(0 != activate_threads_~tmp___0~0); 110062#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110066#L322 assume !(1 == ~t2_pc~0); 110206#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 110205#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109900#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 109901#L751 assume !(0 != activate_threads_~tmp___1~0); 110219#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 110220#L341 assume !(1 == ~t3_pc~0); 110163#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 110164#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 110160#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 110161#L759 assume !(0 != activate_threads_~tmp___2~0); 110391#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110392#L360 assume !(1 == ~t4_pc~0); 110469#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 110467#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 110330#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 110331#L767 assume !(0 != activate_threads_~tmp___3~0); 110395#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110099#L379 assume !(1 == ~t5_pc~0); 110021#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 110020#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110016#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 109873#L775 assume !(0 != activate_threads_~tmp___4~0); 109874#L775-2 assume !(1 == ~M_E~0); 109877#L659-1 assume !(1 == ~T1_E~0); 109953#L664-1 assume !(1 == ~T2_E~0); 109954#L669-1 assume !(1 == ~T3_E~0); 110222#L674-1 assume !(1 == ~T4_E~0); 110223#L679-1 assume !(1 == ~T5_E~0); 110117#L684-1 assume !(1 == ~E_M~0); 110118#L689-1 assume !(1 == ~E_1~0); 110365#L694-1 assume !(1 == ~E_2~0); 110067#L699-1 assume !(1 == ~E_3~0); 110068#L704-1 assume !(1 == ~E_4~0); 109854#L709-1 assume !(1 == ~E_5~0); 109855#L920-1 [2021-10-11 00:29:33,194 INFO L796 eck$LassoCheckResult]: Loop: 109855#L920-1 assume !false; 115187#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 113529#L566 assume !false; 113127#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 113091#L444 assume !(0 == ~m_st~0); 113092#L448 assume !(0 == ~t1_st~0); 113095#L452 assume !(0 == ~t2_st~0); 113097#L456 assume !(0 == ~t3_st~0); 113093#L460 assume !(0 == ~t4_st~0); 113094#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 113096#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 111234#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 111235#L491 assume !(0 != eval_~tmp~0); 113079#L581 start_simulation_~kernel_st~0 := 2; 113077#L399-1 start_simulation_~kernel_st~0 := 3; 113074#L591-2 assume !(0 == ~M_E~0); 113075#L591-4 assume !(0 == ~T1_E~0); 113069#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 113070#L601-3 assume !(0 == ~T3_E~0); 113063#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 113064#L611-3 assume !(0 == ~T5_E~0); 113057#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 113058#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 113051#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 113052#L631-3 assume !(0 == ~E_3~0); 113044#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 113045#L641-3 assume !(0 == ~E_5~0); 113038#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 113039#L284-21 assume !(1 == ~m_pc~0); 110712#L284-23 is_master_triggered_~__retres1~0 := 0; 110713#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110702#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 110703#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 110696#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 110697#L303-21 assume 1 == ~t1_pc~0; 115013#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 110669#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 110670#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 110648#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 110649#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110632#L322-21 assume !(1 == ~t2_pc~0); 110626#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 110627#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110619#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 110614#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 110615#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 115775#L341-21 assume !(1 == ~t3_pc~0); 110603#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 110604#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 110596#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 110597#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 110591#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110592#L360-21 assume !(1 == ~t4_pc~0); 110445#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 110446#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 110318#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 110319#L767-21 assume !(0 != activate_threads_~tmp___3~0); 110451#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110063#L379-21 assume !(1 == ~t5_pc~0); 110065#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 110090#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110002#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 110003#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 110081#L775-23 assume !(1 == ~M_E~0); 110286#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109957#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109958#L669-3 assume !(1 == ~T3_E~0); 110227#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110228#L679-3 assume !(1 == ~T5_E~0); 110103#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 110104#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 115646#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 110047#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110048#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109859#L709-3 assume !(1 == ~E_5~0); 109860#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 115644#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 115443#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 115378#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 110183#L939 assume !(0 == start_simulation_~tmp~3); 110184#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 115470#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 115465#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 115461#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 115459#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 115457#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 115455#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 115452#L952 assume !(0 != start_simulation_~tmp___0~1); 109855#L920-1 [2021-10-11 00:29:33,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:33,194 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-10-11 00:29:33,197 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:33,197 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129867487] [2021-10-11 00:29:33,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:33,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:33,210 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:33,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:33,230 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:33,268 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:33,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:33,269 INFO L82 PathProgramCache]: Analyzing trace with hash 260430250, now seen corresponding path program 1 times [2021-10-11 00:29:33,269 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:33,269 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083569996] [2021-10-11 00:29:33,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:33,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:33,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:33,346 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083569996] [2021-10-11 00:29:33,347 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:33,347 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-11 00:29:33,347 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058159066] [2021-10-11 00:29:33,347 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:33,348 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:33,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-11 00:29:33,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-11 00:29:33,348 INFO L87 Difference]: Start difference. First operand 6103 states and 8758 transitions. cyclomatic complexity: 2657 Second operand 5 states. [2021-10-11 00:29:33,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:33,677 INFO L93 Difference]: Finished difference Result 12099 states and 17253 transitions. [2021-10-11 00:29:33,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-11 00:29:33,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12099 states and 17253 transitions. [2021-10-11 00:29:33,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12016 [2021-10-11 00:29:33,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12099 states to 12099 states and 17253 transitions. [2021-10-11 00:29:33,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12099 [2021-10-11 00:29:33,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12099 [2021-10-11 00:29:33,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12099 states and 17253 transitions. [2021-10-11 00:29:33,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:33,792 INFO L692 BuchiCegarLoop]: Abstraction has 12099 states and 17253 transitions. [2021-10-11 00:29:33,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12099 states and 17253 transitions. [2021-10-11 00:29:33,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12099 to 6259. [2021-10-11 00:29:33,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6259 states. [2021-10-11 00:29:33,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6259 states to 6259 states and 8869 transitions. [2021-10-11 00:29:33,902 INFO L715 BuchiCegarLoop]: Abstraction has 6259 states and 8869 transitions. [2021-10-11 00:29:33,902 INFO L595 BuchiCegarLoop]: Abstraction has 6259 states and 8869 transitions. [2021-10-11 00:29:33,902 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-11 00:29:33,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6259 states and 8869 transitions. [2021-10-11 00:29:33,924 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6176 [2021-10-11 00:29:33,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:33,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:33,926 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:33,926 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:33,927 INFO L794 eck$LassoCheckResult]: Stem: 128640#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 128484#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 128462#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 128449#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 128450#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128161#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128162#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128431#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128432#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 128330#L431-1 assume !(0 == ~M_E~0); 128331#L591-1 assume !(0 == ~T1_E~0); 128335#L596-1 assume !(0 == ~T2_E~0); 128336#L601-1 assume !(0 == ~T3_E~0); 128403#L606-1 assume !(0 == ~T4_E~0); 128266#L611-1 assume !(0 == ~T5_E~0); 128267#L616-1 assume !(0 == ~E_M~0); 128076#L621-1 assume !(0 == ~E_1~0); 128077#L626-1 assume !(0 == ~E_2~0); 128172#L631-1 assume !(0 == ~E_3~0); 128173#L636-1 assume !(0 == ~E_4~0); 128456#L641-1 assume !(0 == ~E_5~0); 128457#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128562#L284 assume !(1 == ~m_pc~0); 128542#L284-2 is_master_triggered_~__retres1~0 := 0; 128543#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 128482#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 128483#L735 assume !(0 != activate_threads_~tmp~1); 128723#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128182#L303 assume !(1 == ~t1_pc~0); 128183#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 128245#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 128255#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 128278#L743 assume !(0 != activate_threads_~tmp___0~0); 128279#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128283#L322 assume !(1 == ~t2_pc~0); 128439#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 128438#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 128115#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 128116#L751 assume !(0 != activate_threads_~tmp___1~0); 128451#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128452#L341 assume !(1 == ~t3_pc~0); 128393#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 128394#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128390#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 128391#L759 assume !(0 != activate_threads_~tmp___2~0); 128652#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 128653#L360 assume !(1 == ~t4_pc~0); 128758#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 128756#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128571#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 128572#L767 assume !(0 != activate_threads_~tmp___3~0); 128656#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128327#L379 assume !(1 == ~t5_pc~0); 128239#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 128238#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128234#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 128088#L775 assume !(0 != activate_threads_~tmp___4~0); 128089#L775-2 assume !(1 == ~M_E~0); 128092#L659-1 assume !(1 == ~T1_E~0); 128170#L664-1 assume !(1 == ~T2_E~0); 128171#L669-1 assume !(1 == ~T3_E~0); 128454#L674-1 assume !(1 == ~T4_E~0); 128455#L679-1 assume !(1 == ~T5_E~0); 128347#L684-1 assume !(1 == ~E_M~0); 128348#L689-1 assume !(1 == ~E_1~0); 128625#L694-1 assume !(1 == ~E_2~0); 128284#L699-1 assume !(1 == ~E_3~0); 128285#L704-1 assume !(1 == ~E_4~0); 128069#L709-1 assume !(1 == ~E_5~0); 128070#L920-1 [2021-10-11 00:29:33,927 INFO L796 eck$LassoCheckResult]: Loop: 128070#L920-1 assume !false; 131386#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 131385#L566 assume !false; 131384#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 131377#L444 assume !(0 == ~m_st~0); 131378#L448 assume !(0 == ~t1_st~0); 131381#L452 assume !(0 == ~t2_st~0); 131383#L456 assume !(0 == ~t3_st~0); 131379#L460 assume !(0 == ~t4_st~0); 131380#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 131382#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 130576#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 130577#L491 assume !(0 != eval_~tmp~0); 132408#L581 start_simulation_~kernel_st~0 := 2; 132404#L399-1 start_simulation_~kernel_st~0 := 3; 132405#L591-2 assume !(0 == ~M_E~0); 132400#L591-4 assume !(0 == ~T1_E~0); 132401#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132396#L601-3 assume !(0 == ~T3_E~0); 132397#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132392#L611-3 assume !(0 == ~T5_E~0); 132393#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 132388#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132389#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132384#L631-3 assume !(0 == ~E_3~0); 132385#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132376#L641-3 assume !(0 == ~E_5~0); 132377#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128511#L284-21 assume !(1 == ~m_pc~0); 128512#L284-23 is_master_triggered_~__retres1~0 := 0; 131523#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 131524#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 131515#L735-21 assume !(0 != activate_threads_~tmp~1); 131516#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 131503#L303-21 assume !(1 == ~t1_pc~0); 131504#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 131489#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 131490#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 131477#L743-21 assume !(0 != activate_threads_~tmp___0~0); 131476#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 131470#L322-21 assume !(1 == ~t2_pc~0); 130482#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 131463#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 131464#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 131455#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 131456#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 131444#L341-21 assume !(1 == ~t3_pc~0); 131446#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 131435#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 131436#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 131427#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 131428#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130877#L360-21 assume !(1 == ~t4_pc~0); 130876#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 130875#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 130874#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 130873#L767-21 assume !(0 != activate_threads_~tmp___3~0); 130872#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 130871#L379-21 assume 1 == ~t5_pc~0; 130869#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 130868#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 130867#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 130866#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 130865#L775-23 assume !(1 == ~M_E~0); 130769#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130864#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 130863#L669-3 assume !(1 == ~T3_E~0); 130862#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130861#L679-3 assume !(1 == ~T5_E~0); 130860#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 130859#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 130858#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 130857#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 130856#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 130855#L709-3 assume !(1 == ~E_5~0); 130854#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 130852#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 130847#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 130846#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 130844#L939 assume !(0 == start_simulation_~tmp~3); 130845#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 131408#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 131403#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 131400#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 131398#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 131396#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 131394#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 131391#L952 assume !(0 != start_simulation_~tmp___0~1); 128070#L920-1 [2021-10-11 00:29:33,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:33,928 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-10-11 00:29:33,928 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:33,928 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531834916] [2021-10-11 00:29:33,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:33,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:33,945 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:33,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:33,957 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:33,979 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:33,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:33,979 INFO L82 PathProgramCache]: Analyzing trace with hash -20029786, now seen corresponding path program 1 times [2021-10-11 00:29:33,980 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:33,980 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978210365] [2021-10-11 00:29:33,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:33,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:34,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:34,022 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978210365] [2021-10-11 00:29:34,022 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:34,022 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:34,022 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436338642] [2021-10-11 00:29:34,023 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:34,023 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:34,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:34,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:34,024 INFO L87 Difference]: Start difference. First operand 6259 states and 8869 transitions. cyclomatic complexity: 2612 Second operand 3 states. [2021-10-11 00:29:34,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:34,132 INFO L93 Difference]: Finished difference Result 11358 states and 15982 transitions. [2021-10-11 00:29:34,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:34,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11358 states and 15982 transitions. [2021-10-11 00:29:34,187 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11252 [2021-10-11 00:29:34,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11358 states to 11358 states and 15982 transitions. [2021-10-11 00:29:34,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11358 [2021-10-11 00:29:34,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11358 [2021-10-11 00:29:34,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11358 states and 15982 transitions. [2021-10-11 00:29:34,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:34,246 INFO L692 BuchiCegarLoop]: Abstraction has 11358 states and 15982 transitions. [2021-10-11 00:29:34,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11358 states and 15982 transitions. [2021-10-11 00:29:34,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11358 to 11350. [2021-10-11 00:29:34,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11350 states. [2021-10-11 00:29:34,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11350 states to 11350 states and 15974 transitions. [2021-10-11 00:29:34,418 INFO L715 BuchiCegarLoop]: Abstraction has 11350 states and 15974 transitions. [2021-10-11 00:29:34,418 INFO L595 BuchiCegarLoop]: Abstraction has 11350 states and 15974 transitions. [2021-10-11 00:29:34,418 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-11 00:29:34,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11350 states and 15974 transitions. [2021-10-11 00:29:34,463 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11244 [2021-10-11 00:29:34,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:34,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:34,467 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:34,467 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:34,468 INFO L794 eck$LassoCheckResult]: Stem: 146236#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 146103#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 146081#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 146068#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 146069#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145784#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145785#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 146047#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 146048#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145950#L431-1 assume !(0 == ~M_E~0); 145951#L591-1 assume !(0 == ~T1_E~0); 145955#L596-1 assume !(0 == ~T2_E~0); 145956#L601-1 assume !(0 == ~T3_E~0); 146024#L606-1 assume !(0 == ~T4_E~0); 145884#L611-1 assume !(0 == ~T5_E~0); 145885#L616-1 assume !(0 == ~E_M~0); 145699#L621-1 assume !(0 == ~E_1~0); 145700#L626-1 assume !(0 == ~E_2~0); 145795#L631-1 assume !(0 == ~E_3~0); 145796#L636-1 assume !(0 == ~E_4~0); 146075#L641-1 assume !(0 == ~E_5~0); 146076#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 146179#L284 assume !(1 == ~m_pc~0); 146162#L284-2 is_master_triggered_~__retres1~0 := 0; 146163#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 146101#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 146102#L735 assume !(0 != activate_threads_~tmp~1); 146298#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 145809#L303 assume !(1 == ~t1_pc~0); 145810#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 145864#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 146326#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 145898#L743 assume !(0 != activate_threads_~tmp___0~0); 145899#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 145903#L322 assume !(1 == ~t2_pc~0); 146055#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 146054#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145738#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 145739#L751 assume !(0 != activate_threads_~tmp___1~0); 146070#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 146071#L341 assume !(1 == ~t3_pc~0); 146014#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 146015#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 146011#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 146012#L759 assume !(0 != activate_threads_~tmp___2~0); 146247#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 146248#L360 assume !(1 == ~t4_pc~0); 146319#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 146317#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 146187#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 146188#L767 assume !(0 != activate_threads_~tmp___3~0); 146250#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 145949#L379 assume !(1 == ~t5_pc~0); 145858#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 145931#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156331#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 156330#L775 assume !(0 != activate_threads_~tmp___4~0); 156329#L775-2 assume !(1 == ~M_E~0); 156328#L659-1 assume !(1 == ~T1_E~0); 156327#L664-1 assume !(1 == ~T2_E~0); 156326#L669-1 assume !(1 == ~T3_E~0); 156325#L674-1 assume !(1 == ~T4_E~0); 156324#L679-1 assume !(1 == ~T5_E~0); 156323#L684-1 assume !(1 == ~E_M~0); 156322#L689-1 assume !(1 == ~E_1~0); 156321#L694-1 assume !(1 == ~E_2~0); 156320#L699-1 assume !(1 == ~E_3~0); 156319#L704-1 assume !(1 == ~E_4~0); 156318#L709-1 assume !(1 == ~E_5~0); 145693#L920-1 [2021-10-11 00:29:34,468 INFO L796 eck$LassoCheckResult]: Loop: 145693#L920-1 assume !false; 156124#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 156123#L566 assume !false; 146064#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 146065#L444 assume !(0 == ~m_st~0); 155811#L448 assume !(0 == ~t1_st~0); 155814#L452 assume !(0 == ~t2_st~0); 155816#L456 assume !(0 == ~t3_st~0); 155812#L460 assume !(0 == ~t4_st~0); 155813#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 155815#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 157031#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 157030#L491 assume !(0 != eval_~tmp~0); 157029#L581 start_simulation_~kernel_st~0 := 2; 156995#L399-1 start_simulation_~kernel_st~0 := 3; 156994#L591-2 assume !(0 == ~M_E~0); 156993#L591-4 assume !(0 == ~T1_E~0); 156992#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 156991#L601-3 assume !(0 == ~T3_E~0); 156990#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 156989#L611-3 assume !(0 == ~T5_E~0); 156988#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 156987#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 156986#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 156985#L631-3 assume !(0 == ~E_3~0); 156984#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 156982#L641-3 assume !(0 == ~E_5~0); 156980#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156978#L284-21 assume !(1 == ~m_pc~0); 156976#L284-23 is_master_triggered_~__retres1~0 := 0; 156974#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156972#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 146186#L735-21 assume !(0 != activate_threads_~tmp~1); 146148#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 146149#L303-21 assume !(1 == ~t1_pc~0); 146255#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 146281#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 146251#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 146252#L743-21 assume !(0 != activate_threads_~tmp___0~0); 146294#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 145791#L322-21 assume !(1 == ~t2_pc~0); 145792#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 145797#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145728#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 145729#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 146029#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 146030#L341-21 assume !(1 == ~t3_pc~0); 146007#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 146006#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 146003#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 146004#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 146232#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 146233#L360-21 assume !(1 == ~t4_pc~0); 156566#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 156563#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156561#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 156559#L767-21 assume !(0 != activate_threads_~tmp___3~0); 156558#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156557#L379-21 assume !(1 == ~t5_pc~0); 156554#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 156552#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156550#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 156548#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 156547#L775-23 assume !(1 == ~M_E~0); 153924#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 156545#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 156543#L669-3 assume !(1 == ~T3_E~0); 156541#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156539#L679-3 assume !(1 == ~T5_E~0); 156537#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 156535#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 156533#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 156531#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 156529#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 156526#L709-3 assume !(1 == ~E_5~0); 156524#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 145779#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 145780#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 145777#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 145778#L939 assume !(0 == start_simulation_~tmp~3); 146034#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 156341#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 156337#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156336#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 156334#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 156333#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 156332#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 156317#L952 assume !(0 != start_simulation_~tmp___0~1); 145693#L920-1 [2021-10-11 00:29:34,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:34,469 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 4 times [2021-10-11 00:29:34,469 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:34,469 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196462794] [2021-10-11 00:29:34,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:34,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:34,483 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:34,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:34,494 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:34,518 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:34,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:34,519 INFO L82 PathProgramCache]: Analyzing trace with hash -77174011, now seen corresponding path program 1 times [2021-10-11 00:29:34,520 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:34,520 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44125162] [2021-10-11 00:29:34,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:34,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:34,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:34,565 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44125162] [2021-10-11 00:29:34,566 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:34,566 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:34,566 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992003999] [2021-10-11 00:29:34,566 INFO L811 eck$LassoCheckResult]: loop already infeasible [2021-10-11 00:29:34,567 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:34,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:34,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:34,567 INFO L87 Difference]: Start difference. First operand 11350 states and 15974 transitions. cyclomatic complexity: 4626 Second operand 3 states. [2021-10-11 00:29:34,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:34,699 INFO L93 Difference]: Finished difference Result 18281 states and 25445 transitions. [2021-10-11 00:29:34,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:34,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18281 states and 25445 transitions. [2021-10-11 00:29:34,803 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18181 [2021-10-11 00:29:34,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18281 states to 18281 states and 25445 transitions. [2021-10-11 00:29:34,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18281 [2021-10-11 00:29:34,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18281 [2021-10-11 00:29:34,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18281 states and 25445 transitions. [2021-10-11 00:29:34,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:34,909 INFO L692 BuchiCegarLoop]: Abstraction has 18281 states and 25445 transitions. [2021-10-11 00:29:34,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18281 states and 25445 transitions. [2021-10-11 00:29:35,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18281 to 17673. [2021-10-11 00:29:35,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17673 states. [2021-10-11 00:29:35,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17673 states to 17673 states and 24637 transitions. [2021-10-11 00:29:35,166 INFO L715 BuchiCegarLoop]: Abstraction has 17673 states and 24637 transitions. [2021-10-11 00:29:35,166 INFO L595 BuchiCegarLoop]: Abstraction has 17673 states and 24637 transitions. [2021-10-11 00:29:35,166 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-11 00:29:35,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17673 states and 24637 transitions. [2021-10-11 00:29:35,239 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17573 [2021-10-11 00:29:35,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:35,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:35,240 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:35,240 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:35,241 INFO L794 eck$LassoCheckResult]: Stem: 175884#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 175749#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 175727#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 175714#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 175715#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 175421#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 175422#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 175697#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 175698#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 175595#L431-1 assume !(0 == ~M_E~0); 175596#L591-1 assume !(0 == ~T1_E~0); 175599#L596-1 assume !(0 == ~T2_E~0); 175600#L601-1 assume !(0 == ~T3_E~0); 175669#L606-1 assume !(0 == ~T4_E~0); 175521#L611-1 assume !(0 == ~T5_E~0); 175522#L616-1 assume !(0 == ~E_M~0); 175337#L621-1 assume !(0 == ~E_1~0); 175338#L626-1 assume !(0 == ~E_2~0); 175429#L631-1 assume !(0 == ~E_3~0); 175430#L636-1 assume !(0 == ~E_4~0); 175721#L641-1 assume !(0 == ~E_5~0); 175722#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 175825#L284 assume !(1 == ~m_pc~0); 175808#L284-2 is_master_triggered_~__retres1~0 := 0; 175809#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 175747#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 175748#L735 assume !(0 != activate_threads_~tmp~1); 175968#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 175443#L303 assume !(1 == ~t1_pc~0); 175444#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 175499#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 175509#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 175533#L743 assume !(0 != activate_threads_~tmp___0~0); 175534#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 175537#L322 assume !(1 == ~t2_pc~0); 175703#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 175702#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 175377#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 175378#L751 assume !(0 != activate_threads_~tmp___1~0); 175716#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 175717#L341 assume !(1 == ~t3_pc~0); 175658#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 175659#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 175655#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 175656#L759 assume !(0 != activate_threads_~tmp___2~0); 175899#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 175900#L360 assume !(1 == ~t4_pc~0); 175996#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 175994#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 175836#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 175837#L767 assume !(0 != activate_threads_~tmp___3~0); 175902#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 175592#L379 assume !(1 == ~t5_pc~0); 175495#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 175571#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 175489#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 175351#L775 assume !(0 != activate_threads_~tmp___4~0); 175352#L775-2 assume !(1 == ~M_E~0); 180418#L659-1 assume !(1 == ~T1_E~0); 180414#L664-1 assume !(1 == ~T2_E~0); 180412#L669-1 assume !(1 == ~T3_E~0); 180410#L674-1 assume !(1 == ~T4_E~0); 180408#L679-1 assume !(1 == ~T5_E~0); 180405#L684-1 assume !(1 == ~E_M~0); 180403#L689-1 assume !(1 == ~E_1~0); 180401#L694-1 assume !(1 == ~E_2~0); 180400#L699-1 assume !(1 == ~E_3~0); 180398#L704-1 assume !(1 == ~E_4~0); 180396#L709-1 assume !(1 == ~E_5~0); 175332#L920-1 assume !false; 180355#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 180353#L566 [2021-10-11 00:29:35,241 INFO L796 eck$LassoCheckResult]: Loop: 180353#L566 assume !false; 180349#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 180346#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 180345#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 180344#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 180343#L491 assume 0 != eval_~tmp~0; 180342#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 180341#L499 assume !(0 != eval_~tmp_ndt_1~0); 180255#L496 assume !(0 == ~t1_st~0); 180253#L510 assume !(0 == ~t2_st~0); 180249#L524 assume !(0 == ~t3_st~0); 180244#L538 assume !(0 == ~t4_st~0); 180242#L552 assume !(0 == ~t5_st~0); 180353#L566 [2021-10-11 00:29:35,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:35,242 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-10-11 00:29:35,242 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:35,242 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355931292] [2021-10-11 00:29:35,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:35,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:35,255 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:35,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:35,268 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:35,296 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:35,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:35,297 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 1 times [2021-10-11 00:29:35,297 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:35,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457433278] [2021-10-11 00:29:35,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:35,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:35,302 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:35,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:35,304 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:35,307 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:35,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:35,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1743073375, now seen corresponding path program 1 times [2021-10-11 00:29:35,308 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:35,308 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743754069] [2021-10-11 00:29:35,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:35,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:35,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:35,397 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743754069] [2021-10-11 00:29:35,398 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:35,398 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:35,398 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473077175] [2021-10-11 00:29:35,485 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:35,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:35,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:35,486 INFO L87 Difference]: Start difference. First operand 17673 states and 24637 transitions. cyclomatic complexity: 6967 Second operand 3 states. [2021-10-11 00:29:35,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:35,692 INFO L93 Difference]: Finished difference Result 32613 states and 45236 transitions. [2021-10-11 00:29:35,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:35,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32613 states and 45236 transitions. [2021-10-11 00:29:35,866 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 32418 [2021-10-11 00:29:36,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32613 states to 32613 states and 45236 transitions. [2021-10-11 00:29:36,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32613 [2021-10-11 00:29:36,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32613 [2021-10-11 00:29:36,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32613 states and 45236 transitions. [2021-10-11 00:29:36,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:36,074 INFO L692 BuchiCegarLoop]: Abstraction has 32613 states and 45236 transitions. [2021-10-11 00:29:36,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32613 states and 45236 transitions. [2021-10-11 00:29:36,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32613 to 30933. [2021-10-11 00:29:36,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30933 states. [2021-10-11 00:29:36,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30933 states to 30933 states and 43024 transitions. [2021-10-11 00:29:36,465 INFO L715 BuchiCegarLoop]: Abstraction has 30933 states and 43024 transitions. [2021-10-11 00:29:36,465 INFO L595 BuchiCegarLoop]: Abstraction has 30933 states and 43024 transitions. [2021-10-11 00:29:36,465 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-11 00:29:36,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30933 states and 43024 transitions. [2021-10-11 00:29:36,562 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-10-11 00:29:36,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:36,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:36,563 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:36,564 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:36,564 INFO L794 eck$LassoCheckResult]: Stem: 226183#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 226041#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 226019#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 226006#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 226007#L406-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 225715#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 225716#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 225991#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 225992#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 225885#L431-1 assume !(0 == ~M_E~0); 225886#L591-1 assume !(0 == ~T1_E~0); 225889#L596-1 assume !(0 == ~T2_E~0); 225890#L601-1 assume !(0 == ~T3_E~0); 225959#L606-1 assume !(0 == ~T4_E~0); 225817#L611-1 assume !(0 == ~T5_E~0); 225818#L616-1 assume !(0 == ~E_M~0); 225630#L621-1 assume !(0 == ~E_1~0); 225631#L626-1 assume !(0 == ~E_2~0); 225723#L631-1 assume !(0 == ~E_3~0); 225724#L636-1 assume !(0 == ~E_4~0); 226013#L641-1 assume !(0 == ~E_5~0); 226014#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 226119#L284 assume !(1 == ~m_pc~0); 226102#L284-2 is_master_triggered_~__retres1~0 := 0; 226103#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 226039#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 226040#L735 assume !(0 != activate_threads_~tmp~1); 226279#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 225738#L303 assume !(1 == ~t1_pc~0); 225739#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 225795#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 225806#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 225830#L743 assume !(0 != activate_threads_~tmp___0~0); 225831#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 225833#L322 assume !(1 == ~t2_pc~0); 225997#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 225996#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 225670#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 225671#L751 assume !(0 != activate_threads_~tmp___1~0); 226008#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226009#L341 assume !(1 == ~t3_pc~0); 225947#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 225948#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 225944#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 225945#L759 assume !(0 != activate_threads_~tmp___2~0); 226200#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 226201#L360 assume !(1 == ~t4_pc~0); 226307#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 226305#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 226128#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 226129#L767 assume !(0 != activate_threads_~tmp___3~0); 226205#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 225883#L379 assume !(1 == ~t5_pc~0); 225791#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 225862#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 244894#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 244892#L775 assume !(0 != activate_threads_~tmp___4~0); 244890#L775-2 assume !(1 == ~M_E~0); 244888#L659-1 assume !(1 == ~T1_E~0); 244884#L664-1 assume !(1 == ~T2_E~0); 244882#L669-1 assume !(1 == ~T3_E~0); 244880#L674-1 assume !(1 == ~T4_E~0); 244878#L679-1 assume !(1 == ~T5_E~0); 244874#L684-1 assume !(1 == ~E_M~0); 244872#L689-1 assume !(1 == ~E_1~0); 244869#L694-1 assume !(1 == ~E_2~0); 244868#L699-1 assume !(1 == ~E_3~0); 244865#L704-1 assume !(1 == ~E_4~0); 244863#L709-1 assume !(1 == ~E_5~0); 225626#L920-1 assume !false; 241916#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 241914#L566 [2021-10-11 00:29:36,564 INFO L796 eck$LassoCheckResult]: Loop: 241914#L566 assume !false; 241913#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 241908#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 241906#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 241904#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 241902#L491 assume 0 != eval_~tmp~0; 241899#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 241894#L499 assume !(0 != eval_~tmp_ndt_1~0); 241895#L496 assume !(0 == ~t1_st~0); 241931#L510 assume !(0 == ~t2_st~0); 241928#L524 assume !(0 == ~t3_st~0); 241923#L538 assume !(0 == ~t4_st~0); 241920#L552 assume !(0 == ~t5_st~0); 241914#L566 [2021-10-11 00:29:36,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:36,565 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-10-11 00:29:36,565 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:36,565 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293015846] [2021-10-11 00:29:36,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:36,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:36,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:36,589 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293015846] [2021-10-11 00:29:36,589 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:36,589 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:36,589 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986840487] [2021-10-11 00:29:36,590 INFO L799 eck$LassoCheckResult]: stem already infeasible [2021-10-11 00:29:36,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:36,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 2 times [2021-10-11 00:29:36,590 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:36,591 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372854931] [2021-10-11 00:29:36,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:36,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:36,594 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:36,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:36,596 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:36,598 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:36,682 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:36,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:36,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:36,683 INFO L87 Difference]: Start difference. First operand 30933 states and 43024 transitions. cyclomatic complexity: 12094 Second operand 3 states. [2021-10-11 00:29:36,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:36,813 INFO L93 Difference]: Finished difference Result 30846 states and 42897 transitions. [2021-10-11 00:29:36,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:36,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30846 states and 42897 transitions. [2021-10-11 00:29:37,137 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-10-11 00:29:37,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30846 states to 30846 states and 42897 transitions. [2021-10-11 00:29:37,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30846 [2021-10-11 00:29:37,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30846 [2021-10-11 00:29:37,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30846 states and 42897 transitions. [2021-10-11 00:29:37,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:37,482 INFO L692 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-10-11 00:29:37,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30846 states and 42897 transitions. [2021-10-11 00:29:37,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30846 to 30846. [2021-10-11 00:29:37,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30846 states. [2021-10-11 00:29:38,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30846 states to 30846 states and 42897 transitions. [2021-10-11 00:29:38,070 INFO L715 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-10-11 00:29:38,070 INFO L595 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-10-11 00:29:38,070 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-11 00:29:38,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30846 states and 42897 transitions. [2021-10-11 00:29:38,175 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-10-11 00:29:38,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:38,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:38,178 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:38,178 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:38,178 INFO L794 eck$LassoCheckResult]: Stem: 287964#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 287825#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 287803#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 287790#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 287791#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 287497#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 287498#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 287769#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 287770#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 287667#L431-1 assume !(0 == ~M_E~0); 287668#L591-1 assume !(0 == ~T1_E~0); 287671#L596-1 assume !(0 == ~T2_E~0); 287672#L601-1 assume !(0 == ~T3_E~0); 287741#L606-1 assume !(0 == ~T4_E~0); 287598#L611-1 assume !(0 == ~T5_E~0); 287599#L616-1 assume !(0 == ~E_M~0); 287415#L621-1 assume !(0 == ~E_1~0); 287416#L626-1 assume !(0 == ~E_2~0); 287505#L631-1 assume !(0 == ~E_3~0); 287506#L636-1 assume !(0 == ~E_4~0); 287797#L641-1 assume !(0 == ~E_5~0); 287798#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 287900#L284 assume !(1 == ~m_pc~0); 287881#L284-2 is_master_triggered_~__retres1~0 := 0; 287882#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 287823#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 287824#L735 assume !(0 != activate_threads_~tmp~1); 288055#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 287521#L303 assume !(1 == ~t1_pc~0); 287522#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 287576#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 287586#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 287610#L743 assume !(0 != activate_threads_~tmp___0~0); 287611#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 287614#L322 assume !(1 == ~t2_pc~0); 287775#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 287774#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 287454#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 287455#L751 assume !(0 != activate_threads_~tmp___1~0); 287792#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 287793#L341 assume !(1 == ~t3_pc~0); 287730#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 287731#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 287727#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 287728#L759 assume !(0 != activate_threads_~tmp___2~0); 287981#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 287982#L360 assume !(1 == ~t4_pc~0); 288078#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 288077#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 287910#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 287911#L767 assume !(0 != activate_threads_~tmp___3~0); 287985#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 287664#L379 assume !(1 == ~t5_pc~0); 287572#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 287643#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 302270#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 302269#L775 assume !(0 != activate_threads_~tmp___4~0); 302268#L775-2 assume !(1 == ~M_E~0); 302267#L659-1 assume !(1 == ~T1_E~0); 302266#L664-1 assume !(1 == ~T2_E~0); 302265#L669-1 assume !(1 == ~T3_E~0); 302264#L674-1 assume !(1 == ~T4_E~0); 302263#L679-1 assume !(1 == ~T5_E~0); 302262#L684-1 assume !(1 == ~E_M~0); 302261#L689-1 assume !(1 == ~E_1~0); 302260#L694-1 assume !(1 == ~E_2~0); 302259#L699-1 assume !(1 == ~E_3~0); 302258#L704-1 assume !(1 == ~E_4~0); 302257#L709-1 assume !(1 == ~E_5~0); 287411#L920-1 assume !false; 302240#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 302238#L566 [2021-10-11 00:29:38,178 INFO L796 eck$LassoCheckResult]: Loop: 302238#L566 assume !false; 302235#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 302232#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 302230#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 302228#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 302226#L491 assume 0 != eval_~tmp~0; 302224#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 302222#L499 assume !(0 != eval_~tmp_ndt_1~0); 300107#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 300105#L513 assume !(0 != eval_~tmp_ndt_2~0); 300104#L510 assume !(0 == ~t2_st~0); 300102#L524 assume !(0 == ~t3_st~0); 300098#L538 assume !(0 == ~t4_st~0); 300097#L552 assume !(0 == ~t5_st~0); 302238#L566 [2021-10-11 00:29:38,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:38,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-10-11 00:29:38,179 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:38,179 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156743759] [2021-10-11 00:29:38,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:38,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:38,190 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:38,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:38,200 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:38,371 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:38,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:38,372 INFO L82 PathProgramCache]: Analyzing trace with hash 706455497, now seen corresponding path program 1 times [2021-10-11 00:29:38,372 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:38,372 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628777091] [2021-10-11 00:29:38,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:38,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:38,375 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:38,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:38,377 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:38,380 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:38,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:38,381 INFO L82 PathProgramCache]: Analyzing trace with hash 1606943435, now seen corresponding path program 1 times [2021-10-11 00:29:38,381 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:38,381 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364475764] [2021-10-11 00:29:38,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:38,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:38,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:38,422 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364475764] [2021-10-11 00:29:38,422 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:38,423 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:38,423 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814888236] [2021-10-11 00:29:38,551 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:38,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:38,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:38,552 INFO L87 Difference]: Start difference. First operand 30846 states and 42897 transitions. cyclomatic complexity: 12054 Second operand 3 states. [2021-10-11 00:29:38,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:38,786 INFO L93 Difference]: Finished difference Result 57752 states and 80047 transitions. [2021-10-11 00:29:38,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:38,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57752 states and 80047 transitions. [2021-10-11 00:29:39,234 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 57628 [2021-10-11 00:29:39,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57752 states to 57752 states and 80047 transitions. [2021-10-11 00:29:39,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57752 [2021-10-11 00:29:39,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57752 [2021-10-11 00:29:39,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57752 states and 80047 transitions. [2021-10-11 00:29:39,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:39,475 INFO L692 BuchiCegarLoop]: Abstraction has 57752 states and 80047 transitions. [2021-10-11 00:29:39,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57752 states and 80047 transitions. [2021-10-11 00:29:40,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57752 to 56436. [2021-10-11 00:29:40,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56436 states. [2021-10-11 00:29:40,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56436 states to 56436 states and 78311 transitions. [2021-10-11 00:29:40,362 INFO L715 BuchiCegarLoop]: Abstraction has 56436 states and 78311 transitions. [2021-10-11 00:29:40,362 INFO L595 BuchiCegarLoop]: Abstraction has 56436 states and 78311 transitions. [2021-10-11 00:29:40,362 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-11 00:29:40,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56436 states and 78311 transitions. [2021-10-11 00:29:40,520 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56312 [2021-10-11 00:29:40,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:40,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:40,522 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:40,522 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:40,522 INFO L794 eck$LassoCheckResult]: Stem: 376566#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 376434#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 376412#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 376399#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 376400#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 376104#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 376105#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 376379#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 376380#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 376280#L431-1 assume !(0 == ~M_E~0); 376281#L591-1 assume !(0 == ~T1_E~0); 376285#L596-1 assume !(0 == ~T2_E~0); 376286#L601-1 assume !(0 == ~T3_E~0); 376355#L606-1 assume !(0 == ~T4_E~0); 376206#L611-1 assume !(0 == ~T5_E~0); 376207#L616-1 assume !(0 == ~E_M~0); 376022#L621-1 assume !(0 == ~E_1~0); 376023#L626-1 assume !(0 == ~E_2~0); 376114#L631-1 assume !(0 == ~E_3~0); 376115#L636-1 assume !(0 == ~E_4~0); 376406#L641-1 assume !(0 == ~E_5~0); 376407#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 376508#L284 assume !(1 == ~m_pc~0); 376489#L284-2 is_master_triggered_~__retres1~0 := 0; 376490#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 376432#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 376433#L735 assume !(0 != activate_threads_~tmp~1); 376649#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 376129#L303 assume !(1 == ~t1_pc~0); 376130#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 376185#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 376691#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 376220#L743 assume !(0 != activate_threads_~tmp___0~0); 376221#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 376225#L322 assume !(1 == ~t2_pc~0); 376387#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 376386#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 376062#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 376063#L751 assume !(0 != activate_threads_~tmp___1~0); 376401#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 376402#L341 assume !(1 == ~t3_pc~0); 376345#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 376346#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 376342#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 376343#L759 assume !(0 != activate_threads_~tmp___2~0); 376577#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 376578#L360 assume !(1 == ~t4_pc~0); 376678#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 376676#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 376515#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 376516#L767 assume !(0 != activate_threads_~tmp___3~0); 376580#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 376278#L379 assume !(1 == ~t5_pc~0); 376179#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 376256#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 411909#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 411908#L775 assume !(0 != activate_threads_~tmp___4~0); 411907#L775-2 assume !(1 == ~M_E~0); 411906#L659-1 assume !(1 == ~T1_E~0); 411905#L664-1 assume !(1 == ~T2_E~0); 411904#L669-1 assume !(1 == ~T3_E~0); 411903#L674-1 assume !(1 == ~T4_E~0); 411901#L679-1 assume !(1 == ~T5_E~0); 411899#L684-1 assume !(1 == ~E_M~0); 411897#L689-1 assume !(1 == ~E_1~0); 411895#L694-1 assume !(1 == ~E_2~0); 411893#L699-1 assume !(1 == ~E_3~0); 411891#L704-1 assume !(1 == ~E_4~0); 411887#L709-1 assume !(1 == ~E_5~0); 376015#L920-1 assume !false; 411766#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 411763#L566 [2021-10-11 00:29:40,523 INFO L796 eck$LassoCheckResult]: Loop: 411763#L566 assume !false; 411760#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 411759#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 411758#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 411757#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 411756#L491 assume 0 != eval_~tmp~0; 411754#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 411750#L499 assume !(0 != eval_~tmp_ndt_1~0); 411748#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 411720#L513 assume !(0 != eval_~tmp_ndt_2~0); 411746#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 403313#L527 assume !(0 != eval_~tmp_ndt_3~0); 411755#L524 assume !(0 == ~t3_st~0); 411753#L538 assume !(0 == ~t4_st~0); 411770#L552 assume !(0 == ~t5_st~0); 411763#L566 [2021-10-11 00:29:40,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:40,523 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-10-11 00:29:40,523 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:40,524 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262831565] [2021-10-11 00:29:40,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:40,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:40,534 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:40,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:40,544 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:40,565 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:40,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:40,566 INFO L82 PathProgramCache]: Analyzing trace with hash 258069692, now seen corresponding path program 1 times [2021-10-11 00:29:40,566 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:40,566 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929152870] [2021-10-11 00:29:40,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:40,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:40,570 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:40,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:40,573 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:40,575 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:40,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:40,576 INFO L82 PathProgramCache]: Analyzing trace with hash -1891575302, now seen corresponding path program 1 times [2021-10-11 00:29:40,576 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:40,576 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551986637] [2021-10-11 00:29:40,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:40,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:40,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:40,614 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551986637] [2021-10-11 00:29:40,614 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:40,615 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:40,615 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342373057] [2021-10-11 00:29:40,754 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:40,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:40,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:40,755 INFO L87 Difference]: Start difference. First operand 56436 states and 78311 transitions. cyclomatic complexity: 21878 Second operand 3 states. [2021-10-11 00:29:41,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:41,289 INFO L93 Difference]: Finished difference Result 101612 states and 140795 transitions. [2021-10-11 00:29:41,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:41,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101612 states and 140795 transitions. [2021-10-11 00:29:42,021 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 101456 [2021-10-11 00:29:42,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101612 states to 101612 states and 140795 transitions. [2021-10-11 00:29:42,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101612 [2021-10-11 00:29:42,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101612 [2021-10-11 00:29:42,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101612 states and 140795 transitions. [2021-10-11 00:29:42,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:42,449 INFO L692 BuchiCegarLoop]: Abstraction has 101612 states and 140795 transitions. [2021-10-11 00:29:42,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101612 states and 140795 transitions. [2021-10-11 00:29:43,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101612 to 97916. [2021-10-11 00:29:43,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97916 states. [2021-10-11 00:29:43,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97916 states to 97916 states and 136091 transitions. [2021-10-11 00:29:43,867 INFO L715 BuchiCegarLoop]: Abstraction has 97916 states and 136091 transitions. [2021-10-11 00:29:43,867 INFO L595 BuchiCegarLoop]: Abstraction has 97916 states and 136091 transitions. [2021-10-11 00:29:43,867 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-11 00:29:43,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97916 states and 136091 transitions. [2021-10-11 00:29:44,125 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 97760 [2021-10-11 00:29:44,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:44,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:44,127 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:44,128 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:44,128 INFO L794 eck$LassoCheckResult]: Stem: 534680#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 534528#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 534506#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 534492#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 534493#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 534159#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 534160#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 534469#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 534470#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 534350#L431-1 assume !(0 == ~M_E~0); 534351#L591-1 assume !(0 == ~T1_E~0); 534356#L596-1 assume !(0 == ~T2_E~0); 534357#L601-1 assume !(0 == ~T3_E~0); 534431#L606-1 assume !(0 == ~T4_E~0); 534262#L611-1 assume !(0 == ~T5_E~0); 534263#L616-1 assume !(0 == ~E_M~0); 534078#L621-1 assume !(0 == ~E_1~0); 534079#L626-1 assume !(0 == ~E_2~0); 534167#L631-1 assume !(0 == ~E_3~0); 534168#L636-1 assume !(0 == ~E_4~0); 534499#L641-1 assume !(0 == ~E_5~0); 534500#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 534608#L284 assume !(1 == ~m_pc~0); 534590#L284-2 is_master_triggered_~__retres1~0 := 0; 534591#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 534526#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 534527#L735 assume !(0 != activate_threads_~tmp~1); 534791#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 534180#L303 assume !(1 == ~t1_pc~0); 534181#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 534238#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 534836#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 534279#L743 assume !(0 != activate_threads_~tmp___0~0); 534280#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 534284#L322 assume !(1 == ~t2_pc~0); 534476#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 534475#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 534118#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 534119#L751 assume !(0 != activate_threads_~tmp___1~0); 534494#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 534495#L341 assume !(1 == ~t3_pc~0); 534421#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 534422#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 534418#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 534419#L759 assume !(0 != activate_threads_~tmp___2~0); 534700#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 534701#L360 assume !(1 == ~t4_pc~0); 534824#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 534822#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 534616#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 534617#L767 assume !(0 != activate_threads_~tmp___3~0); 534704#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 534347#L379 assume !(1 == ~t5_pc~0); 534235#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 534316#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 534344#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 534090#L775 assume !(0 != activate_threads_~tmp___4~0); 534091#L775-2 assume !(1 == ~M_E~0); 534560#L659-1 assume !(1 == ~T1_E~0); 534561#L664-1 assume !(1 == ~T2_E~0); 534793#L669-1 assume !(1 == ~T3_E~0); 534794#L674-1 assume !(1 == ~T4_E~0); 559074#L679-1 assume !(1 == ~T5_E~0); 559072#L684-1 assume !(1 == ~E_M~0); 559070#L689-1 assume !(1 == ~E_1~0); 559068#L694-1 assume !(1 == ~E_2~0); 559066#L699-1 assume !(1 == ~E_3~0); 559064#L704-1 assume !(1 == ~E_4~0); 559060#L709-1 assume !(1 == ~E_5~0); 534071#L920-1 assume !false; 559033#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 559031#L566 [2021-10-11 00:29:44,128 INFO L796 eck$LassoCheckResult]: Loop: 559031#L566 assume !false; 559028#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 559025#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 559021#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 559019#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 559017#L491 assume 0 != eval_~tmp~0; 559014#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 559007#L499 assume !(0 != eval_~tmp_ndt_1~0); 558761#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 558753#L513 assume !(0 != eval_~tmp_ndt_2~0); 558742#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 549709#L527 assume !(0 != eval_~tmp_ndt_3~0); 558735#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 555759#L541 assume !(0 != eval_~tmp_ndt_4~0); 559484#L538 assume !(0 == ~t4_st~0); 559037#L552 assume !(0 == ~t5_st~0); 559031#L566 [2021-10-11 00:29:44,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:44,129 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-10-11 00:29:44,129 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:44,129 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039281736] [2021-10-11 00:29:44,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:44,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:44,139 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:44,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:44,148 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:44,166 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:44,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:44,167 INFO L82 PathProgramCache]: Analyzing trace with hash -595166546, now seen corresponding path program 1 times [2021-10-11 00:29:44,167 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:44,168 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238745169] [2021-10-11 00:29:44,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:44,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:44,171 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:44,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:44,174 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:44,176 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:44,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:44,177 INFO L82 PathProgramCache]: Analyzing trace with hash 1485315376, now seen corresponding path program 1 times [2021-10-11 00:29:44,177 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:44,177 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745835653] [2021-10-11 00:29:44,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:44,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:44,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:44,215 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745835653] [2021-10-11 00:29:44,215 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:44,215 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-11 00:29:44,215 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108743804] [2021-10-11 00:29:44,350 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:44,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:44,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:44,351 INFO L87 Difference]: Start difference. First operand 97916 states and 136091 transitions. cyclomatic complexity: 38178 Second operand 3 states. [2021-10-11 00:29:45,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:45,269 INFO L93 Difference]: Finished difference Result 184020 states and 255179 transitions. [2021-10-11 00:29:45,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:45,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184020 states and 255179 transitions. [2021-10-11 00:29:46,445 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 183800 [2021-10-11 00:29:46,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184020 states to 184020 states and 255179 transitions. [2021-10-11 00:29:46,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184020 [2021-10-11 00:29:46,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184020 [2021-10-11 00:29:46,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184020 states and 255179 transitions. [2021-10-11 00:29:47,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:47,051 INFO L692 BuchiCegarLoop]: Abstraction has 184020 states and 255179 transitions. [2021-10-11 00:29:47,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184020 states and 255179 transitions. [2021-10-11 00:29:49,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184020 to 182900. [2021-10-11 00:29:49,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182900 states. [2021-10-11 00:29:49,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182900 states to 182900 states and 253835 transitions. [2021-10-11 00:29:49,478 INFO L715 BuchiCegarLoop]: Abstraction has 182900 states and 253835 transitions. [2021-10-11 00:29:49,478 INFO L595 BuchiCegarLoop]: Abstraction has 182900 states and 253835 transitions. [2021-10-11 00:29:49,478 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-11 00:29:49,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182900 states and 253835 transitions. [2021-10-11 00:29:50,610 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 182680 [2021-10-11 00:29:50,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:29:50,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:29:50,622 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:50,622 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:29:50,623 INFO L794 eck$LassoCheckResult]: Stem: 816621#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 816466#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 816444#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 816431#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 816432#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 816103#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 816104#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 816404#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 816405#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 816288#L431-1 assume !(0 == ~M_E~0); 816289#L591-1 assume !(0 == ~T1_E~0); 816294#L596-1 assume !(0 == ~T2_E~0); 816295#L601-1 assume !(0 == ~T3_E~0); 816369#L606-1 assume !(0 == ~T4_E~0); 816208#L611-1 assume !(0 == ~T5_E~0); 816209#L616-1 assume !(0 == ~E_M~0); 816021#L621-1 assume !(0 == ~E_1~0); 816022#L626-1 assume !(0 == ~E_2~0); 816113#L631-1 assume !(0 == ~E_3~0); 816114#L636-1 assume !(0 == ~E_4~0); 816438#L641-1 assume !(0 == ~E_5~0); 816439#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 816549#L284 assume !(1 == ~m_pc~0); 816529#L284-2 is_master_triggered_~__retres1~0 := 0; 816530#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 816464#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 816465#L735 assume !(0 != activate_threads_~tmp~1); 816737#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 816126#L303 assume !(1 == ~t1_pc~0); 816127#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 816185#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 816791#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 816224#L743 assume !(0 != activate_threads_~tmp___0~0); 816225#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 816228#L322 assume !(1 == ~t2_pc~0); 816410#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 816409#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 816062#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 816063#L751 assume !(0 != activate_threads_~tmp___1~0); 816433#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 816434#L341 assume !(1 == ~t3_pc~0); 816359#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 816360#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 816356#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 816357#L759 assume !(0 != activate_threads_~tmp___2~0); 816642#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 816643#L360 assume !(1 == ~t4_pc~0); 816775#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 816773#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 816558#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 816559#L767 assume !(0 != activate_threads_~tmp___3~0); 816648#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 816284#L379 assume !(1 == ~t5_pc~0); 816182#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 816264#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 816175#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 816176#L775 assume !(0 != activate_threads_~tmp___4~0); 816038#L775-2 assume !(1 == ~M_E~0); 816039#L659-1 assume !(1 == ~T1_E~0); 816111#L664-1 assume !(1 == ~T2_E~0); 816112#L669-1 assume !(1 == ~T3_E~0); 816436#L674-1 assume !(1 == ~T4_E~0); 816437#L679-1 assume !(1 == ~T5_E~0); 816309#L684-1 assume !(1 == ~E_M~0); 816310#L689-1 assume !(1 == ~E_1~0); 816600#L694-1 assume !(1 == ~E_2~0); 816601#L699-1 assume !(1 == ~E_3~0); 816644#L704-1 assume !(1 == ~E_4~0); 816645#L709-1 assume !(1 == ~E_5~0); 816015#L920-1 assume !false; 875949#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 870861#L566 [2021-10-11 00:29:50,623 INFO L796 eck$LassoCheckResult]: Loop: 870861#L566 assume !false; 875938#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 875926#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 875922#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 875923#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 874286#L491 assume 0 != eval_~tmp~0; 874287#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 882388#L499 assume !(0 != eval_~tmp_ndt_1~0); 882197#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 882163#L513 assume !(0 != eval_~tmp_ndt_2~0); 857815#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 857808#L527 assume !(0 != eval_~tmp_ndt_3~0); 857809#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 866602#L541 assume !(0 != eval_~tmp_ndt_4~0); 866715#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 866268#L555 assume !(0 != eval_~tmp_ndt_5~0); 870867#L552 assume !(0 == ~t5_st~0); 870861#L566 [2021-10-11 00:29:50,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:50,623 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-10-11 00:29:50,623 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:50,624 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399506606] [2021-10-11 00:29:50,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:50,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:50,632 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:50,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:50,665 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:50,698 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:50,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:50,715 INFO L82 PathProgramCache]: Analyzing trace with hash -1270466089, now seen corresponding path program 1 times [2021-10-11 00:29:50,715 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:50,716 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947718937] [2021-10-11 00:29:50,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:50,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:50,725 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:50,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:29:50,728 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:29:50,730 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:29:50,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:29:50,731 INFO L82 PathProgramCache]: Analyzing trace with hash -1200035947, now seen corresponding path program 1 times [2021-10-11 00:29:50,732 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:29:50,732 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172503720] [2021-10-11 00:29:50,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:29:50,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-11 00:29:50,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-11 00:29:50,797 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172503720] [2021-10-11 00:29:50,813 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-11 00:29:50,814 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-11 00:29:50,814 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497325705] [2021-10-11 00:29:50,958 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-11 00:29:50,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-11 00:29:50,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-11 00:29:50,959 INFO L87 Difference]: Start difference. First operand 182900 states and 253835 transitions. cyclomatic complexity: 70938 Second operand 3 states. [2021-10-11 00:29:51,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-11 00:29:51,832 INFO L93 Difference]: Finished difference Result 311228 states and 432723 transitions. [2021-10-11 00:29:51,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-11 00:29:51,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 311228 states and 432723 transitions. [2021-10-11 00:29:54,141 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 310880 [2021-10-11 00:29:55,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 311228 states to 311228 states and 432723 transitions. [2021-10-11 00:29:55,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 311228 [2021-10-11 00:29:55,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 311228 [2021-10-11 00:29:55,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 311228 states and 432723 transitions. [2021-10-11 00:29:55,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-11 00:29:55,846 INFO L692 BuchiCegarLoop]: Abstraction has 311228 states and 432723 transitions. [2021-10-11 00:29:55,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311228 states and 432723 transitions. [2021-10-11 00:29:58,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311228 to 308540. [2021-10-11 00:29:58,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308540 states. [2021-10-11 00:30:00,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308540 states to 308540 states and 430035 transitions. [2021-10-11 00:30:00,509 INFO L715 BuchiCegarLoop]: Abstraction has 308540 states and 430035 transitions. [2021-10-11 00:30:00,510 INFO L595 BuchiCegarLoop]: Abstraction has 308540 states and 430035 transitions. [2021-10-11 00:30:00,510 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-11 00:30:00,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308540 states and 430035 transitions. [2021-10-11 00:30:01,741 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 308192 [2021-10-11 00:30:01,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-11 00:30:01,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-11 00:30:01,742 INFO L853 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:30:01,742 INFO L854 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-11 00:30:01,743 INFO L794 eck$LassoCheckResult]: Stem: 1310739#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1310585#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1310563#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1310547#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1310548#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1310242#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1310243#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1310528#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1310529#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1310415#L431-1 assume !(0 == ~M_E~0); 1310416#L591-1 assume !(0 == ~T1_E~0); 1310419#L596-1 assume !(0 == ~T2_E~0); 1310420#L601-1 assume !(0 == ~T3_E~0); 1310493#L606-1 assume !(0 == ~T4_E~0); 1310340#L611-1 assume !(0 == ~T5_E~0); 1310341#L616-1 assume !(0 == ~E_M~0); 1310157#L621-1 assume !(0 == ~E_1~0); 1310158#L626-1 assume !(0 == ~E_2~0); 1310248#L631-1 assume !(0 == ~E_3~0); 1310249#L636-1 assume !(0 == ~E_4~0); 1310555#L641-1 assume !(0 == ~E_5~0); 1310556#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1310669#L284 assume !(1 == ~m_pc~0); 1310650#L284-2 is_master_triggered_~__retres1~0 := 0; 1310651#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1310583#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1310584#L735 assume !(0 != activate_threads_~tmp~1); 1310859#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1310262#L303 assume !(1 == ~t1_pc~0); 1310263#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1310318#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1310329#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1310355#L743 assume !(0 != activate_threads_~tmp___0~0); 1310356#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1310358#L322 assume !(1 == ~t2_pc~0); 1310534#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 1310533#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1310197#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1310198#L751 assume !(0 != activate_threads_~tmp___1~0); 1310549#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1310550#L341 assume !(1 == ~t3_pc~0); 1310482#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1310483#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1310479#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1310480#L759 assume !(0 != activate_threads_~tmp___2~0); 1310759#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1310760#L360 assume !(1 == ~t4_pc~0); 1310897#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 1310893#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1310679#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1310680#L767 assume !(0 != activate_threads_~tmp___3~0); 1310764#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1310412#L379 assume !(1 == ~t5_pc~0); 1310313#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1310393#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1405040#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1405039#L775 assume !(0 != activate_threads_~tmp___4~0); 1405038#L775-2 assume !(1 == ~M_E~0); 1405037#L659-1 assume !(1 == ~T1_E~0); 1405036#L664-1 assume !(1 == ~T2_E~0); 1405035#L669-1 assume !(1 == ~T3_E~0); 1405034#L674-1 assume !(1 == ~T4_E~0); 1405033#L679-1 assume !(1 == ~T5_E~0); 1405032#L684-1 assume !(1 == ~E_M~0); 1405031#L689-1 assume !(1 == ~E_1~0); 1405030#L694-1 assume !(1 == ~E_2~0); 1405028#L699-1 assume !(1 == ~E_3~0); 1405026#L704-1 assume !(1 == ~E_4~0); 1405024#L709-1 assume !(1 == ~E_5~0); 1310153#L920-1 assume !false; 1405021#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1368633#L566 [2021-10-11 00:30:01,743 INFO L796 eck$LassoCheckResult]: Loop: 1368633#L566 assume !false; 1405018#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1405014#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1405012#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1405010#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1405009#L491 assume 0 != eval_~tmp~0; 1401649#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1401647#L499 assume !(0 != eval_~tmp_ndt_1~0); 1383345#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1383343#L513 assume !(0 != eval_~tmp_ndt_2~0); 1383344#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1388310#L527 assume !(0 != eval_~tmp_ndt_3~0); 1368642#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 1368640#L541 assume !(0 != eval_~tmp_ndt_4~0); 1368639#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 1368637#L555 assume !(0 != eval_~tmp_ndt_5~0); 1368635#L552 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 1363973#L569 assume !(0 != eval_~tmp_ndt_6~0); 1368633#L566 [2021-10-11 00:30:01,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:30:01,744 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-10-11 00:30:01,744 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:30:01,744 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549692900] [2021-10-11 00:30:01,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:30:01,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,756 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,766 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,787 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:30:01,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:30:01,788 INFO L82 PathProgramCache]: Analyzing trace with hash -729747053, now seen corresponding path program 1 times [2021-10-11 00:30:01,789 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:30:01,789 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037509434] [2021-10-11 00:30:01,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:30:01,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,793 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,796 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,799 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:30:01,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-11 00:30:01,800 INFO L82 PathProgramCache]: Analyzing trace with hash 1453587349, now seen corresponding path program 1 times [2021-10-11 00:30:01,800 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-11 00:30:01,800 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562811563] [2021-10-11 00:30:01,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-11 00:30:01,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,813 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-11 00:30:01,824 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-11 00:30:01,867 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-11 00:30:01,974 WARN L197 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2021-10-11 00:30:04,606 WARN L197 SmtUtils]: Spent 2.56 s on a formula simplification. DAG size of input: 251 DAG size of output: 179 [2021-10-11 00:30:05,193 WARN L197 SmtUtils]: Spent 507.00 ms on a formula simplification that was a NOOP. DAG size: 153 [2021-10-11 00:30:05,284 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 11.10 12:30:05 BoogieIcfgContainer [2021-10-11 00:30:05,285 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-11 00:30:05,288 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-11 00:30:05,288 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-11 00:30:05,288 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-11 00:30:05,289 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.10 12:29:26" (3/4) ... [2021-10-11 00:30:05,292 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-11 00:30:05,380 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_350f7ff9-2c2f-4f71-ad72-310fed035acc/bin/uautomizer-Z5i5R5N3CC/witness.graphml [2021-10-11 00:30:05,380 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-11 00:30:05,382 INFO L168 Benchmark]: Toolchain (without parser) took 40485.82 ms. Allocated memory was 111.1 MB in the beginning and 14.1 GB in the end (delta: 14.0 GB). Free memory was 70.9 MB in the beginning and 10.9 GB in the end (delta: -10.8 GB). Peak memory consumption was 3.1 GB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,383 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 111.1 MB. Free memory was 87.9 MB in the beginning and 87.8 MB in the end (delta: 73.7 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-11 00:30:05,383 INFO L168 Benchmark]: CACSL2BoogieTranslator took 514.64 ms. Allocated memory is still 111.1 MB. Free memory was 70.7 MB in the beginning and 79.7 MB in the end (delta: -8.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,384 INFO L168 Benchmark]: Boogie Procedure Inliner took 88.29 ms. Allocated memory is still 111.1 MB. Free memory was 79.7 MB in the beginning and 74.7 MB in the end (delta: 4.9 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,384 INFO L168 Benchmark]: Boogie Preprocessor took 75.01 ms. Allocated memory is still 111.1 MB. Free memory was 74.4 MB in the beginning and 69.8 MB in the end (delta: 4.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,385 INFO L168 Benchmark]: RCFGBuilder took 1359.17 ms. Allocated memory was 111.1 MB in the beginning and 144.7 MB in the end (delta: 33.6 MB). Free memory was 69.8 MB in the beginning and 104.0 MB in the end (delta: -34.1 MB). Peak memory consumption was 60.2 MB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,385 INFO L168 Benchmark]: BuchiAutomizer took 38347.02 ms. Allocated memory was 144.7 MB in the beginning and 14.1 GB in the end (delta: 13.9 GB). Free memory was 104.0 MB in the beginning and 10.9 GB in the end (delta: -10.8 GB). Peak memory consumption was 3.7 GB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,386 INFO L168 Benchmark]: Witness Printer took 92.60 ms. Allocated memory is still 14.1 GB. Free memory was 10.9 GB in the beginning and 10.9 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-11 00:30:05,388 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 111.1 MB. Free memory was 87.9 MB in the beginning and 87.8 MB in the end (delta: 73.7 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 514.64 ms. Allocated memory is still 111.1 MB. Free memory was 70.7 MB in the beginning and 79.7 MB in the end (delta: -8.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 88.29 ms. Allocated memory is still 111.1 MB. Free memory was 79.7 MB in the beginning and 74.7 MB in the end (delta: 4.9 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 75.01 ms. Allocated memory is still 111.1 MB. Free memory was 74.4 MB in the beginning and 69.8 MB in the end (delta: 4.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1359.17 ms. Allocated memory was 111.1 MB in the beginning and 144.7 MB in the end (delta: 33.6 MB). Free memory was 69.8 MB in the beginning and 104.0 MB in the end (delta: -34.1 MB). Peak memory consumption was 60.2 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 38347.02 ms. Allocated memory was 144.7 MB in the beginning and 14.1 GB in the end (delta: 13.9 GB). Free memory was 104.0 MB in the beginning and 10.9 GB in the end (delta: -10.8 GB). Peak memory consumption was 3.7 GB. Max. memory is 16.1 GB. * Witness Printer took 92.60 ms. Allocated memory is still 14.1 GB. Free memory was 10.9 GB in the beginning and 10.9 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 308540 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 38.2s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 7.1s. Construction of modules took 0.9s. Büchi inclusion checks took 4.0s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 12.1s AutomataMinimizationTime, 23 MinimizatonAttempts, 39199 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 9.4s Buchi closure took 0.4s. Biggest automaton had 308540 states and ocurred in iteration 23. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 20431 SDtfs, 23947 SDslu, 19208 SDs, 0 SdLazy, 738 SolverSat, 324 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 486]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=12522} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=12522, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@58fdc230=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7bbcd2cb=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@399a5b25=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41aa90f7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50b37aaf=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1cc9fed5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17e5d0d=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d15bccf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12925b17=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49cd6b05=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b3134dd=0, NULL=12524, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28037f6a=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@61b39a2e=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@771010a8=0, T1_E=2, NULL=12525, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=12523, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cf018d4=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 486]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L965] int __retres1 ; [L876] m_i = 1 [L877] t1_i = 1 [L878] t2_i = 1 [L879] t3_i = 1 [L880] t4_i = 1 [L881] t5_i = 1 [L906] int kernel_st ; [L907] int tmp ; [L908] int tmp___0 ; [L912] kernel_st = 0 [L406] COND TRUE m_i == 1 [L407] m_st = 0 [L411] COND TRUE t1_i == 1 [L412] t1_st = 0 [L416] COND TRUE t2_i == 1 [L417] t2_st = 0 [L421] COND TRUE t3_i == 1 [L422] t3_st = 0 [L426] COND TRUE t4_i == 1 [L427] t4_st = 0 [L431] COND TRUE t5_i == 1 [L432] t5_st = 0 [L591] COND FALSE !(M_E == 0) [L596] COND FALSE !(T1_E == 0) [L601] COND FALSE !(T2_E == 0) [L606] COND FALSE !(T3_E == 0) [L611] COND FALSE !(T4_E == 0) [L616] COND FALSE !(T5_E == 0) [L621] COND FALSE !(E_M == 0) [L626] COND FALSE !(E_1 == 0) [L631] COND FALSE !(E_2 == 0) [L636] COND FALSE !(E_3 == 0) [L641] COND FALSE !(E_4 == 0) [L646] COND FALSE !(E_5 == 0) [L724] int tmp ; [L725] int tmp___0 ; [L726] int tmp___1 ; [L727] int tmp___2 ; [L728] int tmp___3 ; [L729] int tmp___4 ; [L281] int __retres1 ; [L284] COND FALSE !(m_pc == 1) [L294] __retres1 = 0 [L296] return (__retres1); [L733] tmp = is_master_triggered() [L735] COND FALSE !(\read(tmp)) [L300] int __retres1 ; [L303] COND FALSE !(t1_pc == 1) [L313] __retres1 = 0 [L315] return (__retres1); [L741] tmp___0 = is_transmit1_triggered() [L743] COND FALSE !(\read(tmp___0)) [L319] int __retres1 ; [L322] COND FALSE !(t2_pc == 1) [L332] __retres1 = 0 [L334] return (__retres1); [L749] tmp___1 = is_transmit2_triggered() [L751] COND FALSE !(\read(tmp___1)) [L338] int __retres1 ; [L341] COND FALSE !(t3_pc == 1) [L351] __retres1 = 0 [L353] return (__retres1); [L757] tmp___2 = is_transmit3_triggered() [L759] COND FALSE !(\read(tmp___2)) [L357] int __retres1 ; [L360] COND FALSE !(t4_pc == 1) [L370] __retres1 = 0 [L372] return (__retres1); [L765] tmp___3 = is_transmit4_triggered() [L767] COND FALSE !(\read(tmp___3)) [L376] int __retres1 ; [L379] COND FALSE !(t5_pc == 1) [L389] __retres1 = 0 [L391] return (__retres1); [L773] tmp___4 = is_transmit5_triggered() [L775] COND FALSE !(\read(tmp___4)) [L659] COND FALSE !(M_E == 1) [L664] COND FALSE !(T1_E == 1) [L669] COND FALSE !(T2_E == 1) [L674] COND FALSE !(T3_E == 1) [L679] COND FALSE !(T4_E == 1) [L684] COND FALSE !(T5_E == 1) [L689] COND FALSE !(E_M == 1) [L694] COND FALSE !(E_1 == 1) [L699] COND FALSE !(E_2 == 1) [L704] COND FALSE !(E_3 == 1) [L709] COND FALSE !(E_4 == 1) [L714] COND FALSE !(E_5 == 1) [L920] COND TRUE 1 [L923] kernel_st = 1 [L482] int tmp ; Loop: [L486] COND TRUE 1 [L441] int __retres1 ; [L444] COND TRUE m_st == 0 [L445] __retres1 = 1 [L477] return (__retres1); [L489] tmp = exists_runnable_thread() [L491] COND TRUE \read(tmp) [L496] COND TRUE m_st == 0 [L497] int tmp_ndt_1; [L498] tmp_ndt_1 = __VERIFIER_nondet_int() [L499] COND FALSE !(\read(tmp_ndt_1)) [L510] COND TRUE t1_st == 0 [L511] int tmp_ndt_2; [L512] tmp_ndt_2 = __VERIFIER_nondet_int() [L513] COND FALSE !(\read(tmp_ndt_2)) [L524] COND TRUE t2_st == 0 [L525] int tmp_ndt_3; [L526] tmp_ndt_3 = __VERIFIER_nondet_int() [L527] COND FALSE !(\read(tmp_ndt_3)) [L538] COND TRUE t3_st == 0 [L539] int tmp_ndt_4; [L540] tmp_ndt_4 = __VERIFIER_nondet_int() [L541] COND FALSE !(\read(tmp_ndt_4)) [L552] COND TRUE t4_st == 0 [L553] int tmp_ndt_5; [L554] tmp_ndt_5 = __VERIFIER_nondet_int() [L555] COND FALSE !(\read(tmp_ndt_5)) [L566] COND TRUE t5_st == 0 [L567] int tmp_ndt_6; [L568] tmp_ndt_6 = __VERIFIER_nondet_int() [L569] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...