./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4e77c044 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4b4145914802a18ceef375a77d9a4f2f13e6c70b .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-4e77c04 [2021-10-13 01:09:06,741 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-13 01:09:06,745 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-13 01:09:06,810 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-13 01:09:06,810 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-13 01:09:06,814 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-13 01:09:06,817 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-13 01:09:06,821 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-13 01:09:06,824 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-13 01:09:06,830 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-13 01:09:06,838 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-13 01:09:06,840 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-13 01:09:06,841 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-13 01:09:06,843 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-13 01:09:06,846 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-13 01:09:06,854 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-13 01:09:06,856 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-13 01:09:06,857 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-13 01:09:06,859 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-13 01:09:06,867 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-13 01:09:06,869 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-13 01:09:06,870 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-13 01:09:06,874 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-13 01:09:06,875 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-13 01:09:06,885 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-13 01:09:06,886 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-13 01:09:06,886 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-13 01:09:06,888 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-13 01:09:06,889 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-13 01:09:06,891 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-13 01:09:06,892 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-13 01:09:06,893 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-13 01:09:06,895 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-13 01:09:06,896 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-13 01:09:06,898 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-13 01:09:06,898 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-13 01:09:06,899 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-13 01:09:06,899 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-13 01:09:06,899 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-13 01:09:06,900 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-13 01:09:06,901 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-13 01:09:06,903 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-13 01:09:06,957 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-13 01:09:06,960 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-13 01:09:06,960 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-13 01:09:06,961 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-13 01:09:06,963 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-13 01:09:06,963 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-13 01:09:06,963 INFO L138 SettingsManager]: * Use SBE=true [2021-10-13 01:09:06,964 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-13 01:09:06,964 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-13 01:09:06,964 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-13 01:09:06,965 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-13 01:09:06,965 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-13 01:09:06,966 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-13 01:09:06,966 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-13 01:09:06,966 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-13 01:09:06,966 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-13 01:09:06,967 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-13 01:09:06,967 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-13 01:09:06,967 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-13 01:09:06,967 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-13 01:09:06,968 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-13 01:09:06,968 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-13 01:09:06,968 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-13 01:09:06,968 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-13 01:09:06,969 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-13 01:09:06,969 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-13 01:09:06,969 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-13 01:09:06,969 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-13 01:09:06,970 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-13 01:09:06,970 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-13 01:09:06,970 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-13 01:09:06,970 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-13 01:09:06,972 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-13 01:09:06,972 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4b4145914802a18ceef375a77d9a4f2f13e6c70b [2021-10-13 01:09:07,196 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-13 01:09:07,217 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-13 01:09:07,219 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-13 01:09:07,221 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-13 01:09:07,221 INFO L275 PluginConnector]: CDTParser initialized [2021-10-13 01:09:07,222 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-10-13 01:09:07,324 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/data/cabdc4a94/d08909f295694a85841fda15d716059d/FLAG7a2f704b3 [2021-10-13 01:09:07,887 INFO L306 CDTParser]: Found 1 translation units. [2021-10-13 01:09:07,888 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-10-13 01:09:07,908 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/data/cabdc4a94/d08909f295694a85841fda15d716059d/FLAG7a2f704b3 [2021-10-13 01:09:08,231 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/data/cabdc4a94/d08909f295694a85841fda15d716059d [2021-10-13 01:09:08,234 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-13 01:09:08,235 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-13 01:09:08,237 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-13 01:09:08,237 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-13 01:09:08,241 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-13 01:09:08,242 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,243 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@16f6b830 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08, skipping insertion in model container [2021-10-13 01:09:08,243 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,250 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-13 01:09:08,277 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-13 01:09:08,407 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[366,379] [2021-10-13 01:09:08,476 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:09:08,493 INFO L203 MainTranslator]: Completed pre-run [2021-10-13 01:09:08,505 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[366,379] [2021-10-13 01:09:08,535 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:09:08,568 INFO L208 MainTranslator]: Completed translation [2021-10-13 01:09:08,568 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08 WrapperNode [2021-10-13 01:09:08,568 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-13 01:09:08,570 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-13 01:09:08,570 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-13 01:09:08,570 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-13 01:09:08,577 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,589 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,628 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-13 01:09:08,629 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-13 01:09:08,630 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-13 01:09:08,630 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-13 01:09:08,644 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,645 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,670 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,671 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,685 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,697 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,700 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,707 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-13 01:09:08,708 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-13 01:09:08,708 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-13 01:09:08,709 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-13 01:09:08,731 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (1/1) ... [2021-10-13 01:09:08,753 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-13 01:09:08,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/z3 [2021-10-13 01:09:08,800 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-13 01:09:08,826 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-13 01:09:08,856 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-13 01:09:08,857 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-13 01:09:08,857 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-13 01:09:08,857 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-13 01:09:09,498 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-13 01:09:09,499 INFO L299 CfgBuilder]: Removed 103 assume(true) statements. [2021-10-13 01:09:09,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:09:09 BoogieIcfgContainer [2021-10-13 01:09:09,502 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-13 01:09:09,503 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-13 01:09:09,503 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-13 01:09:09,511 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-13 01:09:09,512 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:09:09,512 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 01:09:08" (1/3) ... [2021-10-13 01:09:09,515 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@583ae4fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:09:09, skipping insertion in model container [2021-10-13 01:09:09,515 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:09:09,515 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:09:08" (2/3) ... [2021-10-13 01:09:09,516 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@583ae4fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:09:09, skipping insertion in model container [2021-10-13 01:09:09,516 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:09:09,516 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:09:09" (3/3) ... [2021-10-13 01:09:09,518 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2021-10-13 01:09:09,576 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-13 01:09:09,576 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-13 01:09:09,577 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-13 01:09:09,577 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-13 01:09:09,577 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-13 01:09:09,577 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-13 01:09:09,577 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-13 01:09:09,577 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-13 01:09:09,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:09,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2021-10-13 01:09:09,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:09,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:09,676 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:09,676 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:09,676 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-13 01:09:09,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:09,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2021-10-13 01:09:09,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:09,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:09,702 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:09,703 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:09,711 INFO L791 eck$LassoCheckResult]: Stem: 206#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 125#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26#L508true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 186#L216true assume !(1 == ~m_i~0);~m_st~0 := 2; 100#L223-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 44#L228-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 53#L233-1true assume !(0 == ~M_E~0); 101#L336-1true assume !(0 == ~T1_E~0); 95#L341-1true assume !(0 == ~T2_E~0); 19#L346-1true assume !(0 == ~E_M~0); 120#L351-1true assume !(0 == ~E_1~0); 22#L356-1true assume !(0 == ~E_2~0); 111#L361-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 109#L158true assume 1 == ~m_pc~0; 156#L159true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 140#L169true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L170true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35#L417true assume !(0 != activate_threads_~tmp~1); 152#L417-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 137#L177true assume 1 == ~t1_pc~0; 25#L178true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14#L188true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73#L189true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 188#L425true assume !(0 != activate_threads_~tmp___0~0); 210#L425-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50#L196true assume !(1 == ~t2_pc~0); 211#L196-2true is_transmit2_triggered_~__retres1~2 := 0; 57#L207true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 190#L208true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54#L433true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 135#L433-2true assume !(1 == ~M_E~0); 180#L374-1true assume !(1 == ~T1_E~0); 29#L379-1true assume !(1 == ~T2_E~0); 24#L384-1true assume !(1 == ~E_M~0); 142#L389-1true assume 1 == ~E_1~0;~E_1~0 := 2; 131#L394-1true assume !(1 == ~E_2~0); 214#L545-1true [2021-10-13 01:09:09,719 INFO L793 eck$LassoCheckResult]: Loop: 214#L545-1true assume !false; 31#L546true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 39#L311true assume false; 122#L326true start_simulation_~kernel_st~0 := 2; 48#L216-1true start_simulation_~kernel_st~0 := 3; 158#L336-2true assume 0 == ~M_E~0;~M_E~0 := 1; 201#L336-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 112#L341-3true assume !(0 == ~T2_E~0); 139#L346-3true assume 0 == ~E_M~0;~E_M~0 := 1; 61#L351-3true assume 0 == ~E_1~0;~E_1~0 := 1; 161#L356-3true assume 0 == ~E_2~0;~E_2~0 := 1; 102#L361-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124#L158-12true assume 1 == ~m_pc~0; 145#L159-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 110#L169-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 81#L170-4true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21#L417-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 72#L417-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4#L177-12true assume !(1 == ~t1_pc~0); 15#L177-14true is_transmit1_triggered_~__retres1~1 := 0; 114#L188-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90#L189-4true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 47#L425-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 88#L425-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203#L196-12true assume !(1 == ~t2_pc~0); 215#L196-14true is_transmit2_triggered_~__retres1~2 := 0; 157#L207-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41#L208-4true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 171#L433-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 103#L433-14true assume !(1 == ~M_E~0); 134#L374-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 56#L379-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 64#L384-3true assume 1 == ~E_M~0;~E_M~0 := 2; 117#L389-3true assume 1 == ~E_1~0;~E_1~0 := 2; 216#L394-3true assume 1 == ~E_2~0;~E_2~0 := 2; 16#L399-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17#L246-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 217#L263-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 163#L264-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 13#L564true assume !(0 == start_simulation_~tmp~3); 153#L564-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 108#L246-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 174#L263-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 209#L264-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 165#L519true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 175#L526true stop_simulation_#res := stop_simulation_~__retres2~0; 173#L527true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 143#L577true assume !(0 != start_simulation_~tmp___0~1); 214#L545-1true [2021-10-13 01:09:09,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:09,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2021-10-13 01:09:09,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:09,734 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210815982] [2021-10-13 01:09:09,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:09,736 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:09,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:09,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:09,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:09,918 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210815982] [2021-10-13 01:09:09,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210815982] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:09,920 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:09,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:09,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177996243] [2021-10-13 01:09:09,926 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:09,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:09,927 INFO L82 PathProgramCache]: Analyzing trace with hash -1944420535, now seen corresponding path program 1 times [2021-10-13 01:09:09,928 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:09,928 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420777617] [2021-10-13 01:09:09,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:09,928 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:09,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:09,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:09,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:09,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420777617] [2021-10-13 01:09:09,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420777617] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:09,951 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:09,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:09:09,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816465176] [2021-10-13 01:09:09,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:09,954 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:09,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:09,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:09,970 INFO L87 Difference]: Start difference. First operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:10,000 INFO L93 Difference]: Finished difference Result 217 states and 327 transitions. [2021-10-13 01:09:10,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:10,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 327 transitions. [2021-10-13 01:09:10,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-13 01:09:10,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 212 states and 322 transitions. [2021-10-13 01:09:10,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2021-10-13 01:09:10,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2021-10-13 01:09:10,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 322 transitions. [2021-10-13 01:09:10,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:10,053 INFO L681 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-13 01:09:10,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 322 transitions. [2021-10-13 01:09:10,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2021-10-13 01:09:10,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.5188679245283019) internal successors, (322), 211 states have internal predecessors, (322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 322 transitions. [2021-10-13 01:09:10,126 INFO L704 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-13 01:09:10,126 INFO L587 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-13 01:09:10,126 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-13 01:09:10,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 322 transitions. [2021-10-13 01:09:10,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-13 01:09:10,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:10,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:10,131 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,131 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,132 INFO L791 eck$LassoCheckResult]: Stem: 654#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 617#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 489#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 490#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 595#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 522#L228-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 523#L233-1 assume !(0 == ~M_E~0); 539#L336-1 assume !(0 == ~T1_E~0); 589#L341-1 assume !(0 == ~T2_E~0); 475#L346-1 assume !(0 == ~E_M~0); 476#L351-1 assume !(0 == ~E_1~0); 481#L356-1 assume !(0 == ~E_2~0); 482#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 606#L158 assume 1 == ~m_pc~0; 607#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 604#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 628#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 505#L417 assume !(0 != activate_threads_~tmp~1); 506#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 627#L177 assume 1 == ~t1_pc~0; 487#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 466#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 467#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 565#L425 assume !(0 != activate_threads_~tmp___0~0); 652#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 532#L196 assume !(1 == ~t2_pc~0); 533#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 546#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 547#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 540#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 541#L433-2 assume !(1 == ~M_E~0); 626#L374-1 assume !(1 == ~T1_E~0); 496#L379-1 assume !(1 == ~T2_E~0); 485#L384-1 assume !(1 == ~E_M~0); 486#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 621#L394-1 assume !(1 == ~E_2~0); 622#L545-1 [2021-10-13 01:09:10,132 INFO L793 eck$LassoCheckResult]: Loop: 622#L545-1 assume !false; 498#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 494#L311 assume !false; 512#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 535#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 518#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 629#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 591#L278 assume !(0 != eval_~tmp~0); 592#L326 start_simulation_~kernel_st~0 := 2; 529#L216-1 start_simulation_~kernel_st~0 := 3; 530#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 638#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 609#L341-3 assume !(0 == ~T2_E~0); 610#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 551#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 552#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 596#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 597#L158-12 assume !(1 == ~m_pc~0); 615#L158-14 is_master_triggered_~__retres1~0 := 0; 608#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 570#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 479#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 480#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 446#L177-12 assume !(1 == ~t1_pc~0); 448#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 468#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 582#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 527#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 528#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 579#L196-12 assume 1 == ~t2_pc~0; 649#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 637#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 515#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 516#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 598#L433-14 assume !(1 == ~M_E~0); 599#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 544#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 545#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 555#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 613#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 469#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 470#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 455#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 640#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 464#L564 assume !(0 == start_simulation_~tmp~3); 465#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 605#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 484#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 648#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 642#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 643#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 647#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 630#L577 assume !(0 != start_simulation_~tmp___0~1); 622#L545-1 [2021-10-13 01:09:10,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,133 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2021-10-13 01:09:10,134 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,134 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140596538] [2021-10-13 01:09:10,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,135 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,184 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,185 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140596538] [2021-10-13 01:09:10,185 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140596538] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,185 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,185 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:10,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960311147] [2021-10-13 01:09:10,186 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:10,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,187 INFO L82 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 1 times [2021-10-13 01:09:10,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294646244] [2021-10-13 01:09:10,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,188 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,241 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,241 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294646244] [2021-10-13 01:09:10,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294646244] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,242 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,242 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:10,242 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834694292] [2021-10-13 01:09:10,243 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:10,243 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:10,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:10,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:10,244 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:10,262 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2021-10-13 01:09:10,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:10,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 321 transitions. [2021-10-13 01:09:10,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-13 01:09:10,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 321 transitions. [2021-10-13 01:09:10,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2021-10-13 01:09:10,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2021-10-13 01:09:10,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 321 transitions. [2021-10-13 01:09:10,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:10,271 INFO L681 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-13 01:09:10,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 321 transitions. [2021-10-13 01:09:10,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2021-10-13 01:09:10,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.5141509433962264) internal successors, (321), 211 states have internal predecessors, (321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 321 transitions. [2021-10-13 01:09:10,282 INFO L704 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-13 01:09:10,282 INFO L587 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-13 01:09:10,282 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-13 01:09:10,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 321 transitions. [2021-10-13 01:09:10,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-13 01:09:10,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:10,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:10,286 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,286 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,287 INFO L791 eck$LassoCheckResult]: Stem: 1085#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1048#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 920#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 921#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1026#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 953#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 954#L233-1 assume !(0 == ~M_E~0); 970#L336-1 assume !(0 == ~T1_E~0); 1020#L341-1 assume !(0 == ~T2_E~0); 906#L346-1 assume !(0 == ~E_M~0); 907#L351-1 assume !(0 == ~E_1~0); 912#L356-1 assume !(0 == ~E_2~0); 913#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1037#L158 assume 1 == ~m_pc~0; 1038#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1035#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1059#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 936#L417 assume !(0 != activate_threads_~tmp~1); 937#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1058#L177 assume 1 == ~t1_pc~0; 918#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 897#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 898#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 996#L425 assume !(0 != activate_threads_~tmp___0~0); 1083#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 963#L196 assume !(1 == ~t2_pc~0); 964#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 977#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 978#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 971#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 972#L433-2 assume !(1 == ~M_E~0); 1057#L374-1 assume !(1 == ~T1_E~0); 927#L379-1 assume !(1 == ~T2_E~0); 916#L384-1 assume !(1 == ~E_M~0); 917#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1052#L394-1 assume !(1 == ~E_2~0); 1053#L545-1 [2021-10-13 01:09:10,287 INFO L793 eck$LassoCheckResult]: Loop: 1053#L545-1 assume !false; 929#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 925#L311 assume !false; 943#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 966#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 949#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1060#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1022#L278 assume !(0 != eval_~tmp~0); 1023#L326 start_simulation_~kernel_st~0 := 2; 960#L216-1 start_simulation_~kernel_st~0 := 3; 961#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1069#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1040#L341-3 assume !(0 == ~T2_E~0); 1041#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 982#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 983#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1027#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1028#L158-12 assume !(1 == ~m_pc~0); 1046#L158-14 is_master_triggered_~__retres1~0 := 0; 1039#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1001#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 910#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 911#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 877#L177-12 assume 1 == ~t1_pc~0; 878#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 899#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1013#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 958#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 959#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1010#L196-12 assume 1 == ~t2_pc~0; 1080#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1068#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 946#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 947#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1029#L433-14 assume !(1 == ~M_E~0); 1030#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 976#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 986#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1044#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 900#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 901#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 886#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1071#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 895#L564 assume !(0 == start_simulation_~tmp~3); 896#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1036#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 915#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1079#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1073#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1074#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 1078#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1061#L577 assume !(0 != start_simulation_~tmp___0~1); 1053#L545-1 [2021-10-13 01:09:10,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,288 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2021-10-13 01:09:10,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,288 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324436786] [2021-10-13 01:09:10,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,289 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,338 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,338 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324436786] [2021-10-13 01:09:10,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324436786] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,339 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,339 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:09:10,339 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243198793] [2021-10-13 01:09:10,340 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:10,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 1 times [2021-10-13 01:09:10,340 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,341 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387281594] [2021-10-13 01:09:10,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,341 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387281594] [2021-10-13 01:09:10,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387281594] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,420 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:10,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075100587] [2021-10-13 01:09:10,421 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:10,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:10,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:10,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:10,422 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. cyclomatic complexity: 110 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:10,503 INFO L93 Difference]: Finished difference Result 377 states and 559 transitions. [2021-10-13 01:09:10,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:10,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 559 transitions. [2021-10-13 01:09:10,508 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 338 [2021-10-13 01:09:10,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 559 transitions. [2021-10-13 01:09:10,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2021-10-13 01:09:10,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2021-10-13 01:09:10,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 377 states and 559 transitions. [2021-10-13 01:09:10,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:10,521 INFO L681 BuchiCegarLoop]: Abstraction has 377 states and 559 transitions. [2021-10-13 01:09:10,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states and 559 transitions. [2021-10-13 01:09:10,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 358. [2021-10-13 01:09:10,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 358 states, 358 states have (on average 1.488826815642458) internal successors, (533), 357 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 533 transitions. [2021-10-13 01:09:10,552 INFO L704 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2021-10-13 01:09:10,552 INFO L587 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2021-10-13 01:09:10,552 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-13 01:09:10,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 358 states and 533 transitions. [2021-10-13 01:09:10,554 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2021-10-13 01:09:10,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:10,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:10,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,559 INFO L791 eck$LassoCheckResult]: Stem: 1693#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1650#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1517#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1518#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1627#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1552#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1553#L233-1 assume !(0 == ~M_E~0); 1569#L336-1 assume !(0 == ~T1_E~0); 1621#L341-1 assume !(0 == ~T2_E~0); 1503#L346-1 assume !(0 == ~E_M~0); 1504#L351-1 assume !(0 == ~E_1~0); 1509#L356-1 assume !(0 == ~E_2~0); 1510#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1639#L158 assume !(1 == ~m_pc~0); 1636#L158-2 is_master_triggered_~__retres1~0 := 0; 1637#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1660#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1535#L417 assume !(0 != activate_threads_~tmp~1); 1536#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1659#L177 assume 1 == ~t1_pc~0; 1515#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1494#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1495#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1595#L425 assume !(0 != activate_threads_~tmp___0~0); 1690#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1562#L196 assume !(1 == ~t2_pc~0); 1563#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 1576#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1577#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1570#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1571#L433-2 assume !(1 == ~M_E~0); 1658#L374-1 assume !(1 == ~T1_E~0); 1524#L379-1 assume !(1 == ~T2_E~0); 1513#L384-1 assume !(1 == ~E_M~0); 1514#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1653#L394-1 assume !(1 == ~E_2~0); 1654#L545-1 [2021-10-13 01:09:10,561 INFO L793 eck$LassoCheckResult]: Loop: 1654#L545-1 assume !false; 1526#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1522#L311 assume !false; 1542#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1565#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1548#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1661#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1623#L278 assume !(0 != eval_~tmp~0); 1624#L326 start_simulation_~kernel_st~0 := 2; 1825#L216-1 start_simulation_~kernel_st~0 := 3; 1824#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1823#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1822#L341-3 assume !(0 == ~T2_E~0); 1821#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1820#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1674#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1628#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1629#L158-12 assume !(1 == ~m_pc~0); 1649#L158-14 is_master_triggered_~__retres1~0 := 0; 1640#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1600#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1507#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1508#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1472#L177-12 assume 1 == ~t1_pc~0; 1473#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1496#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1614#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1557#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1558#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1611#L196-12 assume 1 == ~t2_pc~0; 1687#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1672#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1545#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1546#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1630#L433-14 assume !(1 == ~M_E~0); 1631#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1575#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1585#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1645#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1497#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1498#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1482#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1675#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1491#L564 assume !(0 == start_simulation_~tmp~3); 1492#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1638#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1512#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1686#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1677#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1678#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 1685#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1662#L577 assume !(0 != start_simulation_~tmp___0~1); 1654#L545-1 [2021-10-13 01:09:10,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,561 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2021-10-13 01:09:10,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,563 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151324092] [2021-10-13 01:09:10,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,563 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,652 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151324092] [2021-10-13 01:09:10,652 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151324092] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,652 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,652 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:10,653 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702594221] [2021-10-13 01:09:10,653 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:10,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 2 times [2021-10-13 01:09:10,654 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:10,654 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121682436] [2021-10-13 01:09:10,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:10,655 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:10,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:10,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:10,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:10,718 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121682436] [2021-10-13 01:09:10,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121682436] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:10,718 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:10,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:10,719 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995382041] [2021-10-13 01:09:10,719 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:10,719 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:10,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:09:10,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:09:10,721 INFO L87 Difference]: Start difference. First operand 358 states and 533 transitions. cyclomatic complexity: 177 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:10,885 INFO L93 Difference]: Finished difference Result 792 states and 1155 transitions. [2021-10-13 01:09:10,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:09:10,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1155 transitions. [2021-10-13 01:09:10,895 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 727 [2021-10-13 01:09:10,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1155 transitions. [2021-10-13 01:09:10,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2021-10-13 01:09:10,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2021-10-13 01:09:10,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1155 transitions. [2021-10-13 01:09:10,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:10,906 INFO L681 BuchiCegarLoop]: Abstraction has 792 states and 1155 transitions. [2021-10-13 01:09:10,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1155 transitions. [2021-10-13 01:09:10,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 623. [2021-10-13 01:09:10,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 623 states, 623 states have (on average 1.4751203852327448) internal successors, (919), 622 states have internal predecessors, (919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:10,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 919 transitions. [2021-10-13 01:09:10,975 INFO L704 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2021-10-13 01:09:10,975 INFO L587 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2021-10-13 01:09:10,976 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-13 01:09:10,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 623 states and 919 transitions. [2021-10-13 01:09:10,981 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 584 [2021-10-13 01:09:10,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:10,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:10,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:10,998 INFO L791 eck$LassoCheckResult]: Stem: 2867#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2810#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2674#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2675#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 2786#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2707#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2708#L233-1 assume !(0 == ~M_E~0); 2725#L336-1 assume !(0 == ~T1_E~0); 2780#L341-1 assume !(0 == ~T2_E~0); 2660#L346-1 assume !(0 == ~E_M~0); 2661#L351-1 assume !(0 == ~E_1~0); 2666#L356-1 assume !(0 == ~E_2~0); 2667#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2799#L158 assume !(1 == ~m_pc~0); 2796#L158-2 is_master_triggered_~__retres1~0 := 0; 2797#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2825#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2690#L417 assume !(0 != activate_threads_~tmp~1); 2691#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2823#L177 assume !(1 == ~t1_pc~0); 2824#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 2651#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2652#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2756#L425 assume !(0 != activate_threads_~tmp___0~0); 2859#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2722#L196 assume !(1 == ~t2_pc~0); 2723#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 2732#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2733#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2726#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2727#L433-2 assume !(1 == ~M_E~0); 2822#L374-1 assume !(1 == ~T1_E~0); 2679#L379-1 assume !(1 == ~T2_E~0); 2670#L384-1 assume !(1 == ~E_M~0); 2671#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2816#L394-1 assume !(1 == ~E_2~0); 2817#L545-1 [2021-10-13 01:09:10,998 INFO L793 eck$LassoCheckResult]: Loop: 2817#L545-1 assume !false; 2681#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2677#L311 assume !false; 2697#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2718#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2703#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2826#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2782#L278 assume !(0 != eval_~tmp~0); 2783#L326 start_simulation_~kernel_st~0 := 2; 2715#L216-1 start_simulation_~kernel_st~0 := 3; 2716#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2838#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2801#L341-3 assume !(0 == ~T2_E~0); 2802#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2737#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2738#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2789#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2790#L158-12 assume !(1 == ~m_pc~0); 2809#L158-14 is_master_triggered_~__retres1~0 := 0; 2800#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2760#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2664#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2665#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2632#L177-12 assume !(1 == ~t1_pc~0); 2633#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 2653#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2773#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2713#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2714#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2770#L196-12 assume 1 == ~t2_pc~0; 2854#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2837#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2700#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2701#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2787#L433-14 assume !(1 == ~M_E~0); 2788#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2730#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2731#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2741#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2806#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2654#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2655#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2640#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2843#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2649#L564 assume !(0 == start_simulation_~tmp~3); 2650#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2798#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2669#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2852#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2845#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2846#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 2851#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2827#L577 assume !(0 != start_simulation_~tmp___0~1); 2817#L545-1 [2021-10-13 01:09:10,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:10,999 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2021-10-13 01:09:11,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110167110] [2021-10-13 01:09:11,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,000 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,088 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110167110] [2021-10-13 01:09:11,088 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110167110] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,088 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:09:11,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260500039] [2021-10-13 01:09:11,091 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:11,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 2 times [2021-10-13 01:09:11,092 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,092 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364638630] [2021-10-13 01:09:11,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,092 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,155 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364638630] [2021-10-13 01:09:11,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364638630] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,155 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,156 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,156 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261895179] [2021-10-13 01:09:11,156 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:11,157 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:11,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:09:11,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:09:11,159 INFO L87 Difference]: Start difference. First operand 623 states and 919 transitions. cyclomatic complexity: 298 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:11,280 INFO L93 Difference]: Finished difference Result 1454 states and 2154 transitions. [2021-10-13 01:09:11,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:09:11,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1454 states and 2154 transitions. [2021-10-13 01:09:11,295 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2021-10-13 01:09:11,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1454 states to 1454 states and 2154 transitions. [2021-10-13 01:09:11,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1454 [2021-10-13 01:09:11,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1454 [2021-10-13 01:09:11,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1454 states and 2154 transitions. [2021-10-13 01:09:11,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:11,314 INFO L681 BuchiCegarLoop]: Abstraction has 1454 states and 2154 transitions. [2021-10-13 01:09:11,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1454 states and 2154 transitions. [2021-10-13 01:09:11,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1454 to 674. [2021-10-13 01:09:11,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.4391691394658754) internal successors, (970), 673 states have internal predecessors, (970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 970 transitions. [2021-10-13 01:09:11,338 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2021-10-13 01:09:11,338 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2021-10-13 01:09:11,338 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-13 01:09:11,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 970 transitions. [2021-10-13 01:09:11,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-13 01:09:11,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:11,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:11,346 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,346 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,346 INFO L791 eck$LassoCheckResult]: Stem: 4980#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4912#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4765#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4766#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 4886#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4801#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4802#L233-1 assume !(0 == ~M_E~0); 4819#L336-1 assume !(0 == ~T1_E~0); 4879#L341-1 assume !(0 == ~T2_E~0); 4753#L346-1 assume !(0 == ~E_M~0); 4754#L351-1 assume !(0 == ~E_1~0); 4759#L356-1 assume !(0 == ~E_2~0); 4760#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4899#L158 assume !(1 == ~m_pc~0); 4896#L158-2 is_master_triggered_~__retres1~0 := 0; 4897#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4928#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4784#L417 assume !(0 != activate_threads_~tmp~1); 4785#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4926#L177 assume !(1 == ~t1_pc~0); 4927#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 4743#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4744#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4851#L425 assume !(0 != activate_threads_~tmp___0~0); 4968#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4814#L196 assume !(1 == ~t2_pc~0); 4815#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 4826#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4827#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4820#L433 assume !(0 != activate_threads_~tmp___1~0); 4821#L433-2 assume !(1 == ~M_E~0); 4923#L374-1 assume !(1 == ~T1_E~0); 4772#L379-1 assume !(1 == ~T2_E~0); 4763#L384-1 assume !(1 == ~E_M~0); 4764#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4918#L394-1 assume !(1 == ~E_2~0); 4919#L545-1 [2021-10-13 01:09:11,348 INFO L793 eck$LassoCheckResult]: Loop: 4919#L545-1 assume !false; 5146#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5143#L311 assume !false; 4852#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4817#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4800#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4929#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4882#L278 assume !(0 != eval_~tmp~0); 4883#L326 start_simulation_~kernel_st~0 := 2; 5098#L216-1 start_simulation_~kernel_st~0 := 3; 5092#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5090#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5088#L341-3 assume !(0 == ~T2_E~0); 5087#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5086#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5082#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5080#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5078#L158-12 assume !(1 == ~m_pc~0); 5079#L158-14 is_master_triggered_~__retres1~0 := 0; 5322#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5321#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5320#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5319#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5318#L177-12 assume !(1 == ~t1_pc~0); 5287#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 5317#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5316#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5315#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5314#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5313#L196-12 assume !(1 == ~t2_pc~0); 5312#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 5310#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5308#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5306#L433-12 assume !(0 != activate_threads_~tmp___1~0); 5304#L433-14 assume !(1 == ~M_E~0); 5270#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5268#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5266#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5264#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5262#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5260#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5256#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5254#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5250#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5247#L564 assume !(0 == start_simulation_~tmp~3); 5248#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5351#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5346#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5303#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5302#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5300#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 5295#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5292#L577 assume !(0 != start_simulation_~tmp___0~1); 4919#L545-1 [2021-10-13 01:09:11,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330394, now seen corresponding path program 1 times [2021-10-13 01:09:11,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542291040] [2021-10-13 01:09:11,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,350 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,401 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,401 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542291040] [2021-10-13 01:09:11,402 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542291040] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,402 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,402 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196069076] [2021-10-13 01:09:11,404 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:11,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,405 INFO L82 PathProgramCache]: Analyzing trace with hash 817558789, now seen corresponding path program 1 times [2021-10-13 01:09:11,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,406 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299501195] [2021-10-13 01:09:11,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,406 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,462 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299501195] [2021-10-13 01:09:11,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299501195] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,463 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,463 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,463 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874675084] [2021-10-13 01:09:11,464 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:11,464 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:11,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:09:11,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:09:11,465 INFO L87 Difference]: Start difference. First operand 674 states and 970 transitions. cyclomatic complexity: 298 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:11,590 INFO L93 Difference]: Finished difference Result 1102 states and 1558 transitions. [2021-10-13 01:09:11,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:09:11,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1102 states and 1558 transitions. [2021-10-13 01:09:11,601 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 994 [2021-10-13 01:09:11,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1102 states to 1102 states and 1558 transitions. [2021-10-13 01:09:11,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1102 [2021-10-13 01:09:11,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1102 [2021-10-13 01:09:11,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1102 states and 1558 transitions. [2021-10-13 01:09:11,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:11,615 INFO L681 BuchiCegarLoop]: Abstraction has 1102 states and 1558 transitions. [2021-10-13 01:09:11,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1102 states and 1558 transitions. [2021-10-13 01:09:11,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1102 to 1080. [2021-10-13 01:09:11,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1080 states, 1080 states have (on average 1.4185185185185185) internal successors, (1532), 1079 states have internal predecessors, (1532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1080 states to 1080 states and 1532 transitions. [2021-10-13 01:09:11,638 INFO L704 BuchiCegarLoop]: Abstraction has 1080 states and 1532 transitions. [2021-10-13 01:09:11,639 INFO L587 BuchiCegarLoop]: Abstraction has 1080 states and 1532 transitions. [2021-10-13 01:09:11,639 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-13 01:09:11,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1080 states and 1532 transitions. [2021-10-13 01:09:11,667 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 980 [2021-10-13 01:09:11,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:11,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:11,669 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,669 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,670 INFO L791 eck$LassoCheckResult]: Stem: 6774#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6701#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6550#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6551#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 6673#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6587#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6588#L233-1 assume !(0 == ~M_E~0); 6605#L336-1 assume !(0 == ~T1_E~0); 6666#L341-1 assume !(0 == ~T2_E~0); 6537#L346-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6538#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6698#L356-1 assume !(0 == ~E_2~0); 7256#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6686#L158 assume !(1 == ~m_pc~0); 6687#L158-2 is_master_triggered_~__retres1~0 := 0; 7250#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7237#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7238#L417 assume !(0 != activate_threads_~tmp~1); 7231#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7232#L177 assume !(1 == ~t1_pc~0); 7230#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 7229#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7227#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7225#L425 assume !(0 != activate_threads_~tmp___0~0); 7223#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7221#L196 assume !(1 == ~t2_pc~0); 7219#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 7236#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7233#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7210#L433 assume !(0 != activate_threads_~tmp___1~0); 6712#L433-2 assume !(1 == ~M_E~0); 6713#L374-1 assume !(1 == ~T1_E~0); 6557#L379-1 assume !(1 == ~T2_E~0); 6548#L384-1 assume !(1 == ~E_M~0); 6549#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6706#L394-1 assume !(1 == ~E_2~0); 6707#L545-1 [2021-10-13 01:09:11,670 INFO L793 eck$LassoCheckResult]: Loop: 6707#L545-1 assume !false; 7182#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7475#L311 assume !false; 7474#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7172#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7173#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7162#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7163#L278 assume !(0 != eval_~tmp~0); 7469#L326 start_simulation_~kernel_st~0 := 2; 7585#L216-1 start_simulation_~kernel_st~0 := 3; 7584#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7583#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7582#L341-3 assume !(0 == ~T2_E~0); 7581#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6718#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6620#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6676#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6677#L158-12 assume !(1 == ~m_pc~0); 6700#L158-14 is_master_triggered_~__retres1~0 := 0; 6688#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6689#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6542#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6543#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6508#L177-12 assume !(1 == ~t1_pc~0); 6509#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 6530#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6658#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6659#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7531#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7530#L196-12 assume !(1 == ~t2_pc~0); 7526#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 7524#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7522#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7520#L433-12 assume !(0 != activate_threads_~tmp___1~0); 7518#L433-14 assume !(1 == ~M_E~0); 7517#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7513#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7511#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7507#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7504#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7502#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7498#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7495#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7493#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7491#L564 assume !(0 == start_simulation_~tmp~3); 7489#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7487#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7485#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7484#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7483#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7482#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 7481#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7195#L577 assume !(0 != start_simulation_~tmp___0~1); 6707#L545-1 [2021-10-13 01:09:11,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,671 INFO L82 PathProgramCache]: Analyzing trace with hash 335369254, now seen corresponding path program 1 times [2021-10-13 01:09:11,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,672 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866352064] [2021-10-13 01:09:11,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,672 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,695 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866352064] [2021-10-13 01:09:11,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866352064] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:09:11,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657312443] [2021-10-13 01:09:11,697 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:11,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,697 INFO L82 PathProgramCache]: Analyzing trace with hash 817558789, now seen corresponding path program 2 times [2021-10-13 01:09:11,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538661451] [2021-10-13 01:09:11,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,698 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,728 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538661451] [2021-10-13 01:09:11,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538661451] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,729 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787436514] [2021-10-13 01:09:11,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:11,730 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:11,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:11,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:11,731 INFO L87 Difference]: Start difference. First operand 1080 states and 1532 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:11,764 INFO L93 Difference]: Finished difference Result 1051 states and 1463 transitions. [2021-10-13 01:09:11,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:11,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1051 states and 1463 transitions. [2021-10-13 01:09:11,775 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 980 [2021-10-13 01:09:11,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1051 states to 1051 states and 1463 transitions. [2021-10-13 01:09:11,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1051 [2021-10-13 01:09:11,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1051 [2021-10-13 01:09:11,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1051 states and 1463 transitions. [2021-10-13 01:09:11,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:11,789 INFO L681 BuchiCegarLoop]: Abstraction has 1051 states and 1463 transitions. [2021-10-13 01:09:11,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1051 states and 1463 transitions. [2021-10-13 01:09:11,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1051 to 816. [2021-10-13 01:09:11,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 816 states, 816 states have (on average 1.3848039215686274) internal successors, (1130), 815 states have internal predecessors, (1130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 816 states to 816 states and 1130 transitions. [2021-10-13 01:09:11,809 INFO L704 BuchiCegarLoop]: Abstraction has 816 states and 1130 transitions. [2021-10-13 01:09:11,810 INFO L587 BuchiCegarLoop]: Abstraction has 816 states and 1130 transitions. [2021-10-13 01:09:11,810 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-13 01:09:11,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 816 states and 1130 transitions. [2021-10-13 01:09:11,816 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 746 [2021-10-13 01:09:11,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:11,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:11,819 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,820 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:11,820 INFO L791 eck$LassoCheckResult]: Stem: 8889#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8830#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8687#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8688#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 8805#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8721#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8722#L233-1 assume !(0 == ~M_E~0); 8739#L336-1 assume !(0 == ~T1_E~0); 8798#L341-1 assume !(0 == ~T2_E~0); 8675#L346-1 assume !(0 == ~E_M~0); 8676#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8828#L356-1 assume !(0 == ~E_2~0); 9448#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9447#L158 assume !(1 == ~m_pc~0); 9446#L158-2 is_master_triggered_~__retres1~0 := 0; 9445#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9444#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9443#L417 assume !(0 != activate_threads_~tmp~1); 9442#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9441#L177 assume !(1 == ~t1_pc~0); 9440#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 9439#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9438#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9437#L425 assume !(0 != activate_threads_~tmp___0~0); 9436#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9435#L196 assume !(1 == ~t2_pc~0); 9434#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 9450#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9449#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9427#L433 assume !(0 != activate_threads_~tmp___1~0); 9426#L433-2 assume !(1 == ~M_E~0); 9425#L374-1 assume !(1 == ~T1_E~0); 9424#L379-1 assume !(1 == ~T2_E~0); 9423#L384-1 assume !(1 == ~E_M~0); 9422#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8834#L394-1 assume !(1 == ~E_2~0); 8835#L545-1 [2021-10-13 01:09:11,821 INFO L793 eck$LassoCheckResult]: Loop: 8835#L545-1 assume !false; 9311#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9288#L311 assume !false; 9286#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9280#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9278#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9276#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9271#L278 assume !(0 != eval_~tmp~0); 9272#L326 start_simulation_~kernel_st~0 := 2; 9412#L216-1 start_simulation_~kernel_st~0 := 3; 9411#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9410#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9409#L341-3 assume !(0 == ~T2_E~0); 9408#L346-3 assume !(0 == ~E_M~0); 9407#L351-3 assume !(0 == ~E_1~0); 8860#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8808#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8809#L158-12 assume !(1 == ~m_pc~0); 8829#L158-14 is_master_triggered_~__retres1~0 := 0; 8818#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8776#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8679#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8680#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8646#L177-12 assume !(1 == ~t1_pc~0); 8647#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 9362#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9360#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9357#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9355#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9353#L196-12 assume !(1 == ~t2_pc~0); 9349#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 9347#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9345#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9343#L433-12 assume !(0 != activate_threads_~tmp___1~0); 9341#L433-14 assume !(1 == ~M_E~0); 9340#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9336#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9315#L384-3 assume !(1 == ~E_M~0); 9291#L389-3 assume !(1 == ~E_1~0); 9289#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9287#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9284#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9279#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9277#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9274#L564 assume !(0 == start_simulation_~tmp~3); 9275#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9338#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9335#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9334#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9333#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9321#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 9319#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9318#L577 assume !(0 != start_simulation_~tmp___0~1); 8835#L545-1 [2021-10-13 01:09:11,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,821 INFO L82 PathProgramCache]: Analyzing trace with hash -2036370008, now seen corresponding path program 1 times [2021-10-13 01:09:11,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,822 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501456418] [2021-10-13 01:09:11,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,822 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,865 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501456418] [2021-10-13 01:09:11,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501456418] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,865 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1350739357] [2021-10-13 01:09:11,866 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:11,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:11,867 INFO L82 PathProgramCache]: Analyzing trace with hash -405580411, now seen corresponding path program 1 times [2021-10-13 01:09:11,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:11,867 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052098767] [2021-10-13 01:09:11,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:11,868 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:11,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:11,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:11,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:11,897 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052098767] [2021-10-13 01:09:11,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052098767] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:11,902 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:11,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:11,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243853258] [2021-10-13 01:09:11,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:11,904 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:11,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:09:11,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:09:11,905 INFO L87 Difference]: Start difference. First operand 816 states and 1130 transitions. cyclomatic complexity: 316 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:11,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:11,982 INFO L93 Difference]: Finished difference Result 916 states and 1264 transitions. [2021-10-13 01:09:11,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:09:11,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 916 states and 1264 transitions. [2021-10-13 01:09:11,992 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 866 [2021-10-13 01:09:12,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 916 states to 916 states and 1264 transitions. [2021-10-13 01:09:12,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 916 [2021-10-13 01:09:12,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 916 [2021-10-13 01:09:12,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 916 states and 1264 transitions. [2021-10-13 01:09:12,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,009 INFO L681 BuchiCegarLoop]: Abstraction has 916 states and 1264 transitions. [2021-10-13 01:09:12,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states and 1264 transitions. [2021-10-13 01:09:12,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 674. [2021-10-13 01:09:12,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.3753709198813056) internal successors, (927), 673 states have internal predecessors, (927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 927 transitions. [2021-10-13 01:09:12,029 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 927 transitions. [2021-10-13 01:09:12,029 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 927 transitions. [2021-10-13 01:09:12,029 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-13 01:09:12,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 927 transitions. [2021-10-13 01:09:12,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-13 01:09:12,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,035 INFO L791 eck$LassoCheckResult]: Stem: 10634#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10573#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10430#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10431#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 10546#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10465#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10466#L233-1 assume !(0 == ~M_E~0); 10483#L336-1 assume !(0 == ~T1_E~0); 10540#L341-1 assume !(0 == ~T2_E~0); 10418#L346-1 assume !(0 == ~E_M~0); 10419#L351-1 assume !(0 == ~E_1~0); 10424#L356-1 assume !(0 == ~E_2~0); 10425#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10558#L158 assume !(1 == ~m_pc~0); 10555#L158-2 is_master_triggered_~__retres1~0 := 0; 10556#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10586#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10447#L417 assume !(0 != activate_threads_~tmp~1); 10448#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10583#L177 assume !(1 == ~t1_pc~0); 10584#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 10408#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10409#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10512#L425 assume !(0 != activate_threads_~tmp___0~0); 10623#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10476#L196 assume !(1 == ~t2_pc~0); 10477#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 10635#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10652#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10484#L433 assume !(0 != activate_threads_~tmp___1~0); 10485#L433-2 assume !(1 == ~M_E~0); 10582#L374-1 assume !(1 == ~T1_E~0); 10437#L379-1 assume !(1 == ~T2_E~0); 10428#L384-1 assume !(1 == ~E_M~0); 10429#L389-1 assume !(1 == ~E_1~0); 10576#L394-1 assume !(1 == ~E_2~0); 10577#L545-1 [2021-10-13 01:09:12,036 INFO L793 eck$LassoCheckResult]: Loop: 10577#L545-1 assume !false; 11001#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10454#L311 assume !false; 10455#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10998#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10997#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10996#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10982#L278 assume !(0 != eval_~tmp~0); 10571#L326 start_simulation_~kernel_st~0 := 2; 10473#L216-1 start_simulation_~kernel_st~0 := 3; 10474#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10600#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10561#L341-3 assume !(0 == ~T2_E~0); 10562#L346-3 assume !(0 == ~E_M~0); 10497#L351-3 assume !(0 == ~E_1~0); 10498#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10547#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10548#L158-12 assume !(1 == ~m_pc~0); 10572#L158-14 is_master_triggered_~__retres1~0 := 0; 10559#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10518#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10422#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10423#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10388#L177-12 assume !(1 == ~t1_pc~0); 10389#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 11032#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10534#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10471#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10472#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10530#L196-12 assume 1 == ~t2_pc~0; 10632#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11028#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11026#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11024#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10614#L433-14 assume !(1 == ~M_E~0); 11021#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10488#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10489#L384-3 assume !(1 == ~E_M~0); 10501#L389-3 assume !(1 == ~E_1~0); 10565#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10412#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10413#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10396#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10637#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11011#L564 assume !(0 == start_simulation_~tmp~3); 11012#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11038#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11036#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11035#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 11034#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11006#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 11005#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 11004#L577 assume !(0 != start_simulation_~tmp___0~1); 10577#L545-1 [2021-10-13 01:09:12,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,036 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2021-10-13 01:09:12,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,037 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831422227] [2021-10-13 01:09:12,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,037 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,060 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:12,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,099 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:12,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,100 INFO L82 PathProgramCache]: Analyzing trace with hash 2002463016, now seen corresponding path program 1 times [2021-10-13 01:09:12,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,100 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435362958] [2021-10-13 01:09:12,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,101 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,122 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435362958] [2021-10-13 01:09:12,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435362958] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,123 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,123 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:12,123 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398774776] [2021-10-13 01:09:12,124 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:12,124 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:12,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:12,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:12,125 INFO L87 Difference]: Start difference. First operand 674 states and 927 transitions. cyclomatic complexity: 255 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:12,147 INFO L93 Difference]: Finished difference Result 818 states and 1111 transitions. [2021-10-13 01:09:12,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:12,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 818 states and 1111 transitions. [2021-10-13 01:09:12,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 748 [2021-10-13 01:09:12,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 818 states to 818 states and 1111 transitions. [2021-10-13 01:09:12,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 818 [2021-10-13 01:09:12,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 818 [2021-10-13 01:09:12,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 818 states and 1111 transitions. [2021-10-13 01:09:12,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,170 INFO L681 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-13 01:09:12,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 818 states and 1111 transitions. [2021-10-13 01:09:12,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 818 to 818. [2021-10-13 01:09:12,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 818 states, 818 states have (on average 1.3581907090464547) internal successors, (1111), 817 states have internal predecessors, (1111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 818 states to 818 states and 1111 transitions. [2021-10-13 01:09:12,186 INFO L704 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-13 01:09:12,186 INFO L587 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-13 01:09:12,186 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-13 01:09:12,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 818 states and 1111 transitions. [2021-10-13 01:09:12,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 748 [2021-10-13 01:09:12,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,193 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,193 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,193 INFO L791 eck$LassoCheckResult]: Stem: 12138#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12072#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11928#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11929#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 12047#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11961#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11962#L233-1 assume 0 == ~M_E~0;~M_E~0 := 1; 11979#L336-1 assume !(0 == ~T1_E~0); 12039#L341-1 assume !(0 == ~T2_E~0); 11916#L346-1 assume !(0 == ~E_M~0); 11917#L351-1 assume !(0 == ~E_1~0); 11922#L356-1 assume !(0 == ~E_2~0); 11923#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12059#L158 assume !(1 == ~m_pc~0); 12056#L158-2 is_master_triggered_~__retres1~0 := 0; 12057#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12083#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11943#L417 assume !(0 != activate_threads_~tmp~1); 11944#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12081#L177 assume !(1 == ~t1_pc~0); 12082#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 11907#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11908#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12011#L425 assume !(0 != activate_threads_~tmp___0~0); 12128#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11972#L196 assume !(1 == ~t2_pc~0); 11973#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 11987#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11988#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11981#L433 assume !(0 != activate_threads_~tmp___1~0); 11982#L433-2 assume 1 == ~M_E~0;~M_E~0 := 2; 12080#L374-1 assume !(1 == ~T1_E~0); 11935#L379-1 assume !(1 == ~T2_E~0); 11926#L384-1 assume !(1 == ~E_M~0); 11927#L389-1 assume !(1 == ~E_1~0); 12075#L394-1 assume !(1 == ~E_2~0); 12076#L545-1 [2021-10-13 01:09:12,193 INFO L793 eck$LassoCheckResult]: Loop: 12076#L545-1 assume !false; 12350#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12326#L311 assume !false; 12349#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11975#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11957#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12084#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12085#L278 assume !(0 != eval_~tmp~0); 12070#L326 start_simulation_~kernel_st~0 := 2; 11969#L216-1 start_simulation_~kernel_st~0 := 3; 11970#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12099#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12061#L341-3 assume !(0 == ~T2_E~0); 12062#L346-3 assume !(0 == ~E_M~0); 11993#L351-3 assume !(0 == ~E_1~0); 11994#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12048#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12049#L158-12 assume !(1 == ~m_pc~0); 12071#L158-14 is_master_triggered_~__retres1~0 := 0; 12060#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12017#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11920#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11921#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12010#L177-12 assume !(1 == ~t1_pc~0); 12518#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 12516#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12514#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12512#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12510#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12506#L196-12 assume !(1 == ~t2_pc~0); 12502#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 12500#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12498#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12495#L433-12 assume !(0 != activate_threads_~tmp___1~0); 12493#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 12489#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12487#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12485#L384-3 assume !(1 == ~E_M~0); 12483#L389-3 assume !(1 == ~E_1~0); 12481#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12479#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12475#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12472#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12470#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 12467#L564 assume !(0 == start_simulation_~tmp~3); 12464#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12372#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12367#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12365#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 12105#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12106#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 12115#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12116#L577 assume !(0 != start_simulation_~tmp___0~1); 12076#L545-1 [2021-10-13 01:09:12,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,194 INFO L82 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2021-10-13 01:09:12,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,194 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511816038] [2021-10-13 01:09:12,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,195 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,216 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,216 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511816038] [2021-10-13 01:09:12,216 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511816038] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,216 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,216 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:09:12,216 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954347753] [2021-10-13 01:09:12,217 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:12,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,218 INFO L82 PathProgramCache]: Analyzing trace with hash 1283363331, now seen corresponding path program 1 times [2021-10-13 01:09:12,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,218 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138959767] [2021-10-13 01:09:12,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,219 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,253 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138959767] [2021-10-13 01:09:12,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138959767] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,254 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:09:12,254 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147990333] [2021-10-13 01:09:12,255 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:12,255 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:12,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:12,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:12,256 INFO L87 Difference]: Start difference. First operand 818 states and 1111 transitions. cyclomatic complexity: 295 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:12,278 INFO L93 Difference]: Finished difference Result 674 states and 913 transitions. [2021-10-13 01:09:12,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:12,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 674 states and 913 transitions. [2021-10-13 01:09:12,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-13 01:09:12,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 674 states to 674 states and 913 transitions. [2021-10-13 01:09:12,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 674 [2021-10-13 01:09:12,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 674 [2021-10-13 01:09:12,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 674 states and 913 transitions. [2021-10-13 01:09:12,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,311 INFO L681 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-13 01:09:12,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states and 913 transitions. [2021-10-13 01:09:12,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 674. [2021-10-13 01:09:12,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.3545994065281899) internal successors, (913), 673 states have internal predecessors, (913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 913 transitions. [2021-10-13 01:09:12,324 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-13 01:09:12,324 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-13 01:09:12,327 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-13 01:09:12,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 913 transitions. [2021-10-13 01:09:12,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-13 01:09:12,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,339 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,339 INFO L791 eck$LassoCheckResult]: Stem: 13620#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13564#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13429#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13430#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 13540#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13461#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13462#L233-1 assume !(0 == ~M_E~0); 13480#L336-1 assume !(0 == ~T1_E~0); 13533#L341-1 assume !(0 == ~T2_E~0); 13417#L346-1 assume !(0 == ~E_M~0); 13418#L351-1 assume !(0 == ~E_1~0); 13423#L356-1 assume !(0 == ~E_2~0); 13424#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13552#L158 assume !(1 == ~m_pc~0); 13549#L158-2 is_master_triggered_~__retres1~0 := 0; 13550#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13579#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13444#L417 assume !(0 != activate_threads_~tmp~1); 13445#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13576#L177 assume !(1 == ~t1_pc~0); 13577#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 13407#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13408#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13509#L425 assume !(0 != activate_threads_~tmp___0~0); 13614#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13473#L196 assume !(1 == ~t2_pc~0); 13474#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 13621#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13616#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13481#L433 assume !(0 != activate_threads_~tmp___1~0); 13482#L433-2 assume !(1 == ~M_E~0); 13575#L374-1 assume !(1 == ~T1_E~0); 13436#L379-1 assume !(1 == ~T2_E~0); 13427#L384-1 assume !(1 == ~E_M~0); 13428#L389-1 assume !(1 == ~E_1~0); 13570#L394-1 assume !(1 == ~E_2~0); 13571#L545-1 [2021-10-13 01:09:12,339 INFO L793 eck$LassoCheckResult]: Loop: 13571#L545-1 assume !false; 13877#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13875#L311 assume !false; 13871#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13868#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13736#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13732#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 13729#L278 assume !(0 != eval_~tmp~0); 13730#L326 start_simulation_~kernel_st~0 := 2; 14026#L216-1 start_simulation_~kernel_st~0 := 3; 14025#L336-2 assume !(0 == ~M_E~0); 14024#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14023#L341-3 assume !(0 == ~T2_E~0); 13578#L346-3 assume !(0 == ~E_M~0); 13493#L351-3 assume !(0 == ~E_1~0); 13494#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13541#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13542#L158-12 assume !(1 == ~m_pc~0); 13563#L158-14 is_master_triggered_~__retres1~0 := 0; 13553#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13514#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13421#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13422#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13508#L177-12 assume !(1 == ~t1_pc~0); 13828#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 13964#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13962#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13960#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13958#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13951#L196-12 assume !(1 == ~t2_pc~0); 13947#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 13945#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13943#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13941#L433-12 assume !(0 != activate_threads_~tmp___1~0); 13939#L433-14 assume !(1 == ~M_E~0); 13935#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13933#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13931#L384-3 assume !(1 == ~E_M~0); 13929#L389-3 assume !(1 == ~E_1~0); 13926#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13924#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13920#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13917#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13915#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 13913#L564 assume !(0 == start_simulation_~tmp~3); 13908#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13900#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13897#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13894#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 13892#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13890#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 13888#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 13886#L577 assume !(0 != start_simulation_~tmp___0~1); 13571#L545-1 [2021-10-13 01:09:12,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,341 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2021-10-13 01:09:12,341 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,346 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246867428] [2021-10-13 01:09:12,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,348 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,356 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:12,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,383 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:12,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,384 INFO L82 PathProgramCache]: Analyzing trace with hash -1302973689, now seen corresponding path program 1 times [2021-10-13 01:09:12,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,384 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230630509] [2021-10-13 01:09:12,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,413 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,413 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230630509] [2021-10-13 01:09:12,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230630509] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,413 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:09:12,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658860406] [2021-10-13 01:09:12,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:12,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:12,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:09:12,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:09:12,417 INFO L87 Difference]: Start difference. First operand 674 states and 913 transitions. cyclomatic complexity: 241 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:12,506 INFO L93 Difference]: Finished difference Result 1156 states and 1546 transitions. [2021-10-13 01:09:12,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-13 01:09:12,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1156 states and 1546 transitions. [2021-10-13 01:09:12,541 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1112 [2021-10-13 01:09:12,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1156 states to 1156 states and 1546 transitions. [2021-10-13 01:09:12,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1156 [2021-10-13 01:09:12,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1156 [2021-10-13 01:09:12,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1156 states and 1546 transitions. [2021-10-13 01:09:12,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,555 INFO L681 BuchiCegarLoop]: Abstraction has 1156 states and 1546 transitions. [2021-10-13 01:09:12,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states and 1546 transitions. [2021-10-13 01:09:12,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 686. [2021-10-13 01:09:12,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.348396501457726) internal successors, (925), 685 states have internal predecessors, (925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 925 transitions. [2021-10-13 01:09:12,572 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 925 transitions. [2021-10-13 01:09:12,573 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 925 transitions. [2021-10-13 01:09:12,573 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-13 01:09:12,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 925 transitions. [2021-10-13 01:09:12,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 644 [2021-10-13 01:09:12,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,579 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,579 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,579 INFO L791 eck$LassoCheckResult]: Stem: 15485#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 15418#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15276#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15277#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 15391#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15309#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15310#L233-1 assume !(0 == ~M_E~0); 15327#L336-1 assume !(0 == ~T1_E~0); 15386#L341-1 assume !(0 == ~T2_E~0); 15262#L346-1 assume !(0 == ~E_M~0); 15263#L351-1 assume !(0 == ~E_1~0); 15268#L356-1 assume !(0 == ~E_2~0); 15269#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15403#L158 assume !(1 == ~m_pc~0); 15400#L158-2 is_master_triggered_~__retres1~0 := 0; 15401#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15430#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15291#L417 assume !(0 != activate_threads_~tmp~1); 15292#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15428#L177 assume !(1 == ~t1_pc~0); 15429#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 15253#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15254#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15361#L425 assume !(0 != activate_threads_~tmp___0~0); 15474#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15324#L196 assume !(1 == ~t2_pc~0); 15325#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 15486#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15475#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15328#L433 assume !(0 != activate_threads_~tmp___1~0); 15329#L433-2 assume !(1 == ~M_E~0); 15427#L374-1 assume !(1 == ~T1_E~0); 15281#L379-1 assume !(1 == ~T2_E~0); 15272#L384-1 assume !(1 == ~E_M~0); 15273#L389-1 assume !(1 == ~E_1~0); 15421#L394-1 assume !(1 == ~E_2~0); 15422#L545-1 [2021-10-13 01:09:12,579 INFO L793 eck$LassoCheckResult]: Loop: 15422#L545-1 assume !false; 15284#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15279#L311 assume !false; 15298#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15320#L246 assume !(0 == ~m_st~0); 15321#L250 assume !(0 == ~t1_st~0); 15306#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 15308#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15487#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 15895#L278 assume !(0 != eval_~tmp~0); 15414#L326 start_simulation_~kernel_st~0 := 2; 15317#L216-1 start_simulation_~kernel_st~0 := 3; 15318#L336-2 assume !(0 == ~M_E~0); 15446#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15406#L341-3 assume !(0 == ~T2_E~0); 15407#L346-3 assume !(0 == ~E_M~0); 15339#L351-3 assume !(0 == ~E_1~0); 15340#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15392#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15393#L158-12 assume !(1 == ~m_pc~0); 15417#L158-14 is_master_triggered_~__retres1~0 := 0; 15404#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15405#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15266#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15267#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15233#L177-12 assume !(1 == ~t1_pc~0); 15234#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 15255#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15379#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15315#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15316#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15376#L196-12 assume 1 == ~t2_pc~0; 15852#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15850#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15848#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15846#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15845#L433-14 assume !(1 == ~M_E~0); 15844#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15843#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15842#L384-3 assume !(1 == ~E_M~0); 15841#L389-3 assume !(1 == ~E_1~0); 15840#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15839#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15837#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15833#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15830#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 15824#L564 assume !(0 == start_simulation_~tmp~3); 15820#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15402#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15271#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15461#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 15451#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15452#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 15756#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15432#L577 assume !(0 != start_simulation_~tmp___0~1); 15422#L545-1 [2021-10-13 01:09:12,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2021-10-13 01:09:12,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,580 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543137379] [2021-10-13 01:09:12,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,581 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,590 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:12,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,614 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:12,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1261903409, now seen corresponding path program 1 times [2021-10-13 01:09:12,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,617 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357450150] [2021-10-13 01:09:12,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,617 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,703 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,703 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357450150] [2021-10-13 01:09:12,703 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357450150] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,703 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,703 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:09:12,703 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987579154] [2021-10-13 01:09:12,704 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:12,704 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:12,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:09:12,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:09:12,705 INFO L87 Difference]: Start difference. First operand 686 states and 925 transitions. cyclomatic complexity: 241 Second operand has 5 states, 5 states have (on average 11.0) internal successors, (55), 5 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:12,805 INFO L93 Difference]: Finished difference Result 928 states and 1244 transitions. [2021-10-13 01:09:12,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:09:12,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 928 states and 1244 transitions. [2021-10-13 01:09:12,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 886 [2021-10-13 01:09:12,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 928 states to 928 states and 1244 transitions. [2021-10-13 01:09:12,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 928 [2021-10-13 01:09:12,823 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 928 [2021-10-13 01:09:12,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 928 states and 1244 transitions. [2021-10-13 01:09:12,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,825 INFO L681 BuchiCegarLoop]: Abstraction has 928 states and 1244 transitions. [2021-10-13 01:09:12,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 928 states and 1244 transitions. [2021-10-13 01:09:12,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 928 to 692. [2021-10-13 01:09:12,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 692 states, 692 states have (on average 1.323699421965318) internal successors, (916), 691 states have internal predecessors, (916), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 692 states to 692 states and 916 transitions. [2021-10-13 01:09:12,841 INFO L704 BuchiCegarLoop]: Abstraction has 692 states and 916 transitions. [2021-10-13 01:09:12,841 INFO L587 BuchiCegarLoop]: Abstraction has 692 states and 916 transitions. [2021-10-13 01:09:12,841 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-13 01:09:12,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 692 states and 916 transitions. [2021-10-13 01:09:12,846 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 650 [2021-10-13 01:09:12,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,847 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,848 INFO L791 eck$LassoCheckResult]: Stem: 17141#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17053#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16903#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16904#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 17025#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16938#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16939#L233-1 assume !(0 == ~M_E~0); 16957#L336-1 assume !(0 == ~T1_E~0); 17019#L341-1 assume !(0 == ~T2_E~0); 16891#L346-1 assume !(0 == ~E_M~0); 16892#L351-1 assume !(0 == ~E_1~0); 16897#L356-1 assume !(0 == ~E_2~0); 16898#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17038#L158 assume !(1 == ~m_pc~0); 17035#L158-2 is_master_triggered_~__retres1~0 := 0; 17036#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17070#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16920#L417 assume !(0 != activate_threads_~tmp~1); 16921#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17067#L177 assume !(1 == ~t1_pc~0); 17068#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 16882#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16883#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16992#L425 assume !(0 != activate_threads_~tmp___0~0); 17121#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16954#L196 assume !(1 == ~t2_pc~0); 16955#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 17144#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17125#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16958#L433 assume !(0 != activate_threads_~tmp___1~0); 16959#L433-2 assume !(1 == ~M_E~0); 17064#L374-1 assume !(1 == ~T1_E~0); 16910#L379-1 assume !(1 == ~T2_E~0); 16901#L384-1 assume !(1 == ~E_M~0); 16902#L389-1 assume !(1 == ~E_1~0); 17058#L394-1 assume !(1 == ~E_2~0); 17059#L545-1 [2021-10-13 01:09:12,848 INFO L793 eck$LassoCheckResult]: Loop: 17059#L545-1 assume !false; 17445#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 17443#L311 assume !false; 17418#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17413#L246 assume !(0 == ~m_st~0); 17414#L250 assume !(0 == ~t1_st~0); 17415#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 17416#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17403#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 17404#L278 assume !(0 != eval_~tmp~0); 17500#L326 start_simulation_~kernel_st~0 := 2; 17499#L216-1 start_simulation_~kernel_st~0 := 3; 17498#L336-2 assume !(0 == ~M_E~0); 17497#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17496#L341-3 assume !(0 == ~T2_E~0); 17495#L346-3 assume !(0 == ~E_M~0); 17494#L351-3 assume !(0 == ~E_1~0); 17092#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17026#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17027#L158-12 assume !(1 == ~m_pc~0); 17052#L158-14 is_master_triggered_~__retres1~0 := 0; 17039#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16997#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16895#L417-12 assume !(0 != activate_threads_~tmp~1); 16896#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16860#L177-12 assume !(1 == ~t1_pc~0); 16861#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 16884#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17011#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16944#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16945#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17008#L196-12 assume 1 == ~t2_pc~0; 17136#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17391#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17388#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17385#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17382#L433-14 assume !(1 == ~M_E~0); 17063#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16962#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16963#L384-3 assume !(1 == ~E_M~0); 16974#L389-3 assume !(1 == ~E_1~0); 17047#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17375#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17372#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17369#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17093#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 17094#L564 assume !(0 == start_simulation_~tmp~3); 17364#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17466#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17463#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17461#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 17459#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17456#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 17453#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 17450#L577 assume !(0 != start_simulation_~tmp___0~1); 17059#L545-1 [2021-10-13 01:09:12,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2021-10-13 01:09:12,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,849 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708954393] [2021-10-13 01:09:12,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,849 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,857 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:12,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,878 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:12,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,880 INFO L82 PathProgramCache]: Analyzing trace with hash 1536663023, now seen corresponding path program 1 times [2021-10-13 01:09:12,880 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,880 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474599894] [2021-10-13 01:09:12,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,880 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:12,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:12,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:12,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474599894] [2021-10-13 01:09:12,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474599894] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:12,900 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:12,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:12,901 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896179493] [2021-10-13 01:09:12,901 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:09:12,901 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:12,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:12,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:12,907 INFO L87 Difference]: Start difference. First operand 692 states and 916 transitions. cyclomatic complexity: 226 Second operand has 3 states, 3 states have (on average 18.333333333333332) internal successors, (55), 3 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:12,941 INFO L93 Difference]: Finished difference Result 917 states and 1198 transitions. [2021-10-13 01:09:12,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:12,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 917 states and 1198 transitions. [2021-10-13 01:09:12,949 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 873 [2021-10-13 01:09:12,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 917 states to 917 states and 1198 transitions. [2021-10-13 01:09:12,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 917 [2021-10-13 01:09:12,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 917 [2021-10-13 01:09:12,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 917 states and 1198 transitions. [2021-10-13 01:09:12,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:12,959 INFO L681 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-13 01:09:12,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 917 states and 1198 transitions. [2021-10-13 01:09:12,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 917 to 917. [2021-10-13 01:09:12,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 917 states, 917 states have (on average 1.306434023991276) internal successors, (1198), 916 states have internal predecessors, (1198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:12,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 917 states to 917 states and 1198 transitions. [2021-10-13 01:09:12,979 INFO L704 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-13 01:09:12,980 INFO L587 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-13 01:09:12,980 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-13 01:09:12,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 917 states and 1198 transitions. [2021-10-13 01:09:12,989 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 873 [2021-10-13 01:09:12,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:12,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:12,990 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:12,990 INFO L791 eck$LassoCheckResult]: Stem: 18724#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18659#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18516#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18517#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 18633#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18552#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18553#L233-1 assume !(0 == ~M_E~0); 18571#L336-1 assume !(0 == ~T1_E~0); 18628#L341-1 assume !(0 == ~T2_E~0); 18504#L346-1 assume !(0 == ~E_M~0); 18505#L351-1 assume !(0 == ~E_1~0); 18510#L356-1 assume !(0 == ~E_2~0); 18511#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18646#L158 assume !(1 == ~m_pc~0); 18642#L158-2 is_master_triggered_~__retres1~0 := 0; 18643#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18675#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18534#L417 assume !(0 != activate_threads_~tmp~1); 18535#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18672#L177 assume !(1 == ~t1_pc~0); 18673#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 18494#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18495#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18601#L425 assume !(0 != activate_threads_~tmp___0~0); 18714#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18564#L196 assume !(1 == ~t2_pc~0); 18565#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 18578#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18579#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18572#L433 assume !(0 != activate_threads_~tmp___1~0); 18573#L433-2 assume !(1 == ~M_E~0); 18671#L374-1 assume !(1 == ~T1_E~0); 18523#L379-1 assume !(1 == ~T2_E~0); 18514#L384-1 assume !(1 == ~E_M~0); 18515#L389-1 assume !(1 == ~E_1~0); 18666#L394-1 assume !(1 == ~E_2~0); 18667#L545-1 assume !false; 18768#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 18763#L311 [2021-10-13 01:09:12,990 INFO L793 eck$LassoCheckResult]: Loop: 18763#L311 assume !false; 18761#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18759#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18756#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18754#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 18752#L278 assume 0 != eval_~tmp~0; 18750#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 18747#L286 assume !(0 != eval_~tmp_ndt_1~0); 18748#L283 assume !(0 == ~t1_st~0); 18772#L297 assume !(0 == ~t2_st~0); 18763#L311 [2021-10-13 01:09:12,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:12,991 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2021-10-13 01:09:12,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:12,992 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136466388] [2021-10-13 01:09:12,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:12,992 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:12,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:12,999 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,016 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1924965839, now seen corresponding path program 1 times [2021-10-13 01:09:13,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,017 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58025467] [2021-10-13 01:09:13,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,018 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,022 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,027 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,028 INFO L82 PathProgramCache]: Analyzing trace with hash -460324554, now seen corresponding path program 1 times [2021-10-13 01:09:13,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,030 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217395006] [2021-10-13 01:09:13,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,031 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:13,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:13,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:13,051 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217395006] [2021-10-13 01:09:13,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217395006] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:13,051 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:13,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:13,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815864332] [2021-10-13 01:09:13,151 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:13,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:13,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:13,152 INFO L87 Difference]: Start difference. First operand 917 states and 1198 transitions. cyclomatic complexity: 284 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:13,194 INFO L93 Difference]: Finished difference Result 1643 states and 2118 transitions. [2021-10-13 01:09:13,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:13,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1643 states and 2118 transitions. [2021-10-13 01:09:13,206 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1560 [2021-10-13 01:09:13,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1643 states to 1643 states and 2118 transitions. [2021-10-13 01:09:13,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1643 [2021-10-13 01:09:13,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1643 [2021-10-13 01:09:13,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1643 states and 2118 transitions. [2021-10-13 01:09:13,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:13,226 INFO L681 BuchiCegarLoop]: Abstraction has 1643 states and 2118 transitions. [2021-10-13 01:09:13,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1643 states and 2118 transitions. [2021-10-13 01:09:13,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1643 to 1591. [2021-10-13 01:09:13,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1591 states, 1591 states have (on average 1.2910119421747328) internal successors, (2054), 1590 states have internal predecessors, (2054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1591 states to 1591 states and 2054 transitions. [2021-10-13 01:09:13,263 INFO L704 BuchiCegarLoop]: Abstraction has 1591 states and 2054 transitions. [2021-10-13 01:09:13,263 INFO L587 BuchiCegarLoop]: Abstraction has 1591 states and 2054 transitions. [2021-10-13 01:09:13,263 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-13 01:09:13,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1591 states and 2054 transitions. [2021-10-13 01:09:13,271 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-13 01:09:13,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:13,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:13,272 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,272 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,272 INFO L791 eck$LassoCheckResult]: Stem: 21305#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21234#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21086#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21087#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 21208#L223-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 21122#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21123#L233-1 assume !(0 == ~M_E~0); 21141#L336-1 assume !(0 == ~T1_E~0); 21202#L341-1 assume !(0 == ~T2_E~0); 21074#L346-1 assume !(0 == ~E_M~0); 21075#L351-1 assume !(0 == ~E_1~0); 21080#L356-1 assume !(0 == ~E_2~0); 21081#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21222#L158 assume !(1 == ~m_pc~0); 21219#L158-2 is_master_triggered_~__retres1~0 := 0; 21220#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21252#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21104#L417 assume !(0 != activate_threads_~tmp~1); 21105#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21246#L177 assume !(1 == ~t1_pc~0); 21247#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 21306#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22188#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22187#L425 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21300#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21138#L196 assume !(1 == ~t2_pc~0); 21139#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 21148#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21149#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21142#L433 assume !(0 != activate_threads_~tmp___1~0); 21143#L433-2 assume !(1 == ~M_E~0); 21245#L374-1 assume !(1 == ~T1_E~0); 21093#L379-1 assume !(1 == ~T2_E~0); 21094#L384-1 assume !(1 == ~E_M~0); 21254#L389-1 assume !(1 == ~E_1~0); 21255#L394-1 assume !(1 == ~E_2~0); 22161#L545-1 assume !false; 22151#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22149#L311 [2021-10-13 01:09:13,273 INFO L793 eck$LassoCheckResult]: Loop: 22149#L311 assume !false; 22147#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22146#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22145#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22143#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 22140#L278 assume 0 != eval_~tmp~0; 22136#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 22131#L286 assume !(0 != eval_~tmp_ndt_1~0); 22132#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 22162#L300 assume !(0 != eval_~tmp_ndt_2~0); 22155#L297 assume !(0 == ~t2_st~0); 22149#L311 [2021-10-13 01:09:13,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,274 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2021-10-13 01:09:13,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,274 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15214195] [2021-10-13 01:09:13,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,274 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:13,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:13,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:13,294 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15214195] [2021-10-13 01:09:13,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15214195] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:13,294 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:13,295 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:09:13,295 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549160767] [2021-10-13 01:09:13,295 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:09:13,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,295 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 1 times [2021-10-13 01:09:13,296 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,296 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33567833] [2021-10-13 01:09:13,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,296 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,301 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,321 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,417 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:13,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:13,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:13,418 INFO L87 Difference]: Start difference. First operand 1591 states and 2054 transitions. cyclomatic complexity: 466 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:13,432 INFO L93 Difference]: Finished difference Result 1554 states and 2006 transitions. [2021-10-13 01:09:13,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:13,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1554 states and 2006 transitions. [2021-10-13 01:09:13,442 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-13 01:09:13,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1554 states to 1554 states and 2006 transitions. [2021-10-13 01:09:13,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1554 [2021-10-13 01:09:13,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1554 [2021-10-13 01:09:13,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1554 states and 2006 transitions. [2021-10-13 01:09:13,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:13,459 INFO L681 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-13 01:09:13,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1554 states and 2006 transitions. [2021-10-13 01:09:13,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1554 to 1554. [2021-10-13 01:09:13,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1554 states, 1554 states have (on average 1.2908622908622909) internal successors, (2006), 1553 states have internal predecessors, (2006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 1554 states and 2006 transitions. [2021-10-13 01:09:13,494 INFO L704 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-13 01:09:13,494 INFO L587 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-13 01:09:13,494 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-13 01:09:13,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1554 states and 2006 transitions. [2021-10-13 01:09:13,501 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-13 01:09:13,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:13,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:13,502 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,502 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,503 INFO L791 eck$LassoCheckResult]: Stem: 24444#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24377#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24236#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24237#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 24353#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24271#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24272#L233-1 assume !(0 == ~M_E~0); 24290#L336-1 assume !(0 == ~T1_E~0); 24347#L341-1 assume !(0 == ~T2_E~0); 24224#L346-1 assume !(0 == ~E_M~0); 24225#L351-1 assume !(0 == ~E_1~0); 24230#L356-1 assume !(0 == ~E_2~0); 24231#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24365#L158 assume !(1 == ~m_pc~0); 24362#L158-2 is_master_triggered_~__retres1~0 := 0; 24363#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24392#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 24253#L417 assume !(0 != activate_threads_~tmp~1); 24254#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24389#L177 assume !(1 == ~t1_pc~0); 24390#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 24214#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24215#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 24319#L425 assume !(0 != activate_threads_~tmp___0~0); 24436#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24283#L196 assume !(1 == ~t2_pc~0); 24284#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 24297#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24298#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 24291#L433 assume !(0 != activate_threads_~tmp___1~0); 24292#L433-2 assume !(1 == ~M_E~0); 24388#L374-1 assume !(1 == ~T1_E~0); 24243#L379-1 assume !(1 == ~T2_E~0); 24234#L384-1 assume !(1 == ~E_M~0); 24235#L389-1 assume !(1 == ~E_1~0); 24382#L394-1 assume !(1 == ~E_2~0); 24383#L545-1 assume !false; 25105#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 24989#L311 [2021-10-13 01:09:13,503 INFO L793 eck$LassoCheckResult]: Loop: 24989#L311 assume !false; 24988#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 24880#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 24881#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 24902#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 24901#L278 assume 0 != eval_~tmp~0; 24900#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 24644#L286 assume !(0 != eval_~tmp_ndt_1~0); 24640#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 24636#L300 assume !(0 != eval_~tmp_ndt_2~0); 24638#L297 assume !(0 == ~t2_st~0); 24989#L311 [2021-10-13 01:09:13,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,503 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2021-10-13 01:09:13,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,504 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446699149] [2021-10-13 01:09:13,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,504 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,514 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,525 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,525 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 2 times [2021-10-13 01:09:13,526 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,526 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452552972] [2021-10-13 01:09:13,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,526 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,529 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,534 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,535 INFO L82 PathProgramCache]: Analyzing trace with hash -1385264103, now seen corresponding path program 1 times [2021-10-13 01:09:13,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,535 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920869818] [2021-10-13 01:09:13,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,536 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:09:13,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:09:13,563 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:09:13,564 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920869818] [2021-10-13 01:09:13,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920869818] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:09:13,564 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:09:13,564 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:09:13,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414832602] [2021-10-13 01:09:13,664 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:09:13,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:09:13,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:09:13,665 INFO L87 Difference]: Start difference. First operand 1554 states and 2006 transitions. cyclomatic complexity: 455 Second operand has 3 states, 2 states have (on average 24.5) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:09:13,710 INFO L93 Difference]: Finished difference Result 2438 states and 3112 transitions. [2021-10-13 01:09:13,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:09:13,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2438 states and 3112 transitions. [2021-10-13 01:09:13,726 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2388 [2021-10-13 01:09:13,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2438 states to 2438 states and 3112 transitions. [2021-10-13 01:09:13,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2438 [2021-10-13 01:09:13,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2438 [2021-10-13 01:09:13,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2438 states and 3112 transitions. [2021-10-13 01:09:13,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:09:13,758 INFO L681 BuchiCegarLoop]: Abstraction has 2438 states and 3112 transitions. [2021-10-13 01:09:13,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states and 3112 transitions. [2021-10-13 01:09:13,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2390. [2021-10-13 01:09:13,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2390 states, 2390 states have (on average 1.2820083682008367) internal successors, (3064), 2389 states have internal predecessors, (3064), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:09:13,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2390 states to 2390 states and 3064 transitions. [2021-10-13 01:09:13,808 INFO L704 BuchiCegarLoop]: Abstraction has 2390 states and 3064 transitions. [2021-10-13 01:09:13,808 INFO L587 BuchiCegarLoop]: Abstraction has 2390 states and 3064 transitions. [2021-10-13 01:09:13,808 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-13 01:09:13,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2390 states and 3064 transitions. [2021-10-13 01:09:13,818 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2340 [2021-10-13 01:09:13,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:09:13,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:09:13,819 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,819 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:09:13,819 INFO L791 eck$LassoCheckResult]: Stem: 28462#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 28387#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28237#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28238#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 28360#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28272#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28273#L233-1 assume !(0 == ~M_E~0); 28291#L336-1 assume !(0 == ~T1_E~0); 28354#L341-1 assume !(0 == ~T2_E~0); 28225#L346-1 assume !(0 == ~E_M~0); 28226#L351-1 assume !(0 == ~E_1~0); 28231#L356-1 assume !(0 == ~E_2~0); 28232#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28372#L158 assume !(1 == ~m_pc~0); 28369#L158-2 is_master_triggered_~__retres1~0 := 0; 28370#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28404#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 28254#L417 assume !(0 != activate_threads_~tmp~1); 28255#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28401#L177 assume !(1 == ~t1_pc~0); 28402#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 28214#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28215#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28322#L425 assume !(0 != activate_threads_~tmp___0~0); 28451#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28284#L196 assume !(1 == ~t2_pc~0); 28285#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 28298#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28299#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28292#L433 assume !(0 != activate_threads_~tmp___1~0); 28293#L433-2 assume !(1 == ~M_E~0); 28398#L374-1 assume !(1 == ~T1_E~0); 28243#L379-1 assume !(1 == ~T2_E~0); 28235#L384-1 assume !(1 == ~E_M~0); 28236#L389-1 assume !(1 == ~E_1~0); 28392#L394-1 assume !(1 == ~E_2~0); 28393#L545-1 assume !false; 29509#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29507#L311 [2021-10-13 01:09:13,820 INFO L793 eck$LassoCheckResult]: Loop: 29507#L311 assume !false; 29505#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29502#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29496#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29493#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 29489#L278 assume 0 != eval_~tmp~0; 29304#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 29301#L286 assume !(0 != eval_~tmp_ndt_1~0); 29298#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 29239#L300 assume !(0 != eval_~tmp_ndt_2~0); 29240#L297 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 29510#L314 assume !(0 != eval_~tmp_ndt_3~0); 29507#L311 [2021-10-13 01:09:13,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,820 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2021-10-13 01:09:13,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,821 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136708917] [2021-10-13 01:09:13,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,822 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,830 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,851 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,852 INFO L82 PathProgramCache]: Analyzing trace with hash 1235481233, now seen corresponding path program 1 times [2021-10-13 01:09:13,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,852 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853654306] [2021-10-13 01:09:13,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,852 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,856 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,859 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:13,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:09:13,861 INFO L82 PathProgramCache]: Analyzing trace with hash 6483030, now seen corresponding path program 1 times [2021-10-13 01:09:13,861 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:09:13,861 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649344621] [2021-10-13 01:09:13,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:09:13,861 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:09:13,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,872 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:09:13,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:09:13,887 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:09:15,214 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.10 01:09:15 BoogieIcfgContainer [2021-10-13 01:09:15,215 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-13 01:09:15,215 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-13 01:09:15,215 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-13 01:09:15,215 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-13 01:09:15,216 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:09:09" (3/4) ... [2021-10-13 01:09:15,218 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-13 01:09:15,271 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/witness.graphml [2021-10-13 01:09:15,272 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-13 01:09:15,273 INFO L168 Benchmark]: Toolchain (without parser) took 7037.07 ms. Allocated memory was 98.6 MB in the beginning and 167.8 MB in the end (delta: 69.2 MB). Free memory was 61.3 MB in the beginning and 69.8 MB in the end (delta: -8.5 MB). Peak memory consumption was 60.8 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,274 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 98.6 MB. Free memory is still 63.8 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-13 01:09:15,274 INFO L168 Benchmark]: CACSL2BoogieTranslator took 331.79 ms. Allocated memory is still 98.6 MB. Free memory was 61.1 MB in the beginning and 48.2 MB in the end (delta: 12.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,275 INFO L168 Benchmark]: Boogie Procedure Inliner took 59.19 ms. Allocated memory is still 98.6 MB. Free memory was 48.1 MB in the beginning and 45.2 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,275 INFO L168 Benchmark]: Boogie Preprocessor took 77.79 ms. Allocated memory was 98.6 MB in the beginning and 125.8 MB in the end (delta: 27.3 MB). Free memory was 45.2 MB in the beginning and 101.7 MB in the end (delta: -56.5 MB). Peak memory consumption was 6.0 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,276 INFO L168 Benchmark]: RCFGBuilder took 793.80 ms. Allocated memory is still 125.8 MB. Free memory was 101.6 MB in the beginning and 78.4 MB in the end (delta: 23.2 MB). Peak memory consumption was 25.8 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,276 INFO L168 Benchmark]: BuchiAutomizer took 5711.95 ms. Allocated memory was 125.8 MB in the beginning and 167.8 MB in the end (delta: 41.9 MB). Free memory was 78.4 MB in the beginning and 72.9 MB in the end (delta: 5.6 MB). Peak memory consumption was 85.7 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,276 INFO L168 Benchmark]: Witness Printer took 56.53 ms. Allocated memory is still 167.8 MB. Free memory was 72.9 MB in the beginning and 69.8 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-13 01:09:15,279 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 98.6 MB. Free memory is still 63.8 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 331.79 ms. Allocated memory is still 98.6 MB. Free memory was 61.1 MB in the beginning and 48.2 MB in the end (delta: 12.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 59.19 ms. Allocated memory is still 98.6 MB. Free memory was 48.1 MB in the beginning and 45.2 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 77.79 ms. Allocated memory was 98.6 MB in the beginning and 125.8 MB in the end (delta: 27.3 MB). Free memory was 45.2 MB in the beginning and 101.7 MB in the end (delta: -56.5 MB). Peak memory consumption was 6.0 MB. Max. memory is 16.1 GB. * RCFGBuilder took 793.80 ms. Allocated memory is still 125.8 MB. Free memory was 101.6 MB in the beginning and 78.4 MB in the end (delta: 23.2 MB). Peak memory consumption was 25.8 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 5711.95 ms. Allocated memory was 125.8 MB in the beginning and 167.8 MB in the end (delta: 41.9 MB). Free memory was 78.4 MB in the beginning and 72.9 MB in the end (delta: 5.6 MB). Peak memory consumption was 85.7 MB. Max. memory is 16.1 GB. * Witness Printer took 56.53 ms. Allocated memory is still 167.8 MB. Free memory was 72.9 MB in the beginning and 69.8 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2390 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 3.3s. Construction of modules took 0.5s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 455.1ms AutomataMinimizationTime, 16 MinimizatonAttempts, 2273 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 2390 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5205 SDtfs, 6133 SDslu, 4842 SDs, 0 SdLazy, 453 SolverSat, 162 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 504.9ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 273]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=21807} State at position 1 is {NULL=0, token=0, NULL=21807, tmp=1, __retres1=0, kernel_st=1, t2_st=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a53957e=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79c4ea8=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25938943=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d1144d8=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52d5e44=0, NULL=21810, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=21809, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=21808, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@218c3d23=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@af9fecb=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@287d5869=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77e4dc69=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 273]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int M_E = 2; [L26] int T1_E = 2; [L27] int T2_E = 2; [L28] int E_M = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L35] int token ; [L37] int local ; [L590] int __retres1 ; [L504] m_i = 1 [L505] t1_i = 1 [L506] t2_i = 1 [L531] int kernel_st ; [L532] int tmp ; [L533] int tmp___0 ; [L537] kernel_st = 0 [L223] COND TRUE m_i == 1 [L224] m_st = 0 [L228] COND TRUE t1_i == 1 [L229] t1_st = 0 [L233] COND TRUE t2_i == 1 [L234] t2_st = 0 [L336] COND FALSE !(M_E == 0) [L341] COND FALSE !(T1_E == 0) [L346] COND FALSE !(T2_E == 0) [L351] COND FALSE !(E_M == 0) [L356] COND FALSE !(E_1 == 0) [L361] COND FALSE !(E_2 == 0) [L409] int tmp ; [L410] int tmp___0 ; [L411] int tmp___1 ; [L155] int __retres1 ; [L158] COND FALSE !(m_pc == 1) [L168] __retres1 = 0 [L170] return (__retres1); [L415] tmp = is_master_triggered() [L417] COND FALSE !(\read(tmp)) [L174] int __retres1 ; [L177] COND FALSE !(t1_pc == 1) [L187] __retres1 = 0 [L189] return (__retres1); [L423] tmp___0 = is_transmit1_triggered() [L425] COND FALSE !(\read(tmp___0)) [L193] int __retres1 ; [L196] COND FALSE !(t2_pc == 1) [L206] __retres1 = 0 [L208] return (__retres1); [L431] tmp___1 = is_transmit2_triggered() [L433] COND FALSE !(\read(tmp___1)) [L374] COND FALSE !(M_E == 1) [L379] COND FALSE !(T1_E == 1) [L384] COND FALSE !(T2_E == 1) [L389] COND FALSE !(E_M == 1) [L394] COND FALSE !(E_1 == 1) [L399] COND FALSE !(E_2 == 1) [L545] COND TRUE 1 [L548] kernel_st = 1 [L269] int tmp ; Loop: [L273] COND TRUE 1 [L243] int __retres1 ; [L246] COND TRUE m_st == 0 [L247] __retres1 = 1 [L264] return (__retres1); [L276] tmp = exists_runnable_thread() [L278] COND TRUE \read(tmp) [L283] COND TRUE m_st == 0 [L284] int tmp_ndt_1; [L285] tmp_ndt_1 = __VERIFIER_nondet_int() [L286] COND FALSE !(\read(tmp_ndt_1)) [L297] COND TRUE t1_st == 0 [L298] int tmp_ndt_2; [L299] tmp_ndt_2 = __VERIFIER_nondet_int() [L300] COND FALSE !(\read(tmp_ndt_2)) [L311] COND TRUE t2_st == 0 [L312] int tmp_ndt_3; [L313] tmp_ndt_3 = __VERIFIER_nondet_int() [L314] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-13 01:09:15,356 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f6b84ed5-9f24-46f7-94b2-9d665e7eecb7/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...