./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4e77c044 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6f4939d7f3486eae7bf09c50c45409459f826dc8 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-4e77c04 [2021-10-13 01:19:37,736 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-13 01:19:37,738 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-13 01:19:37,769 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-13 01:19:37,770 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-13 01:19:37,771 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-13 01:19:37,773 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-13 01:19:37,776 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-13 01:19:37,778 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-13 01:19:37,780 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-13 01:19:37,781 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-13 01:19:37,783 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-13 01:19:37,783 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-13 01:19:37,785 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-13 01:19:37,786 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-13 01:19:37,788 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-13 01:19:37,789 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-13 01:19:37,790 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-13 01:19:37,793 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-13 01:19:37,795 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-13 01:19:37,797 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-13 01:19:37,799 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-13 01:19:37,800 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-13 01:19:37,802 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-13 01:19:37,806 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-13 01:19:37,806 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-13 01:19:37,807 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-13 01:19:37,808 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-13 01:19:37,809 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-13 01:19:37,810 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-13 01:19:37,810 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-13 01:19:37,811 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-13 01:19:37,813 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-13 01:19:37,814 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-13 01:19:37,815 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-13 01:19:37,815 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-13 01:19:37,816 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-13 01:19:37,817 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-13 01:19:37,817 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-13 01:19:37,818 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-13 01:19:37,819 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-13 01:19:37,820 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-13 01:19:37,846 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-13 01:19:37,847 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-13 01:19:37,847 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-13 01:19:37,848 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-13 01:19:37,849 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-13 01:19:37,849 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-13 01:19:37,849 INFO L138 SettingsManager]: * Use SBE=true [2021-10-13 01:19:37,850 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-13 01:19:37,850 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-13 01:19:37,850 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-13 01:19:37,850 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-13 01:19:37,851 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-13 01:19:37,851 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-13 01:19:37,851 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-13 01:19:37,851 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-13 01:19:37,852 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-13 01:19:37,852 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-13 01:19:37,852 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-13 01:19:37,852 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-13 01:19:37,852 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-13 01:19:37,853 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-13 01:19:37,853 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-13 01:19:37,853 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-13 01:19:37,853 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-13 01:19:37,854 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-13 01:19:37,854 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-13 01:19:37,854 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-13 01:19:37,854 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-13 01:19:37,855 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-13 01:19:37,855 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-13 01:19:37,855 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-13 01:19:37,856 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-13 01:19:37,857 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-13 01:19:37,857 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6f4939d7f3486eae7bf09c50c45409459f826dc8 [2021-10-13 01:19:38,178 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-13 01:19:38,216 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-13 01:19:38,219 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-13 01:19:38,220 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-13 01:19:38,222 INFO L275 PluginConnector]: CDTParser initialized [2021-10-13 01:19:38,223 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/../../sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-10-13 01:19:38,293 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/data/5f08b368b/aa24f0072df84062bf5d902aedfcd445/FLAGc8b5e56dd [2021-10-13 01:19:38,850 INFO L306 CDTParser]: Found 1 translation units. [2021-10-13 01:19:38,853 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-10-13 01:19:38,874 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/data/5f08b368b/aa24f0072df84062bf5d902aedfcd445/FLAGc8b5e56dd [2021-10-13 01:19:39,163 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/data/5f08b368b/aa24f0072df84062bf5d902aedfcd445 [2021-10-13 01:19:39,172 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-13 01:19:39,174 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-13 01:19:39,178 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-13 01:19:39,179 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-13 01:19:39,182 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-13 01:19:39,183 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,185 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13cf6d49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39, skipping insertion in model container [2021-10-13 01:19:39,185 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,193 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-13 01:19:39,253 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-13 01:19:39,474 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/sv-benchmarks/c/systemc/transmitter.06.cil.c[401,414] [2021-10-13 01:19:39,580 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:19:39,606 INFO L203 MainTranslator]: Completed pre-run [2021-10-13 01:19:39,620 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/sv-benchmarks/c/systemc/transmitter.06.cil.c[401,414] [2021-10-13 01:19:39,689 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:19:39,717 INFO L208 MainTranslator]: Completed translation [2021-10-13 01:19:39,718 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39 WrapperNode [2021-10-13 01:19:39,718 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-13 01:19:39,720 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-13 01:19:39,720 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-13 01:19:39,721 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-13 01:19:39,729 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,756 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,862 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-13 01:19:39,863 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-13 01:19:39,863 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-13 01:19:39,864 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-13 01:19:39,872 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,873 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,888 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,898 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,931 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,982 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,985 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:39,993 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-13 01:19:40,000 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-13 01:19:40,001 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-13 01:19:40,001 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-13 01:19:40,003 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (1/1) ... [2021-10-13 01:19:40,011 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-13 01:19:40,023 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/z3 [2021-10-13 01:19:40,039 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-13 01:19:40,056 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-13 01:19:40,093 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-13 01:19:40,093 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-13 01:19:40,093 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-13 01:19:40,093 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-13 01:19:41,678 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-13 01:19:41,682 INFO L299 CfgBuilder]: Removed 218 assume(true) statements. [2021-10-13 01:19:41,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:19:41 BoogieIcfgContainer [2021-10-13 01:19:41,687 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-13 01:19:41,689 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-13 01:19:41,690 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-13 01:19:41,694 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-13 01:19:41,695 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:19:41,695 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 01:19:39" (1/3) ... [2021-10-13 01:19:41,696 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4cbc9259 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:19:41, skipping insertion in model container [2021-10-13 01:19:41,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:19:41,697 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:19:39" (2/3) ... [2021-10-13 01:19:41,697 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4cbc9259 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:19:41, skipping insertion in model container [2021-10-13 01:19:41,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:19:41,698 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:19:41" (3/3) ... [2021-10-13 01:19:41,699 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2021-10-13 01:19:41,752 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-13 01:19:41,752 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-13 01:19:41,752 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-13 01:19:41,753 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-13 01:19:41,753 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-13 01:19:41,753 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-13 01:19:41,753 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-13 01:19:41,753 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-13 01:19:41,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 611 states, 610 states have (on average 1.5475409836065575) internal successors, (944), 610 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:41,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 522 [2021-10-13 01:19:41,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:41,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:41,873 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:41,873 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:41,874 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-13 01:19:41,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 611 states, 610 states have (on average 1.5475409836065575) internal successors, (944), 610 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:41,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 522 [2021-10-13 01:19:41,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:41,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:41,915 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:41,917 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:41,931 INFO L791 eck$LassoCheckResult]: Stem: 598#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 516#L-1true havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 136#L979true havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 580#L446true assume !(1 == ~m_i~0);~m_st~0 := 2; 199#L453-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 155#L458-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 300#L463-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 303#L468-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 409#L473-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 137#L478-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 404#L483-1true assume !(0 == ~M_E~0); 558#L662-1true assume !(0 == ~T1_E~0); 280#L667-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 385#L672-1true assume !(0 == ~T3_E~0); 163#L677-1true assume !(0 == ~T4_E~0); 346#L682-1true assume !(0 == ~T5_E~0); 444#L687-1true assume !(0 == ~T6_E~0); 520#L692-1true assume !(0 == ~E_1~0); 330#L697-1true assume !(0 == ~E_2~0); 573#L702-1true assume !(0 == ~E_3~0); 392#L707-1true assume 0 == ~E_4~0;~E_4~0 := 1; 248#L712-1true assume !(0 == ~E_5~0); 376#L717-1true assume !(0 == ~E_6~0); 358#L722-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 157#L312true assume 1 == ~m_pc~0; 30#L313true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4#L323true is_master_triggered_#res := is_master_triggered_~__retres1~0; 328#L324true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 62#L817true assume !(0 != activate_threads_~tmp~1); 481#L817-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 170#L331true assume !(1 == ~t1_pc~0); 142#L331-2true is_transmit1_triggered_~__retres1~1 := 0; 40#L342true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 568#L343true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 147#L825true assume !(0 != activate_threads_~tmp___0~0); 458#L825-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120#L350true assume 1 == ~t2_pc~0; 394#L351true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 252#L361true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 455#L362true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 53#L833true assume !(0 != activate_threads_~tmp___1~0); 533#L833-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 513#L369true assume 1 == ~t3_pc~0; 316#L370true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 246#L380true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76#L381true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 259#L841true assume !(0 != activate_threads_~tmp___2~0); 143#L841-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 338#L388true assume !(1 == ~t4_pc~0); 177#L388-2true is_transmit4_triggered_~__retres1~4 := 0; 77#L399true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 399#L400true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 153#L849true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 342#L849-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14#L407true assume 1 == ~t5_pc~0; 582#L408true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20#L418true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5#L419true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 278#L857true assume !(0 != activate_threads_~tmp___4~0); 81#L857-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 291#L426true assume !(1 == ~t6_pc~0); 355#L426-2true is_transmit6_triggered_~__retres1~6 := 0; 471#L437true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 571#L438true activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 427#L865true assume !(0 != activate_threads_~tmp___5~0); 34#L865-2true assume !(1 == ~M_E~0); 71#L735-1true assume !(1 == ~T1_E~0); 135#L740-1true assume !(1 == ~T2_E~0); 55#L745-1true assume !(1 == ~T3_E~0); 456#L750-1true assume !(1 == ~T4_E~0); 390#L755-1true assume !(1 == ~T5_E~0); 361#L760-1true assume !(1 == ~T6_E~0); 552#L765-1true assume 1 == ~E_1~0;~E_1~0 := 2; 525#L770-1true assume !(1 == ~E_2~0); 215#L775-1true assume !(1 == ~E_3~0); 167#L780-1true assume !(1 == ~E_4~0); 340#L785-1true assume !(1 == ~E_5~0); 436#L790-1true assume !(1 == ~E_6~0); 380#L1016-1true [2021-10-13 01:19:41,934 INFO L793 eck$LassoCheckResult]: Loop: 380#L1016-1true assume !false; 387#L1017true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 430#L637true assume false; 301#L652true start_simulation_~kernel_st~0 := 2; 548#L446-1true start_simulation_~kernel_st~0 := 3; 223#L662-2true assume !(0 == ~M_E~0); 569#L662-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 209#L667-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 375#L672-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 98#L677-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 604#L682-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 419#L687-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 121#L692-3true assume 0 == ~E_1~0;~E_1~0 := 1; 545#L697-3true assume !(0 == ~E_2~0); 182#L702-3true assume 0 == ~E_3~0;~E_3~0 := 1; 295#L707-3true assume 0 == ~E_4~0;~E_4~0 := 1; 327#L712-3true assume 0 == ~E_5~0;~E_5~0 := 1; 67#L717-3true assume 0 == ~E_6~0;~E_6~0 := 1; 322#L722-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 500#L312-21true assume 1 == ~m_pc~0; 583#L313-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 232#L323-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 8#L324-7true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 238#L817-21true assume !(0 != activate_threads_~tmp~1); 414#L817-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 239#L331-21true assume 1 == ~t1_pc~0; 200#L332-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 117#L342-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28#L343-7true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 485#L825-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 452#L825-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 365#L350-21true assume !(1 == ~t2_pc~0); 88#L350-23true is_transmit2_triggered_~__retres1~2 := 0; 531#L361-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 554#L362-7true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 24#L833-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 72#L833-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 258#L369-21true assume 1 == ~t3_pc~0; 265#L370-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9#L380-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 472#L381-7true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 398#L841-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 83#L841-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 541#L388-21true assume 1 == ~t4_pc~0; 368#L389-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10#L399-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129#L400-7true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 297#L849-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 184#L849-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 442#L407-21true assume 1 == ~t5_pc~0; 179#L408-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 48#L418-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 225#L419-7true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 17#L857-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 312#L857-23true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 527#L426-21true assume 1 == ~t6_pc~0; 78#L427-7true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 131#L437-7true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 140#L438-7true activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 236#L865-21true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 212#L865-23true assume 1 == ~M_E~0;~M_E~0 := 2; 59#L735-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 439#L740-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 416#L745-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 434#L750-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 66#L755-3true assume !(1 == ~T5_E~0); 543#L760-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 220#L765-3true assume 1 == ~E_1~0;~E_1~0 := 2; 194#L770-3true assume 1 == ~E_2~0;~E_2~0 := 2; 253#L775-3true assume 1 == ~E_3~0;~E_3~0 := 2; 268#L780-3true assume 1 == ~E_4~0;~E_4~0 := 2; 37#L785-3true assume 1 == ~E_5~0;~E_5~0 := 2; 356#L790-3true assume 1 == ~E_6~0;~E_6~0 := 2; 429#L795-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 222#L496-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 570#L533-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 463#L534-1true start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 359#L1035true assume !(0 == start_simulation_~tmp~3); 261#L1035-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 413#L496-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 331#L533-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 382#L534-2true stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 111#L990true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 555#L997true stop_simulation_#res := stop_simulation_~__retres2~0; 242#L998true start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 208#L1048true assume !(0 != start_simulation_~tmp___0~1); 380#L1016-1true [2021-10-13 01:19:41,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:41,943 INFO L82 PathProgramCache]: Analyzing trace with hash 1207060675, now seen corresponding path program 1 times [2021-10-13 01:19:41,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:41,953 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413024158] [2021-10-13 01:19:41,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:41,955 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,218 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,219 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413024158] [2021-10-13 01:19:42,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413024158] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,221 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,221 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:42,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810195564] [2021-10-13 01:19:42,229 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:42,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:42,232 INFO L82 PathProgramCache]: Analyzing trace with hash 616912365, now seen corresponding path program 1 times [2021-10-13 01:19:42,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:42,233 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065512538] [2021-10-13 01:19:42,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:42,234 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,300 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,301 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065512538] [2021-10-13 01:19:42,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1065512538] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,302 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:42,303 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328165155] [2021-10-13 01:19:42,304 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:42,306 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:42,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:42,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:42,324 INFO L87 Difference]: Start difference. First operand has 611 states, 610 states have (on average 1.5475409836065575) internal successors, (944), 610 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:42,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:42,388 INFO L93 Difference]: Finished difference Result 611 states and 922 transitions. [2021-10-13 01:19:42,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:42,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 611 states and 922 transitions. [2021-10-13 01:19:42,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:42,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 611 states to 606 states and 917 transitions. [2021-10-13 01:19:42,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:42,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:42,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 917 transitions. [2021-10-13 01:19:42,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:42,416 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2021-10-13 01:19:42,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 917 transitions. [2021-10-13 01:19:42,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:42,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.5132013201320131) internal successors, (917), 605 states have internal predecessors, (917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:42,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 917 transitions. [2021-10-13 01:19:42,498 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2021-10-13 01:19:42,498 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2021-10-13 01:19:42,499 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-13 01:19:42,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 917 transitions. [2021-10-13 01:19:42,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:42,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:42,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:42,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:42,517 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:42,517 INFO L791 eck$LassoCheckResult]: Stem: 1836#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1824#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1492#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1493#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 1586#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1527#L458-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1528#L463-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1701#L468-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1706#L473-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1494#L478-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1495#L483-1 assume !(0 == ~M_E~0); 1775#L662-1 assume !(0 == ~T1_E~0); 1686#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1687#L672-1 assume !(0 == ~T3_E~0); 1538#L677-1 assume !(0 == ~T4_E~0); 1539#L682-1 assume !(0 == ~T5_E~0); 1741#L687-1 assume !(0 == ~T6_E~0); 1798#L692-1 assume !(0 == ~E_1~0); 1729#L697-1 assume !(0 == ~E_2~0); 1730#L702-1 assume !(0 == ~E_3~0); 1771#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1651#L712-1 assume !(0 == ~E_5~0); 1652#L717-1 assume !(0 == ~E_6~0); 1751#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1529#L312 assume 1 == ~m_pc~0; 1287#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1233#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1234#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1357#L817 assume !(0 != activate_threads_~tmp~1); 1358#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1549#L331 assume !(1 == ~t1_pc~0); 1503#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 1310#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1311#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1512#L825 assume !(0 != activate_threads_~tmp___0~0); 1513#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1469#L350 assume 1 == ~t2_pc~0; 1470#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1656#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1657#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1337#L833 assume !(0 != activate_threads_~tmp___1~0); 1338#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1823#L369 assume 1 == ~t3_pc~0; 1717#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1408#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1389#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1390#L841 assume !(0 != activate_threads_~tmp___2~0); 1507#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1508#L388 assume !(1 == ~t4_pc~0); 1559#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 1391#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1392#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1523#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1524#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1256#L407 assume 1 == ~t5_pc~0; 1257#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1267#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1235#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1236#L857 assume !(0 != activate_threads_~tmp___4~0); 1398#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1399#L426 assume !(1 == ~t6_pc~0); 1694#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 1747#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1812#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1790#L865 assume !(0 != activate_threads_~tmp___5~0); 1296#L865-2 assume !(1 == ~M_E~0); 1297#L735-1 assume !(1 == ~T1_E~0); 1377#L740-1 assume !(1 == ~T2_E~0); 1342#L745-1 assume !(1 == ~T3_E~0); 1343#L750-1 assume !(1 == ~T4_E~0); 1769#L755-1 assume !(1 == ~T5_E~0); 1752#L760-1 assume !(1 == ~T6_E~0); 1753#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1825#L770-1 assume !(1 == ~E_2~0); 1612#L775-1 assume !(1 == ~E_3~0); 1545#L780-1 assume !(1 == ~E_4~0); 1546#L785-1 assume !(1 == ~E_5~0); 1736#L790-1 assume !(1 == ~E_6~0); 1599#L1016-1 [2021-10-13 01:19:42,519 INFO L793 eck$LassoCheckResult]: Loop: 1599#L1016-1 assume !false; 1765#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1665#L637 assume !false; 1792#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1670#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1301#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1511#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1776#L548 assume !(0 != eval_~tmp~0); 1704#L652 start_simulation_~kernel_st~0 := 2; 1705#L446-1 start_simulation_~kernel_st~0 := 3; 1621#L662-2 assume !(0 == ~M_E~0); 1622#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1603#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1604#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1425#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1426#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1786#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1472#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1473#L697-3 assume !(0 == ~E_2~0); 1567#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1568#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1697#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1370#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1371#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1722#L312-21 assume !(1 == ~m_pc~0); 1819#L312-23 is_master_triggered_~__retres1~0 := 0; 1632#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1241#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1242#L817-21 assume !(0 != activate_threads_~tmp~1); 1640#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1641#L331-21 assume 1 == ~t1_pc~0; 1587#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1465#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1283#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1284#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1805#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1758#L350-21 assume 1 == ~t2_pc~0; 1400#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1401#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1826#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1275#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1276#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1378#L369-21 assume !(1 == ~t3_pc~0); 1563#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 1243#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1244#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1773#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1403#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1404#L388-21 assume !(1 == ~t4_pc~0); 1433#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 1245#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1246#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1484#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1565#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1566#L407-21 assume 1 == ~t5_pc~0; 1560#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1329#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1330#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1261#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1262#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1713#L426-21 assume 1 == ~t6_pc~0; 1386#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1387#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1488#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1499#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1607#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1351#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1352#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1782#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1783#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1366#L755-3 assume !(1 == ~T5_E~0); 1367#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1616#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1578#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1579#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1658#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1303#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1304#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1748#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1619#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1437#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1809#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1750#L1035 assume !(0 == start_simulation_~tmp~3); 1662#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1663#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1583#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1731#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 1453#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1454#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 1644#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 1598#L1048 assume !(0 != start_simulation_~tmp___0~1); 1599#L1016-1 [2021-10-13 01:19:42,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:42,520 INFO L82 PathProgramCache]: Analyzing trace with hash -527043775, now seen corresponding path program 1 times [2021-10-13 01:19:42,520 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:42,521 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106850385] [2021-10-13 01:19:42,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:42,521 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,669 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106850385] [2021-10-13 01:19:42,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106850385] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,669 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:42,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302913333] [2021-10-13 01:19:42,671 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:42,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:42,673 INFO L82 PathProgramCache]: Analyzing trace with hash -1624232190, now seen corresponding path program 1 times [2021-10-13 01:19:42,674 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:42,674 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196708599] [2021-10-13 01:19:42,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:42,676 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,782 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,782 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196708599] [2021-10-13 01:19:42,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196708599] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,783 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,783 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:42,783 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31700237] [2021-10-13 01:19:42,784 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:42,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:42,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:42,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:42,785 INFO L87 Difference]: Start difference. First operand 606 states and 917 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:42,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:42,804 INFO L93 Difference]: Finished difference Result 606 states and 916 transitions. [2021-10-13 01:19:42,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:42,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 916 transitions. [2021-10-13 01:19:42,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:42,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 916 transitions. [2021-10-13 01:19:42,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:42,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:42,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 916 transitions. [2021-10-13 01:19:42,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:42,820 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2021-10-13 01:19:42,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 916 transitions. [2021-10-13 01:19:42,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:42,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.5115511551155116) internal successors, (916), 605 states have internal predecessors, (916), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:42,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 916 transitions. [2021-10-13 01:19:42,835 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2021-10-13 01:19:42,836 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2021-10-13 01:19:42,836 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-13 01:19:42,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 916 transitions. [2021-10-13 01:19:42,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:42,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:42,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:42,843 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:42,843 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:42,843 INFO L791 eck$LassoCheckResult]: Stem: 3055#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 3043#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2711#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2712#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 2805#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2746#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2747#L463-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2920#L468-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2925#L473-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2713#L478-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2714#L483-1 assume !(0 == ~M_E~0); 2994#L662-1 assume !(0 == ~T1_E~0); 2905#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2906#L672-1 assume !(0 == ~T3_E~0); 2757#L677-1 assume !(0 == ~T4_E~0); 2758#L682-1 assume !(0 == ~T5_E~0); 2961#L687-1 assume !(0 == ~T6_E~0); 3018#L692-1 assume !(0 == ~E_1~0); 2948#L697-1 assume !(0 == ~E_2~0); 2949#L702-1 assume !(0 == ~E_3~0); 2990#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2870#L712-1 assume !(0 == ~E_5~0); 2871#L717-1 assume !(0 == ~E_6~0); 2970#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2748#L312 assume 1 == ~m_pc~0; 2506#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2452#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2453#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2576#L817 assume !(0 != activate_threads_~tmp~1); 2577#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2768#L331 assume !(1 == ~t1_pc~0); 2722#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 2529#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2530#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2731#L825 assume !(0 != activate_threads_~tmp___0~0); 2732#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2688#L350 assume 1 == ~t2_pc~0; 2689#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2875#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2876#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2556#L833 assume !(0 != activate_threads_~tmp___1~0); 2557#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3042#L369 assume 1 == ~t3_pc~0; 2936#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2627#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2608#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2609#L841 assume !(0 != activate_threads_~tmp___2~0); 2726#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2727#L388 assume !(1 == ~t4_pc~0); 2778#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 2610#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2611#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2742#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2743#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2475#L407 assume 1 == ~t5_pc~0; 2476#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2488#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2454#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2455#L857 assume !(0 != activate_threads_~tmp___4~0); 2617#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2618#L426 assume !(1 == ~t6_pc~0); 2913#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 2966#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3031#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3009#L865 assume !(0 != activate_threads_~tmp___5~0); 2515#L865-2 assume !(1 == ~M_E~0); 2516#L735-1 assume !(1 == ~T1_E~0); 2597#L740-1 assume !(1 == ~T2_E~0); 2561#L745-1 assume !(1 == ~T3_E~0); 2562#L750-1 assume !(1 == ~T4_E~0); 2988#L755-1 assume !(1 == ~T5_E~0); 2971#L760-1 assume !(1 == ~T6_E~0); 2972#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3044#L770-1 assume !(1 == ~E_2~0); 2831#L775-1 assume !(1 == ~E_3~0); 2764#L780-1 assume !(1 == ~E_4~0); 2765#L785-1 assume !(1 == ~E_5~0); 2955#L790-1 assume !(1 == ~E_6~0); 2820#L1016-1 [2021-10-13 01:19:42,844 INFO L793 eck$LassoCheckResult]: Loop: 2820#L1016-1 assume !false; 2984#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2884#L637 assume !false; 3011#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2891#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2520#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2730#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2995#L548 assume !(0 != eval_~tmp~0); 2923#L652 start_simulation_~kernel_st~0 := 2; 2924#L446-1 start_simulation_~kernel_st~0 := 3; 2840#L662-2 assume !(0 == ~M_E~0); 2841#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2822#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2823#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2647#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2648#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3005#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2691#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2692#L697-3 assume !(0 == ~E_2~0); 2786#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2787#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2917#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2587#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2588#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2941#L312-21 assume !(1 == ~m_pc~0); 3038#L312-23 is_master_triggered_~__retres1~0 := 0; 2851#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2460#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2461#L817-21 assume !(0 != activate_threads_~tmp~1); 2859#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2860#L331-21 assume 1 == ~t1_pc~0; 2806#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2684#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2502#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2503#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3024#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2976#L350-21 assume 1 == ~t2_pc~0; 2619#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2620#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3045#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2494#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2495#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2596#L369-21 assume !(1 == ~t3_pc~0); 2782#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 2462#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2463#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2992#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2624#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2625#L388-21 assume 1 == ~t4_pc~0; 2978#L389-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2464#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2465#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2704#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2784#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2785#L407-21 assume 1 == ~t5_pc~0; 2780#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2548#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2549#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2480#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2481#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2933#L426-21 assume 1 == ~t6_pc~0; 2605#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2606#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2707#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2718#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2826#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2570#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2571#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3001#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3002#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2585#L755-3 assume !(1 == ~T5_E~0); 2586#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2835#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2797#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2798#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2877#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2522#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2523#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2967#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2838#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2658#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3028#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2969#L1035 assume !(0 == start_simulation_~tmp~3); 2881#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2882#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2802#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2950#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 2673#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2674#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 2863#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 2819#L1048 assume !(0 != start_simulation_~tmp___0~1); 2820#L1016-1 [2021-10-13 01:19:42,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:42,845 INFO L82 PathProgramCache]: Analyzing trace with hash 1383998783, now seen corresponding path program 1 times [2021-10-13 01:19:42,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:42,845 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221435654] [2021-10-13 01:19:42,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:42,846 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,882 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,883 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221435654] [2021-10-13 01:19:42,883 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221435654] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,883 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,883 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:42,883 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160572121] [2021-10-13 01:19:42,884 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:42,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:42,885 INFO L82 PathProgramCache]: Analyzing trace with hash 772204801, now seen corresponding path program 1 times [2021-10-13 01:19:42,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:42,885 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830230825] [2021-10-13 01:19:42,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:42,886 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:42,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:42,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:42,968 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:42,969 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830230825] [2021-10-13 01:19:42,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830230825] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:42,969 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:42,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:42,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78093656] [2021-10-13 01:19:42,974 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:42,974 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:42,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:42,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:42,975 INFO L87 Difference]: Start difference. First operand 606 states and 916 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:42,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:42,995 INFO L93 Difference]: Finished difference Result 606 states and 915 transitions. [2021-10-13 01:19:42,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:42,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 915 transitions. [2021-10-13 01:19:43,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 915 transitions. [2021-10-13 01:19:43,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 915 transitions. [2021-10-13 01:19:43,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,012 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2021-10-13 01:19:43,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 915 transitions. [2021-10-13 01:19:43,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.50990099009901) internal successors, (915), 605 states have internal predecessors, (915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 915 transitions. [2021-10-13 01:19:43,028 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2021-10-13 01:19:43,028 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2021-10-13 01:19:43,029 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-13 01:19:43,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 915 transitions. [2021-10-13 01:19:43,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,038 INFO L791 eck$LassoCheckResult]: Stem: 4274#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4262#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3930#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3931#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 4024#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3965#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3966#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4139#L468-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4144#L473-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3932#L478-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3933#L483-1 assume !(0 == ~M_E~0); 4213#L662-1 assume !(0 == ~T1_E~0); 4124#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4125#L672-1 assume !(0 == ~T3_E~0); 3976#L677-1 assume !(0 == ~T4_E~0); 3977#L682-1 assume !(0 == ~T5_E~0); 4179#L687-1 assume !(0 == ~T6_E~0); 4236#L692-1 assume !(0 == ~E_1~0); 4167#L697-1 assume !(0 == ~E_2~0); 4168#L702-1 assume !(0 == ~E_3~0); 4208#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4089#L712-1 assume !(0 == ~E_5~0); 4090#L717-1 assume !(0 == ~E_6~0); 4188#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3967#L312 assume 1 == ~m_pc~0; 3725#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3671#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3672#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3795#L817 assume !(0 != activate_threads_~tmp~1); 3796#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3987#L331 assume !(1 == ~t1_pc~0); 3941#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 3748#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3749#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3950#L825 assume !(0 != activate_threads_~tmp___0~0); 3951#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3907#L350 assume 1 == ~t2_pc~0; 3908#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4094#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4095#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3775#L833 assume !(0 != activate_threads_~tmp___1~0); 3776#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4261#L369 assume 1 == ~t3_pc~0; 4155#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3846#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3824#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3825#L841 assume !(0 != activate_threads_~tmp___2~0); 3942#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3943#L388 assume !(1 == ~t4_pc~0); 3997#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 3826#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3827#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3961#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3962#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3692#L407 assume 1 == ~t5_pc~0; 3693#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3705#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3673#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3674#L857 assume !(0 != activate_threads_~tmp___4~0); 3836#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3837#L426 assume !(1 == ~t6_pc~0); 4132#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 4185#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4250#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4228#L865 assume !(0 != activate_threads_~tmp___5~0); 3734#L865-2 assume !(1 == ~M_E~0); 3735#L735-1 assume !(1 == ~T1_E~0); 3815#L740-1 assume !(1 == ~T2_E~0); 3780#L745-1 assume !(1 == ~T3_E~0); 3781#L750-1 assume !(1 == ~T4_E~0); 4207#L755-1 assume !(1 == ~T5_E~0); 4190#L760-1 assume !(1 == ~T6_E~0); 4191#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4263#L770-1 assume !(1 == ~E_2~0); 4049#L775-1 assume !(1 == ~E_3~0); 3983#L780-1 assume !(1 == ~E_4~0); 3984#L785-1 assume !(1 == ~E_5~0); 4174#L790-1 assume !(1 == ~E_6~0); 4039#L1016-1 [2021-10-13 01:19:43,039 INFO L793 eck$LassoCheckResult]: Loop: 4039#L1016-1 assume !false; 4203#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4101#L637 assume !false; 4229#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4108#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3739#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3949#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4214#L548 assume !(0 != eval_~tmp~0); 4140#L652 start_simulation_~kernel_st~0 := 2; 4141#L446-1 start_simulation_~kernel_st~0 := 3; 4059#L662-2 assume !(0 == ~M_E~0); 4060#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4040#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4041#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3863#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3864#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4224#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3910#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3911#L697-3 assume !(0 == ~E_2~0); 4003#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4004#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4135#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3806#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3807#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4160#L312-21 assume !(1 == ~m_pc~0); 4257#L312-23 is_master_triggered_~__retres1~0 := 0; 4070#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3679#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3680#L817-21 assume !(0 != activate_threads_~tmp~1); 4078#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4079#L331-21 assume 1 == ~t1_pc~0; 4025#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3903#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3721#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3722#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4243#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4195#L350-21 assume !(1 == ~t2_pc~0); 3840#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 3839#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4264#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3713#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3714#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3816#L369-21 assume !(1 == ~t3_pc~0); 4001#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 3681#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3682#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4211#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3843#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3844#L388-21 assume 1 == ~t4_pc~0; 4197#L389-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3683#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3684#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3923#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4005#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4006#L407-21 assume !(1 == ~t5_pc~0); 4000#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 3767#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3768#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3701#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3702#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4152#L426-21 assume 1 == ~t6_pc~0; 3828#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3829#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3926#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3937#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4045#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3789#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3790#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4220#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4221#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3804#L755-3 assume !(1 == ~T5_E~0); 3805#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4054#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4016#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4017#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4096#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3741#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3742#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4186#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4057#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3877#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4247#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4189#L1035 assume !(0 == start_simulation_~tmp~3); 4102#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4103#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4021#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4169#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 3892#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3893#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 4082#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 4038#L1048 assume !(0 != start_simulation_~tmp___0~1); 4039#L1016-1 [2021-10-13 01:19:43,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,041 INFO L82 PathProgramCache]: Analyzing trace with hash 1307097985, now seen corresponding path program 1 times [2021-10-13 01:19:43,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566052073] [2021-10-13 01:19:43,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,042 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,097 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,097 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566052073] [2021-10-13 01:19:43,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566052073] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,097 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,098 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,098 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236477566] [2021-10-13 01:19:43,098 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,099 INFO L82 PathProgramCache]: Analyzing trace with hash 789336131, now seen corresponding path program 1 times [2021-10-13 01:19:43,099 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,099 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537743562] [2021-10-13 01:19:43,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,100 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,159 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,159 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537743562] [2021-10-13 01:19:43,159 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537743562] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,159 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,159 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,160 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118409895] [2021-10-13 01:19:43,160 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,160 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,161 INFO L87 Difference]: Start difference. First operand 606 states and 915 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:43,175 INFO L93 Difference]: Finished difference Result 606 states and 914 transitions. [2021-10-13 01:19:43,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:43,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 914 transitions. [2021-10-13 01:19:43,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 914 transitions. [2021-10-13 01:19:43,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 914 transitions. [2021-10-13 01:19:43,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,193 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2021-10-13 01:19:43,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 914 transitions. [2021-10-13 01:19:43,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.5082508250825082) internal successors, (914), 605 states have internal predecessors, (914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 914 transitions. [2021-10-13 01:19:43,208 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2021-10-13 01:19:43,208 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2021-10-13 01:19:43,208 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-13 01:19:43,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 914 transitions. [2021-10-13 01:19:43,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,221 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,221 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,221 INFO L791 eck$LassoCheckResult]: Stem: 5493#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5481#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5149#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5150#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 5243#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5184#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5185#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5358#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5363#L473-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5151#L478-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5152#L483-1 assume !(0 == ~M_E~0); 5432#L662-1 assume !(0 == ~T1_E~0); 5343#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5344#L672-1 assume !(0 == ~T3_E~0); 5195#L677-1 assume !(0 == ~T4_E~0); 5196#L682-1 assume !(0 == ~T5_E~0); 5398#L687-1 assume !(0 == ~T6_E~0); 5455#L692-1 assume !(0 == ~E_1~0); 5386#L697-1 assume !(0 == ~E_2~0); 5387#L702-1 assume !(0 == ~E_3~0); 5427#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5308#L712-1 assume !(0 == ~E_5~0); 5309#L717-1 assume !(0 == ~E_6~0); 5407#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5186#L312 assume 1 == ~m_pc~0; 4944#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4890#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4891#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5014#L817 assume !(0 != activate_threads_~tmp~1); 5015#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5206#L331 assume !(1 == ~t1_pc~0); 5160#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 4967#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4968#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5169#L825 assume !(0 != activate_threads_~tmp___0~0); 5170#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5126#L350 assume 1 == ~t2_pc~0; 5127#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5313#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5314#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4994#L833 assume !(0 != activate_threads_~tmp___1~0); 4995#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5480#L369 assume 1 == ~t3_pc~0; 5374#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5065#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5043#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5044#L841 assume !(0 != activate_threads_~tmp___2~0); 5161#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5162#L388 assume !(1 == ~t4_pc~0); 5216#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 5045#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5046#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5180#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5181#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4911#L407 assume 1 == ~t5_pc~0; 4912#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4924#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4892#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4893#L857 assume !(0 != activate_threads_~tmp___4~0); 5055#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5056#L426 assume !(1 == ~t6_pc~0); 5351#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 5404#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5469#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5447#L865 assume !(0 != activate_threads_~tmp___5~0); 4953#L865-2 assume !(1 == ~M_E~0); 4954#L735-1 assume !(1 == ~T1_E~0); 5034#L740-1 assume !(1 == ~T2_E~0); 4999#L745-1 assume !(1 == ~T3_E~0); 5000#L750-1 assume !(1 == ~T4_E~0); 5426#L755-1 assume !(1 == ~T5_E~0); 5409#L760-1 assume !(1 == ~T6_E~0); 5410#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5482#L770-1 assume !(1 == ~E_2~0); 5268#L775-1 assume !(1 == ~E_3~0); 5202#L780-1 assume !(1 == ~E_4~0); 5203#L785-1 assume !(1 == ~E_5~0); 5393#L790-1 assume !(1 == ~E_6~0); 5258#L1016-1 [2021-10-13 01:19:43,222 INFO L793 eck$LassoCheckResult]: Loop: 5258#L1016-1 assume !false; 5422#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5320#L637 assume !false; 5448#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5327#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4958#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5168#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5433#L548 assume !(0 != eval_~tmp~0); 5359#L652 start_simulation_~kernel_st~0 := 2; 5360#L446-1 start_simulation_~kernel_st~0 := 3; 5278#L662-2 assume !(0 == ~M_E~0); 5279#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5259#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5260#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5082#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5083#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5443#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5129#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5130#L697-3 assume !(0 == ~E_2~0); 5222#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5223#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5354#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5025#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5026#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5379#L312-21 assume !(1 == ~m_pc~0); 5476#L312-23 is_master_triggered_~__retres1~0 := 0; 5289#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4898#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4899#L817-21 assume !(0 != activate_threads_~tmp~1); 5297#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5298#L331-21 assume 1 == ~t1_pc~0; 5244#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5122#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4940#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4941#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5462#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5414#L350-21 assume 1 == ~t2_pc~0; 5057#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5058#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5483#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4932#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4933#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5035#L369-21 assume !(1 == ~t3_pc~0); 5220#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 4900#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4901#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5430#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5062#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5063#L388-21 assume !(1 == ~t4_pc~0); 5090#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 4902#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4903#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5142#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5224#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5225#L407-21 assume 1 == ~t5_pc~0; 5218#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4986#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4987#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4920#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4921#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5371#L426-21 assume 1 == ~t6_pc~0; 5047#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5048#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5145#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5156#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5264#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5008#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5009#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5439#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5440#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5023#L755-3 assume !(1 == ~T5_E~0); 5024#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5273#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5235#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5236#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5315#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4960#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4961#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5405#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5276#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5096#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5466#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5408#L1035 assume !(0 == start_simulation_~tmp~3); 5321#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5322#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5240#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5388#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 5111#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5112#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 5301#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 5257#L1048 assume !(0 != start_simulation_~tmp___0~1); 5258#L1016-1 [2021-10-13 01:19:43,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,222 INFO L82 PathProgramCache]: Analyzing trace with hash -2020518657, now seen corresponding path program 1 times [2021-10-13 01:19:43,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,223 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772713907] [2021-10-13 01:19:43,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,223 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,262 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772713907] [2021-10-13 01:19:43,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772713907] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,262 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497312840] [2021-10-13 01:19:43,264 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,265 INFO L82 PathProgramCache]: Analyzing trace with hash -1624232190, now seen corresponding path program 2 times [2021-10-13 01:19:43,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729621349] [2021-10-13 01:19:43,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,266 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,324 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729621349] [2021-10-13 01:19:43,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729621349] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,324 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803488206] [2021-10-13 01:19:43,325 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,329 INFO L87 Difference]: Start difference. First operand 606 states and 914 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:43,343 INFO L93 Difference]: Finished difference Result 606 states and 913 transitions. [2021-10-13 01:19:43,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:43,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 913 transitions. [2021-10-13 01:19:43,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 913 transitions. [2021-10-13 01:19:43,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 913 transitions. [2021-10-13 01:19:43,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,358 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2021-10-13 01:19:43,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 913 transitions. [2021-10-13 01:19:43,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.5066006600660067) internal successors, (913), 605 states have internal predecessors, (913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 913 transitions. [2021-10-13 01:19:43,374 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2021-10-13 01:19:43,374 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2021-10-13 01:19:43,375 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-13 01:19:43,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 913 transitions. [2021-10-13 01:19:43,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,381 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,381 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,381 INFO L791 eck$LassoCheckResult]: Stem: 6712#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6700#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6368#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6369#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 6462#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6403#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6404#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6577#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6582#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6370#L478-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6371#L483-1 assume !(0 == ~M_E~0); 6651#L662-1 assume !(0 == ~T1_E~0); 6562#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6563#L672-1 assume !(0 == ~T3_E~0); 6414#L677-1 assume !(0 == ~T4_E~0); 6415#L682-1 assume !(0 == ~T5_E~0); 6617#L687-1 assume !(0 == ~T6_E~0); 6674#L692-1 assume !(0 == ~E_1~0); 6605#L697-1 assume !(0 == ~E_2~0); 6606#L702-1 assume !(0 == ~E_3~0); 6646#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6527#L712-1 assume !(0 == ~E_5~0); 6528#L717-1 assume !(0 == ~E_6~0); 6626#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6405#L312 assume 1 == ~m_pc~0; 6163#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6109#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6110#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6233#L817 assume !(0 != activate_threads_~tmp~1); 6234#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6425#L331 assume !(1 == ~t1_pc~0); 6379#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 6186#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6187#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6388#L825 assume !(0 != activate_threads_~tmp___0~0); 6389#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6345#L350 assume 1 == ~t2_pc~0; 6346#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6532#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6533#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6213#L833 assume !(0 != activate_threads_~tmp___1~0); 6214#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6699#L369 assume 1 == ~t3_pc~0; 6593#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6284#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6262#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6263#L841 assume !(0 != activate_threads_~tmp___2~0); 6380#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6381#L388 assume !(1 == ~t4_pc~0); 6435#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 6264#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6265#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6399#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6400#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6130#L407 assume 1 == ~t5_pc~0; 6131#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6143#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6111#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6112#L857 assume !(0 != activate_threads_~tmp___4~0); 6274#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6275#L426 assume !(1 == ~t6_pc~0); 6570#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 6623#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6688#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6666#L865 assume !(0 != activate_threads_~tmp___5~0); 6172#L865-2 assume !(1 == ~M_E~0); 6173#L735-1 assume !(1 == ~T1_E~0); 6253#L740-1 assume !(1 == ~T2_E~0); 6218#L745-1 assume !(1 == ~T3_E~0); 6219#L750-1 assume !(1 == ~T4_E~0); 6645#L755-1 assume !(1 == ~T5_E~0); 6628#L760-1 assume !(1 == ~T6_E~0); 6629#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6701#L770-1 assume !(1 == ~E_2~0); 6487#L775-1 assume !(1 == ~E_3~0); 6421#L780-1 assume !(1 == ~E_4~0); 6422#L785-1 assume !(1 == ~E_5~0); 6612#L790-1 assume !(1 == ~E_6~0); 6477#L1016-1 [2021-10-13 01:19:43,382 INFO L793 eck$LassoCheckResult]: Loop: 6477#L1016-1 assume !false; 6641#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 6539#L637 assume !false; 6667#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6546#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6177#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6387#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6652#L548 assume !(0 != eval_~tmp~0); 6578#L652 start_simulation_~kernel_st~0 := 2; 6579#L446-1 start_simulation_~kernel_st~0 := 3; 6497#L662-2 assume !(0 == ~M_E~0); 6498#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6478#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6479#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6301#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6302#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6662#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6348#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6349#L697-3 assume !(0 == ~E_2~0); 6441#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6442#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6573#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6244#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6245#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6598#L312-21 assume !(1 == ~m_pc~0); 6695#L312-23 is_master_triggered_~__retres1~0 := 0; 6508#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6117#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6118#L817-21 assume !(0 != activate_threads_~tmp~1); 6516#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6517#L331-21 assume !(1 == ~t1_pc~0); 6464#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 6341#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6159#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6160#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6681#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6633#L350-21 assume 1 == ~t2_pc~0; 6276#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6277#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6702#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6151#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6152#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6254#L369-21 assume !(1 == ~t3_pc~0); 6439#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 6119#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6120#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6649#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6281#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6282#L388-21 assume !(1 == ~t4_pc~0); 6309#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 6121#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6122#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6361#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6443#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6444#L407-21 assume 1 == ~t5_pc~0; 6437#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6205#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6206#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6139#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6140#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6590#L426-21 assume 1 == ~t6_pc~0; 6266#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6267#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6364#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6375#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6483#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6227#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6228#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6658#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6659#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6242#L755-3 assume !(1 == ~T5_E~0); 6243#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6492#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6454#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6455#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6534#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6179#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6180#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6624#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6495#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6315#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6685#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6627#L1035 assume !(0 == start_simulation_~tmp~3); 6540#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6541#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6459#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6607#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 6330#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6331#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 6520#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 6476#L1048 assume !(0 != start_simulation_~tmp___0~1); 6477#L1016-1 [2021-10-13 01:19:43,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,382 INFO L82 PathProgramCache]: Analyzing trace with hash 365990849, now seen corresponding path program 1 times [2021-10-13 01:19:43,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,383 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851655279] [2021-10-13 01:19:43,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,384 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,422 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851655279] [2021-10-13 01:19:43,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851655279] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,423 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,424 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411510167] [2021-10-13 01:19:43,426 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,427 INFO L82 PathProgramCache]: Analyzing trace with hash -595700029, now seen corresponding path program 1 times [2021-10-13 01:19:43,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666868463] [2021-10-13 01:19:43,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,428 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,472 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666868463] [2021-10-13 01:19:43,472 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666868463] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,472 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315086728] [2021-10-13 01:19:43,475 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,476 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,480 INFO L87 Difference]: Start difference. First operand 606 states and 913 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:43,496 INFO L93 Difference]: Finished difference Result 606 states and 912 transitions. [2021-10-13 01:19:43,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:43,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 912 transitions. [2021-10-13 01:19:43,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 912 transitions. [2021-10-13 01:19:43,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 912 transitions. [2021-10-13 01:19:43,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,516 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2021-10-13 01:19:43,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 912 transitions. [2021-10-13 01:19:43,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.504950495049505) internal successors, (912), 605 states have internal predecessors, (912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 912 transitions. [2021-10-13 01:19:43,557 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2021-10-13 01:19:43,557 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2021-10-13 01:19:43,558 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-13 01:19:43,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 912 transitions. [2021-10-13 01:19:43,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,566 INFO L791 eck$LassoCheckResult]: Stem: 7931#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 7919#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7587#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7588#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 7681#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7622#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7623#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7796#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7801#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7589#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7590#L483-1 assume !(0 == ~M_E~0); 7870#L662-1 assume !(0 == ~T1_E~0); 7781#L667-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7782#L672-1 assume !(0 == ~T3_E~0); 7633#L677-1 assume !(0 == ~T4_E~0); 7634#L682-1 assume !(0 == ~T5_E~0); 7836#L687-1 assume !(0 == ~T6_E~0); 7893#L692-1 assume !(0 == ~E_1~0); 7824#L697-1 assume !(0 == ~E_2~0); 7825#L702-1 assume !(0 == ~E_3~0); 7866#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7746#L712-1 assume !(0 == ~E_5~0); 7747#L717-1 assume !(0 == ~E_6~0); 7846#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7624#L312 assume 1 == ~m_pc~0; 7382#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7328#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7329#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7452#L817 assume !(0 != activate_threads_~tmp~1); 7453#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7644#L331 assume !(1 == ~t1_pc~0); 7598#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 7405#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7406#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7607#L825 assume !(0 != activate_threads_~tmp___0~0); 7608#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7564#L350 assume 1 == ~t2_pc~0; 7565#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7751#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7752#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7432#L833 assume !(0 != activate_threads_~tmp___1~0); 7433#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7918#L369 assume 1 == ~t3_pc~0; 7812#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7503#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7484#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7485#L841 assume !(0 != activate_threads_~tmp___2~0); 7602#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7603#L388 assume !(1 == ~t4_pc~0); 7654#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 7486#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7487#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7618#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7619#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7351#L407 assume 1 == ~t5_pc~0; 7352#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7362#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7330#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7331#L857 assume !(0 != activate_threads_~tmp___4~0); 7493#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7494#L426 assume !(1 == ~t6_pc~0); 7789#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 7842#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7907#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7885#L865 assume !(0 != activate_threads_~tmp___5~0); 7391#L865-2 assume !(1 == ~M_E~0); 7392#L735-1 assume !(1 == ~T1_E~0); 7472#L740-1 assume !(1 == ~T2_E~0); 7437#L745-1 assume !(1 == ~T3_E~0); 7438#L750-1 assume !(1 == ~T4_E~0); 7864#L755-1 assume !(1 == ~T5_E~0); 7847#L760-1 assume !(1 == ~T6_E~0); 7848#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7920#L770-1 assume !(1 == ~E_2~0); 7707#L775-1 assume !(1 == ~E_3~0); 7640#L780-1 assume !(1 == ~E_4~0); 7641#L785-1 assume !(1 == ~E_5~0); 7831#L790-1 assume !(1 == ~E_6~0); 7694#L1016-1 [2021-10-13 01:19:43,567 INFO L793 eck$LassoCheckResult]: Loop: 7694#L1016-1 assume !false; 7860#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7760#L637 assume !false; 7887#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7765#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7396#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7606#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7871#L548 assume !(0 != eval_~tmp~0); 7799#L652 start_simulation_~kernel_st~0 := 2; 7800#L446-1 start_simulation_~kernel_st~0 := 3; 7716#L662-2 assume !(0 == ~M_E~0); 7717#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7698#L667-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7699#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7520#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7521#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7881#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7567#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7568#L697-3 assume !(0 == ~E_2~0); 7662#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7663#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7792#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7465#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7466#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7817#L312-21 assume !(1 == ~m_pc~0); 7914#L312-23 is_master_triggered_~__retres1~0 := 0; 7727#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7336#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7337#L817-21 assume !(0 != activate_threads_~tmp~1); 7735#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7736#L331-21 assume 1 == ~t1_pc~0; 7682#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7560#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7378#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7379#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7900#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7853#L350-21 assume 1 == ~t2_pc~0; 7495#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7496#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7921#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7370#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7371#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7473#L369-21 assume !(1 == ~t3_pc~0); 7658#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 7338#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7339#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7868#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7500#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7501#L388-21 assume !(1 == ~t4_pc~0); 7528#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 7340#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7341#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7579#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7660#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7661#L407-21 assume 1 == ~t5_pc~0; 7655#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7424#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7425#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7356#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7357#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7808#L426-21 assume 1 == ~t6_pc~0; 7481#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7482#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7583#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7594#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7702#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7446#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7447#L740-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7877#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7878#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7461#L755-3 assume !(1 == ~T5_E~0); 7462#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7711#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7673#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7674#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7753#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7398#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7399#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7843#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7714#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7532#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7904#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7845#L1035 assume !(0 == start_simulation_~tmp~3); 7757#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7758#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7678#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7826#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 7548#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7549#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 7739#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 7693#L1048 assume !(0 != start_simulation_~tmp___0~1); 7694#L1016-1 [2021-10-13 01:19:43,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,568 INFO L82 PathProgramCache]: Analyzing trace with hash 858617023, now seen corresponding path program 1 times [2021-10-13 01:19:43,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,569 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322725434] [2021-10-13 01:19:43,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,569 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,606 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322725434] [2021-10-13 01:19:43,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322725434] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,607 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,607 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:43,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153744732] [2021-10-13 01:19:43,608 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1624232190, now seen corresponding path program 3 times [2021-10-13 01:19:43,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,609 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175111355] [2021-10-13 01:19:43,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,610 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,668 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175111355] [2021-10-13 01:19:43,668 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175111355] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,669 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574272210] [2021-10-13 01:19:43,670 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,670 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,671 INFO L87 Difference]: Start difference. First operand 606 states and 912 transitions. cyclomatic complexity: 307 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 2 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:43,694 INFO L93 Difference]: Finished difference Result 606 states and 907 transitions. [2021-10-13 01:19:43,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:43,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 907 transitions. [2021-10-13 01:19:43,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 907 transitions. [2021-10-13 01:19:43,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 907 transitions. [2021-10-13 01:19:43,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,709 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2021-10-13 01:19:43,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 907 transitions. [2021-10-13 01:19:43,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.4966996699669968) internal successors, (907), 605 states have internal predecessors, (907), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 907 transitions. [2021-10-13 01:19:43,725 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2021-10-13 01:19:43,725 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2021-10-13 01:19:43,725 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-13 01:19:43,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 907 transitions. [2021-10-13 01:19:43,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,732 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,732 INFO L791 eck$LassoCheckResult]: Stem: 9150#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9138#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8806#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8807#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 8900#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8841#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8842#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9015#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9020#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8808#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8809#L483-1 assume !(0 == ~M_E~0); 9089#L662-1 assume !(0 == ~T1_E~0); 9000#L667-1 assume !(0 == ~T2_E~0); 9001#L672-1 assume !(0 == ~T3_E~0); 8852#L677-1 assume !(0 == ~T4_E~0); 8853#L682-1 assume !(0 == ~T5_E~0); 9056#L687-1 assume !(0 == ~T6_E~0); 9113#L692-1 assume !(0 == ~E_1~0); 9043#L697-1 assume !(0 == ~E_2~0); 9044#L702-1 assume !(0 == ~E_3~0); 9085#L707-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8965#L712-1 assume !(0 == ~E_5~0); 8966#L717-1 assume !(0 == ~E_6~0); 9065#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8843#L312 assume 1 == ~m_pc~0; 8601#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8547#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8548#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8671#L817 assume !(0 != activate_threads_~tmp~1); 8672#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8863#L331 assume !(1 == ~t1_pc~0); 8817#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 8624#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8625#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8826#L825 assume !(0 != activate_threads_~tmp___0~0); 8827#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8783#L350 assume 1 == ~t2_pc~0; 8784#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8970#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8971#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8651#L833 assume !(0 != activate_threads_~tmp___1~0); 8652#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9137#L369 assume 1 == ~t3_pc~0; 9031#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8722#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8703#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8704#L841 assume !(0 != activate_threads_~tmp___2~0); 8821#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8822#L388 assume !(1 == ~t4_pc~0); 8873#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 8705#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8706#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8837#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8838#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8570#L407 assume 1 == ~t5_pc~0; 8571#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8583#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8549#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8550#L857 assume !(0 != activate_threads_~tmp___4~0); 8712#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8713#L426 assume !(1 == ~t6_pc~0); 9008#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 9061#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9126#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9104#L865 assume !(0 != activate_threads_~tmp___5~0); 8610#L865-2 assume !(1 == ~M_E~0); 8611#L735-1 assume !(1 == ~T1_E~0); 8692#L740-1 assume !(1 == ~T2_E~0); 8656#L745-1 assume !(1 == ~T3_E~0); 8657#L750-1 assume !(1 == ~T4_E~0); 9083#L755-1 assume !(1 == ~T5_E~0); 9066#L760-1 assume !(1 == ~T6_E~0); 9067#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9139#L770-1 assume !(1 == ~E_2~0); 8926#L775-1 assume !(1 == ~E_3~0); 8859#L780-1 assume !(1 == ~E_4~0); 8860#L785-1 assume !(1 == ~E_5~0); 9050#L790-1 assume !(1 == ~E_6~0); 8913#L1016-1 [2021-10-13 01:19:43,732 INFO L793 eck$LassoCheckResult]: Loop: 8913#L1016-1 assume !false; 9079#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8979#L637 assume !false; 9106#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8986#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8615#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8825#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 9090#L548 assume !(0 != eval_~tmp~0); 9018#L652 start_simulation_~kernel_st~0 := 2; 9019#L446-1 start_simulation_~kernel_st~0 := 3; 8935#L662-2 assume !(0 == ~M_E~0); 8936#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8917#L667-3 assume !(0 == ~T2_E~0); 8918#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8739#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8740#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9100#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8786#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8787#L697-3 assume !(0 == ~E_2~0); 8881#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8882#L707-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9012#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8684#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8685#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9036#L312-21 assume !(1 == ~m_pc~0); 9133#L312-23 is_master_triggered_~__retres1~0 := 0; 8946#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8555#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8556#L817-21 assume !(0 != activate_threads_~tmp~1); 8954#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8955#L331-21 assume 1 == ~t1_pc~0; 8901#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8779#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8597#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8598#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9119#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9071#L350-21 assume 1 == ~t2_pc~0; 8714#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8715#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9140#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8589#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8590#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8691#L369-21 assume !(1 == ~t3_pc~0); 8877#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 8557#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8558#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9087#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8719#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8720#L388-21 assume 1 == ~t4_pc~0; 9073#L389-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8559#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8560#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8799#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8879#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8880#L407-21 assume 1 == ~t5_pc~0; 8874#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8643#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8644#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8575#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8576#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9028#L426-21 assume 1 == ~t6_pc~0; 8700#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8701#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8802#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8813#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8921#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 8665#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8666#L740-3 assume !(1 == ~T2_E~0); 9096#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9097#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8680#L755-3 assume !(1 == ~T5_E~0); 8681#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8930#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8892#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8893#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8972#L780-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8617#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8618#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9062#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8933#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8753#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9123#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9064#L1035 assume !(0 == start_simulation_~tmp~3); 8976#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8977#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8897#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9045#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 8768#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8769#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 8958#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 8912#L1048 assume !(0 != start_simulation_~tmp___0~1); 8913#L1016-1 [2021-10-13 01:19:43,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,733 INFO L82 PathProgramCache]: Analyzing trace with hash 126649597, now seen corresponding path program 1 times [2021-10-13 01:19:43,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,734 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353849592] [2021-10-13 01:19:43,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,734 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353849592] [2021-10-13 01:19:43,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353849592] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,766 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:43,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556017190] [2021-10-13 01:19:43,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,768 INFO L82 PathProgramCache]: Analyzing trace with hash 878431041, now seen corresponding path program 1 times [2021-10-13 01:19:43,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268493926] [2021-10-13 01:19:43,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,769 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,808 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268493926] [2021-10-13 01:19:43,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268493926] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,816 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,816 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477605072] [2021-10-13 01:19:43,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,818 INFO L87 Difference]: Start difference. First operand 606 states and 907 transitions. cyclomatic complexity: 302 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 2 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:43,870 INFO L93 Difference]: Finished difference Result 606 states and 894 transitions. [2021-10-13 01:19:43,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:43,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 894 transitions. [2021-10-13 01:19:43,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 894 transitions. [2021-10-13 01:19:43,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2021-10-13 01:19:43,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2021-10-13 01:19:43,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 894 transitions. [2021-10-13 01:19:43,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:43,891 INFO L681 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2021-10-13 01:19:43,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 894 transitions. [2021-10-13 01:19:43,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2021-10-13 01:19:43,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606 states, 606 states have (on average 1.4752475247524752) internal successors, (894), 605 states have internal predecessors, (894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:43,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 894 transitions. [2021-10-13 01:19:43,907 INFO L704 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2021-10-13 01:19:43,908 INFO L587 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2021-10-13 01:19:43,908 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-13 01:19:43,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 894 transitions. [2021-10-13 01:19:43,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2021-10-13 01:19:43,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:43,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:43,914 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:43,914 INFO L791 eck$LassoCheckResult]: Stem: 10369#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 10357#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10023#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10024#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 10116#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10058#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10059#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10231#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10236#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10025#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10026#L483-1 assume !(0 == ~M_E~0); 10306#L662-1 assume !(0 == ~T1_E~0); 10216#L667-1 assume !(0 == ~T2_E~0); 10217#L672-1 assume !(0 == ~T3_E~0); 10069#L677-1 assume !(0 == ~T4_E~0); 10070#L682-1 assume !(0 == ~T5_E~0); 10273#L687-1 assume !(0 == ~T6_E~0); 10330#L692-1 assume !(0 == ~E_1~0); 10259#L697-1 assume !(0 == ~E_2~0); 10260#L702-1 assume !(0 == ~E_3~0); 10302#L707-1 assume !(0 == ~E_4~0); 10181#L712-1 assume !(0 == ~E_5~0); 10182#L717-1 assume !(0 == ~E_6~0); 10282#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10060#L312 assume 1 == ~m_pc~0; 9820#L313 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9768#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9769#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9891#L817 assume !(0 != activate_threads_~tmp~1); 9892#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10080#L331 assume !(1 == ~t1_pc~0); 10034#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 9841#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9842#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10043#L825 assume !(0 != activate_threads_~tmp___0~0); 10044#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10002#L350 assume 1 == ~t2_pc~0; 10003#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10186#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10187#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9868#L833 assume !(0 != activate_threads_~tmp___1~0); 9869#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10356#L369 assume 1 == ~t3_pc~0; 10247#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9939#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9920#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9921#L841 assume !(0 != activate_threads_~tmp___2~0); 10038#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10039#L388 assume !(1 == ~t4_pc~0); 10090#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 9922#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9923#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10054#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10055#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9787#L407 assume 1 == ~t5_pc~0; 9788#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9800#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9766#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9767#L857 assume !(0 != activate_threads_~tmp___4~0); 9929#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9930#L426 assume !(1 == ~t6_pc~0); 10224#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 10278#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10344#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10321#L865 assume !(0 != activate_threads_~tmp___5~0); 9828#L865-2 assume !(1 == ~M_E~0); 9829#L735-1 assume !(1 == ~T1_E~0); 9908#L740-1 assume !(1 == ~T2_E~0); 9873#L745-1 assume !(1 == ~T3_E~0); 9874#L750-1 assume !(1 == ~T4_E~0); 10300#L755-1 assume !(1 == ~T5_E~0); 10283#L760-1 assume !(1 == ~T6_E~0); 10284#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10358#L770-1 assume !(1 == ~E_2~0); 10141#L775-1 assume !(1 == ~E_3~0); 10076#L780-1 assume !(1 == ~E_4~0); 10077#L785-1 assume !(1 == ~E_5~0); 10267#L790-1 assume !(1 == ~E_6~0); 10131#L1016-1 [2021-10-13 01:19:43,915 INFO L793 eck$LassoCheckResult]: Loop: 10131#L1016-1 assume !false; 10296#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 10193#L637 assume !false; 10322#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10200#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9833#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10042#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 10307#L548 assume !(0 != eval_~tmp~0); 10232#L652 start_simulation_~kernel_st~0 := 2; 10233#L446-1 start_simulation_~kernel_st~0 := 3; 10151#L662-2 assume !(0 == ~M_E~0); 10152#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10132#L667-3 assume !(0 == ~T2_E~0); 10133#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9956#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9957#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10317#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10000#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10001#L697-3 assume !(0 == ~E_2~0); 10096#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10097#L707-3 assume !(0 == ~E_4~0); 10227#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9899#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9900#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10252#L312-21 assume !(1 == ~m_pc~0); 10352#L312-23 is_master_triggered_~__retres1~0 := 0; 10162#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9774#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9775#L817-21 assume !(0 != activate_threads_~tmp~1); 10170#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10171#L331-21 assume 1 == ~t1_pc~0; 10117#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9996#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9816#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9817#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10336#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10288#L350-21 assume 1 == ~t2_pc~0; 9931#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9932#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10359#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9808#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9809#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9909#L369-21 assume !(1 == ~t3_pc~0); 10094#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 9776#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9777#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10304#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9936#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9937#L388-21 assume !(1 == ~t4_pc~0); 9964#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 9778#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9779#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10016#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10098#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10099#L407-21 assume 1 == ~t5_pc~0; 10092#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9860#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9861#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9796#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9797#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10244#L426-21 assume 1 == ~t6_pc~0; 9917#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9918#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10019#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10030#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10137#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9882#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9883#L740-3 assume !(1 == ~T2_E~0); 10313#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10314#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9897#L755-3 assume !(1 == ~T5_E~0); 9898#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10146#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10108#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10109#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10188#L780-3 assume !(1 == ~E_4~0); 9835#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9836#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10279#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10149#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9970#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10340#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 10281#L1035 assume !(0 == start_simulation_~tmp~3); 10194#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10195#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10113#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10261#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 9985#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9986#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 10174#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 10130#L1048 assume !(0 != start_simulation_~tmp___0~1); 10131#L1016-1 [2021-10-13 01:19:43,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,915 INFO L82 PathProgramCache]: Analyzing trace with hash 560378683, now seen corresponding path program 1 times [2021-10-13 01:19:43,916 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,916 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389265435] [2021-10-13 01:19:43,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,916 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,955 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389265435] [2021-10-13 01:19:43,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389265435] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,956 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,956 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:43,956 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372704021] [2021-10-13 01:19:43,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:43,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:43,958 INFO L82 PathProgramCache]: Analyzing trace with hash 788542338, now seen corresponding path program 1 times [2021-10-13 01:19:43,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:43,958 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593978321] [2021-10-13 01:19:43,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:43,959 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:43,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:43,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:43,992 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:43,992 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593978321] [2021-10-13 01:19:43,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593978321] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:43,993 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:43,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:43,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890634569] [2021-10-13 01:19:43,993 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:43,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:43,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:43,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:43,994 INFO L87 Difference]: Start difference. First operand 606 states and 894 transitions. cyclomatic complexity: 289 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 2 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:44,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:44,066 INFO L93 Difference]: Finished difference Result 1117 states and 1630 transitions. [2021-10-13 01:19:44,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:44,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1117 states and 1630 transitions. [2021-10-13 01:19:44,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1032 [2021-10-13 01:19:44,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1117 states to 1117 states and 1630 transitions. [2021-10-13 01:19:44,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1117 [2021-10-13 01:19:44,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1117 [2021-10-13 01:19:44,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1117 states and 1630 transitions. [2021-10-13 01:19:44,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:44,095 INFO L681 BuchiCegarLoop]: Abstraction has 1117 states and 1630 transitions. [2021-10-13 01:19:44,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1117 states and 1630 transitions. [2021-10-13 01:19:44,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1117 to 1068. [2021-10-13 01:19:44,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1068 states, 1068 states have (on average 1.4634831460674158) internal successors, (1563), 1067 states have internal predecessors, (1563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:44,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1068 states to 1068 states and 1563 transitions. [2021-10-13 01:19:44,124 INFO L704 BuchiCegarLoop]: Abstraction has 1068 states and 1563 transitions. [2021-10-13 01:19:44,124 INFO L587 BuchiCegarLoop]: Abstraction has 1068 states and 1563 transitions. [2021-10-13 01:19:44,124 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-13 01:19:44,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1068 states and 1563 transitions. [2021-10-13 01:19:44,131 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 983 [2021-10-13 01:19:44,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:44,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:44,133 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:44,133 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:44,133 INFO L791 eck$LassoCheckResult]: Stem: 12158#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12135#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11752#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11753#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 11846#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11787#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11788#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11973#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11978#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11754#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11755#L483-1 assume !(0 == ~M_E~0); 12062#L662-1 assume !(0 == ~T1_E~0); 11956#L667-1 assume !(0 == ~T2_E~0); 11957#L672-1 assume !(0 == ~T3_E~0); 11799#L677-1 assume !(0 == ~T4_E~0); 11800#L682-1 assume !(0 == ~T5_E~0); 12017#L687-1 assume !(0 == ~T6_E~0); 12091#L692-1 assume !(0 == ~E_1~0); 12003#L697-1 assume !(0 == ~E_2~0); 12004#L702-1 assume !(0 == ~E_3~0); 12055#L707-1 assume !(0 == ~E_4~0); 11920#L712-1 assume !(0 == ~E_5~0); 11921#L717-1 assume !(0 == ~E_6~0); 12031#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11789#L312 assume !(1 == ~m_pc~0); 11669#L312-2 is_master_triggered_~__retres1~0 := 0; 11496#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11497#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11616#L817 assume !(0 != activate_threads_~tmp~1); 11617#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11810#L331 assume !(1 == ~t1_pc~0); 11763#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 11569#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11570#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11772#L825 assume !(0 != activate_threads_~tmp___0~0); 11773#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11728#L350 assume 1 == ~t2_pc~0; 11729#L351 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11925#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11926#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11596#L833 assume !(0 != activate_threads_~tmp___1~0); 11597#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12134#L369 assume 1 == ~t3_pc~0; 11989#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11666#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11644#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11645#L841 assume !(0 != activate_threads_~tmp___2~0); 11764#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11765#L388 assume !(1 == ~t4_pc~0); 11820#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 11646#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11647#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11783#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11784#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11517#L407 assume 1 == ~t5_pc~0; 11518#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11530#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11498#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11499#L857 assume !(0 != activate_threads_~tmp___4~0); 11656#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11657#L426 assume !(1 == ~t6_pc~0); 11965#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 12028#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12114#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12081#L865 assume !(0 != activate_threads_~tmp___5~0); 11556#L865-2 assume !(1 == ~M_E~0); 11557#L735-1 assume !(1 == ~T1_E~0); 11635#L740-1 assume !(1 == ~T2_E~0); 11601#L745-1 assume !(1 == ~T3_E~0); 11602#L750-1 assume !(1 == ~T4_E~0); 12054#L755-1 assume !(1 == ~T5_E~0); 12034#L760-1 assume !(1 == ~T6_E~0); 12035#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12136#L770-1 assume !(1 == ~E_2~0); 11875#L775-1 assume !(1 == ~E_3~0); 11806#L780-1 assume !(1 == ~E_4~0); 11807#L785-1 assume !(1 == ~E_5~0); 12011#L790-1 assume !(1 == ~E_6~0); 11863#L1016-1 [2021-10-13 01:19:44,133 INFO L793 eck$LassoCheckResult]: Loop: 11863#L1016-1 assume !false; 12048#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 11933#L637 assume !false; 12083#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11941#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11561#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11771#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 12063#L548 assume !(0 != eval_~tmp~0); 11974#L652 start_simulation_~kernel_st~0 := 2; 11975#L446-1 start_simulation_~kernel_st~0 := 3; 11887#L662-2 assume !(0 == ~M_E~0); 11888#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11864#L667-3 assume !(0 == ~T2_E~0); 11865#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11684#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11685#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12074#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11731#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11732#L697-3 assume !(0 == ~E_2~0); 11826#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11827#L707-3 assume !(0 == ~E_4~0); 11968#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11627#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11628#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11994#L312-21 assume !(1 == ~m_pc~0); 12129#L312-23 is_master_triggered_~__retres1~0 := 0; 12526#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12525#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12524#L817-21 assume !(0 != activate_threads_~tmp~1); 12523#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12522#L331-21 assume 1 == ~t1_pc~0; 12520#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12519#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12518#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12517#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12516#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12515#L350-21 assume 1 == ~t2_pc~0; 12513#L351-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12140#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12141#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12507#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12506#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12505#L369-21 assume 1 == ~t3_pc~0; 12503#L370-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12502#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12501#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12500#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11663#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11664#L388-21 assume !(1 == ~t4_pc~0); 12042#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 12497#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11744#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11745#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12308#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12307#L407-21 assume 1 == ~t5_pc~0; 12305#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12304#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12303#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12302#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12301#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12300#L426-21 assume 1 == ~t6_pc~0; 11648#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11649#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11748#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11759#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11905#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 12296#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12295#L740-3 assume !(1 == ~T2_E~0); 12294#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12086#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11625#L755-3 assume !(1 == ~T5_E~0); 11626#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11882#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11838#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11839#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11927#L780-3 assume !(1 == ~E_4~0); 11563#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11564#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12029#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12279#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 12278#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12109#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 12110#L1035 assume !(0 == start_simulation_~tmp~3); 11934#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11935#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11843#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12005#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 11713#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11714#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 11912#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 11862#L1048 assume !(0 != start_simulation_~tmp___0~1); 11863#L1016-1 [2021-10-13 01:19:44,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:44,157 INFO L82 PathProgramCache]: Analyzing trace with hash 663179930, now seen corresponding path program 1 times [2021-10-13 01:19:44,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:44,158 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056244915] [2021-10-13 01:19:44,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:44,158 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:44,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:44,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:44,197 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:44,198 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056244915] [2021-10-13 01:19:44,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056244915] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:44,198 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:44,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:44,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215366621] [2021-10-13 01:19:44,199 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:44,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:44,200 INFO L82 PathProgramCache]: Analyzing trace with hash -679660991, now seen corresponding path program 1 times [2021-10-13 01:19:44,200 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:44,200 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782565037] [2021-10-13 01:19:44,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:44,201 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:44,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:44,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:44,259 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:44,259 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782565037] [2021-10-13 01:19:44,259 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782565037] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:44,259 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:44,260 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:44,260 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934683568] [2021-10-13 01:19:44,260 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:44,260 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:44,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:19:44,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:19:44,261 INFO L87 Difference]: Start difference. First operand 1068 states and 1563 transitions. cyclomatic complexity: 497 Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:44,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:44,438 INFO L93 Difference]: Finished difference Result 2461 states and 3560 transitions. [2021-10-13 01:19:44,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:19:44,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2461 states and 3560 transitions. [2021-10-13 01:19:44,460 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2320 [2021-10-13 01:19:44,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2461 states to 2461 states and 3560 transitions. [2021-10-13 01:19:44,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2461 [2021-10-13 01:19:44,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2461 [2021-10-13 01:19:44,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2461 states and 3560 transitions. [2021-10-13 01:19:44,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:44,488 INFO L681 BuchiCegarLoop]: Abstraction has 2461 states and 3560 transitions. [2021-10-13 01:19:44,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2461 states and 3560 transitions. [2021-10-13 01:19:44,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2461 to 1935. [2021-10-13 01:19:44,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1935 states, 1935 states have (on average 1.455297157622739) internal successors, (2816), 1934 states have internal predecessors, (2816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:44,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1935 states to 1935 states and 2816 transitions. [2021-10-13 01:19:44,533 INFO L704 BuchiCegarLoop]: Abstraction has 1935 states and 2816 transitions. [2021-10-13 01:19:44,533 INFO L587 BuchiCegarLoop]: Abstraction has 1935 states and 2816 transitions. [2021-10-13 01:19:44,534 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-13 01:19:44,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1935 states and 2816 transitions. [2021-10-13 01:19:44,546 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1850 [2021-10-13 01:19:44,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:44,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:44,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:44,548 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:44,548 INFO L791 eck$LassoCheckResult]: Stem: 15696#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 15668#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15291#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15292#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 15388#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15326#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15327#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15516#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15521#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15293#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15294#L483-1 assume !(0 == ~M_E~0); 15601#L662-1 assume !(0 == ~T1_E~0); 15494#L667-1 assume !(0 == ~T2_E~0); 15495#L672-1 assume !(0 == ~T3_E~0); 15338#L677-1 assume !(0 == ~T4_E~0); 15339#L682-1 assume !(0 == ~T5_E~0); 15562#L687-1 assume !(0 == ~T6_E~0); 15631#L692-1 assume !(0 == ~E_1~0); 15546#L697-1 assume !(0 == ~E_2~0); 15547#L702-1 assume !(0 == ~E_3~0); 15594#L707-1 assume !(0 == ~E_4~0); 15460#L712-1 assume !(0 == ~E_5~0); 15461#L717-1 assume !(0 == ~E_6~0); 15574#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15329#L312 assume !(1 == ~m_pc~0); 15207#L312-2 is_master_triggered_~__retres1~0 := 0; 15035#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15036#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15155#L817 assume !(0 != activate_threads_~tmp~1); 15156#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15349#L331 assume !(1 == ~t1_pc~0); 15302#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 15108#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15109#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15311#L825 assume !(0 != activate_threads_~tmp___0~0); 15312#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15268#L350 assume !(1 == ~t2_pc~0); 15269#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 15465#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15466#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15135#L833 assume !(0 != activate_threads_~tmp___1~0); 15136#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15667#L369 assume 1 == ~t3_pc~0; 15534#L370 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15204#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15182#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15183#L841 assume !(0 != activate_threads_~tmp___2~0); 15303#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15304#L388 assume !(1 == ~t4_pc~0); 15359#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 15184#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15185#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15322#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15323#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15056#L407 assume 1 == ~t5_pc~0; 15057#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15069#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15037#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15038#L857 assume !(0 != activate_threads_~tmp___4~0); 15194#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15195#L426 assume !(1 == ~t6_pc~0); 15506#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 15571#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15647#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 15623#L865 assume !(0 != activate_threads_~tmp___5~0); 15095#L865-2 assume !(1 == ~M_E~0); 15096#L735-1 assume !(1 == ~T1_E~0); 15173#L740-1 assume !(1 == ~T2_E~0); 15140#L745-1 assume !(1 == ~T3_E~0); 15141#L750-1 assume !(1 == ~T4_E~0); 15593#L755-1 assume !(1 == ~T5_E~0); 15576#L760-1 assume !(1 == ~T6_E~0); 15577#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15669#L770-1 assume !(1 == ~E_2~0); 15416#L775-1 assume !(1 == ~E_3~0); 15345#L780-1 assume !(1 == ~E_4~0); 15346#L785-1 assume !(1 == ~E_5~0); 15557#L790-1 assume !(1 == ~E_6~0); 15405#L1016-1 [2021-10-13 01:19:44,548 INFO L793 eck$LassoCheckResult]: Loop: 15405#L1016-1 assume !false; 15589#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 15473#L637 assume !false; 15624#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15480#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15100#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15310#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15602#L548 assume !(0 != eval_~tmp~0); 15517#L652 start_simulation_~kernel_st~0 := 2; 15518#L446-1 start_simulation_~kernel_st~0 := 3; 15427#L662-2 assume !(0 == ~M_E~0); 15428#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15406#L667-3 assume !(0 == ~T2_E~0); 15407#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15225#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15226#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15615#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15616#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16917#L697-3 assume !(0 == ~E_2~0); 16902#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15511#L707-3 assume !(0 == ~E_4~0); 15512#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15165#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15166#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15539#L312-21 assume !(1 == ~m_pc~0); 15659#L312-23 is_master_triggered_~__retres1~0 := 0; 15687#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16865#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16864#L817-21 assume !(0 != activate_threads_~tmp~1); 16863#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16862#L331-21 assume 1 == ~t1_pc~0; 16860#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16859#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15085#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15086#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15639#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15581#L350-21 assume !(1 == ~t2_pc~0); 15208#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 15209#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15672#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15077#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15078#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15174#L369-21 assume !(1 == ~t3_pc~0); 15363#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 15045#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15046#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15599#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15199#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15200#L388-21 assume !(1 == ~t4_pc~0); 15232#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 15047#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15048#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15284#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15367#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15368#L407-21 assume 1 == ~t5_pc~0; 15361#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15127#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15128#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15065#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15066#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15531#L426-21 assume 1 == ~t6_pc~0; 15186#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15187#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15287#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 15298#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 15412#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 15149#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15150#L740-3 assume !(1 == ~T2_E~0); 15611#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15612#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15163#L755-3 assume !(1 == ~T5_E~0); 15164#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15422#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15380#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15381#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15467#L780-3 assume !(1 == ~E_4~0); 15102#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15103#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15572#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15425#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15238#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15643#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 15575#L1035 assume !(0 == start_simulation_~tmp~3); 15474#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15475#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15385#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15548#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 15253#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15254#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 15453#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 15404#L1048 assume !(0 != start_simulation_~tmp___0~1); 15405#L1016-1 [2021-10-13 01:19:44,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:44,549 INFO L82 PathProgramCache]: Analyzing trace with hash -1492334471, now seen corresponding path program 1 times [2021-10-13 01:19:44,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:44,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460051294] [2021-10-13 01:19:44,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:44,550 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:44,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:44,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:44,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:44,600 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460051294] [2021-10-13 01:19:44,600 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460051294] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:44,600 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:44,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:44,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688251274] [2021-10-13 01:19:44,601 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:44,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:44,602 INFO L82 PathProgramCache]: Analyzing trace with hash -319586301, now seen corresponding path program 1 times [2021-10-13 01:19:44,602 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:44,602 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985607284] [2021-10-13 01:19:44,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:44,602 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:44,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:44,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:44,633 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:44,634 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985607284] [2021-10-13 01:19:44,634 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985607284] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:44,634 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:44,634 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:44,634 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120647154] [2021-10-13 01:19:44,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:44,635 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:44,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:19:44,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:19:44,636 INFO L87 Difference]: Start difference. First operand 1935 states and 2816 transitions. cyclomatic complexity: 883 Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:44,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:44,811 INFO L93 Difference]: Finished difference Result 4526 states and 6516 transitions. [2021-10-13 01:19:44,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:19:44,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4526 states and 6516 transitions. [2021-10-13 01:19:44,849 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4329 [2021-10-13 01:19:44,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4526 states to 4526 states and 6516 transitions. [2021-10-13 01:19:44,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4526 [2021-10-13 01:19:44,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4526 [2021-10-13 01:19:44,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4526 states and 6516 transitions. [2021-10-13 01:19:44,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:44,903 INFO L681 BuchiCegarLoop]: Abstraction has 4526 states and 6516 transitions. [2021-10-13 01:19:44,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4526 states and 6516 transitions. [2021-10-13 01:19:45,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4526 to 3558. [2021-10-13 01:19:45,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3558 states, 3558 states have (on average 1.4477234401349073) internal successors, (5151), 3557 states have internal predecessors, (5151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:45,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3558 states to 3558 states and 5151 transitions. [2021-10-13 01:19:45,056 INFO L704 BuchiCegarLoop]: Abstraction has 3558 states and 5151 transitions. [2021-10-13 01:19:45,056 INFO L587 BuchiCegarLoop]: Abstraction has 3558 states and 5151 transitions. [2021-10-13 01:19:45,056 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-13 01:19:45,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3558 states and 5151 transitions. [2021-10-13 01:19:45,072 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3472 [2021-10-13 01:19:45,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:45,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:45,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:45,075 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:45,075 INFO L791 eck$LassoCheckResult]: Stem: 22173#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 22147#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21761#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21762#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 21860#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21796#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21797#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21987#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21992#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21763#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21764#L483-1 assume !(0 == ~M_E~0); 22073#L662-1 assume !(0 == ~T1_E~0); 21969#L667-1 assume !(0 == ~T2_E~0); 21970#L672-1 assume !(0 == ~T3_E~0); 21808#L677-1 assume !(0 == ~T4_E~0); 21809#L682-1 assume !(0 == ~T5_E~0); 22028#L687-1 assume !(0 == ~T6_E~0); 22100#L692-1 assume !(0 == ~E_1~0); 22015#L697-1 assume !(0 == ~E_2~0); 22016#L702-1 assume !(0 == ~E_3~0); 22066#L707-1 assume !(0 == ~E_4~0); 21926#L712-1 assume !(0 == ~E_5~0); 21927#L717-1 assume !(0 == ~E_6~0); 22041#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21799#L312 assume !(1 == ~m_pc~0); 21677#L312-2 is_master_triggered_~__retres1~0 := 0; 21506#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21507#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21625#L817 assume !(0 != activate_threads_~tmp~1); 21626#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21819#L331 assume !(1 == ~t1_pc~0); 21772#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 21579#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21580#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21781#L825 assume !(0 != activate_threads_~tmp___0~0); 21782#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21738#L350 assume !(1 == ~t2_pc~0); 21739#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 21933#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21934#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21606#L833 assume !(0 != activate_threads_~tmp___1~0); 21607#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22145#L369 assume !(1 == ~t3_pc~0); 21673#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 21674#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21652#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21653#L841 assume !(0 != activate_threads_~tmp___2~0); 21773#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21774#L388 assume !(1 == ~t4_pc~0); 21830#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 21654#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21655#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21792#L849 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21793#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21527#L407 assume 1 == ~t5_pc~0; 21528#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21540#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21508#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21509#L857 assume !(0 != activate_threads_~tmp___4~0); 21664#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21665#L426 assume !(1 == ~t6_pc~0); 21978#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 22038#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22119#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22091#L865 assume !(0 != activate_threads_~tmp___5~0); 21566#L865-2 assume !(1 == ~M_E~0); 21567#L735-1 assume !(1 == ~T1_E~0); 21643#L740-1 assume !(1 == ~T2_E~0); 21610#L745-1 assume !(1 == ~T3_E~0); 21611#L750-1 assume !(1 == ~T4_E~0); 22065#L755-1 assume !(1 == ~T5_E~0); 22043#L760-1 assume !(1 == ~T6_E~0); 22044#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 22148#L770-1 assume !(1 == ~E_2~0); 21887#L775-1 assume !(1 == ~E_3~0); 21815#L780-1 assume !(1 == ~E_4~0); 21816#L785-1 assume !(1 == ~E_5~0); 22023#L790-1 assume !(1 == ~E_6~0); 21877#L1016-1 [2021-10-13 01:19:45,076 INFO L793 eck$LassoCheckResult]: Loop: 21877#L1016-1 assume !false; 22060#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 21942#L637 assume !false; 22092#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 21953#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21571#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 21780#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 22074#L548 assume !(0 != eval_~tmp~0); 21988#L652 start_simulation_~kernel_st~0 := 2; 21989#L446-1 start_simulation_~kernel_st~0 := 3; 21898#L662-2 assume !(0 == ~M_E~0); 21899#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21878#L667-3 assume !(0 == ~T2_E~0); 21879#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22058#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24837#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24836#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24835#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24834#L697-3 assume !(0 == ~E_2~0); 24833#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24831#L707-3 assume !(0 == ~E_4~0); 24829#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24827#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24825#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24824#L312-21 assume !(1 == ~m_pc~0); 24822#L312-23 is_master_triggered_~__retres1~0 := 0; 24820#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24818#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 24816#L817-21 assume !(0 != activate_threads_~tmp~1); 24813#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24811#L331-21 assume 1 == ~t1_pc~0; 24808#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24806#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24804#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 24802#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24801#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22048#L350-21 assume !(1 == ~t2_pc~0); 21678#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 21679#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22149#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21548#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21549#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21644#L369-21 assume !(1 == ~t3_pc~0); 21834#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 21516#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21517#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22070#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21669#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21670#L388-21 assume !(1 == ~t4_pc~0); 21702#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 21518#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21519#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21753#L849-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21838#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21839#L407-21 assume 1 == ~t5_pc~0; 21832#L408-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21597#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21598#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21534#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21535#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22000#L426-21 assume 1 == ~t6_pc~0; 21656#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21657#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21757#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21768#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21884#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 21619#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21620#L740-3 assume !(1 == ~T2_E~0); 22081#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22082#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21633#L755-3 assume !(1 == ~T5_E~0); 21634#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21893#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21852#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21853#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21935#L780-3 assume !(1 == ~E_4~0); 21573#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21574#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22039#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 21896#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21708#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22115#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 22042#L1035 assume !(0 == start_simulation_~tmp~3); 21943#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 21944#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21857#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22017#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 21723#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21724#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 21919#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 21876#L1048 assume !(0 != start_simulation_~tmp___0~1); 21877#L1016-1 [2021-10-13 01:19:45,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:45,076 INFO L82 PathProgramCache]: Analyzing trace with hash 1037816216, now seen corresponding path program 1 times [2021-10-13 01:19:45,076 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:45,077 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521818325] [2021-10-13 01:19:45,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:45,077 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:45,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:45,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:45,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:45,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521818325] [2021-10-13 01:19:45,126 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521818325] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:45,126 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:45,126 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:19:45,127 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574994940] [2021-10-13 01:19:45,128 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:45,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:45,128 INFO L82 PathProgramCache]: Analyzing trace with hash -319586301, now seen corresponding path program 2 times [2021-10-13 01:19:45,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:45,129 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118616601] [2021-10-13 01:19:45,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:45,129 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:45,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:45,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:45,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:45,165 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118616601] [2021-10-13 01:19:45,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118616601] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:45,165 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:45,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:45,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33253444] [2021-10-13 01:19:45,166 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:45,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:45,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:19:45,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:19:45,167 INFO L87 Difference]: Start difference. First operand 3558 states and 5151 transitions. cyclomatic complexity: 1595 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:45,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:45,326 INFO L93 Difference]: Finished difference Result 5034 states and 7246 transitions. [2021-10-13 01:19:45,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:19:45,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5034 states and 7246 transitions. [2021-10-13 01:19:45,368 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4944 [2021-10-13 01:19:45,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5034 states to 5034 states and 7246 transitions. [2021-10-13 01:19:45,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5034 [2021-10-13 01:19:45,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5034 [2021-10-13 01:19:45,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5034 states and 7246 transitions. [2021-10-13 01:19:45,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:45,431 INFO L681 BuchiCegarLoop]: Abstraction has 5034 states and 7246 transitions. [2021-10-13 01:19:45,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5034 states and 7246 transitions. [2021-10-13 01:19:45,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5034 to 3570. [2021-10-13 01:19:45,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3570 states, 3570 states have (on average 1.4324929971988796) internal successors, (5114), 3569 states have internal predecessors, (5114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:45,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 5114 transitions. [2021-10-13 01:19:45,591 INFO L704 BuchiCegarLoop]: Abstraction has 3570 states and 5114 transitions. [2021-10-13 01:19:45,591 INFO L587 BuchiCegarLoop]: Abstraction has 3570 states and 5114 transitions. [2021-10-13 01:19:45,591 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-13 01:19:45,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3570 states and 5114 transitions. [2021-10-13 01:19:45,607 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3484 [2021-10-13 01:19:45,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:45,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:45,609 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:45,609 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:45,609 INFO L791 eck$LassoCheckResult]: Stem: 30814#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 30779#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 30367#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30368#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 30469#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30404#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30405#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30604#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30609#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30369#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30370#L483-1 assume !(0 == ~M_E~0); 30696#L662-1 assume !(0 == ~T1_E~0); 30583#L667-1 assume !(0 == ~T2_E~0); 30584#L672-1 assume !(0 == ~T3_E~0); 30415#L677-1 assume !(0 == ~T4_E~0); 30416#L682-1 assume !(0 == ~T5_E~0); 30649#L687-1 assume !(0 == ~T6_E~0); 30729#L692-1 assume !(0 == ~E_1~0); 30635#L697-1 assume !(0 == ~E_2~0); 30636#L702-1 assume !(0 == ~E_3~0); 30689#L707-1 assume !(0 == ~E_4~0); 30541#L712-1 assume !(0 == ~E_5~0); 30542#L717-1 assume !(0 == ~E_6~0); 30662#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30406#L312 assume !(1 == ~m_pc~0); 30283#L312-2 is_master_triggered_~__retres1~0 := 0; 30111#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30112#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30230#L817 assume !(0 != activate_threads_~tmp~1); 30231#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30426#L331 assume !(1 == ~t1_pc~0); 30379#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 30184#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30185#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30388#L825 assume !(0 != activate_threads_~tmp___0~0); 30389#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30344#L350 assume !(1 == ~t2_pc~0); 30345#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 30547#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30548#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30211#L833 assume !(0 != activate_threads_~tmp___1~0); 30212#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30776#L369 assume !(1 == ~t3_pc~0); 30279#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 30280#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30258#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30259#L841 assume !(0 != activate_threads_~tmp___2~0); 30380#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30381#L388 assume !(1 == ~t4_pc~0); 30437#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 30260#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30261#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30400#L849 assume !(0 != activate_threads_~tmp___3~0); 30401#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30132#L407 assume 1 == ~t5_pc~0; 30133#L408 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 30145#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30113#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 30114#L857 assume !(0 != activate_threads_~tmp___4~0); 30270#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30271#L426 assume !(1 == ~t6_pc~0); 30593#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 30659#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30753#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 30715#L865 assume !(0 != activate_threads_~tmp___5~0); 30171#L865-2 assume !(1 == ~M_E~0); 30172#L735-1 assume !(1 == ~T1_E~0); 30249#L740-1 assume !(1 == ~T2_E~0); 30215#L745-1 assume !(1 == ~T3_E~0); 30216#L750-1 assume !(1 == ~T4_E~0); 30687#L755-1 assume !(1 == ~T5_E~0); 30665#L760-1 assume !(1 == ~T6_E~0); 30666#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30781#L770-1 assume !(1 == ~E_2~0); 30499#L775-1 assume !(1 == ~E_3~0); 30422#L780-1 assume !(1 == ~E_4~0); 30423#L785-1 assume !(1 == ~E_5~0); 30643#L790-1 assume !(1 == ~E_6~0); 30719#L1016-1 [2021-10-13 01:19:45,610 INFO L793 eck$LassoCheckResult]: Loop: 30719#L1016-1 assume !false; 31972#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 31966#L637 assume !false; 31963#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 31960#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 31953#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 31951#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 31946#L548 assume !(0 != eval_~tmp~0); 31947#L652 start_simulation_~kernel_st~0 := 2; 33424#L446-1 start_simulation_~kernel_st~0 := 3; 33423#L662-2 assume !(0 == ~M_E~0); 33422#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33421#L667-3 assume !(0 == ~T2_E~0); 33420#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33419#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33417#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33415#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33413#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33411#L697-3 assume !(0 == ~E_2~0); 33408#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33406#L707-3 assume !(0 == ~E_4~0); 33404#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33401#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32704#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32702#L312-21 assume !(1 == ~m_pc~0); 32699#L312-23 is_master_triggered_~__retres1~0 := 0; 32697#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32696#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32691#L817-21 assume !(0 != activate_threads_~tmp~1); 32690#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32689#L331-21 assume !(1 == ~t1_pc~0); 32688#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 32685#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32686#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 33321#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33320#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33319#L350-21 assume !(1 == ~t2_pc~0); 32210#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 30786#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30787#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30153#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30154#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30250#L369-21 assume !(1 == ~t3_pc~0); 32148#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 32147#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32146#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 32145#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32144#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32143#L388-21 assume !(1 == ~t4_pc~0); 32141#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 32139#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32137#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32135#L849-21 assume !(0 != activate_threads_~tmp___3~0); 32133#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32130#L407-21 assume !(1 == ~t5_pc~0); 32128#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 32125#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32123#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32121#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32119#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32117#L426-21 assume !(1 == ~t6_pc~0); 32113#L426-23 is_transmit6_triggered_~__retres1~6 := 0; 32111#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32109#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32107#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32105#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 32103#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32100#L740-3 assume !(1 == ~T2_E~0); 32098#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32096#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32094#L755-3 assume !(1 == ~T5_E~0); 32091#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32087#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32084#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32080#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32075#L780-3 assume !(1 == ~E_4~0); 32071#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32067#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32065#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 32055#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 32050#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 32046#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 32042#L1035 assume !(0 == start_simulation_~tmp~3); 32037#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 32018#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 32013#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 32008#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 32004#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 31999#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 31993#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 31986#L1048 assume !(0 != start_simulation_~tmp___0~1); 30719#L1016-1 [2021-10-13 01:19:45,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:45,611 INFO L82 PathProgramCache]: Analyzing trace with hash 1099855830, now seen corresponding path program 1 times [2021-10-13 01:19:45,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:45,613 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636308750] [2021-10-13 01:19:45,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:45,613 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:45,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:45,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:45,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:45,660 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636308750] [2021-10-13 01:19:45,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636308750] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:45,660 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:45,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:45,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341998959] [2021-10-13 01:19:45,662 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:45,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:45,662 INFO L82 PathProgramCache]: Analyzing trace with hash -1782632312, now seen corresponding path program 1 times [2021-10-13 01:19:45,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:45,663 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090013003] [2021-10-13 01:19:45,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:45,663 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:45,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:45,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:45,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:45,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090013003] [2021-10-13 01:19:45,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090013003] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:45,690 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:45,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:45,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193351333] [2021-10-13 01:19:45,692 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:45,692 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:45,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:19:45,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:19:45,693 INFO L87 Difference]: Start difference. First operand 3570 states and 5114 transitions. cyclomatic complexity: 1546 Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:45,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:45,863 INFO L93 Difference]: Finished difference Result 8329 states and 11827 transitions. [2021-10-13 01:19:45,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:19:45,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8329 states and 11827 transitions. [2021-10-13 01:19:45,911 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8020 [2021-10-13 01:19:46,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8329 states to 8329 states and 11827 transitions. [2021-10-13 01:19:46,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8329 [2021-10-13 01:19:46,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8329 [2021-10-13 01:19:46,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8329 states and 11827 transitions. [2021-10-13 01:19:46,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:46,059 INFO L681 BuchiCegarLoop]: Abstraction has 8329 states and 11827 transitions. [2021-10-13 01:19:46,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8329 states and 11827 transitions. [2021-10-13 01:19:46,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8329 to 6609. [2021-10-13 01:19:46,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6609 states, 6609 states have (on average 1.4275987290059011) internal successors, (9435), 6608 states have internal predecessors, (9435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:46,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6609 states to 6609 states and 9435 transitions. [2021-10-13 01:19:46,229 INFO L704 BuchiCegarLoop]: Abstraction has 6609 states and 9435 transitions. [2021-10-13 01:19:46,229 INFO L587 BuchiCegarLoop]: Abstraction has 6609 states and 9435 transitions. [2021-10-13 01:19:46,229 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-13 01:19:46,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6609 states and 9435 transitions. [2021-10-13 01:19:46,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6520 [2021-10-13 01:19:46,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:46,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:46,263 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:46,263 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:46,264 INFO L791 eck$LassoCheckResult]: Stem: 42704#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 42676#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 42273#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 42274#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 42375#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42309#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42310#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42505#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42510#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42275#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42276#L483-1 assume !(0 == ~M_E~0); 42597#L662-1 assume !(0 == ~T1_E~0); 42486#L667-1 assume !(0 == ~T2_E~0); 42487#L672-1 assume !(0 == ~T3_E~0); 42321#L677-1 assume !(0 == ~T4_E~0); 42322#L682-1 assume !(0 == ~T5_E~0); 42552#L687-1 assume !(0 == ~T6_E~0); 42629#L692-1 assume !(0 == ~E_1~0); 42537#L697-1 assume !(0 == ~E_2~0); 42538#L702-1 assume !(0 == ~E_3~0); 42591#L707-1 assume !(0 == ~E_4~0); 42444#L712-1 assume !(0 == ~E_5~0); 42445#L717-1 assume !(0 == ~E_6~0); 42565#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42312#L312 assume !(1 == ~m_pc~0); 42188#L312-2 is_master_triggered_~__retres1~0 := 0; 42020#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42021#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42137#L817 assume !(0 != activate_threads_~tmp~1); 42138#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42332#L331 assume !(1 == ~t1_pc~0); 42284#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 42091#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42092#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42293#L825 assume !(0 != activate_threads_~tmp___0~0); 42294#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42250#L350 assume !(1 == ~t2_pc~0); 42251#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 42451#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42452#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42118#L833 assume !(0 != activate_threads_~tmp___1~0); 42119#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42675#L369 assume !(1 == ~t3_pc~0); 42184#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 42185#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42164#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42165#L841 assume !(0 != activate_threads_~tmp___2~0); 42285#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42286#L388 assume !(1 == ~t4_pc~0); 42342#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 42166#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42167#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 42305#L849 assume !(0 != activate_threads_~tmp___3~0); 42306#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42041#L407 assume !(1 == ~t5_pc~0); 42042#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 42053#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42022#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 42023#L857 assume !(0 != activate_threads_~tmp___4~0); 42175#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 42176#L426 assume !(1 == ~t6_pc~0); 42495#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 42562#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 42648#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 42619#L865 assume !(0 != activate_threads_~tmp___5~0); 42078#L865-2 assume !(1 == ~M_E~0); 42079#L735-1 assume !(1 == ~T1_E~0); 42155#L740-1 assume !(1 == ~T2_E~0); 42122#L745-1 assume !(1 == ~T3_E~0); 42123#L750-1 assume !(1 == ~T4_E~0); 42590#L755-1 assume !(1 == ~T5_E~0); 42567#L760-1 assume !(1 == ~T6_E~0); 42568#L765-1 assume 1 == ~E_1~0;~E_1~0 := 2; 42681#L770-1 assume !(1 == ~E_2~0); 42404#L775-1 assume !(1 == ~E_3~0); 42328#L780-1 assume !(1 == ~E_4~0); 42329#L785-1 assume !(1 == ~E_5~0); 42547#L790-1 assume !(1 == ~E_6~0); 42393#L1016-1 [2021-10-13 01:19:46,264 INFO L793 eck$LassoCheckResult]: Loop: 42393#L1016-1 assume !false; 42585#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 42460#L637 assume !false; 42624#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 42470#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 42083#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 42292#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 42598#L548 assume !(0 != eval_~tmp~0); 42684#L652 start_simulation_~kernel_st~0 := 2; 48626#L446-1 start_simulation_~kernel_st~0 := 3; 48625#L662-2 assume !(0 == ~M_E~0); 48624#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48623#L667-3 assume !(0 == ~T2_E~0); 48622#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48621#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48620#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48619#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48618#L692-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48617#L697-3 assume !(0 == ~E_2~0); 48616#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48615#L707-3 assume !(0 == ~E_4~0); 48614#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48613#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48612#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48611#L312-21 assume !(1 == ~m_pc~0); 48610#L312-23 is_master_triggered_~__retres1~0 := 0; 48609#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48608#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48607#L817-21 assume !(0 != activate_threads_~tmp~1); 48606#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48605#L331-21 assume 1 == ~t1_pc~0; 48603#L332-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 42246#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42068#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42069#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 42639#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42573#L350-21 assume !(1 == ~t2_pc~0); 42189#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 42190#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42682#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42060#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42061#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42156#L369-21 assume !(1 == ~t3_pc~0); 42347#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 42030#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42031#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42594#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42180#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42181#L388-21 assume !(1 == ~t4_pc~0); 42215#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 42032#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42033#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 42264#L849-21 assume !(0 != activate_threads_~tmp___3~0); 42351#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42352#L407-21 assume !(1 == ~t5_pc~0); 42615#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 42109#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42110#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 42047#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 42048#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 42522#L426-21 assume 1 == ~t6_pc~0; 42168#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 42169#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 42268#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 42280#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 42400#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 42131#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42132#L740-3 assume !(1 == ~T2_E~0); 42607#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42608#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42145#L755-3 assume !(1 == ~T5_E~0); 42146#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42410#L765-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42366#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42367#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42453#L780-3 assume !(1 == ~E_4~0); 42085#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42086#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42563#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 42413#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 42221#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 42643#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 42566#L1035 assume !(0 == start_simulation_~tmp~3); 42461#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 42462#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 42371#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 42539#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 42236#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 42237#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 42436#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 42392#L1048 assume !(0 != start_simulation_~tmp___0~1); 42393#L1016-1 [2021-10-13 01:19:46,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:46,265 INFO L82 PathProgramCache]: Analyzing trace with hash -490539147, now seen corresponding path program 1 times [2021-10-13 01:19:46,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:46,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219716904] [2021-10-13 01:19:46,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:46,266 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:46,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:46,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:46,318 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:46,318 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219716904] [2021-10-13 01:19:46,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219716904] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:46,318 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:46,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:46,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905779670] [2021-10-13 01:19:46,319 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:46,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:46,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1039693498, now seen corresponding path program 1 times [2021-10-13 01:19:46,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:46,320 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409839896] [2021-10-13 01:19:46,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:46,321 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:46,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:46,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:46,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:46,354 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409839896] [2021-10-13 01:19:46,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409839896] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:46,354 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:46,354 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:46,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868673975] [2021-10-13 01:19:46,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:46,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:46,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:46,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:46,358 INFO L87 Difference]: Start difference. First operand 6609 states and 9435 transitions. cyclomatic complexity: 2828 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 2 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:46,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:46,424 INFO L93 Difference]: Finished difference Result 6609 states and 9296 transitions. [2021-10-13 01:19:46,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:46,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6609 states and 9296 transitions. [2021-10-13 01:19:46,467 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6520 [2021-10-13 01:19:46,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6609 states to 6609 states and 9296 transitions. [2021-10-13 01:19:46,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6609 [2021-10-13 01:19:46,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6609 [2021-10-13 01:19:46,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6609 states and 9296 transitions. [2021-10-13 01:19:46,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:46,598 INFO L681 BuchiCegarLoop]: Abstraction has 6609 states and 9296 transitions. [2021-10-13 01:19:46,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6609 states and 9296 transitions. [2021-10-13 01:19:46,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6609 to 6609. [2021-10-13 01:19:46,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6609 states, 6609 states have (on average 1.406566802844606) internal successors, (9296), 6608 states have internal predecessors, (9296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:46,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6609 states to 6609 states and 9296 transitions. [2021-10-13 01:19:46,724 INFO L704 BuchiCegarLoop]: Abstraction has 6609 states and 9296 transitions. [2021-10-13 01:19:46,724 INFO L587 BuchiCegarLoop]: Abstraction has 6609 states and 9296 transitions. [2021-10-13 01:19:46,724 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-13 01:19:46,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6609 states and 9296 transitions. [2021-10-13 01:19:46,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6520 [2021-10-13 01:19:46,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:46,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:46,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:46,753 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:46,753 INFO L791 eck$LassoCheckResult]: Stem: 55923#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 55897#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 55495#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55496#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 55592#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55530#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55531#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55721#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55726#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55497#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55498#L483-1 assume !(0 == ~M_E~0); 55818#L662-1 assume !(0 == ~T1_E~0); 55701#L667-1 assume !(0 == ~T2_E~0); 55702#L672-1 assume !(0 == ~T3_E~0); 55541#L677-1 assume !(0 == ~T4_E~0); 55542#L682-1 assume !(0 == ~T5_E~0); 55769#L687-1 assume !(0 == ~T6_E~0); 55854#L692-1 assume !(0 == ~E_1~0); 55753#L697-1 assume !(0 == ~E_2~0); 55754#L702-1 assume !(0 == ~E_3~0); 55812#L707-1 assume !(0 == ~E_4~0); 55658#L712-1 assume !(0 == ~E_5~0); 55659#L717-1 assume !(0 == ~E_6~0); 55785#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55532#L312 assume !(1 == ~m_pc~0); 55413#L312-2 is_master_triggered_~__retres1~0 := 0; 55245#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55246#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 55365#L817 assume !(0 != activate_threads_~tmp~1); 55366#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55552#L331 assume !(1 == ~t1_pc~0); 55506#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 55316#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55317#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55515#L825 assume !(0 != activate_threads_~tmp___0~0); 55516#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55474#L350 assume !(1 == ~t2_pc~0); 55475#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 55666#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55667#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55343#L833 assume !(0 != activate_threads_~tmp___1~0); 55344#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55894#L369 assume !(1 == ~t3_pc~0); 55409#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 55410#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55392#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 55393#L841 assume !(0 != activate_threads_~tmp___2~0); 55510#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55511#L388 assume !(1 == ~t4_pc~0); 55562#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 55394#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55395#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 55526#L849 assume !(0 != activate_threads_~tmp___3~0); 55527#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55268#L407 assume !(1 == ~t5_pc~0); 55269#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 55280#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55247#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55248#L857 assume !(0 != activate_threads_~tmp___4~0); 55400#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 55401#L426 assume !(1 == ~t6_pc~0); 55712#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 55779#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 55872#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 55839#L865 assume !(0 != activate_threads_~tmp___5~0); 55303#L865-2 assume !(1 == ~M_E~0); 55304#L735-1 assume !(1 == ~T1_E~0); 55380#L740-1 assume !(1 == ~T2_E~0); 55347#L745-1 assume !(1 == ~T3_E~0); 55348#L750-1 assume !(1 == ~T4_E~0); 55809#L755-1 assume !(1 == ~T5_E~0); 55786#L760-1 assume !(1 == ~T6_E~0); 55787#L765-1 assume !(1 == ~E_1~0); 55899#L770-1 assume !(1 == ~E_2~0); 55619#L775-1 assume !(1 == ~E_3~0); 55548#L780-1 assume !(1 == ~E_4~0); 55549#L785-1 assume !(1 == ~E_5~0); 55761#L790-1 assume !(1 == ~E_6~0); 55845#L1016-1 [2021-10-13 01:19:46,753 INFO L793 eck$LassoCheckResult]: Loop: 55845#L1016-1 assume !false; 60324#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 60318#L637 assume !false; 60315#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60316#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60830#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60828#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 60826#L548 assume !(0 != eval_~tmp~0); 60824#L652 start_simulation_~kernel_st~0 := 2; 60822#L446-1 start_simulation_~kernel_st~0 := 3; 60820#L662-2 assume !(0 == ~M_E~0); 60818#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60815#L667-3 assume !(0 == ~T2_E~0); 60814#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60812#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60810#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60809#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60808#L692-3 assume !(0 == ~E_1~0); 60806#L697-3 assume !(0 == ~E_2~0); 60805#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60798#L707-3 assume !(0 == ~E_4~0); 60795#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60793#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60791#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60787#L312-21 assume !(1 == ~m_pc~0); 60782#L312-23 is_master_triggered_~__retres1~0 := 0; 60755#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60753#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 60751#L817-21 assume !(0 != activate_threads_~tmp~1); 60749#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60664#L331-21 assume !(1 == ~t1_pc~0); 60661#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 60658#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60656#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 60654#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60652#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60650#L350-21 assume !(1 == ~t2_pc~0); 59022#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 60645#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60643#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 60641#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 60552#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60551#L369-21 assume !(1 == ~t3_pc~0); 59564#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 60550#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60549#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 60548#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 60544#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60541#L388-21 assume !(1 == ~t4_pc~0); 60538#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 60536#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60533#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 60530#L849-21 assume !(0 != activate_threads_~tmp___3~0); 60529#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60528#L407-21 assume !(1 == ~t5_pc~0); 58757#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 60520#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60518#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 60516#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 60514#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 60511#L426-21 assume !(1 == ~t6_pc~0); 60506#L426-23 is_transmit6_triggered_~__retres1~6 := 0; 60503#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60501#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 60499#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 60497#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 60495#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60493#L740-3 assume !(1 == ~T2_E~0); 60491#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60489#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60487#L755-3 assume !(1 == ~T5_E~0); 60485#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60482#L765-3 assume !(1 == ~E_1~0); 60479#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60476#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60473#L780-3 assume !(1 == ~E_4~0); 60470#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60466#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60467#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60456#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60457#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60449#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 60450#L1035 assume !(0 == start_simulation_~tmp~3); 60445#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60418#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60415#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60413#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 60411#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 60409#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 60406#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 60405#L1048 assume !(0 != start_simulation_~tmp___0~1); 55845#L1016-1 [2021-10-13 01:19:46,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:46,754 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 1 times [2021-10-13 01:19:46,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:46,755 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662393487] [2021-10-13 01:19:46,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:46,755 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:46,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:46,766 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:46,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:46,819 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:46,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:46,820 INFO L82 PathProgramCache]: Analyzing trace with hash 1710614088, now seen corresponding path program 1 times [2021-10-13 01:19:46,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:46,820 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580662047] [2021-10-13 01:19:46,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:46,821 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:46,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:46,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:46,849 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:46,849 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580662047] [2021-10-13 01:19:46,850 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580662047] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:46,850 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:46,850 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:46,850 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93744327] [2021-10-13 01:19:46,850 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:46,851 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:46,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:46,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:46,852 INFO L87 Difference]: Start difference. First operand 6609 states and 9296 transitions. cyclomatic complexity: 2689 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:46,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:46,911 INFO L93 Difference]: Finished difference Result 7627 states and 10701 transitions. [2021-10-13 01:19:46,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:46,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7627 states and 10701 transitions. [2021-10-13 01:19:47,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7480 [2021-10-13 01:19:47,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7627 states to 7627 states and 10701 transitions. [2021-10-13 01:19:47,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7627 [2021-10-13 01:19:47,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7627 [2021-10-13 01:19:47,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7627 states and 10701 transitions. [2021-10-13 01:19:47,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:47,062 INFO L681 BuchiCegarLoop]: Abstraction has 7627 states and 10701 transitions. [2021-10-13 01:19:47,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7627 states and 10701 transitions. [2021-10-13 01:19:47,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7627 to 7627. [2021-10-13 01:19:47,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7627 states, 7627 states have (on average 1.403041825095057) internal successors, (10701), 7626 states have internal predecessors, (10701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:47,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7627 states to 7627 states and 10701 transitions. [2021-10-13 01:19:47,183 INFO L704 BuchiCegarLoop]: Abstraction has 7627 states and 10701 transitions. [2021-10-13 01:19:47,183 INFO L587 BuchiCegarLoop]: Abstraction has 7627 states and 10701 transitions. [2021-10-13 01:19:47,183 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-13 01:19:47,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7627 states and 10701 transitions. [2021-10-13 01:19:47,209 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7480 [2021-10-13 01:19:47,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:47,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:47,213 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:47,213 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:47,213 INFO L791 eck$LassoCheckResult]: Stem: 70190#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 70149#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 69739#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 69740#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 69844#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69776#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69777#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69978#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69983#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69741#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69742#L483-1 assume !(0 == ~M_E~0); 70073#L662-1 assume !(0 == ~T1_E~0); 69958#L667-1 assume !(0 == ~T2_E~0); 69959#L672-1 assume !(0 == ~T3_E~0); 69788#L677-1 assume !(0 == ~T4_E~0); 69789#L682-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70024#L687-1 assume !(0 == ~T6_E~0); 70226#L692-1 assume !(0 == ~E_1~0); 70010#L697-1 assume !(0 == ~E_2~0); 70011#L702-1 assume !(0 == ~E_3~0); 70225#L707-1 assume !(0 == ~E_4~0); 70224#L712-1 assume !(0 == ~E_5~0); 70223#L717-1 assume !(0 == ~E_6~0); 70222#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69779#L312 assume !(1 == ~m_pc~0); 69655#L312-2 is_master_triggered_~__retres1~0 := 0; 69656#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70008#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69607#L817 assume !(0 != activate_threads_~tmp~1); 69608#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69799#L331 assume !(1 == ~t1_pc~0); 69800#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 69558#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69559#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69760#L825 assume !(0 != activate_threads_~tmp___0~0); 69761#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69717#L350 assume !(1 == ~t2_pc~0); 69718#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 70214#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70213#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 70212#L833 assume !(0 != activate_threads_~tmp___1~0); 70157#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70147#L369 assume !(1 == ~t3_pc~0); 69651#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 69652#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69910#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70208#L841 assume !(0 != activate_threads_~tmp___2~0); 69755#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69756#L388 assume !(1 == ~t4_pc~0); 69810#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 69811#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70204#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 70203#L849 assume !(0 != activate_threads_~tmp___3~0); 70202#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70201#L407 assume !(1 == ~t5_pc~0); 70200#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 69522#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69489#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 69490#L857 assume !(0 != activate_threads_~tmp___4~0); 70198#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69968#L426 assume !(1 == ~t6_pc~0); 69969#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 70197#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70175#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 70095#L865 assume !(0 != activate_threads_~tmp___5~0); 69545#L865-2 assume !(1 == ~M_E~0); 69546#L735-1 assume !(1 == ~T1_E~0); 69738#L740-1 assume !(1 == ~T2_E~0); 69589#L745-1 assume !(1 == ~T3_E~0); 69590#L750-1 assume !(1 == ~T4_E~0); 70064#L755-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70043#L760-1 assume !(1 == ~T6_E~0); 70044#L765-1 assume !(1 == ~E_1~0); 70154#L770-1 assume !(1 == ~E_2~0); 69872#L775-1 assume !(1 == ~E_3~0); 69795#L780-1 assume !(1 == ~E_4~0); 69796#L785-1 assume !(1 == ~E_5~0); 70018#L790-1 assume !(1 == ~E_6~0); 70099#L1016-1 [2021-10-13 01:19:47,214 INFO L793 eck$LassoCheckResult]: Loop: 70099#L1016-1 assume !false; 70063#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 69930#L637 assume !false; 70097#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 69941#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 69550#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 69759#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 70074#L548 assume !(0 != eval_~tmp~0); 69981#L652 start_simulation_~kernel_st~0 := 2; 69982#L446-1 start_simulation_~kernel_st~0 := 3; 69881#L662-2 assume !(0 == ~M_E~0); 69882#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69862#L667-3 assume !(0 == ~T2_E~0); 69863#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69674#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69675#L682-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70086#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69715#L692-3 assume !(0 == ~E_1~0); 69716#L697-3 assume !(0 == ~E_2~0); 69818#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69819#L707-3 assume !(0 == ~E_4~0); 69974#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69614#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69615#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70002#L312-21 assume !(1 == ~m_pc~0); 70140#L312-23 is_master_triggered_~__retres1~0 := 0; 69890#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69495#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69496#L817-21 assume !(0 != activate_threads_~tmp~1); 69898#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69899#L331-21 assume !(1 == ~t1_pc~0); 69846#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 69711#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69535#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69536#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70114#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70049#L350-21 assume !(1 == ~t2_pc~0); 70050#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 77054#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77053#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 77052#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 77051#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69925#L369-21 assume !(1 == ~t3_pc~0); 69816#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 69497#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69498#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70070#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 69649#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69650#L388-21 assume !(1 == ~t4_pc~0); 69680#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 69499#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69500#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 69730#L849-21 assume !(0 != activate_threads_~tmp___3~0); 69820#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69821#L407-21 assume !(1 == ~t5_pc~0); 70090#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 69576#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69577#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 69514#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 69515#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69992#L426-21 assume !(1 == ~t6_pc~0); 69633#L426-23 is_transmit6_triggered_~__retres1~6 := 0; 69632#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 69733#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 69746#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 69867#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 69598#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69599#L740-3 assume !(1 == ~T2_E~0); 70081#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70082#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69612#L755-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69613#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69876#L765-3 assume !(1 == ~E_1~0); 69833#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69834#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69921#L780-3 assume !(1 == ~E_4~0); 69552#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69553#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70036#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 69879#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 69684#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 70118#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 70038#L1035 assume !(0 == start_simulation_~tmp~3); 70040#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 76539#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 76538#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 76537#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 76535#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 76505#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 76504#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 76503#L1048 assume !(0 != start_simulation_~tmp___0~1); 70099#L1016-1 [2021-10-13 01:19:47,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:47,214 INFO L82 PathProgramCache]: Analyzing trace with hash 793462387, now seen corresponding path program 1 times [2021-10-13 01:19:47,215 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:47,216 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961752992] [2021-10-13 01:19:47,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:47,216 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:47,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:47,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:47,250 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:47,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961752992] [2021-10-13 01:19:47,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961752992] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:47,251 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:47,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:19:47,251 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73900492] [2021-10-13 01:19:47,252 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:47,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:47,252 INFO L82 PathProgramCache]: Analyzing trace with hash 1287912262, now seen corresponding path program 1 times [2021-10-13 01:19:47,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:47,253 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713943661] [2021-10-13 01:19:47,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:47,253 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:47,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:47,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:47,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:47,287 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713943661] [2021-10-13 01:19:47,288 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713943661] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:47,288 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:47,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:19:47,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629022319] [2021-10-13 01:19:47,289 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:47,289 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:47,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:47,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:47,290 INFO L87 Difference]: Start difference. First operand 7627 states and 10701 transitions. cyclomatic complexity: 3076 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 2 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:47,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:47,404 INFO L93 Difference]: Finished difference Result 6609 states and 9246 transitions. [2021-10-13 01:19:47,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:47,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6609 states and 9246 transitions. [2021-10-13 01:19:47,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6520 [2021-10-13 01:19:47,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6609 states to 6609 states and 9246 transitions. [2021-10-13 01:19:47,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6609 [2021-10-13 01:19:47,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6609 [2021-10-13 01:19:47,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6609 states and 9246 transitions. [2021-10-13 01:19:47,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:47,475 INFO L681 BuchiCegarLoop]: Abstraction has 6609 states and 9246 transitions. [2021-10-13 01:19:47,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6609 states and 9246 transitions. [2021-10-13 01:19:47,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6609 to 6609. [2021-10-13 01:19:47,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6609 states, 6609 states have (on average 1.3990013617793917) internal successors, (9246), 6608 states have internal predecessors, (9246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:47,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6609 states to 6609 states and 9246 transitions. [2021-10-13 01:19:47,581 INFO L704 BuchiCegarLoop]: Abstraction has 6609 states and 9246 transitions. [2021-10-13 01:19:47,581 INFO L587 BuchiCegarLoop]: Abstraction has 6609 states and 9246 transitions. [2021-10-13 01:19:47,581 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-13 01:19:47,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6609 states and 9246 transitions. [2021-10-13 01:19:47,666 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6520 [2021-10-13 01:19:47,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:47,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:47,680 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:47,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:47,681 INFO L791 eck$LassoCheckResult]: Stem: 84438#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 84405#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 83988#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 83989#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 84092#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84024#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84025#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84222#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84227#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83990#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83991#L483-1 assume !(0 == ~M_E~0); 84329#L662-1 assume !(0 == ~T1_E~0); 84205#L667-1 assume !(0 == ~T2_E~0); 84206#L672-1 assume !(0 == ~T3_E~0); 84035#L677-1 assume !(0 == ~T4_E~0); 84036#L682-1 assume !(0 == ~T5_E~0); 84276#L687-1 assume !(0 == ~T6_E~0); 84358#L692-1 assume !(0 == ~E_1~0); 84260#L697-1 assume !(0 == ~E_2~0); 84261#L702-1 assume !(0 == ~E_3~0); 84322#L707-1 assume !(0 == ~E_4~0); 84161#L712-1 assume !(0 == ~E_5~0); 84162#L717-1 assume !(0 == ~E_6~0); 84291#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84026#L312 assume !(1 == ~m_pc~0); 83902#L312-2 is_master_triggered_~__retres1~0 := 0; 83732#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 83733#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 83850#L817 assume !(0 != activate_threads_~tmp~1); 83851#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84047#L331 assume !(1 == ~t1_pc~0); 83999#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 83804#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 83805#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 84008#L825 assume !(0 != activate_threads_~tmp___0~0); 84009#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83965#L350 assume !(1 == ~t2_pc~0); 83966#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 84169#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84170#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 83831#L833 assume !(0 != activate_threads_~tmp___1~0); 83832#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84403#L369 assume !(1 == ~t3_pc~0); 83898#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 83899#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83881#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 83882#L841 assume !(0 != activate_threads_~tmp___2~0); 84003#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84004#L388 assume !(1 == ~t4_pc~0); 84057#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 83883#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 83884#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 84020#L849 assume !(0 != activate_threads_~tmp___3~0); 84021#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 83755#L407 assume !(1 == ~t5_pc~0); 83756#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 83765#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83734#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 83735#L857 assume !(0 != activate_threads_~tmp___4~0); 83889#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83890#L426 assume !(1 == ~t6_pc~0); 84214#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 84285#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 84379#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 84349#L865 assume !(0 != activate_threads_~tmp___5~0); 83790#L865-2 assume !(1 == ~M_E~0); 83791#L735-1 assume !(1 == ~T1_E~0); 83870#L740-1 assume !(1 == ~T2_E~0); 83835#L745-1 assume !(1 == ~T3_E~0); 83836#L750-1 assume !(1 == ~T4_E~0); 84318#L755-1 assume !(1 == ~T5_E~0); 84294#L760-1 assume !(1 == ~T6_E~0); 84295#L765-1 assume !(1 == ~E_1~0); 84408#L770-1 assume !(1 == ~E_2~0); 84119#L775-1 assume !(1 == ~E_3~0); 84043#L780-1 assume !(1 == ~E_4~0); 84044#L785-1 assume !(1 == ~E_5~0); 84269#L790-1 assume !(1 == ~E_6~0); 84103#L1016-1 [2021-10-13 01:19:47,681 INFO L793 eck$LassoCheckResult]: Loop: 84103#L1016-1 assume !false; 84313#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 84180#L637 assume !false; 84352#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 84188#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 83795#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 84007#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 84330#L548 assume !(0 != eval_~tmp~0); 84415#L652 start_simulation_~kernel_st~0 := 2; 90238#L446-1 start_simulation_~kernel_st~0 := 3; 90237#L662-2 assume !(0 == ~M_E~0); 90236#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 90177#L667-3 assume !(0 == ~T2_E~0); 89930#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89929#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89928#L682-3 assume !(0 == ~T5_E~0); 89927#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 89926#L692-3 assume !(0 == ~E_1~0); 89925#L697-3 assume !(0 == ~E_2~0); 89924#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89922#L707-3 assume !(0 == ~E_4~0); 89919#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89917#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 89915#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89913#L312-21 assume !(1 == ~m_pc~0); 89910#L312-23 is_master_triggered_~__retres1~0 := 0; 89907#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 89905#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 89903#L817-21 assume !(0 != activate_threads_~tmp~1); 89901#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 89899#L331-21 assume !(1 == ~t1_pc~0); 89896#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 89894#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89893#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 89891#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 89889#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 89887#L350-21 assume !(1 == ~t2_pc~0); 87954#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 89884#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 89883#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 89881#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 89879#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 89877#L369-21 assume !(1 == ~t3_pc~0); 89081#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 90064#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90063#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 90062#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 90061#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 90060#L388-21 assume !(1 == ~t4_pc~0); 90058#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 90057#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90056#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 90055#L849-21 assume !(0 != activate_threads_~tmp___3~0); 90053#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90051#L407-21 assume !(1 == ~t5_pc~0); 87265#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 90046#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90043#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 90040#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 90036#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 90031#L426-21 assume 1 == ~t6_pc~0; 90033#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 90095#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 90094#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 90093#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 90092#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 90091#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90090#L740-3 assume !(1 == ~T2_E~0); 90089#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90088#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90087#L755-3 assume !(1 == ~T5_E~0); 90014#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90009#L765-3 assume !(1 == ~E_1~0); 90010#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84171#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84172#L780-3 assume !(1 == ~E_4~0); 83799#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83800#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 84348#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 84129#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 83933#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 84374#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 84289#L1035 assume !(0 == start_simulation_~tmp~3); 84177#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 84178#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 84088#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 84262#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 83949#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 83950#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 84153#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 84102#L1048 assume !(0 != start_simulation_~tmp___0~1); 84103#L1016-1 [2021-10-13 01:19:47,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:47,682 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 2 times [2021-10-13 01:19:47,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:47,683 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093988450] [2021-10-13 01:19:47,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:47,683 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:47,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:47,716 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:47,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:47,756 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:47,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:47,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1404748165, now seen corresponding path program 1 times [2021-10-13 01:19:47,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:47,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912054458] [2021-10-13 01:19:47,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:47,758 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:47,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:47,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:47,807 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:47,807 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912054458] [2021-10-13 01:19:47,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912054458] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:47,808 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:47,808 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:19:47,808 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419780389] [2021-10-13 01:19:47,808 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:47,809 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:47,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:19:47,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:19:47,810 INFO L87 Difference]: Start difference. First operand 6609 states and 9246 transitions. cyclomatic complexity: 2639 Second operand has 5 states, 5 states have (on average 18.2) internal successors, (91), 5 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:48,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:48,070 INFO L93 Difference]: Finished difference Result 11793 states and 16286 transitions. [2021-10-13 01:19:48,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-13 01:19:48,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11793 states and 16286 transitions. [2021-10-13 01:19:48,140 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11696 [2021-10-13 01:19:48,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11793 states to 11793 states and 16286 transitions. [2021-10-13 01:19:48,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11793 [2021-10-13 01:19:48,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11793 [2021-10-13 01:19:48,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11793 states and 16286 transitions. [2021-10-13 01:19:48,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:48,218 INFO L681 BuchiCegarLoop]: Abstraction has 11793 states and 16286 transitions. [2021-10-13 01:19:48,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11793 states and 16286 transitions. [2021-10-13 01:19:48,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11793 to 6657. [2021-10-13 01:19:48,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6657 states, 6657 states have (on average 1.3961243803515098) internal successors, (9294), 6656 states have internal predecessors, (9294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:48,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6657 states to 6657 states and 9294 transitions. [2021-10-13 01:19:48,383 INFO L704 BuchiCegarLoop]: Abstraction has 6657 states and 9294 transitions. [2021-10-13 01:19:48,383 INFO L587 BuchiCegarLoop]: Abstraction has 6657 states and 9294 transitions. [2021-10-13 01:19:48,383 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-13 01:19:48,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6657 states and 9294 transitions. [2021-10-13 01:19:48,411 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6568 [2021-10-13 01:19:48,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:48,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:48,415 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:48,415 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:48,415 INFO L791 eck$LassoCheckResult]: Stem: 102835#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 102803#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 102402#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 102403#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 102507#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102439#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102440#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102635#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102640#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102404#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 102405#L483-1 assume !(0 == ~M_E~0); 102729#L662-1 assume !(0 == ~T1_E~0); 102618#L667-1 assume !(0 == ~T2_E~0); 102619#L672-1 assume !(0 == ~T3_E~0); 102451#L677-1 assume !(0 == ~T4_E~0); 102452#L682-1 assume !(0 == ~T5_E~0); 102683#L687-1 assume !(0 == ~T6_E~0); 102762#L692-1 assume !(0 == ~E_1~0); 102668#L697-1 assume !(0 == ~E_2~0); 102669#L702-1 assume !(0 == ~E_3~0); 102722#L707-1 assume !(0 == ~E_4~0); 102572#L712-1 assume !(0 == ~E_5~0); 102573#L717-1 assume !(0 == ~E_6~0); 102697#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 102442#L312 assume !(1 == ~m_pc~0); 102318#L312-2 is_master_triggered_~__retres1~0 := 0; 102150#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 102151#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 102267#L817 assume !(0 != activate_threads_~tmp~1); 102268#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 102462#L331 assume !(1 == ~t1_pc~0); 102413#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 102221#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 102222#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 102423#L825 assume !(0 != activate_threads_~tmp___0~0); 102424#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 102379#L350 assume !(1 == ~t2_pc~0); 102380#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 102580#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 102581#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 102248#L833 assume !(0 != activate_threads_~tmp___1~0); 102249#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 102802#L369 assume !(1 == ~t3_pc~0); 102314#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 102315#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 102297#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 102298#L841 assume !(0 != activate_threads_~tmp___2~0); 102417#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 102418#L388 assume !(1 == ~t4_pc~0); 102472#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 102299#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 102300#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 102435#L849 assume !(0 != activate_threads_~tmp___3~0); 102436#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 102173#L407 assume !(1 == ~t5_pc~0); 102174#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 102183#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 102152#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 102153#L857 assume !(0 != activate_threads_~tmp___4~0); 102305#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 102306#L426 assume !(1 == ~t6_pc~0); 102626#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 102692#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 102781#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 102751#L865 assume !(0 != activate_threads_~tmp___5~0); 102208#L865-2 assume !(1 == ~M_E~0); 102209#L735-1 assume !(1 == ~T1_E~0); 102286#L740-1 assume !(1 == ~T2_E~0); 102252#L745-1 assume !(1 == ~T3_E~0); 102253#L750-1 assume !(1 == ~T4_E~0); 102719#L755-1 assume !(1 == ~T5_E~0); 102698#L760-1 assume !(1 == ~T6_E~0); 102699#L765-1 assume !(1 == ~E_1~0); 102805#L770-1 assume !(1 == ~E_2~0); 102533#L775-1 assume !(1 == ~E_3~0); 102458#L780-1 assume !(1 == ~E_4~0); 102459#L785-1 assume !(1 == ~E_5~0); 102677#L790-1 assume !(1 == ~E_6~0); 102518#L1016-1 [2021-10-13 01:19:48,416 INFO L793 eck$LassoCheckResult]: Loop: 102518#L1016-1 assume !false; 102714#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 102592#L637 assume !false; 102753#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 102603#L496 assume !(0 == ~m_st~0); 102604#L500 assume !(0 == ~t1_st~0); 102819#L504 assume !(0 == ~t2_st~0); 102212#L508 assume !(0 == ~t3_st~0); 102214#L512 assume !(0 == ~t4_st~0); 102471#L516 assume !(0 == ~t5_st~0); 102512#L520 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 102421#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 102422#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 102730#L548 assume !(0 != eval_~tmp~0); 102638#L652 start_simulation_~kernel_st~0 := 2; 102639#L446-1 start_simulation_~kernel_st~0 := 3; 102543#L662-2 assume !(0 == ~M_E~0); 102544#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102524#L667-3 assume !(0 == ~T2_E~0); 102525#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102338#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102339#L682-3 assume !(0 == ~T5_E~0); 102741#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102381#L692-3 assume !(0 == ~E_1~0); 102382#L697-3 assume !(0 == ~E_2~0); 102483#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102484#L707-3 assume !(0 == ~E_4~0); 102632#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102666#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 107368#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107321#L312-21 assume !(1 == ~m_pc~0); 107322#L312-23 is_master_triggered_~__retres1~0 := 0; 107313#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107314#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 107307#L817-21 assume !(0 != activate_threads_~tmp~1); 107308#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107302#L331-21 assume !(1 == ~t1_pc~0); 107301#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 107293#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107294#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 106976#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 106977#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 106463#L350-21 assume !(1 == ~t2_pc~0); 102875#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 102807#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 102808#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 108195#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 102284#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 102285#L369-21 assume !(1 == ~t3_pc~0); 102477#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 102158#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 102159#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 102725#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 102726#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 102817#L388-21 assume !(1 == ~t4_pc~0); 102344#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 102162#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 102163#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 102394#L849-21 assume !(0 != activate_threads_~tmp___3~0); 102479#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 102480#L407-21 assume !(1 == ~t5_pc~0); 102745#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 102240#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 102241#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 102179#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 102180#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 102650#L426-21 assume 1 == ~t6_pc~0; 102294#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 102295#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 102397#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 102409#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 102529#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 102261#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102262#L740-3 assume !(1 == ~T2_E~0); 102737#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102738#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102756#L755-3 assume !(1 == ~T5_E~0); 108719#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108319#L765-3 assume !(1 == ~E_1~0); 108318#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102582#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102583#L780-3 assume !(1 == ~E_4~0); 102217#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102218#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102693#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 102750#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 108307#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 108306#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 108305#L1035 assume !(0 == start_simulation_~tmp~3); 108302#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 102735#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 102502#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 102670#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 102364#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 102365#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 102564#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 102517#L1048 assume !(0 != start_simulation_~tmp___0~1); 102518#L1016-1 [2021-10-13 01:19:48,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:48,417 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 3 times [2021-10-13 01:19:48,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:48,421 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319855654] [2021-10-13 01:19:48,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:48,421 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:48,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:48,433 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:48,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:48,474 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:48,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:48,475 INFO L82 PathProgramCache]: Analyzing trace with hash -1277961130, now seen corresponding path program 1 times [2021-10-13 01:19:48,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:48,476 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066295115] [2021-10-13 01:19:48,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:48,476 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:48,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:48,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:48,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:48,611 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066295115] [2021-10-13 01:19:48,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066295115] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:48,611 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:48,612 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:48,612 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060221427] [2021-10-13 01:19:48,613 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:48,613 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:48,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:48,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:48,614 INFO L87 Difference]: Start difference. First operand 6657 states and 9294 transitions. cyclomatic complexity: 2639 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:48,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:48,734 INFO L93 Difference]: Finished difference Result 12425 states and 17070 transitions. [2021-10-13 01:19:48,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:48,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12425 states and 17070 transitions. [2021-10-13 01:19:48,794 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12336 [2021-10-13 01:19:48,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12425 states to 12425 states and 17070 transitions. [2021-10-13 01:19:48,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12425 [2021-10-13 01:19:48,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12425 [2021-10-13 01:19:48,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12425 states and 17070 transitions. [2021-10-13 01:19:48,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:48,864 INFO L681 BuchiCegarLoop]: Abstraction has 12425 states and 17070 transitions. [2021-10-13 01:19:48,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12425 states and 17070 transitions. [2021-10-13 01:19:49,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12425 to 12077. [2021-10-13 01:19:49,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12077 states, 12077 states have (on average 1.3760039744969776) internal successors, (16618), 12076 states have internal predecessors, (16618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:49,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12077 states to 12077 states and 16618 transitions. [2021-10-13 01:19:49,045 INFO L704 BuchiCegarLoop]: Abstraction has 12077 states and 16618 transitions. [2021-10-13 01:19:49,045 INFO L587 BuchiCegarLoop]: Abstraction has 12077 states and 16618 transitions. [2021-10-13 01:19:49,045 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-13 01:19:49,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12077 states and 16618 transitions. [2021-10-13 01:19:49,084 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11988 [2021-10-13 01:19:49,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:49,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:49,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:49,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:49,088 INFO L791 eck$LassoCheckResult]: Stem: 121971#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 121934#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 121492#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 121493#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 121600#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121529#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121530#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121738#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121743#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121494#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121495#L483-1 assume !(0 == ~M_E~0); 121840#L662-1 assume !(0 == ~T1_E~0); 121712#L667-1 assume !(0 == ~T2_E~0); 121713#L672-1 assume !(0 == ~T3_E~0); 121541#L677-1 assume !(0 == ~T4_E~0); 121542#L682-1 assume !(0 == ~T5_E~0); 121790#L687-1 assume !(0 == ~T6_E~0); 121878#L692-1 assume !(0 == ~E_1~0); 121775#L697-1 assume !(0 == ~E_2~0); 121776#L702-1 assume !(0 == ~E_3~0); 121833#L707-1 assume !(0 == ~E_4~0); 121670#L712-1 assume !(0 == ~E_5~0); 121671#L717-1 assume !(0 == ~E_6~0); 121803#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121532#L312 assume !(1 == ~m_pc~0); 121406#L312-2 is_master_triggered_~__retres1~0 := 0; 121238#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121239#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121356#L817 assume !(0 != activate_threads_~tmp~1); 121357#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121553#L331 assume !(1 == ~t1_pc~0); 121503#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 121309#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121310#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 121513#L825 assume !(0 != activate_threads_~tmp___0~0); 121514#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121468#L350 assume !(1 == ~t2_pc~0); 121469#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 121676#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121677#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 121337#L833 assume !(0 != activate_threads_~tmp___1~0); 121338#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121932#L369 assume !(1 == ~t3_pc~0); 121402#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 121403#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121382#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 121383#L841 assume !(0 != activate_threads_~tmp___2~0); 121504#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121505#L388 assume !(1 == ~t4_pc~0); 121565#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 121384#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121385#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 121525#L849 assume !(0 != activate_threads_~tmp___3~0); 121526#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121259#L407 assume !(1 == ~t5_pc~0); 121260#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 121271#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121240#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 121241#L857 assume !(0 != activate_threads_~tmp___4~0); 121393#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 121394#L426 assume !(1 == ~t6_pc~0); 121727#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 121800#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 121901#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 121868#L865 assume !(0 != activate_threads_~tmp___5~0); 121296#L865-2 assume !(1 == ~M_E~0); 121297#L735-1 assume !(1 == ~T1_E~0); 121373#L740-1 assume !(1 == ~T2_E~0); 121341#L745-1 assume !(1 == ~T3_E~0); 121342#L750-1 assume !(1 == ~T4_E~0); 121832#L755-1 assume !(1 == ~T5_E~0); 121808#L760-1 assume !(1 == ~T6_E~0); 121809#L765-1 assume !(1 == ~E_1~0); 121938#L770-1 assume !(1 == ~E_2~0); 121627#L775-1 assume !(1 == ~E_3~0); 121548#L780-1 assume !(1 == ~E_4~0); 121549#L785-1 assume !(1 == ~E_5~0); 121785#L790-1 assume !(1 == ~E_6~0); 121873#L1016-1 [2021-10-13 01:19:49,088 INFO L793 eck$LassoCheckResult]: Loop: 121873#L1016-1 assume !false; 132697#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 132692#L637 assume !false; 132690#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 132687#L496 assume !(0 == ~m_st~0); 130192#L500 assume !(0 == ~t1_st~0); 130188#L504 assume !(0 == ~t2_st~0); 130189#L508 assume !(0 == ~t3_st~0); 130191#L512 assume !(0 == ~t4_st~0); 130186#L516 assume !(0 == ~t5_st~0); 130187#L520 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 130190#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 130180#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 130181#L548 assume !(0 != eval_~tmp~0); 132154#L652 start_simulation_~kernel_st~0 := 2; 132153#L446-1 start_simulation_~kernel_st~0 := 3; 132152#L662-2 assume !(0 == ~M_E~0); 121954#L662-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 121617#L667-3 assume !(0 == ~T2_E~0); 121618#L672-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121426#L677-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121427#L682-3 assume !(0 == ~T5_E~0); 121857#L687-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121470#L692-3 assume !(0 == ~E_1~0); 121471#L697-3 assume !(0 == ~E_2~0); 121573#L702-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121574#L707-3 assume !(0 == ~E_4~0); 131743#L712-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121368#L717-3 assume 0 == ~E_6~0;~E_6~0 := 1; 121369#L722-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121766#L312-21 assume !(1 == ~m_pc~0); 121926#L312-23 is_master_triggered_~__retres1~0 := 0; 121649#L323-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121246#L324-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121247#L817-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 121658#L817-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132905#L331-21 assume !(1 == ~t1_pc~0); 132901#L331-23 is_transmit1_triggered_~__retres1~1 := 0; 132899#L342-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132897#L343-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132896#L825-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 132895#L825-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132418#L350-21 assume !(1 == ~t2_pc~0); 132414#L350-23 is_transmit2_triggered_~__retres1~2 := 0; 132412#L361-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132409#L362-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 132406#L833-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 132405#L833-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 131322#L369-21 assume !(1 == ~t3_pc~0); 131315#L369-23 is_transmit3_triggered_~__retres1~3 := 0; 131309#L380-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 130422#L381-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 130421#L841-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 130419#L841-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130416#L388-21 assume !(1 == ~t4_pc~0); 130413#L388-23 is_transmit4_triggered_~__retres1~4 := 0; 130410#L399-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 130408#L400-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 130406#L849-21 assume !(0 != activate_threads_~tmp___3~0); 130404#L849-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 130402#L407-21 assume !(1 == ~t5_pc~0); 130400#L407-23 is_transmit5_triggered_~__retres1~5 := 0; 130397#L418-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 130396#L419-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 130393#L857-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 130391#L857-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 130389#L426-21 assume 1 == ~t6_pc~0; 130387#L427-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 130384#L437-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 130380#L438-7 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 130379#L865-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 130375#L865-23 assume 1 == ~M_E~0;~M_E~0 := 2; 130372#L735-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130369#L740-3 assume !(1 == ~T2_E~0); 130366#L745-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 130363#L750-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130359#L755-3 assume !(1 == ~T5_E~0); 130356#L760-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 130353#L765-3 assume !(1 == ~E_1~0); 130350#L770-3 assume 1 == ~E_2~0;~E_2~0 := 2; 130347#L775-3 assume 1 == ~E_3~0;~E_3~0 := 2; 130344#L780-3 assume !(1 == ~E_4~0); 130342#L785-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130340#L790-3 assume 1 == ~E_6~0;~E_6~0 := 2; 130337#L795-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 130334#L496-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 130331#L533-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 130328#L534-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 130324#L1035 assume !(0 == start_simulation_~tmp~3); 130319#L1035-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 130220#L496-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 130221#L533-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 132707#L534-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 132705#L990 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 132703#L997 stop_simulation_#res := stop_simulation_~__retres2~0; 132702#L998 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 132700#L1048 assume !(0 != start_simulation_~tmp___0~1); 121873#L1016-1 [2021-10-13 01:19:49,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:49,089 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 4 times [2021-10-13 01:19:49,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:49,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739270192] [2021-10-13 01:19:49,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:49,090 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:49,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:49,103 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:49,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:49,150 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:49,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:49,151 INFO L82 PathProgramCache]: Analyzing trace with hash -860564524, now seen corresponding path program 1 times [2021-10-13 01:19:49,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:49,151 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960604813] [2021-10-13 01:19:49,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:49,152 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:49,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:49,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:49,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:49,226 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960604813] [2021-10-13 01:19:49,226 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960604813] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:49,226 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:49,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:19:49,227 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527575027] [2021-10-13 01:19:49,228 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:19:49,228 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:49,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:19:49,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:19:49,229 INFO L87 Difference]: Start difference. First operand 12077 states and 16618 transitions. cyclomatic complexity: 4543 Second operand has 5 states, 5 states have (on average 19.4) internal successors, (97), 5 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:49,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:49,596 INFO L93 Difference]: Finished difference Result 19763 states and 27083 transitions. [2021-10-13 01:19:49,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:19:49,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19763 states and 27083 transitions. [2021-10-13 01:19:49,689 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19672 [2021-10-13 01:19:49,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19763 states to 19763 states and 27083 transitions. [2021-10-13 01:19:49,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19763 [2021-10-13 01:19:49,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19763 [2021-10-13 01:19:49,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19763 states and 27083 transitions. [2021-10-13 01:19:49,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:49,792 INFO L681 BuchiCegarLoop]: Abstraction has 19763 states and 27083 transitions. [2021-10-13 01:19:49,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19763 states and 27083 transitions. [2021-10-13 01:19:49,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19763 to 11319. [2021-10-13 01:19:49,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11319 states, 11319 states have (on average 1.3615160349854227) internal successors, (15411), 11318 states have internal predecessors, (15411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:49,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11319 states to 11319 states and 15411 transitions. [2021-10-13 01:19:49,992 INFO L704 BuchiCegarLoop]: Abstraction has 11319 states and 15411 transitions. [2021-10-13 01:19:49,992 INFO L587 BuchiCegarLoop]: Abstraction has 11319 states and 15411 transitions. [2021-10-13 01:19:49,992 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-13 01:19:49,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11319 states and 15411 transitions. [2021-10-13 01:19:50,027 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11228 [2021-10-13 01:19:50,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:50,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:50,029 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:50,029 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:50,029 INFO L791 eck$LassoCheckResult]: Stem: 153786#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 153760#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153344#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 153345#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 153441#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 153380#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153381#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153579#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153584#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153346#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 153347#L483-1 assume !(0 == ~M_E~0); 153678#L662-1 assume !(0 == ~T1_E~0); 153557#L667-1 assume !(0 == ~T2_E~0); 153558#L672-1 assume !(0 == ~T3_E~0); 153391#L677-1 assume !(0 == ~T4_E~0); 153392#L682-1 assume !(0 == ~T5_E~0); 153630#L687-1 assume !(0 == ~T6_E~0); 153710#L692-1 assume !(0 == ~E_1~0); 153616#L697-1 assume !(0 == ~E_2~0); 153617#L702-1 assume !(0 == ~E_3~0); 153671#L707-1 assume !(0 == ~E_4~0); 153514#L712-1 assume !(0 == ~E_5~0); 153515#L717-1 assume !(0 == ~E_6~0); 153644#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 153382#L312 assume !(1 == ~m_pc~0); 153261#L312-2 is_master_triggered_~__retres1~0 := 0; 153091#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 153092#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 153209#L817 assume !(0 != activate_threads_~tmp~1); 153210#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 153402#L331 assume !(1 == ~t1_pc~0); 153355#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 153162#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 153163#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 153364#L825 assume !(0 != activate_threads_~tmp___0~0); 153365#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 153321#L350 assume !(1 == ~t2_pc~0); 153322#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 153522#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 153523#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 153190#L833 assume !(0 != activate_threads_~tmp___1~0); 153191#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 153759#L369 assume !(1 == ~t3_pc~0); 153257#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 153258#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 153237#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 153238#L841 assume !(0 != activate_threads_~tmp___2~0); 153356#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 153357#L388 assume !(1 == ~t4_pc~0); 153412#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 153239#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 153240#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 153376#L849 assume !(0 != activate_threads_~tmp___3~0); 153377#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 153112#L407 assume !(1 == ~t5_pc~0); 153113#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 153124#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 153093#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 153094#L857 assume !(0 != activate_threads_~tmp___4~0); 153248#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 153249#L426 assume !(1 == ~t6_pc~0); 153569#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 153641#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 153736#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 153697#L865 assume !(0 != activate_threads_~tmp___5~0); 153149#L865-2 assume !(1 == ~M_E~0); 153150#L735-1 assume !(1 == ~T1_E~0); 153228#L740-1 assume !(1 == ~T2_E~0); 153194#L745-1 assume !(1 == ~T3_E~0); 153195#L750-1 assume !(1 == ~T4_E~0); 153670#L755-1 assume !(1 == ~T5_E~0); 153648#L760-1 assume !(1 == ~T6_E~0); 153649#L765-1 assume !(1 == ~E_1~0); 153762#L770-1 assume !(1 == ~E_2~0); 153468#L775-1 assume !(1 == ~E_3~0); 153398#L780-1 assume !(1 == ~E_4~0); 153399#L785-1 assume !(1 == ~E_5~0); 153624#L790-1 assume !(1 == ~E_6~0); 153704#L1016-1 assume !false; 155054#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 155048#L637 [2021-10-13 01:19:50,030 INFO L793 eck$LassoCheckResult]: Loop: 155048#L637 assume !false; 155046#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 155043#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 155041#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 155038#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 155036#L548 assume 0 != eval_~tmp~0; 155033#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 155031#L556 assume !(0 != eval_~tmp_ndt_1~0); 155025#L553 assume !(0 == ~t1_st~0); 155020#L567 assume !(0 == ~t2_st~0); 155017#L581 assume !(0 == ~t3_st~0); 155015#L595 assume !(0 == ~t4_st~0); 155072#L609 assume !(0 == ~t5_st~0); 155052#L623 assume !(0 == ~t6_st~0); 155048#L637 [2021-10-13 01:19:50,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:50,030 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 1 times [2021-10-13 01:19:50,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:50,031 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949085985] [2021-10-13 01:19:50,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:50,031 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:50,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:50,043 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:50,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:50,081 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:50,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:50,082 INFO L82 PathProgramCache]: Analyzing trace with hash -435712619, now seen corresponding path program 1 times [2021-10-13 01:19:50,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:50,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665246536] [2021-10-13 01:19:50,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:50,082 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:50,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:50,086 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:50,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:50,091 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:50,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:50,092 INFO L82 PathProgramCache]: Analyzing trace with hash -1300950615, now seen corresponding path program 1 times [2021-10-13 01:19:50,092 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:50,092 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865126615] [2021-10-13 01:19:50,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:50,092 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:50,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:50,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:50,130 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:50,130 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865126615] [2021-10-13 01:19:50,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865126615] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:50,130 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:50,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:50,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255567470] [2021-10-13 01:19:50,267 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:50,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:50,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:50,268 INFO L87 Difference]: Start difference. First operand 11319 states and 15411 transitions. cyclomatic complexity: 4095 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:50,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:50,418 INFO L93 Difference]: Finished difference Result 21233 states and 28656 transitions. [2021-10-13 01:19:50,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:50,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21233 states and 28656 transitions. [2021-10-13 01:19:50,540 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21056 [2021-10-13 01:19:50,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21233 states to 21233 states and 28656 transitions. [2021-10-13 01:19:50,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21233 [2021-10-13 01:19:50,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21233 [2021-10-13 01:19:50,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21233 states and 28656 transitions. [2021-10-13 01:19:50,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:50,667 INFO L681 BuchiCegarLoop]: Abstraction has 21233 states and 28656 transitions. [2021-10-13 01:19:50,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21233 states and 28656 transitions. [2021-10-13 01:19:51,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21233 to 20065. [2021-10-13 01:19:51,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20065 states, 20065 states have (on average 1.353999501619736) internal successors, (27168), 20064 states have internal predecessors, (27168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:51,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20065 states to 20065 states and 27168 transitions. [2021-10-13 01:19:51,114 INFO L704 BuchiCegarLoop]: Abstraction has 20065 states and 27168 transitions. [2021-10-13 01:19:51,114 INFO L587 BuchiCegarLoop]: Abstraction has 20065 states and 27168 transitions. [2021-10-13 01:19:51,114 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-13 01:19:51,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20065 states and 27168 transitions. [2021-10-13 01:19:51,202 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19888 [2021-10-13 01:19:51,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:51,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:51,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:51,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:51,205 INFO L791 eck$LassoCheckResult]: Stem: 186394#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 186353#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 185903#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 185904#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 186005#L453-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 186006#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 187427#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 187426#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 187425#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 187424#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 187423#L483-1 assume !(0 == ~M_E~0); 187422#L662-1 assume !(0 == ~T1_E~0); 187421#L667-1 assume !(0 == ~T2_E~0); 187420#L672-1 assume !(0 == ~T3_E~0); 187419#L677-1 assume !(0 == ~T4_E~0); 187418#L682-1 assume !(0 == ~T5_E~0); 187417#L687-1 assume !(0 == ~T6_E~0); 187416#L692-1 assume !(0 == ~E_1~0); 187415#L697-1 assume !(0 == ~E_2~0); 187414#L702-1 assume !(0 == ~E_3~0); 187413#L707-1 assume !(0 == ~E_4~0); 187412#L712-1 assume !(0 == ~E_5~0); 187411#L717-1 assume !(0 == ~E_6~0); 187410#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 187409#L312 assume !(1 == ~m_pc~0); 187408#L312-2 is_master_triggered_~__retres1~0 := 0; 187407#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 187406#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 187405#L817 assume !(0 != activate_threads_~tmp~1); 187404#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 187402#L331 assume !(1 == ~t1_pc~0); 187401#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 187400#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 187399#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 187398#L825 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 185925#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 185881#L350 assume !(1 == ~t2_pc~0); 185882#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 186090#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 186091#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 185749#L833 assume !(0 != activate_threads_~tmp___1~0); 185750#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 186352#L369 assume !(1 == ~t3_pc~0); 185815#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 185816#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 185795#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 185796#L841 assume !(0 != activate_threads_~tmp___2~0); 185915#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 185916#L388 assume !(1 == ~t4_pc~0); 185973#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 185797#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 185798#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 185936#L849 assume !(0 != activate_threads_~tmp___3~0); 185937#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 185672#L407 assume !(1 == ~t5_pc~0); 185673#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 185684#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 185653#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 185654#L857 assume !(0 != activate_threads_~tmp___4~0); 185806#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 185807#L426 assume !(1 == ~t6_pc~0); 186139#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 186215#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 186323#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 186285#L865 assume !(0 != activate_threads_~tmp___5~0); 185709#L865-2 assume !(1 == ~M_E~0); 185710#L735-1 assume !(1 == ~T1_E~0); 185786#L740-1 assume !(1 == ~T2_E~0); 185753#L745-1 assume !(1 == ~T3_E~0); 185754#L750-1 assume !(1 == ~T4_E~0); 186249#L755-1 assume !(1 == ~T5_E~0); 186220#L760-1 assume !(1 == ~T6_E~0); 186221#L765-1 assume !(1 == ~E_1~0); 187354#L770-1 assume !(1 == ~E_2~0); 187352#L775-1 assume !(1 == ~E_3~0); 187351#L780-1 assume !(1 == ~E_4~0); 187350#L785-1 assume !(1 == ~E_5~0); 187349#L790-1 assume !(1 == ~E_6~0); 187315#L1016-1 assume !false; 187316#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 187297#L637 [2021-10-13 01:19:51,205 INFO L793 eck$LassoCheckResult]: Loop: 187297#L637 assume !false; 187298#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 187290#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 187291#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 187282#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 187283#L548 assume 0 != eval_~tmp~0; 187276#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 187277#L556 assume !(0 != eval_~tmp_ndt_1~0); 187269#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 187267#L570 assume !(0 != eval_~tmp_ndt_2~0); 187266#L567 assume !(0 == ~t2_st~0); 187263#L581 assume !(0 == ~t3_st~0); 187262#L595 assume !(0 == ~t4_st~0); 187324#L609 assume !(0 == ~t5_st~0); 187323#L623 assume !(0 == ~t6_st~0); 187297#L637 [2021-10-13 01:19:51,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:51,206 INFO L82 PathProgramCache]: Analyzing trace with hash 518305429, now seen corresponding path program 1 times [2021-10-13 01:19:51,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:51,206 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553567893] [2021-10-13 01:19:51,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:51,206 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:51,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:51,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:51,233 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:51,233 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553567893] [2021-10-13 01:19:51,233 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553567893] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:51,233 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:51,234 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:51,234 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8520351] [2021-10-13 01:19:51,234 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:19:51,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:51,235 INFO L82 PathProgramCache]: Analyzing trace with hash -2021030379, now seen corresponding path program 1 times [2021-10-13 01:19:51,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:51,235 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378326264] [2021-10-13 01:19:51,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:51,236 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:51,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:51,243 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:51,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:51,248 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:51,410 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:51,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:51,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:51,411 INFO L87 Difference]: Start difference. First operand 20065 states and 27168 transitions. cyclomatic complexity: 7106 Second operand has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:51,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:51,647 INFO L93 Difference]: Finished difference Result 19987 states and 27062 transitions. [2021-10-13 01:19:51,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:51,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19987 states and 27062 transitions. [2021-10-13 01:19:51,734 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19888 [2021-10-13 01:19:51,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19987 states to 19987 states and 27062 transitions. [2021-10-13 01:19:51,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19987 [2021-10-13 01:19:51,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19987 [2021-10-13 01:19:51,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19987 states and 27062 transitions. [2021-10-13 01:19:51,836 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:51,836 INFO L681 BuchiCegarLoop]: Abstraction has 19987 states and 27062 transitions. [2021-10-13 01:19:51,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19987 states and 27062 transitions. [2021-10-13 01:19:52,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19987 to 19987. [2021-10-13 01:19:52,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19987 states, 19987 states have (on average 1.3539800870565868) internal successors, (27062), 19986 states have internal predecessors, (27062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:52,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19987 states to 19987 states and 27062 transitions. [2021-10-13 01:19:52,133 INFO L704 BuchiCegarLoop]: Abstraction has 19987 states and 27062 transitions. [2021-10-13 01:19:52,133 INFO L587 BuchiCegarLoop]: Abstraction has 19987 states and 27062 transitions. [2021-10-13 01:19:52,133 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-13 01:19:52,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19987 states and 27062 transitions. [2021-10-13 01:19:52,343 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19888 [2021-10-13 01:19:52,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:52,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:52,344 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:52,345 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:52,345 INFO L791 eck$LassoCheckResult]: Stem: 226417#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 226381#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 225962#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 225963#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 226066#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 225998#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 225999#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226196#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226201#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 225964#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 225965#L483-1 assume !(0 == ~M_E~0); 226292#L662-1 assume !(0 == ~T1_E~0); 226177#L667-1 assume !(0 == ~T2_E~0); 226178#L672-1 assume !(0 == ~T3_E~0); 226010#L677-1 assume !(0 == ~T4_E~0); 226011#L682-1 assume !(0 == ~T5_E~0); 226241#L687-1 assume !(0 == ~T6_E~0); 226327#L692-1 assume !(0 == ~E_1~0); 226228#L697-1 assume !(0 == ~E_2~0); 226229#L702-1 assume !(0 == ~E_3~0); 226285#L707-1 assume !(0 == ~E_4~0); 226134#L712-1 assume !(0 == ~E_5~0); 226135#L717-1 assume !(0 == ~E_6~0); 226255#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 226001#L312 assume !(1 == ~m_pc~0); 225879#L312-2 is_master_triggered_~__retres1~0 := 0; 225709#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 225710#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 225827#L817 assume !(0 != activate_threads_~tmp~1); 225828#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 226022#L331 assume !(1 == ~t1_pc~0); 225973#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 225780#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 225781#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 225983#L825 assume !(0 != activate_threads_~tmp___0~0); 225984#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 225938#L350 assume !(1 == ~t2_pc~0); 225939#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 226142#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 226143#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 225808#L833 assume !(0 != activate_threads_~tmp___1~0); 225809#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226379#L369 assume !(1 == ~t3_pc~0); 225875#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 225876#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 225855#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 225856#L841 assume !(0 != activate_threads_~tmp___2~0); 225974#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 225975#L388 assume !(1 == ~t4_pc~0); 226033#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 225857#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 225858#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 225994#L849 assume !(0 != activate_threads_~tmp___3~0); 225995#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 225730#L407 assume !(1 == ~t5_pc~0); 225731#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 225742#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 225711#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 225712#L857 assume !(0 != activate_threads_~tmp___4~0); 225866#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 225867#L426 assume !(1 == ~t6_pc~0); 226186#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 226251#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 226350#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 226312#L865 assume !(0 != activate_threads_~tmp___5~0); 225767#L865-2 assume !(1 == ~M_E~0); 225768#L735-1 assume !(1 == ~T1_E~0); 225845#L740-1 assume !(1 == ~T2_E~0); 225812#L745-1 assume !(1 == ~T3_E~0); 225813#L750-1 assume !(1 == ~T4_E~0); 226284#L755-1 assume !(1 == ~T5_E~0); 226258#L760-1 assume !(1 == ~T6_E~0); 226259#L765-1 assume !(1 == ~E_1~0); 226383#L770-1 assume !(1 == ~E_2~0); 226095#L775-1 assume !(1 == ~E_3~0); 226017#L780-1 assume !(1 == ~E_4~0); 226018#L785-1 assume !(1 == ~E_5~0); 226236#L790-1 assume !(1 == ~E_6~0); 226320#L1016-1 assume !false; 228539#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 228529#L637 [2021-10-13 01:19:52,345 INFO L793 eck$LassoCheckResult]: Loop: 228529#L637 assume !false; 228526#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 228518#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 228510#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 228501#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 228495#L548 assume 0 != eval_~tmp~0; 228487#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 228478#L556 assume !(0 != eval_~tmp_ndt_1~0); 228471#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 228438#L570 assume !(0 != eval_~tmp_ndt_2~0); 228464#L567 assume !(0 == ~t2_st~0); 228406#L581 assume !(0 == ~t3_st~0); 228405#L595 assume !(0 == ~t4_st~0); 228544#L609 assume !(0 == ~t5_st~0); 228537#L623 assume !(0 == ~t6_st~0); 228529#L637 [2021-10-13 01:19:52,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:52,346 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 2 times [2021-10-13 01:19:52,346 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:52,346 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730127173] [2021-10-13 01:19:52,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:52,347 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:52,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:52,357 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:52,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:52,385 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:52,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:52,387 INFO L82 PathProgramCache]: Analyzing trace with hash -2021030379, now seen corresponding path program 2 times [2021-10-13 01:19:52,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:52,387 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856249943] [2021-10-13 01:19:52,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:52,388 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:52,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:52,392 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:52,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:52,398 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:52,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:52,399 INFO L82 PathProgramCache]: Analyzing trace with hash 1221362817, now seen corresponding path program 1 times [2021-10-13 01:19:52,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:52,399 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934793182] [2021-10-13 01:19:52,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:52,399 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:52,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:52,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:52,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:52,434 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934793182] [2021-10-13 01:19:52,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934793182] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:52,435 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:52,435 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:52,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119447680] [2021-10-13 01:19:52,563 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:52,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:52,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:52,564 INFO L87 Difference]: Start difference. First operand 19987 states and 27062 transitions. cyclomatic complexity: 7078 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:52,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:52,728 INFO L93 Difference]: Finished difference Result 37907 states and 51030 transitions. [2021-10-13 01:19:52,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:52,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37907 states and 51030 transitions. [2021-10-13 01:19:52,861 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 37792 [2021-10-13 01:19:52,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37907 states to 37907 states and 51030 transitions. [2021-10-13 01:19:52,974 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37907 [2021-10-13 01:19:52,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37907 [2021-10-13 01:19:52,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37907 states and 51030 transitions. [2021-10-13 01:19:53,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:53,252 INFO L681 BuchiCegarLoop]: Abstraction has 37907 states and 51030 transitions. [2021-10-13 01:19:53,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37907 states and 51030 transitions. [2021-10-13 01:19:53,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37907 to 36947. [2021-10-13 01:19:53,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36947 states, 36947 states have (on average 1.3482556093864184) internal successors, (49814), 36946 states have internal predecessors, (49814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:53,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36947 states to 36947 states and 49814 transitions. [2021-10-13 01:19:53,868 INFO L704 BuchiCegarLoop]: Abstraction has 36947 states and 49814 transitions. [2021-10-13 01:19:53,868 INFO L587 BuchiCegarLoop]: Abstraction has 36947 states and 49814 transitions. [2021-10-13 01:19:53,868 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-13 01:19:53,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36947 states and 49814 transitions. [2021-10-13 01:19:54,002 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 36832 [2021-10-13 01:19:54,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:54,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:54,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:54,003 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:54,004 INFO L791 eck$LassoCheckResult]: Stem: 284357#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 284312#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 283867#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 283868#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 283973#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 283904#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 283905#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 284114#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 284119#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 283869#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 283870#L483-1 assume !(0 == ~M_E~0); 284222#L662-1 assume !(0 == ~T1_E~0); 284090#L667-1 assume !(0 == ~T2_E~0); 284091#L672-1 assume !(0 == ~T3_E~0); 283916#L677-1 assume !(0 == ~T4_E~0); 283917#L682-1 assume !(0 == ~T5_E~0); 284169#L687-1 assume !(0 == ~T6_E~0); 284265#L692-1 assume !(0 == ~E_1~0); 284153#L697-1 assume !(0 == ~E_2~0); 284154#L702-1 assume !(0 == ~E_3~0); 284214#L707-1 assume !(0 == ~E_4~0); 284045#L712-1 assume !(0 == ~E_5~0); 284046#L717-1 assume !(0 == ~E_6~0); 284184#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 283907#L312 assume !(1 == ~m_pc~0); 283781#L312-2 is_master_triggered_~__retres1~0 := 0; 283611#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 283612#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 283732#L817 assume !(0 != activate_threads_~tmp~1); 283733#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 283929#L331 assume !(1 == ~t1_pc~0); 283878#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 283684#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 283685#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 283888#L825 assume !(0 != activate_threads_~tmp___0~0); 283889#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 283846#L350 assume !(1 == ~t2_pc~0); 283847#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 284052#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 284053#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 283710#L833 assume !(0 != activate_threads_~tmp___1~0); 283711#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 284310#L369 assume !(1 == ~t3_pc~0); 283777#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 283778#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 283760#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 283761#L841 assume !(0 != activate_threads_~tmp___2~0); 283882#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 283883#L388 assume !(1 == ~t4_pc~0); 283939#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 283762#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 283763#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 283900#L849 assume !(0 != activate_threads_~tmp___3~0); 283901#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 283634#L407 assume !(1 == ~t5_pc~0); 283635#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 283646#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 283613#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 283614#L857 assume !(0 != activate_threads_~tmp___4~0); 283768#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 283769#L426 assume !(1 == ~t6_pc~0); 284103#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 284179#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 284286#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 284251#L865 assume !(0 != activate_threads_~tmp___5~0); 283670#L865-2 assume !(1 == ~M_E~0); 283671#L735-1 assume !(1 == ~T1_E~0); 283749#L740-1 assume !(1 == ~T2_E~0); 283714#L745-1 assume !(1 == ~T3_E~0); 283715#L750-1 assume !(1 == ~T4_E~0); 284212#L755-1 assume !(1 == ~T5_E~0); 284187#L760-1 assume !(1 == ~T6_E~0); 284188#L765-1 assume !(1 == ~E_1~0); 284315#L770-1 assume !(1 == ~E_2~0); 284005#L775-1 assume !(1 == ~E_3~0); 283923#L780-1 assume !(1 == ~E_4~0); 283924#L785-1 assume !(1 == ~E_5~0); 284162#L790-1 assume !(1 == ~E_6~0); 284257#L1016-1 assume !false; 293567#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 293562#L637 [2021-10-13 01:19:54,004 INFO L793 eck$LassoCheckResult]: Loop: 293562#L637 assume !false; 293560#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 293557#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 293555#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 293553#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 293551#L548 assume 0 != eval_~tmp~0; 293548#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 293544#L556 assume !(0 != eval_~tmp_ndt_1~0); 292297#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 292294#L570 assume !(0 != eval_~tmp_ndt_2~0); 292291#L567 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 292039#L584 assume !(0 != eval_~tmp_ndt_3~0); 292287#L581 assume !(0 == ~t3_st~0); 292285#L595 assume !(0 == ~t4_st~0); 291377#L609 assume !(0 == ~t5_st~0); 291375#L623 assume !(0 == ~t6_st~0); 293562#L637 [2021-10-13 01:19:54,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:54,005 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 3 times [2021-10-13 01:19:54,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:54,005 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254209422] [2021-10-13 01:19:54,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:54,006 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:54,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:54,025 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:54,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:54,058 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:54,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:54,059 INFO L82 PathProgramCache]: Analyzing trace with hash 203429809, now seen corresponding path program 1 times [2021-10-13 01:19:54,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:54,060 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697160943] [2021-10-13 01:19:54,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:54,062 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:54,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:54,066 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:54,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:54,071 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:54,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:54,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1933371077, now seen corresponding path program 1 times [2021-10-13 01:19:54,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:54,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541647245] [2021-10-13 01:19:54,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:54,077 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:54,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:54,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:54,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:54,115 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541647245] [2021-10-13 01:19:54,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541647245] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:54,116 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:54,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:54,117 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213581831] [2021-10-13 01:19:54,271 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:54,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:54,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:54,272 INFO L87 Difference]: Start difference. First operand 36947 states and 49814 transitions. cyclomatic complexity: 12870 Second operand has 3 states, 3 states have (on average 32.0) internal successors, (96), 3 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:54,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:54,732 INFO L93 Difference]: Finished difference Result 69939 states and 93942 transitions. [2021-10-13 01:19:54,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:54,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69939 states and 93942 transitions. [2021-10-13 01:19:55,153 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 69792 [2021-10-13 01:19:55,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69939 states to 69939 states and 93942 transitions. [2021-10-13 01:19:55,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69939 [2021-10-13 01:19:55,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69939 [2021-10-13 01:19:55,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69939 states and 93942 transitions. [2021-10-13 01:19:55,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:55,354 INFO L681 BuchiCegarLoop]: Abstraction has 69939 states and 93942 transitions. [2021-10-13 01:19:55,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69939 states and 93942 transitions. [2021-10-13 01:19:56,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69939 to 68243. [2021-10-13 01:19:56,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68243 states, 68243 states have (on average 1.3442257813988248) internal successors, (91734), 68242 states have internal predecessors, (91734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:56,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68243 states to 68243 states and 91734 transitions. [2021-10-13 01:19:56,317 INFO L704 BuchiCegarLoop]: Abstraction has 68243 states and 91734 transitions. [2021-10-13 01:19:56,317 INFO L587 BuchiCegarLoop]: Abstraction has 68243 states and 91734 transitions. [2021-10-13 01:19:56,317 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-13 01:19:56,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68243 states and 91734 transitions. [2021-10-13 01:19:56,515 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 68096 [2021-10-13 01:19:56,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:19:56,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:19:56,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:56,516 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:19:56,516 INFO L791 eck$LassoCheckResult]: Stem: 391271#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 391218#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 390758#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 390759#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 390866#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 390795#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 390796#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 391007#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 391012#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 390760#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 390761#L483-1 assume !(0 == ~M_E~0); 391123#L662-1 assume !(0 == ~T1_E~0); 390987#L667-1 assume !(0 == ~T2_E~0); 390988#L672-1 assume !(0 == ~T3_E~0); 390807#L677-1 assume !(0 == ~T4_E~0); 390808#L682-1 assume !(0 == ~T5_E~0); 391063#L687-1 assume !(0 == ~T6_E~0); 391163#L692-1 assume !(0 == ~E_1~0); 391045#L697-1 assume !(0 == ~E_2~0); 391046#L702-1 assume !(0 == ~E_3~0); 391114#L707-1 assume !(0 == ~E_4~0); 390937#L712-1 assume !(0 == ~E_5~0); 390938#L717-1 assume !(0 == ~E_6~0); 391077#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 390797#L312 assume !(1 == ~m_pc~0); 390674#L312-2 is_master_triggered_~__retres1~0 := 0; 390505#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 390506#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 390622#L817 assume !(0 != activate_threads_~tmp~1); 390623#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 390820#L331 assume !(1 == ~t1_pc~0); 390769#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 390576#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 390577#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 390779#L825 assume !(0 != activate_threads_~tmp___0~0); 390780#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 390736#L350 assume !(1 == ~t2_pc~0); 390737#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 390945#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 390946#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 390603#L833 assume !(0 != activate_threads_~tmp___1~0); 390604#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 391216#L369 assume !(1 == ~t3_pc~0); 390670#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 390671#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 390650#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 390651#L841 assume !(0 != activate_threads_~tmp___2~0); 390770#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 390771#L388 assume !(1 == ~t4_pc~0); 390834#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 390652#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 390653#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 390791#L849 assume !(0 != activate_threads_~tmp___3~0); 390792#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 390526#L407 assume !(1 == ~t5_pc~0); 390527#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 390538#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 390507#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 390508#L857 assume !(0 != activate_threads_~tmp___4~0); 390661#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 390662#L426 assume !(1 == ~t6_pc~0); 390996#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 391074#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 391185#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 391147#L865 assume !(0 != activate_threads_~tmp___5~0); 390564#L865-2 assume !(1 == ~M_E~0); 390565#L735-1 assume !(1 == ~T1_E~0); 390640#L740-1 assume !(1 == ~T2_E~0); 390607#L745-1 assume !(1 == ~T3_E~0); 390608#L750-1 assume !(1 == ~T4_E~0); 391112#L755-1 assume !(1 == ~T5_E~0); 391081#L760-1 assume !(1 == ~T6_E~0); 391082#L765-1 assume !(1 == ~E_1~0); 391225#L770-1 assume !(1 == ~E_2~0); 390896#L775-1 assume !(1 == ~E_3~0); 390814#L780-1 assume !(1 == ~E_4~0); 390815#L785-1 assume !(1 == ~E_5~0); 391056#L790-1 assume !(1 == ~E_6~0); 391158#L1016-1 assume !false; 407739#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 407731#L637 [2021-10-13 01:19:56,516 INFO L793 eck$LassoCheckResult]: Loop: 407731#L637 assume !false; 407732#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 407724#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 407725#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 407717#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 407718#L548 assume 0 != eval_~tmp~0; 407710#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 407711#L556 assume !(0 != eval_~tmp_ndt_1~0); 407706#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 407704#L570 assume !(0 != eval_~tmp_ndt_2~0); 407703#L567 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 405046#L584 assume !(0 != eval_~tmp_ndt_3~0); 399619#L581 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 399616#L598 assume !(0 != eval_~tmp_ndt_4~0); 399617#L595 assume !(0 == ~t4_st~0); 407756#L609 assume !(0 == ~t5_st~0); 407755#L623 assume !(0 == ~t6_st~0); 407731#L637 [2021-10-13 01:19:56,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:56,517 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 4 times [2021-10-13 01:19:56,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:56,517 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083780421] [2021-10-13 01:19:56,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:56,517 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:56,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:56,527 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:56,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:56,559 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:56,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:56,560 INFO L82 PathProgramCache]: Analyzing trace with hash 1822198777, now seen corresponding path program 1 times [2021-10-13 01:19:56,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:56,560 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906917043] [2021-10-13 01:19:56,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:56,561 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:56,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:56,565 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:19:56,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:19:56,570 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:19:56,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:19:56,571 INFO L82 PathProgramCache]: Analyzing trace with hash -384196763, now seen corresponding path program 1 times [2021-10-13 01:19:56,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:19:56,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358703311] [2021-10-13 01:19:56,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:19:56,572 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:19:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:19:56,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:19:56,605 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:19:56,606 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358703311] [2021-10-13 01:19:56,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [358703311] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:19:56,606 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:19:56,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:19:56,606 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23160677] [2021-10-13 01:19:56,782 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:19:56,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:19:56,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:19:56,783 INFO L87 Difference]: Start difference. First operand 68243 states and 91734 transitions. cyclomatic complexity: 23494 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:19:57,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:19:57,512 INFO L93 Difference]: Finished difference Result 108979 states and 146382 transitions. [2021-10-13 01:19:57,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:19:57,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108979 states and 146382 transitions. [2021-10-13 01:19:57,918 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 108768 [2021-10-13 01:19:58,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108979 states to 108979 states and 146382 transitions. [2021-10-13 01:19:58,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108979 [2021-10-13 01:19:58,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108979 [2021-10-13 01:19:58,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108979 states and 146382 transitions. [2021-10-13 01:19:58,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:19:58,660 INFO L681 BuchiCegarLoop]: Abstraction has 108979 states and 146382 transitions. [2021-10-13 01:19:58,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108979 states and 146382 transitions. [2021-10-13 01:19:59,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108979 to 108979. [2021-10-13 01:19:59,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108979 states, 108979 states have (on average 1.3432129125794878) internal successors, (146382), 108978 states have internal predecessors, (146382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:20:00,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108979 states to 108979 states and 146382 transitions. [2021-10-13 01:20:00,536 INFO L704 BuchiCegarLoop]: Abstraction has 108979 states and 146382 transitions. [2021-10-13 01:20:00,536 INFO L587 BuchiCegarLoop]: Abstraction has 108979 states and 146382 transitions. [2021-10-13 01:20:00,536 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-10-13 01:20:00,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108979 states and 146382 transitions. [2021-10-13 01:20:00,832 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 108768 [2021-10-13 01:20:00,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:20:00,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:20:00,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:00,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:00,834 INFO L791 eck$LassoCheckResult]: Stem: 568494#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 568450#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 567991#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 567992#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 568101#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 568028#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 568029#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 568250#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 568255#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 567993#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 567994#L483-1 assume !(0 == ~M_E~0); 568362#L662-1 assume !(0 == ~T1_E~0); 568222#L667-1 assume !(0 == ~T2_E~0); 568223#L672-1 assume !(0 == ~T3_E~0); 568041#L677-1 assume !(0 == ~T4_E~0); 568042#L682-1 assume !(0 == ~T5_E~0); 568308#L687-1 assume !(0 == ~T6_E~0); 568399#L692-1 assume !(0 == ~E_1~0); 568290#L697-1 assume !(0 == ~E_2~0); 568291#L702-1 assume !(0 == ~E_3~0); 568349#L707-1 assume !(0 == ~E_4~0); 568173#L712-1 assume !(0 == ~E_5~0); 568174#L717-1 assume !(0 == ~E_6~0); 568323#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 568032#L312 assume !(1 == ~m_pc~0); 567906#L312-2 is_master_triggered_~__retres1~0 := 0; 567735#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 567736#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 567853#L817 assume !(0 != activate_threads_~tmp~1); 567854#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 568053#L331 assume !(1 == ~t1_pc~0); 568002#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 567807#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 567808#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 568012#L825 assume !(0 != activate_threads_~tmp___0~0); 568013#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 567968#L350 assume !(1 == ~t2_pc~0); 567969#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 568182#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 568183#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 567834#L833 assume !(0 != activate_threads_~tmp___1~0); 567835#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 568449#L369 assume !(1 == ~t3_pc~0); 567902#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 567903#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 567887#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 567888#L841 assume !(0 != activate_threads_~tmp___2~0); 568006#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 568007#L388 assume !(1 == ~t4_pc~0); 568064#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 567885#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 567886#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 568024#L849 assume !(0 != activate_threads_~tmp___3~0); 568025#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 567758#L407 assume !(1 == ~t5_pc~0); 567759#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 567768#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 567737#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 567738#L857 assume !(0 != activate_threads_~tmp___4~0); 567893#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 567894#L426 assume !(1 == ~t6_pc~0); 568237#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 568317#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 568423#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 568386#L865 assume !(0 != activate_threads_~tmp___5~0); 567794#L865-2 assume !(1 == ~M_E~0); 567795#L735-1 assume !(1 == ~T1_E~0); 567874#L740-1 assume !(1 == ~T2_E~0); 567838#L745-1 assume !(1 == ~T3_E~0); 567839#L750-1 assume !(1 == ~T4_E~0); 568347#L755-1 assume !(1 == ~T5_E~0); 568326#L760-1 assume !(1 == ~T6_E~0); 568327#L765-1 assume !(1 == ~E_1~0); 568454#L770-1 assume !(1 == ~E_2~0); 568134#L775-1 assume !(1 == ~E_3~0); 568048#L780-1 assume !(1 == ~E_4~0); 568049#L785-1 assume !(1 == ~E_5~0); 568301#L790-1 assume !(1 == ~E_6~0); 568391#L1016-1 assume !false; 590199#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 590193#L637 [2021-10-13 01:20:00,834 INFO L793 eck$LassoCheckResult]: Loop: 590193#L637 assume !false; 590191#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 590187#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 590184#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 590183#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 590181#L548 assume 0 != eval_~tmp~0; 590178#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 590176#L556 assume !(0 != eval_~tmp_ndt_1~0); 590174#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 590136#L570 assume !(0 != eval_~tmp_ndt_2~0); 590172#L567 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 588073#L584 assume !(0 != eval_~tmp_ndt_3~0); 586137#L581 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 586126#L598 assume !(0 != eval_~tmp_ndt_4~0); 586127#L595 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 590218#L612 assume !(0 != eval_~tmp_ndt_5~0); 590217#L609 assume !(0 == ~t5_st~0); 590197#L623 assume !(0 == ~t6_st~0); 590193#L637 [2021-10-13 01:20:00,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:00,834 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 5 times [2021-10-13 01:20:00,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:00,834 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427555704] [2021-10-13 01:20:00,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:00,835 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:00,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:00,845 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:00,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:00,902 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:00,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:00,903 INFO L82 PathProgramCache]: Analyzing trace with hash 647492045, now seen corresponding path program 1 times [2021-10-13 01:20:00,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:00,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075755343] [2021-10-13 01:20:00,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:00,904 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:00,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:00,913 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:00,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:00,919 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:00,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:00,920 INFO L82 PathProgramCache]: Analyzing trace with hash 968707041, now seen corresponding path program 1 times [2021-10-13 01:20:00,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:00,920 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85917102] [2021-10-13 01:20:00,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:00,921 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:00,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:20:00,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:20:00,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:20:00,957 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85917102] [2021-10-13 01:20:00,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85917102] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:20:00,957 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:20:00,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:20:00,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736122471] [2021-10-13 01:20:01,171 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:20:01,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:20:01,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:20:01,173 INFO L87 Difference]: Start difference. First operand 108979 states and 146382 transitions. cyclomatic complexity: 37406 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:20:02,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:20:02,341 INFO L93 Difference]: Finished difference Result 201427 states and 270278 transitions. [2021-10-13 01:20:02,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:20:02,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201427 states and 270278 transitions. [2021-10-13 01:20:03,054 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 201088 [2021-10-13 01:20:04,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201427 states to 201427 states and 270278 transitions. [2021-10-13 01:20:04,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201427 [2021-10-13 01:20:04,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201427 [2021-10-13 01:20:04,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201427 states and 270278 transitions. [2021-10-13 01:20:04,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:20:04,152 INFO L681 BuchiCegarLoop]: Abstraction has 201427 states and 270278 transitions. [2021-10-13 01:20:04,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201427 states and 270278 transitions. [2021-10-13 01:20:05,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201427 to 198867. [2021-10-13 01:20:06,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198867 states, 198867 states have (on average 1.3423544378906505) internal successors, (266950), 198866 states have internal predecessors, (266950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:20:07,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198867 states to 198867 states and 266950 transitions. [2021-10-13 01:20:07,298 INFO L704 BuchiCegarLoop]: Abstraction has 198867 states and 266950 transitions. [2021-10-13 01:20:07,298 INFO L587 BuchiCegarLoop]: Abstraction has 198867 states and 266950 transitions. [2021-10-13 01:20:07,298 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-10-13 01:20:07,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198867 states and 266950 transitions. [2021-10-13 01:20:08,009 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 198528 [2021-10-13 01:20:08,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:20:08,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:20:08,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:08,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:08,012 INFO L791 eck$LassoCheckResult]: Stem: 878939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 878878#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 878408#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 878409#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 878513#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 878446#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 878447#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 878662#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 878667#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 878410#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 878411#L483-1 assume !(0 == ~M_E~0); 878779#L662-1 assume !(0 == ~T1_E~0); 878635#L667-1 assume !(0 == ~T2_E~0); 878636#L672-1 assume !(0 == ~T3_E~0); 878460#L677-1 assume !(0 == ~T4_E~0); 878461#L682-1 assume !(0 == ~T5_E~0); 878717#L687-1 assume !(0 == ~T6_E~0); 878820#L692-1 assume !(0 == ~E_1~0); 878700#L697-1 assume !(0 == ~E_2~0); 878701#L702-1 assume !(0 == ~E_3~0); 878768#L707-1 assume !(0 == ~E_4~0); 878585#L712-1 assume !(0 == ~E_5~0); 878586#L717-1 assume !(0 == ~E_6~0); 878731#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 878450#L312 assume !(1 == ~m_pc~0); 878321#L312-2 is_master_triggered_~__retres1~0 := 0; 878149#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 878150#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 878268#L817 assume !(0 != activate_threads_~tmp~1); 878269#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 878472#L331 assume !(1 == ~t1_pc~0); 878420#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 878221#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 878222#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 878430#L825 assume !(0 != activate_threads_~tmp___0~0); 878431#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 878385#L350 assume !(1 == ~t2_pc~0); 878386#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 878593#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 878594#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 878249#L833 assume !(0 != activate_threads_~tmp___1~0); 878250#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 878875#L369 assume !(1 == ~t3_pc~0); 878317#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 878318#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 878297#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 878298#L841 assume !(0 != activate_threads_~tmp___2~0); 878421#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 878422#L388 assume !(1 == ~t4_pc~0); 878483#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 878299#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 878300#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 878442#L849 assume !(0 != activate_threads_~tmp___3~0); 878443#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 878170#L407 assume !(1 == ~t5_pc~0); 878171#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 878183#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 878151#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 878152#L857 assume !(0 != activate_threads_~tmp___4~0); 878308#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 878309#L426 assume !(1 == ~t6_pc~0); 878649#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 878728#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 878843#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 878804#L865 assume !(0 != activate_threads_~tmp___5~0); 878209#L865-2 assume !(1 == ~M_E~0); 878210#L735-1 assume !(1 == ~T1_E~0); 878287#L740-1 assume !(1 == ~T2_E~0); 878253#L745-1 assume !(1 == ~T3_E~0); 878254#L750-1 assume !(1 == ~T4_E~0); 878767#L755-1 assume !(1 == ~T5_E~0); 878735#L760-1 assume !(1 == ~T6_E~0); 878736#L765-1 assume !(1 == ~E_1~0); 878885#L770-1 assume !(1 == ~E_2~0); 878542#L775-1 assume !(1 == ~E_3~0); 878467#L780-1 assume !(1 == ~E_4~0); 878468#L785-1 assume !(1 == ~E_5~0); 878711#L790-1 assume !(1 == ~E_6~0); 878811#L1016-1 assume !false; 930050#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 930045#L637 [2021-10-13 01:20:08,012 INFO L793 eck$LassoCheckResult]: Loop: 930045#L637 assume !false; 930043#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 930039#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 930037#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 930035#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 930033#L548 assume 0 != eval_~tmp~0; 930014#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 930015#L556 assume !(0 != eval_~tmp_ndt_1~0); 929976#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 929974#L570 assume !(0 != eval_~tmp_ndt_2~0); 929973#L567 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 919949#L584 assume !(0 != eval_~tmp_ndt_3~0); 914536#L581 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 914531#L598 assume !(0 != eval_~tmp_ndt_4~0); 914533#L595 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 914068#L612 assume !(0 != eval_~tmp_ndt_5~0); 917448#L609 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 917445#L626 assume !(0 != eval_~tmp_ndt_6~0); 917447#L623 assume !(0 == ~t6_st~0); 930045#L637 [2021-10-13 01:20:08,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:08,013 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 6 times [2021-10-13 01:20:08,013 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:08,013 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666073040] [2021-10-13 01:20:08,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:08,014 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:08,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:08,031 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:08,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:08,065 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:08,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:08,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1402773027, now seen corresponding path program 1 times [2021-10-13 01:20:08,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:08,067 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494234587] [2021-10-13 01:20:08,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:08,067 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:08,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:08,072 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:08,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:08,077 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:08,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:08,079 INFO L82 PathProgramCache]: Analyzing trace with hash -35042743, now seen corresponding path program 1 times [2021-10-13 01:20:08,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:08,081 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632626209] [2021-10-13 01:20:08,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:08,081 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:08,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:20:08,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:20:08,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:20:08,115 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632626209] [2021-10-13 01:20:08,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632626209] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:20:08,115 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:20:08,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:20:08,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1573175065] [2021-10-13 01:20:08,353 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:20:08,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:20:08,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:20:08,354 INFO L87 Difference]: Start difference. First operand 198867 states and 266950 transitions. cyclomatic complexity: 68086 Second operand has 3 states, 2 states have (on average 49.5) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:20:10,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:20:10,231 INFO L93 Difference]: Finished difference Result 385683 states and 516454 transitions. [2021-10-13 01:20:10,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:20:10,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385683 states and 516454 transitions. [2021-10-13 01:20:12,586 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 385088 [2021-10-13 01:20:14,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385683 states to 385683 states and 516454 transitions. [2021-10-13 01:20:14,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385683 [2021-10-13 01:20:14,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385683 [2021-10-13 01:20:14,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385683 states and 516454 transitions. [2021-10-13 01:20:14,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:20:14,239 INFO L681 BuchiCegarLoop]: Abstraction has 385683 states and 516454 transitions. [2021-10-13 01:20:14,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385683 states and 516454 transitions. [2021-10-13 01:20:17,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385683 to 385683. [2021-10-13 01:20:18,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 385683 states, 385683 states have (on average 1.3390634277372868) internal successors, (516454), 385682 states have internal predecessors, (516454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:20:20,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385683 states to 385683 states and 516454 transitions. [2021-10-13 01:20:20,165 INFO L704 BuchiCegarLoop]: Abstraction has 385683 states and 516454 transitions. [2021-10-13 01:20:20,165 INFO L587 BuchiCegarLoop]: Abstraction has 385683 states and 516454 transitions. [2021-10-13 01:20:20,166 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-10-13 01:20:20,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 385683 states and 516454 transitions. [2021-10-13 01:20:22,176 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 385088 [2021-10-13 01:20:22,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:20:22,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:20:22,178 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:22,178 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:20:22,178 INFO L791 eck$LassoCheckResult]: Stem: 1463500#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1463437#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1462965#L979 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1462966#L446 assume 1 == ~m_i~0;~m_st~0 := 0; 1463068#L453-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1463002#L458-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1463003#L463-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1463215#L468-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1463220#L473-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1462967#L478-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1462968#L483-1 assume !(0 == ~M_E~0); 1463338#L662-1 assume !(0 == ~T1_E~0); 1463191#L667-1 assume !(0 == ~T2_E~0); 1463192#L672-1 assume !(0 == ~T3_E~0); 1463015#L677-1 assume !(0 == ~T4_E~0); 1463016#L682-1 assume !(0 == ~T5_E~0); 1463271#L687-1 assume !(0 == ~T6_E~0); 1463377#L692-1 assume !(0 == ~E_1~0); 1463252#L697-1 assume !(0 == ~E_2~0); 1463253#L702-1 assume !(0 == ~E_3~0); 1463326#L707-1 assume !(0 == ~E_4~0); 1463142#L712-1 assume !(0 == ~E_5~0); 1463143#L717-1 assume !(0 == ~E_6~0); 1463288#L722-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1463005#L312 assume !(1 == ~m_pc~0); 1462878#L312-2 is_master_triggered_~__retres1~0 := 0; 1462707#L323 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1462708#L324 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1462825#L817 assume !(0 != activate_threads_~tmp~1); 1462826#L817-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1463027#L331 assume !(1 == ~t1_pc~0); 1462976#L331-2 is_transmit1_triggered_~__retres1~1 := 0; 1462779#L342 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1462780#L343 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1462986#L825 assume !(0 != activate_threads_~tmp___0~0); 1462987#L825-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1462941#L350 assume !(1 == ~t2_pc~0); 1462942#L350-2 is_transmit2_triggered_~__retres1~2 := 0; 1463149#L361 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1463150#L362 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1462806#L833 assume !(0 != activate_threads_~tmp___1~0); 1462807#L833-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1463435#L369 assume !(1 == ~t3_pc~0); 1462874#L369-2 is_transmit3_triggered_~__retres1~3 := 0; 1462875#L380 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1462856#L381 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1462857#L841 assume !(0 != activate_threads_~tmp___2~0); 1462977#L841-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1462978#L388 assume !(1 == ~t4_pc~0); 1463038#L388-2 is_transmit4_triggered_~__retres1~4 := 0; 1462854#L399 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1462855#L400 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1462998#L849 assume !(0 != activate_threads_~tmp___3~0); 1462999#L849-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1462728#L407 assume !(1 == ~t5_pc~0); 1462729#L407-2 is_transmit5_triggered_~__retres1~5 := 0; 1462741#L418 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1462709#L419 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1462710#L857 assume !(0 != activate_threads_~tmp___4~0); 1462865#L857-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1462866#L426 assume !(1 == ~t6_pc~0); 1463203#L426-2 is_transmit6_triggered_~__retres1~6 := 0; 1463285#L437 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1463404#L438 activate_threads_#t~ret21 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1463361#L865 assume !(0 != activate_threads_~tmp___5~0); 1462767#L865-2 assume !(1 == ~M_E~0); 1462768#L735-1 assume !(1 == ~T1_E~0); 1462844#L740-1 assume !(1 == ~T2_E~0); 1462810#L745-1 assume !(1 == ~T3_E~0); 1462811#L750-1 assume !(1 == ~T4_E~0); 1463324#L755-1 assume !(1 == ~T5_E~0); 1463292#L760-1 assume !(1 == ~T6_E~0); 1463293#L765-1 assume !(1 == ~E_1~0); 1463441#L770-1 assume !(1 == ~E_2~0); 1463097#L775-1 assume !(1 == ~E_3~0); 1463022#L780-1 assume !(1 == ~E_4~0); 1463023#L785-1 assume !(1 == ~E_5~0); 1463265#L790-1 assume !(1 == ~E_6~0); 1463369#L1016-1 assume !false; 1568849#L1017 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1565452#L637 [2021-10-13 01:20:22,179 INFO L793 eck$LassoCheckResult]: Loop: 1565452#L637 assume !false; 1568846#L544 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1568843#L496 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1568840#L533 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1568837#L534 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1568836#L548 assume 0 != eval_~tmp~0; 1568834#L548-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 1568831#L556 assume !(0 != eval_~tmp_ndt_1~0); 1568828#L553 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1568761#L570 assume !(0 != eval_~tmp_ndt_2~0); 1568826#L567 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1569379#L584 assume !(0 != eval_~tmp_ndt_3~0); 1569377#L581 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1560736#L598 assume !(0 != eval_~tmp_ndt_4~0); 1565459#L595 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 1565457#L612 assume !(0 != eval_~tmp_ndt_5~0); 1565456#L609 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 1564904#L626 assume !(0 != eval_~tmp_ndt_6~0); 1565454#L623 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 1565443#L640 assume !(0 != eval_~tmp_ndt_7~0); 1565452#L637 [2021-10-13 01:20:22,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:22,179 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 7 times [2021-10-13 01:20:22,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:22,180 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143576000] [2021-10-13 01:20:22,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:22,180 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:22,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,191 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:22,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,222 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:22,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:22,223 INFO L82 PathProgramCache]: Analyzing trace with hash -536290327, now seen corresponding path program 1 times [2021-10-13 01:20:22,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:22,223 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50084456] [2021-10-13 01:20:22,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:22,224 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:22,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,228 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:22,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,233 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:22,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:20:22,233 INFO L82 PathProgramCache]: Analyzing trace with hash -1086324483, now seen corresponding path program 1 times [2021-10-13 01:20:22,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:20:22,234 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313885001] [2021-10-13 01:20:22,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:20:22,234 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:20:22,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,243 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:20:22,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:20:22,281 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:20:25,001 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.10 01:20:25 BoogieIcfgContainer [2021-10-13 01:20:25,001 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-13 01:20:25,002 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-13 01:20:25,002 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-13 01:20:25,002 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-13 01:20:25,003 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:19:41" (3/4) ... [2021-10-13 01:20:25,006 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-13 01:20:25,085 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/witness.graphml [2021-10-13 01:20:25,085 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-13 01:20:25,087 INFO L168 Benchmark]: Toolchain (without parser) took 45911.34 ms. Allocated memory was 88.1 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 51.6 MB in the beginning and 10.0 GB in the end (delta: -9.9 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,087 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 88.1 MB. Free memory is still 68.2 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-13 01:20:25,088 INFO L168 Benchmark]: CACSL2BoogieTranslator took 540.46 ms. Allocated memory was 88.1 MB in the beginning and 132.1 MB in the end (delta: 44.0 MB). Free memory was 51.4 MB in the beginning and 102.5 MB in the end (delta: -51.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,088 INFO L168 Benchmark]: Boogie Procedure Inliner took 142.83 ms. Allocated memory is still 132.1 MB. Free memory was 102.5 MB in the beginning and 96.9 MB in the end (delta: 5.6 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,089 INFO L168 Benchmark]: Boogie Preprocessor took 136.12 ms. Allocated memory is still 132.1 MB. Free memory was 96.9 MB in the beginning and 92.0 MB in the end (delta: 4.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,089 INFO L168 Benchmark]: RCFGBuilder took 1687.02 ms. Allocated memory is still 132.1 MB. Free memory was 92.0 MB in the beginning and 98.3 MB in the end (delta: -6.4 MB). Peak memory consumption was 53.8 MB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,090 INFO L168 Benchmark]: BuchiAutomizer took 43312.28 ms. Allocated memory was 132.1 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 98.3 MB in the beginning and 10.0 GB in the end (delta: -9.9 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,090 INFO L168 Benchmark]: Witness Printer took 83.29 ms. Allocated memory is still 14.0 GB. Free memory was 10.0 GB in the beginning and 10.0 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-13 01:20:25,092 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 88.1 MB. Free memory is still 68.2 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 540.46 ms. Allocated memory was 88.1 MB in the beginning and 132.1 MB in the end (delta: 44.0 MB). Free memory was 51.4 MB in the beginning and 102.5 MB in the end (delta: -51.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 142.83 ms. Allocated memory is still 132.1 MB. Free memory was 102.5 MB in the beginning and 96.9 MB in the end (delta: 5.6 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 136.12 ms. Allocated memory is still 132.1 MB. Free memory was 96.9 MB in the beginning and 92.0 MB in the end (delta: 4.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1687.02 ms. Allocated memory is still 132.1 MB. Free memory was 92.0 MB in the beginning and 98.3 MB in the end (delta: -6.4 MB). Peak memory consumption was 53.8 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 43312.28 ms. Allocated memory was 132.1 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 98.3 MB in the beginning and 10.0 GB in the end (delta: -9.9 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. * Witness Printer took 83.29 ms. Allocated memory is still 14.0 GB. Free memory was 10.0 GB in the beginning and 10.0 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 26 terminating modules (26 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.26 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 385683 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 43.2s and 27 iterations. TraceHistogramMax:1. Analysis of lassos took 7.1s. Construction of modules took 0.7s. Büchi inclusion checks took 6.0s. Highest rank in rank-based complementation 0. Minimization of det autom 26. Minimization of nondet autom 0. Automata minimization 14926.5ms AutomataMinimizationTime, 26 MinimizatonAttempts, 25039 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 8.9s Buchi closure took 0.4s. Biggest automaton had 385683 states and ocurred in iteration 26. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 23536 SDtfs, 28112 SDslu, 20538 SDs, 0 SdLazy, 676 SolverSat, 351 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 790.7ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI15 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 543]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=31301} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=31301, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, t4_i=1, E_3=2, t4_pc=0, T6_E=2, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_4=0, \result=0, tmp_ndt_6=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5105728e=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@aef9e9f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@787a1f36=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@43bb3850=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a9d80d2=0, NULL=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a278d6a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@204c05a2=0, tmp=0, __retres1=0, \result=0, m_pc=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@151ede29=0, \result=0, t6_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@729ab557=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@526f3f09=0, NULL=31304, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6ce1fd68=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@36eb9f16=0, E_6=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7530e52d=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3cfc2ece=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30698c41=0, T1_E=2, NULL=31302, tmp_ndt_1=0, NULL=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, NULL=31303, T5_E=2, t2_i=1, T4_E=2, t4_st=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@29860065=0, t1_st=0, t5_pc=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@472f9aab=0, __retres1=0, t2_pc=0, tmp_ndt_7=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, tmp___5=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 543]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int t5_pc = 0; [L23] int t6_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int t3_i ; [L35] int t4_i ; [L36] int t5_i ; [L37] int t6_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L49] int E_5 = 2; [L50] int E_6 = 2; [L1061] int __retres1 ; [L971] m_i = 1 [L972] t1_i = 1 [L973] t2_i = 1 [L974] t3_i = 1 [L975] t4_i = 1 [L976] t5_i = 1 [L977] t6_i = 1 [L1002] int kernel_st ; [L1003] int tmp ; [L1004] int tmp___0 ; [L1008] kernel_st = 0 [L453] COND TRUE m_i == 1 [L454] m_st = 0 [L458] COND TRUE t1_i == 1 [L459] t1_st = 0 [L463] COND TRUE t2_i == 1 [L464] t2_st = 0 [L468] COND TRUE t3_i == 1 [L469] t3_st = 0 [L473] COND TRUE t4_i == 1 [L474] t4_st = 0 [L478] COND TRUE t5_i == 1 [L479] t5_st = 0 [L483] COND TRUE t6_i == 1 [L484] t6_st = 0 [L662] COND FALSE !(M_E == 0) [L667] COND FALSE !(T1_E == 0) [L672] COND FALSE !(T2_E == 0) [L677] COND FALSE !(T3_E == 0) [L682] COND FALSE !(T4_E == 0) [L687] COND FALSE !(T5_E == 0) [L692] COND FALSE !(T6_E == 0) [L697] COND FALSE !(E_1 == 0) [L702] COND FALSE !(E_2 == 0) [L707] COND FALSE !(E_3 == 0) [L712] COND FALSE !(E_4 == 0) [L717] COND FALSE !(E_5 == 0) [L722] COND FALSE !(E_6 == 0) [L805] int tmp ; [L806] int tmp___0 ; [L807] int tmp___1 ; [L808] int tmp___2 ; [L809] int tmp___3 ; [L810] int tmp___4 ; [L811] int tmp___5 ; [L309] int __retres1 ; [L312] COND FALSE !(m_pc == 1) [L322] __retres1 = 0 [L324] return (__retres1); [L815] tmp = is_master_triggered() [L817] COND FALSE !(\read(tmp)) [L328] int __retres1 ; [L331] COND FALSE !(t1_pc == 1) [L341] __retres1 = 0 [L343] return (__retres1); [L823] tmp___0 = is_transmit1_triggered() [L825] COND FALSE !(\read(tmp___0)) [L347] int __retres1 ; [L350] COND FALSE !(t2_pc == 1) [L360] __retres1 = 0 [L362] return (__retres1); [L831] tmp___1 = is_transmit2_triggered() [L833] COND FALSE !(\read(tmp___1)) [L366] int __retres1 ; [L369] COND FALSE !(t3_pc == 1) [L379] __retres1 = 0 [L381] return (__retres1); [L839] tmp___2 = is_transmit3_triggered() [L841] COND FALSE !(\read(tmp___2)) [L385] int __retres1 ; [L388] COND FALSE !(t4_pc == 1) [L398] __retres1 = 0 [L400] return (__retres1); [L847] tmp___3 = is_transmit4_triggered() [L849] COND FALSE !(\read(tmp___3)) [L404] int __retres1 ; [L407] COND FALSE !(t5_pc == 1) [L417] __retres1 = 0 [L419] return (__retres1); [L855] tmp___4 = is_transmit5_triggered() [L857] COND FALSE !(\read(tmp___4)) [L423] int __retres1 ; [L426] COND FALSE !(t6_pc == 1) [L436] __retres1 = 0 [L438] return (__retres1); [L863] tmp___5 = is_transmit6_triggered() [L865] COND FALSE !(\read(tmp___5)) [L735] COND FALSE !(M_E == 1) [L740] COND FALSE !(T1_E == 1) [L745] COND FALSE !(T2_E == 1) [L750] COND FALSE !(T3_E == 1) [L755] COND FALSE !(T4_E == 1) [L760] COND FALSE !(T5_E == 1) [L765] COND FALSE !(T6_E == 1) [L770] COND FALSE !(E_1 == 1) [L775] COND FALSE !(E_2 == 1) [L780] COND FALSE !(E_3 == 1) [L785] COND FALSE !(E_4 == 1) [L790] COND FALSE !(E_5 == 1) [L795] COND FALSE !(E_6 == 1) [L1016] COND TRUE 1 [L1019] kernel_st = 1 [L539] int tmp ; Loop: [L543] COND TRUE 1 [L493] int __retres1 ; [L496] COND TRUE m_st == 0 [L497] __retres1 = 1 [L534] return (__retres1); [L546] tmp = exists_runnable_thread() [L548] COND TRUE \read(tmp) [L553] COND TRUE m_st == 0 [L554] int tmp_ndt_1; [L555] tmp_ndt_1 = __VERIFIER_nondet_int() [L556] COND FALSE !(\read(tmp_ndt_1)) [L567] COND TRUE t1_st == 0 [L568] int tmp_ndt_2; [L569] tmp_ndt_2 = __VERIFIER_nondet_int() [L570] COND FALSE !(\read(tmp_ndt_2)) [L581] COND TRUE t2_st == 0 [L582] int tmp_ndt_3; [L583] tmp_ndt_3 = __VERIFIER_nondet_int() [L584] COND FALSE !(\read(tmp_ndt_3)) [L595] COND TRUE t3_st == 0 [L596] int tmp_ndt_4; [L597] tmp_ndt_4 = __VERIFIER_nondet_int() [L598] COND FALSE !(\read(tmp_ndt_4)) [L609] COND TRUE t4_st == 0 [L610] int tmp_ndt_5; [L611] tmp_ndt_5 = __VERIFIER_nondet_int() [L612] COND FALSE !(\read(tmp_ndt_5)) [L623] COND TRUE t5_st == 0 [L624] int tmp_ndt_6; [L625] tmp_ndt_6 = __VERIFIER_nondet_int() [L626] COND FALSE !(\read(tmp_ndt_6)) [L637] COND TRUE t6_st == 0 [L638] int tmp_ndt_7; [L639] tmp_ndt_7 = __VERIFIER_nondet_int() [L640] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-13 01:20:25,169 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2e2edd2-f373-4edd-ab35-4165eda8ea4a/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...