./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4e77c044 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ab3c8e786b7a020c9c7c3a4249de38e06543ca10 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-4e77c04 [2021-10-13 01:04:44,189 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-13 01:04:44,191 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-13 01:04:44,244 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-13 01:04:44,244 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-13 01:04:44,250 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-13 01:04:44,252 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-13 01:04:44,260 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-13 01:04:44,262 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-13 01:04:44,263 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-13 01:04:44,264 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-13 01:04:44,265 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-13 01:04:44,266 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-13 01:04:44,267 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-13 01:04:44,269 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-13 01:04:44,270 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-13 01:04:44,272 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-13 01:04:44,273 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-13 01:04:44,276 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-13 01:04:44,286 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-13 01:04:44,287 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-13 01:04:44,289 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-13 01:04:44,290 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-13 01:04:44,291 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-13 01:04:44,294 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-13 01:04:44,295 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-13 01:04:44,295 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-13 01:04:44,296 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-13 01:04:44,297 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-13 01:04:44,298 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-13 01:04:44,298 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-13 01:04:44,299 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-13 01:04:44,300 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-13 01:04:44,301 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-13 01:04:44,302 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-13 01:04:44,302 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-13 01:04:44,303 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-13 01:04:44,303 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-13 01:04:44,304 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-13 01:04:44,304 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-13 01:04:44,305 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-13 01:04:44,306 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-13 01:04:44,339 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-13 01:04:44,340 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-13 01:04:44,340 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-13 01:04:44,340 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-13 01:04:44,341 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-13 01:04:44,341 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-13 01:04:44,342 INFO L138 SettingsManager]: * Use SBE=true [2021-10-13 01:04:44,342 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-13 01:04:44,342 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-13 01:04:44,342 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-13 01:04:44,342 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-13 01:04:44,342 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-13 01:04:44,343 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-13 01:04:44,343 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-13 01:04:44,346 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-13 01:04:44,346 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-13 01:04:44,346 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-13 01:04:44,346 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-13 01:04:44,346 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-13 01:04:44,347 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-13 01:04:44,347 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-13 01:04:44,347 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-13 01:04:44,347 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-13 01:04:44,348 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-13 01:04:44,348 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-13 01:04:44,348 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-13 01:04:44,349 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-13 01:04:44,350 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-13 01:04:44,350 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-13 01:04:44,351 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-13 01:04:44,351 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-13 01:04:44,351 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-13 01:04:44,352 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-13 01:04:44,352 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ab3c8e786b7a020c9c7c3a4249de38e06543ca10 [2021-10-13 01:04:44,681 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-13 01:04:44,712 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-13 01:04:44,714 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-13 01:04:44,715 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-13 01:04:44,717 INFO L275 PluginConnector]: CDTParser initialized [2021-10-13 01:04:44,718 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-10-13 01:04:44,789 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/data/39d44480c/a0345aa2f16247faa4e011df4d638450/FLAG8be8b2e67 [2021-10-13 01:04:45,276 INFO L306 CDTParser]: Found 1 translation units. [2021-10-13 01:04:45,286 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-10-13 01:04:45,297 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/data/39d44480c/a0345aa2f16247faa4e011df4d638450/FLAG8be8b2e67 [2021-10-13 01:04:45,624 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/data/39d44480c/a0345aa2f16247faa4e011df4d638450 [2021-10-13 01:04:45,627 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-13 01:04:45,628 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-13 01:04:45,630 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-13 01:04:45,630 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-13 01:04:45,633 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-13 01:04:45,634 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:04:45" (1/1) ... [2021-10-13 01:04:45,635 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@48692eed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:45, skipping insertion in model container [2021-10-13 01:04:45,636 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 01:04:45" (1/1) ... [2021-10-13 01:04:45,643 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-13 01:04:45,681 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-13 01:04:45,854 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/sv-benchmarks/c/systemc/transmitter.05.cil.c[401,414] [2021-10-13 01:04:45,944 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:04:45,953 INFO L203 MainTranslator]: Completed pre-run [2021-10-13 01:04:45,964 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/sv-benchmarks/c/systemc/transmitter.05.cil.c[401,414] [2021-10-13 01:04:46,004 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-13 01:04:46,020 INFO L208 MainTranslator]: Completed translation [2021-10-13 01:04:46,020 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46 WrapperNode [2021-10-13 01:04:46,020 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-13 01:04:46,021 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-13 01:04:46,021 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-13 01:04:46,021 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-13 01:04:46,027 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,047 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,136 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-13 01:04:46,144 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-13 01:04:46,144 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-13 01:04:46,144 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-13 01:04:46,157 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,158 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,164 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,176 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,208 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,238 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,242 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,250 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-13 01:04:46,251 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-13 01:04:46,252 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-13 01:04:46,252 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-13 01:04:46,253 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (1/1) ... [2021-10-13 01:04:46,260 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-13 01:04:46,272 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/z3 [2021-10-13 01:04:46,284 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-13 01:04:46,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-13 01:04:46,328 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-13 01:04:46,329 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-13 01:04:46,330 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-13 01:04:46,330 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-13 01:04:47,399 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-13 01:04:47,399 INFO L299 CfgBuilder]: Removed 181 assume(true) statements. [2021-10-13 01:04:47,402 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:04:47 BoogieIcfgContainer [2021-10-13 01:04:47,402 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-13 01:04:47,404 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-13 01:04:47,404 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-13 01:04:47,407 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-13 01:04:47,408 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:04:47,408 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.10 01:04:45" (1/3) ... [2021-10-13 01:04:47,410 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f6970e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:04:47, skipping insertion in model container [2021-10-13 01:04:47,410 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:04:47,410 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 01:04:46" (2/3) ... [2021-10-13 01:04:47,411 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f6970e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.10 01:04:47, skipping insertion in model container [2021-10-13 01:04:47,411 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-13 01:04:47,411 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:04:47" (3/3) ... [2021-10-13 01:04:47,412 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2021-10-13 01:04:47,453 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-13 01:04:47,454 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-13 01:04:47,454 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-13 01:04:47,454 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-13 01:04:47,454 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-13 01:04:47,454 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-13 01:04:47,454 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-13 01:04:47,454 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-13 01:04:47,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 485 states, 484 states have (on average 1.5557851239669422) internal successors, (753), 484 states have internal predecessors, (753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:47,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2021-10-13 01:04:47,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:47,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:47,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:47,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:47,551 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-13 01:04:47,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 485 states, 484 states have (on average 1.5557851239669422) internal successors, (753), 484 states have internal predecessors, (753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:47,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2021-10-13 01:04:47,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:47,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:47,587 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:47,588 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:47,596 INFO L791 eck$LassoCheckResult]: Stem: 471#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 397#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 242#L855true havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 175#L386true assume !(1 == ~m_i~0);~m_st~0 := 2; 356#L393-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 261#L398-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 452#L403-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 190#L408-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L413-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 371#L418-1true assume !(0 == ~M_E~0); 407#L578-1true assume !(0 == ~T1_E~0); 147#L583-1true assume !(0 == ~T2_E~0); 102#L588-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 60#L593-1true assume !(0 == ~T4_E~0); 55#L598-1true assume !(0 == ~T5_E~0); 449#L603-1true assume !(0 == ~E_1~0); 191#L608-1true assume !(0 == ~E_2~0); 97#L613-1true assume !(0 == ~E_3~0); 168#L618-1true assume !(0 == ~E_4~0); 292#L623-1true assume !(0 == ~E_5~0); 441#L628-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 391#L271true assume 1 == ~m_pc~0; 27#L272true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 366#L282true is_master_triggered_#res := is_master_triggered_~__retres1~0; 201#L283true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 418#L712true assume !(0 != activate_threads_~tmp~1); 288#L712-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 357#L290true assume 1 == ~t1_pc~0; 176#L291true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 323#L301true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 185#L302true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 260#L720true assume !(0 != activate_threads_~tmp___0~0); 467#L720-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 438#L309true assume !(1 == ~t2_pc~0); 486#L309-2true is_transmit2_triggered_~__retres1~2 := 0; 317#L320true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 165#L321true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42#L728true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 250#L728-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 453#L328true assume 1 == ~t3_pc~0; 392#L329true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 99#L339true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 208#L340true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 138#L736true assume !(0 != activate_threads_~tmp___2~0); 411#L736-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 468#L347true assume !(1 == ~t4_pc~0); 43#L347-2true is_transmit4_triggered_~__retres1~4 := 0; 8#L358true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 445#L359true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 265#L744true assume !(0 != activate_threads_~tmp___3~0); 319#L744-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 80#L366true assume 1 == ~t5_pc~0; 243#L367true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 360#L377true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 376#L378true activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 305#L752true assume !(0 != activate_threads_~tmp___4~0); 45#L752-2true assume !(1 == ~M_E~0); 53#L641-1true assume !(1 == ~T1_E~0); 131#L646-1true assume !(1 == ~T2_E~0); 423#L651-1true assume !(1 == ~T3_E~0); 377#L656-1true assume !(1 == ~T4_E~0); 300#L661-1true assume !(1 == ~T5_E~0); 335#L666-1true assume 1 == ~E_1~0;~E_1~0 := 2; 266#L671-1true assume !(1 == ~E_2~0); 108#L676-1true assume !(1 == ~E_3~0); 341#L681-1true assume !(1 == ~E_4~0); 199#L686-1true assume !(1 == ~E_5~0); 54#L892-1true [2021-10-13 01:04:47,598 INFO L793 eck$LassoCheckResult]: Loop: 54#L892-1true assume !false; 313#L893true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 174#L553true assume !true; 228#L568true start_simulation_~kernel_st~0 := 2; 142#L386-1true start_simulation_~kernel_st~0 := 3; 94#L578-2true assume 0 == ~M_E~0;~M_E~0 := 1; 285#L578-4true assume !(0 == ~T1_E~0); 434#L583-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 387#L588-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 216#L593-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 342#L598-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 364#L603-3true assume 0 == ~E_1~0;~E_1~0 := 1; 262#L608-3true assume 0 == ~E_2~0;~E_2~0 := 1; 217#L613-3true assume 0 == ~E_3~0;~E_3~0 := 1; 272#L618-3true assume !(0 == ~E_4~0); 457#L623-3true assume 0 == ~E_5~0;~E_5~0 := 1; 26#L628-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 361#L271-18true assume 1 == ~m_pc~0; 406#L272-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 419#L282-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 466#L283-6true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 68#L712-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 264#L712-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 483#L290-18true assume 1 == ~t1_pc~0; 139#L291-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 153#L301-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 235#L302-6true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 384#L720-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 326#L720-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 162#L309-18true assume !(1 == ~t2_pc~0); 83#L309-20true is_transmit2_triggered_~__retres1~2 := 0; 66#L320-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 238#L321-6true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 101#L728-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 433#L728-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 415#L328-18true assume !(1 == ~t3_pc~0); 372#L328-20true is_transmit3_triggered_~__retres1~3 := 0; 281#L339-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 310#L340-6true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91#L736-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 334#L736-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 352#L347-18true assume 1 == ~t4_pc~0; 140#L348-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 295#L358-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 421#L359-6true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 161#L744-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 58#L744-20true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 378#L366-18true assume 1 == ~t5_pc~0; 110#L367-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 239#L377-6true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 159#L378-6true activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 197#L752-18true assume !(0 != activate_threads_~tmp___4~0); 114#L752-20true assume 1 == ~M_E~0;~M_E~0 := 2; 37#L641-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 182#L646-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 40#L651-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 155#L656-3true assume !(1 == ~T4_E~0); 426#L661-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 436#L666-3true assume 1 == ~E_1~0;~E_1~0 := 2; 381#L671-3true assume 1 == ~E_2~0;~E_2~0 := 2; 193#L676-3true assume 1 == ~E_3~0;~E_3~0 := 2; 282#L681-3true assume 1 == ~E_4~0;~E_4~0 := 2; 241#L686-3true assume 1 == ~E_5~0;~E_5~0 := 2; 156#L691-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 109#L431-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 224#L463-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 21#L464-1true start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 417#L911true assume !(0 == start_simulation_~tmp~3); 339#L911-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 424#L431-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 412#L463-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 127#L464-2true stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 116#L866true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 267#L873true stop_simulation_#res := stop_simulation_~__retres2~0; 179#L874true start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 188#L924true assume !(0 != start_simulation_~tmp___0~1); 54#L892-1true [2021-10-13 01:04:47,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:47,611 INFO L82 PathProgramCache]: Analyzing trace with hash -1450413925, now seen corresponding path program 1 times [2021-10-13 01:04:47,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:47,659 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431524923] [2021-10-13 01:04:47,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:47,660 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:47,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:47,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:47,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:47,922 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431524923] [2021-10-13 01:04:47,924 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431524923] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:47,924 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:47,924 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:47,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655381523] [2021-10-13 01:04:47,933 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:47,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:47,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1048944325, now seen corresponding path program 1 times [2021-10-13 01:04:47,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:47,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308986583] [2021-10-13 01:04:47,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:47,938 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:47,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,004 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,005 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308986583] [2021-10-13 01:04:48,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308986583] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,006 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,006 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:04:48,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800175939] [2021-10-13 01:04:48,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:48,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:48,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:48,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:48,027 INFO L87 Difference]: Start difference. First operand has 485 states, 484 states have (on average 1.5557851239669422) internal successors, (753), 484 states have internal predecessors, (753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:48,091 INFO L93 Difference]: Finished difference Result 485 states and 733 transitions. [2021-10-13 01:04:48,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:48,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 485 states and 733 transitions. [2021-10-13 01:04:48,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 485 states to 480 states and 728 transitions. [2021-10-13 01:04:48,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:48,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:48,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 728 transitions. [2021-10-13 01:04:48,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:48,136 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2021-10-13 01:04:48,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 728 transitions. [2021-10-13 01:04:48,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:48,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.5166666666666666) internal successors, (728), 479 states have internal predecessors, (728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 728 transitions. [2021-10-13 01:04:48,212 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2021-10-13 01:04:48,213 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2021-10-13 01:04:48,213 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-13 01:04:48,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 728 transitions. [2021-10-13 01:04:48,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:48,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:48,229 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,229 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,230 INFO L791 eck$LassoCheckResult]: Stem: 1457#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1443#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1345#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1279#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 1280#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1362#L398-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1363#L403-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1294#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1205#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1206#L418-1 assume !(0 == ~M_E~0); 1433#L578-1 assume !(0 == ~T1_E~0); 1240#L583-1 assume !(0 == ~T2_E~0); 1167#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1097#L593-1 assume !(0 == ~T4_E~0); 1089#L598-1 assume !(0 == ~T5_E~0); 1090#L603-1 assume !(0 == ~E_1~0); 1295#L608-1 assume !(0 == ~E_2~0); 1158#L613-1 assume !(0 == ~E_3~0); 1159#L618-1 assume !(0 == ~E_4~0); 1269#L623-1 assume !(0 == ~E_5~0); 1388#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1439#L271 assume 1 == ~m_pc~0; 1034#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1035#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1307#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1308#L712 assume !(0 != activate_threads_~tmp~1); 1383#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1384#L290 assume 1 == ~t1_pc~0; 1281#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1125#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1290#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1291#L720 assume !(0 != activate_threads_~tmp___0~0); 1361#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1452#L309 assume !(1 == ~t2_pc~0); 1274#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 1273#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1265#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1067#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1068#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1351#L328 assume 1 == ~t3_pc~0; 1440#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1162#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1163#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1227#L736 assume !(0 != activate_threads_~tmp___2~0); 1228#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1447#L347 assume !(1 == ~t4_pc~0); 1069#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 993#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 994#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1367#L744 assume !(0 != activate_threads_~tmp___3~0); 1368#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1132#L366 assume 1 == ~t5_pc~0; 1133#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1112#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1427#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1398#L752 assume !(0 != activate_threads_~tmp___4~0); 1072#L752-2 assume !(1 == ~M_E~0); 1073#L641-1 assume !(1 == ~T1_E~0); 1086#L646-1 assume !(1 == ~T2_E~0); 1213#L651-1 assume !(1 == ~T3_E~0); 1435#L656-1 assume !(1 == ~T4_E~0); 1393#L661-1 assume !(1 == ~T5_E~0); 1394#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1369#L671-1 assume !(1 == ~E_2~0); 1177#L676-1 assume !(1 == ~E_3~0); 1178#L681-1 assume !(1 == ~E_4~0); 1303#L686-1 assume !(1 == ~E_5~0); 1087#L892-1 [2021-10-13 01:04:48,231 INFO L793 eck$LassoCheckResult]: Loop: 1087#L892-1 assume !false; 1088#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1278#L553 assume !false; 1059#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1060#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1173#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1444#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1168#L478 assume !(0 != eval_~tmp~0); 1169#L568 start_simulation_~kernel_st~0 := 2; 1235#L386-1 start_simulation_~kernel_st~0 := 3; 1154#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1155#L578-4 assume !(0 == ~T1_E~0); 1382#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1438#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1325#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1326#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1418#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1364#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1327#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1328#L618-3 assume !(0 == ~E_4~0); 1373#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1032#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1033#L271-18 assume !(1 == ~m_pc~0); 1122#L271-20 is_master_triggered_~__retres1~0 := 0; 1123#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1450#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1113#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1114#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1366#L290-18 assume 1 == ~t1_pc~0; 1229#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1230#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1249#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1341#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1413#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1262#L309-18 assume !(1 == ~t2_pc~0); 1136#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 1109#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1110#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1165#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1166#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1449#L328-18 assume 1 == ~t3_pc~0; 1137#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1138#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1379#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1149#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1150#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1415#L347-18 assume 1 == ~t4_pc~0; 1232#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1233#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1390#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1261#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1094#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1095#L366-18 assume !(1 == ~t5_pc~0); 1052#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 1053#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1257#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1258#L752-18 assume !(0 != activate_threads_~tmp___4~0); 1186#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1057#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1058#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1063#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1064#L656-3 assume !(1 == ~T4_E~0); 1253#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1451#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1436#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1297#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1298#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1344#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1254#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1179#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1127#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1020#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1021#L911 assume !(0 == start_simulation_~tmp~3); 1332#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1417#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 998#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1207#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 1189#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1190#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 1285#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1286#L924 assume !(0 != start_simulation_~tmp___0~1); 1087#L892-1 [2021-10-13 01:04:48,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,232 INFO L82 PathProgramCache]: Analyzing trace with hash -1396021027, now seen corresponding path program 1 times [2021-10-13 01:04:48,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,233 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245834062] [2021-10-13 01:04:48,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,234 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,328 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245834062] [2021-10-13 01:04:48,328 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245834062] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,328 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,328 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005926855] [2021-10-13 01:04:48,330 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:48,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,332 INFO L82 PathProgramCache]: Analyzing trace with hash 225982626, now seen corresponding path program 1 times [2021-10-13 01:04:48,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,332 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835584923] [2021-10-13 01:04:48,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,333 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,422 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835584923] [2021-10-13 01:04:48,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1835584923] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,422 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040216946] [2021-10-13 01:04:48,424 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:48,424 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:48,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:48,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:48,425 INFO L87 Difference]: Start difference. First operand 480 states and 728 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:48,442 INFO L93 Difference]: Finished difference Result 480 states and 727 transitions. [2021-10-13 01:04:48,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:48,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 727 transitions. [2021-10-13 01:04:48,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 727 transitions. [2021-10-13 01:04:48,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:48,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:48,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 727 transitions. [2021-10-13 01:04:48,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:48,455 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2021-10-13 01:04:48,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 727 transitions. [2021-10-13 01:04:48,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:48,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.5145833333333334) internal successors, (727), 479 states have internal predecessors, (727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 727 transitions. [2021-10-13 01:04:48,468 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2021-10-13 01:04:48,468 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2021-10-13 01:04:48,468 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-13 01:04:48,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 727 transitions. [2021-10-13 01:04:48,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:48,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:48,475 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,475 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,475 INFO L791 eck$LassoCheckResult]: Stem: 2424#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2410#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2312#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2246#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 2247#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2329#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2330#L403-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2261#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2172#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2173#L418-1 assume !(0 == ~M_E~0); 2400#L578-1 assume !(0 == ~T1_E~0); 2207#L583-1 assume !(0 == ~T2_E~0); 2134#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2064#L593-1 assume !(0 == ~T4_E~0); 2056#L598-1 assume !(0 == ~T5_E~0); 2057#L603-1 assume !(0 == ~E_1~0); 2262#L608-1 assume !(0 == ~E_2~0); 2125#L613-1 assume !(0 == ~E_3~0); 2126#L618-1 assume !(0 == ~E_4~0); 2236#L623-1 assume !(0 == ~E_5~0); 2355#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2406#L271 assume 1 == ~m_pc~0; 2001#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2002#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2274#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2275#L712 assume !(0 != activate_threads_~tmp~1); 2350#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2351#L290 assume 1 == ~t1_pc~0; 2248#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2092#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2257#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2258#L720 assume !(0 != activate_threads_~tmp___0~0); 2328#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2419#L309 assume !(1 == ~t2_pc~0); 2241#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 2240#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2232#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2034#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2035#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2318#L328 assume 1 == ~t3_pc~0; 2407#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2129#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2130#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2194#L736 assume !(0 != activate_threads_~tmp___2~0); 2195#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2414#L347 assume !(1 == ~t4_pc~0); 2036#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 1960#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1961#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2334#L744 assume !(0 != activate_threads_~tmp___3~0); 2335#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2099#L366 assume 1 == ~t5_pc~0; 2100#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2079#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2394#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2365#L752 assume !(0 != activate_threads_~tmp___4~0); 2039#L752-2 assume !(1 == ~M_E~0); 2040#L641-1 assume !(1 == ~T1_E~0); 2053#L646-1 assume !(1 == ~T2_E~0); 2180#L651-1 assume !(1 == ~T3_E~0); 2402#L656-1 assume !(1 == ~T4_E~0); 2360#L661-1 assume !(1 == ~T5_E~0); 2361#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2336#L671-1 assume !(1 == ~E_2~0); 2144#L676-1 assume !(1 == ~E_3~0); 2145#L681-1 assume !(1 == ~E_4~0); 2270#L686-1 assume !(1 == ~E_5~0); 2054#L892-1 [2021-10-13 01:04:48,476 INFO L793 eck$LassoCheckResult]: Loop: 2054#L892-1 assume !false; 2055#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2245#L553 assume !false; 2026#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2027#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2140#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2411#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2135#L478 assume !(0 != eval_~tmp~0); 2136#L568 start_simulation_~kernel_st~0 := 2; 2202#L386-1 start_simulation_~kernel_st~0 := 3; 2121#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2122#L578-4 assume !(0 == ~T1_E~0); 2349#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2405#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2292#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2293#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2385#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2331#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2294#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2295#L618-3 assume !(0 == ~E_4~0); 2340#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1999#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2000#L271-18 assume !(1 == ~m_pc~0); 2089#L271-20 is_master_triggered_~__retres1~0 := 0; 2090#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2417#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2080#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2081#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2333#L290-18 assume 1 == ~t1_pc~0; 2196#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2197#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2216#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2308#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2380#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2229#L309-18 assume 1 == ~t2_pc~0; 2165#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2076#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2077#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2132#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2133#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2416#L328-18 assume 1 == ~t3_pc~0; 2104#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2105#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2346#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2116#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2117#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2382#L347-18 assume 1 == ~t4_pc~0; 2199#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2200#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2357#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2228#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2061#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2062#L366-18 assume !(1 == ~t5_pc~0); 2019#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 2020#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2224#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2225#L752-18 assume !(0 != activate_threads_~tmp___4~0); 2153#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2024#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2025#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2030#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2031#L656-3 assume !(1 == ~T4_E~0); 2220#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2418#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2403#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2264#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2265#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2311#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2221#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2146#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2094#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1987#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1988#L911 assume !(0 == start_simulation_~tmp~3); 2299#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2384#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1965#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2174#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 2156#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2157#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 2252#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2253#L924 assume !(0 != start_simulation_~tmp___0~1); 2054#L892-1 [2021-10-13 01:04:48,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,476 INFO L82 PathProgramCache]: Analyzing trace with hash -2075293281, now seen corresponding path program 1 times [2021-10-13 01:04:48,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,477 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342357760] [2021-10-13 01:04:48,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,477 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,521 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,521 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342357760] [2021-10-13 01:04:48,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342357760] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,522 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,522 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,522 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258536594] [2021-10-13 01:04:48,523 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:48,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,525 INFO L82 PathProgramCache]: Analyzing trace with hash 2119424801, now seen corresponding path program 1 times [2021-10-13 01:04:48,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,525 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650142607] [2021-10-13 01:04:48,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,526 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,606 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650142607] [2021-10-13 01:04:48,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650142607] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,607 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,607 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1629475973] [2021-10-13 01:04:48,608 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:48,608 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:48,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:48,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:48,612 INFO L87 Difference]: Start difference. First operand 480 states and 727 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:48,624 INFO L93 Difference]: Finished difference Result 480 states and 726 transitions. [2021-10-13 01:04:48,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:48,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 726 transitions. [2021-10-13 01:04:48,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 726 transitions. [2021-10-13 01:04:48,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:48,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:48,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 726 transitions. [2021-10-13 01:04:48,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:48,637 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2021-10-13 01:04:48,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 726 transitions. [2021-10-13 01:04:48,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:48,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.5125) internal successors, (726), 479 states have internal predecessors, (726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 726 transitions. [2021-10-13 01:04:48,648 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2021-10-13 01:04:48,648 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2021-10-13 01:04:48,648 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-13 01:04:48,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 726 transitions. [2021-10-13 01:04:48,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:48,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:48,655 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,655 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,656 INFO L791 eck$LassoCheckResult]: Stem: 3391#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3377#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3279#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3213#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 3214#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3296#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3297#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3228#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3139#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3140#L418-1 assume !(0 == ~M_E~0); 3367#L578-1 assume !(0 == ~T1_E~0); 3174#L583-1 assume !(0 == ~T2_E~0); 3101#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3031#L593-1 assume !(0 == ~T4_E~0); 3023#L598-1 assume !(0 == ~T5_E~0); 3024#L603-1 assume !(0 == ~E_1~0); 3229#L608-1 assume !(0 == ~E_2~0); 3092#L613-1 assume !(0 == ~E_3~0); 3093#L618-1 assume !(0 == ~E_4~0); 3203#L623-1 assume !(0 == ~E_5~0); 3322#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3373#L271 assume 1 == ~m_pc~0; 2968#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2969#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3241#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3242#L712 assume !(0 != activate_threads_~tmp~1); 3317#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3318#L290 assume 1 == ~t1_pc~0; 3215#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3059#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3224#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3225#L720 assume !(0 != activate_threads_~tmp___0~0); 3295#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3386#L309 assume !(1 == ~t2_pc~0); 3208#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 3207#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3199#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3001#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3002#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3285#L328 assume 1 == ~t3_pc~0; 3374#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3096#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3097#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3161#L736 assume !(0 != activate_threads_~tmp___2~0); 3162#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3381#L347 assume !(1 == ~t4_pc~0); 3003#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 2927#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2928#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3301#L744 assume !(0 != activate_threads_~tmp___3~0); 3302#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3066#L366 assume 1 == ~t5_pc~0; 3067#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3046#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3361#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3332#L752 assume !(0 != activate_threads_~tmp___4~0); 3006#L752-2 assume !(1 == ~M_E~0); 3007#L641-1 assume !(1 == ~T1_E~0); 3020#L646-1 assume !(1 == ~T2_E~0); 3147#L651-1 assume !(1 == ~T3_E~0); 3369#L656-1 assume !(1 == ~T4_E~0); 3327#L661-1 assume !(1 == ~T5_E~0); 3328#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3303#L671-1 assume !(1 == ~E_2~0); 3111#L676-1 assume !(1 == ~E_3~0); 3112#L681-1 assume !(1 == ~E_4~0); 3237#L686-1 assume !(1 == ~E_5~0); 3021#L892-1 [2021-10-13 01:04:48,658 INFO L793 eck$LassoCheckResult]: Loop: 3021#L892-1 assume !false; 3022#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3212#L553 assume !false; 2993#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2994#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3107#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3378#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3102#L478 assume !(0 != eval_~tmp~0); 3103#L568 start_simulation_~kernel_st~0 := 2; 3169#L386-1 start_simulation_~kernel_st~0 := 3; 3088#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3089#L578-4 assume !(0 == ~T1_E~0); 3316#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3372#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3259#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3260#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3352#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3298#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3261#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3262#L618-3 assume !(0 == ~E_4~0); 3307#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2966#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2967#L271-18 assume !(1 == ~m_pc~0); 3056#L271-20 is_master_triggered_~__retres1~0 := 0; 3057#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3384#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3047#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3048#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3300#L290-18 assume 1 == ~t1_pc~0; 3163#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3164#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3183#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3275#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3347#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3196#L309-18 assume 1 == ~t2_pc~0; 3132#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3043#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3044#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3099#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3100#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3383#L328-18 assume !(1 == ~t3_pc~0); 3073#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 3072#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3313#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3083#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3084#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3349#L347-18 assume !(1 == ~t4_pc~0); 3168#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 3167#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3324#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3195#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3028#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3029#L366-18 assume !(1 == ~t5_pc~0); 2986#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 2987#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3191#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3192#L752-18 assume !(0 != activate_threads_~tmp___4~0); 3120#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2991#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2992#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2997#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2998#L656-3 assume !(1 == ~T4_E~0); 3187#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3385#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3370#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3231#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3232#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3278#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3188#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3113#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3061#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2954#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2955#L911 assume !(0 == start_simulation_~tmp~3); 3266#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3351#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2932#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3141#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 3123#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3124#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 3219#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3220#L924 assume !(0 != start_simulation_~tmp___0~1); 3021#L892-1 [2021-10-13 01:04:48,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,659 INFO L82 PathProgramCache]: Analyzing trace with hash 258099357, now seen corresponding path program 1 times [2021-10-13 01:04:48,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,659 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775797697] [2021-10-13 01:04:48,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,702 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,745 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,746 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775797697] [2021-10-13 01:04:48,746 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775797697] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,746 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,746 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,747 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152369876] [2021-10-13 01:04:48,747 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:48,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,748 INFO L82 PathProgramCache]: Analyzing trace with hash -1609268125, now seen corresponding path program 1 times [2021-10-13 01:04:48,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,748 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653481957] [2021-10-13 01:04:48,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,748 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,788 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653481957] [2021-10-13 01:04:48,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653481957] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,788 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337320089] [2021-10-13 01:04:48,789 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:48,789 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:48,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:48,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:48,790 INFO L87 Difference]: Start difference. First operand 480 states and 726 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:48,808 INFO L93 Difference]: Finished difference Result 480 states and 725 transitions. [2021-10-13 01:04:48,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:48,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 725 transitions. [2021-10-13 01:04:48,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 725 transitions. [2021-10-13 01:04:48,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:48,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:48,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 725 transitions. [2021-10-13 01:04:48,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:48,823 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2021-10-13 01:04:48,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 725 transitions. [2021-10-13 01:04:48,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:48,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.5104166666666667) internal successors, (725), 479 states have internal predecessors, (725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 725 transitions. [2021-10-13 01:04:48,836 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2021-10-13 01:04:48,836 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2021-10-13 01:04:48,836 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-13 01:04:48,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 725 transitions. [2021-10-13 01:04:48,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:48,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:48,846 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:48,847 INFO L791 eck$LassoCheckResult]: Stem: 4358#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4344#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4246#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4180#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 4181#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4263#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4264#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4195#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4106#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4107#L418-1 assume !(0 == ~M_E~0); 4334#L578-1 assume !(0 == ~T1_E~0); 4141#L583-1 assume !(0 == ~T2_E~0); 4068#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3998#L593-1 assume !(0 == ~T4_E~0); 3990#L598-1 assume !(0 == ~T5_E~0); 3991#L603-1 assume !(0 == ~E_1~0); 4196#L608-1 assume !(0 == ~E_2~0); 4059#L613-1 assume !(0 == ~E_3~0); 4060#L618-1 assume !(0 == ~E_4~0); 4170#L623-1 assume !(0 == ~E_5~0); 4289#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4340#L271 assume 1 == ~m_pc~0; 3935#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3936#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4208#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4209#L712 assume !(0 != activate_threads_~tmp~1); 4284#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4285#L290 assume 1 == ~t1_pc~0; 4182#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4026#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4191#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4192#L720 assume !(0 != activate_threads_~tmp___0~0); 4262#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4353#L309 assume !(1 == ~t2_pc~0); 4175#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 4174#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4166#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3968#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3969#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4252#L328 assume 1 == ~t3_pc~0; 4341#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4063#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4064#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4128#L736 assume !(0 != activate_threads_~tmp___2~0); 4129#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4348#L347 assume !(1 == ~t4_pc~0); 3970#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 3894#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3895#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4268#L744 assume !(0 != activate_threads_~tmp___3~0); 4269#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4033#L366 assume 1 == ~t5_pc~0; 4034#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4013#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4328#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4299#L752 assume !(0 != activate_threads_~tmp___4~0); 3973#L752-2 assume !(1 == ~M_E~0); 3974#L641-1 assume !(1 == ~T1_E~0); 3987#L646-1 assume !(1 == ~T2_E~0); 4114#L651-1 assume !(1 == ~T3_E~0); 4336#L656-1 assume !(1 == ~T4_E~0); 4294#L661-1 assume !(1 == ~T5_E~0); 4295#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4270#L671-1 assume !(1 == ~E_2~0); 4078#L676-1 assume !(1 == ~E_3~0); 4079#L681-1 assume !(1 == ~E_4~0); 4204#L686-1 assume !(1 == ~E_5~0); 3988#L892-1 [2021-10-13 01:04:48,848 INFO L793 eck$LassoCheckResult]: Loop: 3988#L892-1 assume !false; 3989#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4179#L553 assume !false; 3960#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3961#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4074#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4345#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4069#L478 assume !(0 != eval_~tmp~0); 4070#L568 start_simulation_~kernel_st~0 := 2; 4136#L386-1 start_simulation_~kernel_st~0 := 3; 4055#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4056#L578-4 assume !(0 == ~T1_E~0); 4283#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4339#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4226#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4227#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4319#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4265#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4228#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4229#L618-3 assume !(0 == ~E_4~0); 4274#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3933#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3934#L271-18 assume !(1 == ~m_pc~0); 4023#L271-20 is_master_triggered_~__retres1~0 := 0; 4024#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4351#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4014#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4015#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4267#L290-18 assume 1 == ~t1_pc~0; 4130#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4131#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4150#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4242#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4314#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4163#L309-18 assume 1 == ~t2_pc~0; 4099#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4010#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4011#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4066#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4067#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4350#L328-18 assume 1 == ~t3_pc~0; 4038#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4039#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4280#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4050#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4051#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4316#L347-18 assume 1 == ~t4_pc~0; 4133#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4134#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4291#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4162#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3995#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3996#L366-18 assume !(1 == ~t5_pc~0); 3953#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 3954#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4158#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4159#L752-18 assume !(0 != activate_threads_~tmp___4~0); 4087#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3958#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3959#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3964#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3965#L656-3 assume !(1 == ~T4_E~0); 4154#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4352#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4337#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4198#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4199#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4245#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4155#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4080#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4028#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3921#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3922#L911 assume !(0 == start_simulation_~tmp~3); 4233#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4318#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3899#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4108#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 4090#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4091#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 4186#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4187#L924 assume !(0 != start_simulation_~tmp___0~1); 3988#L892-1 [2021-10-13 01:04:48,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,848 INFO L82 PathProgramCache]: Analyzing trace with hash 56275423, now seen corresponding path program 1 times [2021-10-13 01:04:48,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,849 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399351686] [2021-10-13 01:04:48,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,850 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,910 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399351686] [2021-10-13 01:04:48,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [399351686] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,911 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,911 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,911 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074926646] [2021-10-13 01:04:48,912 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:48,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:48,913 INFO L82 PathProgramCache]: Analyzing trace with hash 2119424801, now seen corresponding path program 2 times [2021-10-13 01:04:48,913 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:48,913 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192079038] [2021-10-13 01:04:48,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:48,914 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:48,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:48,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:48,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:48,960 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192079038] [2021-10-13 01:04:48,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192079038] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:48,962 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:48,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:48,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862427193] [2021-10-13 01:04:48,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:48,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:48,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:48,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:48,965 INFO L87 Difference]: Start difference. First operand 480 states and 725 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:48,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:48,979 INFO L93 Difference]: Finished difference Result 480 states and 724 transitions. [2021-10-13 01:04:48,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:48,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 724 transitions. [2021-10-13 01:04:48,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:48,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 724 transitions. [2021-10-13 01:04:48,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:48,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:48,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 724 transitions. [2021-10-13 01:04:48,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:48,992 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2021-10-13 01:04:48,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 724 transitions. [2021-10-13 01:04:49,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:49,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.5083333333333333) internal successors, (724), 479 states have internal predecessors, (724), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 724 transitions. [2021-10-13 01:04:49,005 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2021-10-13 01:04:49,005 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2021-10-13 01:04:49,005 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-13 01:04:49,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 724 transitions. [2021-10-13 01:04:49,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:49,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:49,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:49,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,011 INFO L791 eck$LassoCheckResult]: Stem: 5325#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5311#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5213#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5147#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 5148#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5230#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5231#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5162#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5073#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5074#L418-1 assume !(0 == ~M_E~0); 5301#L578-1 assume !(0 == ~T1_E~0); 5108#L583-1 assume !(0 == ~T2_E~0); 5035#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4965#L593-1 assume !(0 == ~T4_E~0); 4957#L598-1 assume !(0 == ~T5_E~0); 4958#L603-1 assume !(0 == ~E_1~0); 5163#L608-1 assume !(0 == ~E_2~0); 5026#L613-1 assume !(0 == ~E_3~0); 5027#L618-1 assume !(0 == ~E_4~0); 5137#L623-1 assume !(0 == ~E_5~0); 5256#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5307#L271 assume 1 == ~m_pc~0; 4902#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4903#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5175#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5176#L712 assume !(0 != activate_threads_~tmp~1); 5251#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5252#L290 assume 1 == ~t1_pc~0; 5149#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4993#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5158#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5159#L720 assume !(0 != activate_threads_~tmp___0~0); 5229#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5320#L309 assume !(1 == ~t2_pc~0); 5142#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 5141#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5133#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4935#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4936#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5219#L328 assume 1 == ~t3_pc~0; 5308#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5030#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5031#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5095#L736 assume !(0 != activate_threads_~tmp___2~0); 5096#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5315#L347 assume !(1 == ~t4_pc~0); 4937#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 4861#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4862#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5235#L744 assume !(0 != activate_threads_~tmp___3~0); 5236#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5000#L366 assume 1 == ~t5_pc~0; 5001#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4980#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5295#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5266#L752 assume !(0 != activate_threads_~tmp___4~0); 4940#L752-2 assume !(1 == ~M_E~0); 4941#L641-1 assume !(1 == ~T1_E~0); 4954#L646-1 assume !(1 == ~T2_E~0); 5081#L651-1 assume !(1 == ~T3_E~0); 5303#L656-1 assume !(1 == ~T4_E~0); 5261#L661-1 assume !(1 == ~T5_E~0); 5262#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5237#L671-1 assume !(1 == ~E_2~0); 5045#L676-1 assume !(1 == ~E_3~0); 5046#L681-1 assume !(1 == ~E_4~0); 5171#L686-1 assume !(1 == ~E_5~0); 4955#L892-1 [2021-10-13 01:04:49,012 INFO L793 eck$LassoCheckResult]: Loop: 4955#L892-1 assume !false; 4956#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5146#L553 assume !false; 4927#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4928#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5041#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5312#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5036#L478 assume !(0 != eval_~tmp~0); 5037#L568 start_simulation_~kernel_st~0 := 2; 5103#L386-1 start_simulation_~kernel_st~0 := 3; 5022#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5023#L578-4 assume !(0 == ~T1_E~0); 5250#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5306#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5193#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5194#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5286#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5232#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5195#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5196#L618-3 assume !(0 == ~E_4~0); 5241#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4900#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4901#L271-18 assume 1 == ~m_pc~0; 5296#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4991#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5318#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4981#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4982#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5234#L290-18 assume 1 == ~t1_pc~0; 5097#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5098#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5117#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5209#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5281#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5130#L309-18 assume 1 == ~t2_pc~0; 5066#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4977#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4978#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5033#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5034#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5317#L328-18 assume 1 == ~t3_pc~0; 5005#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5006#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5247#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5017#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5018#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5283#L347-18 assume 1 == ~t4_pc~0; 5100#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5101#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5258#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5129#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4962#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4963#L366-18 assume !(1 == ~t5_pc~0); 4920#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 4921#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5125#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5126#L752-18 assume !(0 != activate_threads_~tmp___4~0); 5054#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4925#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4926#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4931#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4932#L656-3 assume !(1 == ~T4_E~0); 5121#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5319#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5304#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5165#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5166#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5212#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5122#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5047#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4995#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4888#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4889#L911 assume !(0 == start_simulation_~tmp~3); 5200#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5285#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4866#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5075#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 5057#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5058#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 5153#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5154#L924 assume !(0 != start_simulation_~tmp___0~1); 4955#L892-1 [2021-10-13 01:04:49,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,013 INFO L82 PathProgramCache]: Analyzing trace with hash -504424355, now seen corresponding path program 1 times [2021-10-13 01:04:49,013 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,013 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177085341] [2021-10-13 01:04:49,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,014 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,056 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177085341] [2021-10-13 01:04:49,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177085341] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,057 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:04:49,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796788178] [2021-10-13 01:04:49,057 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:49,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,058 INFO L82 PathProgramCache]: Analyzing trace with hash -1144211680, now seen corresponding path program 1 times [2021-10-13 01:04:49,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,058 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047191925] [2021-10-13 01:04:49,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,059 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047191925] [2021-10-13 01:04:49,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047191925] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,091 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,091 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:49,092 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717778886] [2021-10-13 01:04:49,092 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:49,092 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:49,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:49,093 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:49,093 INFO L87 Difference]: Start difference. First operand 480 states and 724 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 2 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:49,112 INFO L93 Difference]: Finished difference Result 480 states and 719 transitions. [2021-10-13 01:04:49,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:49,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 719 transitions. [2021-10-13 01:04:49,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:49,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 719 transitions. [2021-10-13 01:04:49,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-10-13 01:04:49,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-10-13 01:04:49,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 719 transitions. [2021-10-13 01:04:49,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:49,124 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2021-10-13 01:04:49,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 719 transitions. [2021-10-13 01:04:49,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2021-10-13 01:04:49,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 480 states have (on average 1.4979166666666666) internal successors, (719), 479 states have internal predecessors, (719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 719 transitions. [2021-10-13 01:04:49,135 INFO L704 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2021-10-13 01:04:49,135 INFO L587 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2021-10-13 01:04:49,135 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-13 01:04:49,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 719 transitions. [2021-10-13 01:04:49,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2021-10-13 01:04:49,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:49,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:49,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,141 INFO L791 eck$LassoCheckResult]: Stem: 6292#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6278#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6180#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6114#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 6115#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6197#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6198#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6129#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6040#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6041#L418-1 assume !(0 == ~M_E~0); 6268#L578-1 assume !(0 == ~T1_E~0); 6075#L583-1 assume !(0 == ~T2_E~0); 6002#L588-1 assume !(0 == ~T3_E~0); 5932#L593-1 assume !(0 == ~T4_E~0); 5924#L598-1 assume !(0 == ~T5_E~0); 5925#L603-1 assume !(0 == ~E_1~0); 6130#L608-1 assume !(0 == ~E_2~0); 5993#L613-1 assume !(0 == ~E_3~0); 5994#L618-1 assume !(0 == ~E_4~0); 6104#L623-1 assume !(0 == ~E_5~0); 6223#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6274#L271 assume 1 == ~m_pc~0; 5869#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5870#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6142#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6143#L712 assume !(0 != activate_threads_~tmp~1); 6218#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6219#L290 assume 1 == ~t1_pc~0; 6116#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5960#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6125#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6126#L720 assume !(0 != activate_threads_~tmp___0~0); 6196#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6287#L309 assume !(1 == ~t2_pc~0); 6109#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 6108#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6100#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5902#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5903#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6186#L328 assume 1 == ~t3_pc~0; 6275#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5997#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5998#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6062#L736 assume !(0 != activate_threads_~tmp___2~0); 6063#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6282#L347 assume !(1 == ~t4_pc~0); 5904#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 5828#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5829#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6202#L744 assume !(0 != activate_threads_~tmp___3~0); 6203#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5967#L366 assume 1 == ~t5_pc~0; 5968#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5947#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6262#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6233#L752 assume !(0 != activate_threads_~tmp___4~0); 5907#L752-2 assume !(1 == ~M_E~0); 5908#L641-1 assume !(1 == ~T1_E~0); 5921#L646-1 assume !(1 == ~T2_E~0); 6048#L651-1 assume !(1 == ~T3_E~0); 6270#L656-1 assume !(1 == ~T4_E~0); 6228#L661-1 assume !(1 == ~T5_E~0); 6229#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6204#L671-1 assume !(1 == ~E_2~0); 6012#L676-1 assume !(1 == ~E_3~0); 6013#L681-1 assume !(1 == ~E_4~0); 6138#L686-1 assume !(1 == ~E_5~0); 5922#L892-1 [2021-10-13 01:04:49,141 INFO L793 eck$LassoCheckResult]: Loop: 5922#L892-1 assume !false; 5923#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6113#L553 assume !false; 5894#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5895#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6008#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6279#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6003#L478 assume !(0 != eval_~tmp~0); 6004#L568 start_simulation_~kernel_st~0 := 2; 6070#L386-1 start_simulation_~kernel_st~0 := 3; 5989#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5990#L578-4 assume !(0 == ~T1_E~0); 6217#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6273#L588-3 assume !(0 == ~T3_E~0); 6160#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6161#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6253#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6199#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6162#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6163#L618-3 assume !(0 == ~E_4~0); 6208#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5867#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5868#L271-18 assume !(1 == ~m_pc~0); 5957#L271-20 is_master_triggered_~__retres1~0 := 0; 5958#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6285#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5948#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5949#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6201#L290-18 assume 1 == ~t1_pc~0; 6064#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6065#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6084#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6176#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6248#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6097#L309-18 assume 1 == ~t2_pc~0; 6033#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5944#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5945#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6000#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6001#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6284#L328-18 assume 1 == ~t3_pc~0; 5972#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5973#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6214#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5984#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5985#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6250#L347-18 assume 1 == ~t4_pc~0; 6067#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6068#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6225#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6096#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5929#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5930#L366-18 assume 1 == ~t5_pc~0; 6016#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5888#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6092#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6093#L752-18 assume !(0 != activate_threads_~tmp___4~0); 6021#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5892#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5893#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5898#L651-3 assume !(1 == ~T3_E~0); 5899#L656-3 assume !(1 == ~T4_E~0); 6088#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6286#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6271#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6132#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6133#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6179#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6089#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6014#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5962#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5855#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5856#L911 assume !(0 == start_simulation_~tmp~3); 6167#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6252#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5833#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6042#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 6024#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6025#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 6120#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 6121#L924 assume !(0 != start_simulation_~tmp___0~1); 5922#L892-1 [2021-10-13 01:04:49,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,142 INFO L82 PathProgramCache]: Analyzing trace with hash 882361055, now seen corresponding path program 1 times [2021-10-13 01:04:49,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943124030] [2021-10-13 01:04:49,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,143 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,171 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,171 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943124030] [2021-10-13 01:04:49,171 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943124030] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,172 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:04:49,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238508322] [2021-10-13 01:04:49,172 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:49,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,173 INFO L82 PathProgramCache]: Analyzing trace with hash 172774176, now seen corresponding path program 1 times [2021-10-13 01:04:49,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,173 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142802014] [2021-10-13 01:04:49,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,174 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,200 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,200 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142802014] [2021-10-13 01:04:49,201 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142802014] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,201 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,201 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:49,201 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2147210299] [2021-10-13 01:04:49,202 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:49,202 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:49,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:49,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:49,203 INFO L87 Difference]: Start difference. First operand 480 states and 719 transitions. cyclomatic complexity: 240 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 2 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:49,257 INFO L93 Difference]: Finished difference Result 878 states and 1299 transitions. [2021-10-13 01:04:49,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:49,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 878 states and 1299 transitions. [2021-10-13 01:04:49,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 805 [2021-10-13 01:04:49,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 878 states to 878 states and 1299 transitions. [2021-10-13 01:04:49,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 878 [2021-10-13 01:04:49,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 878 [2021-10-13 01:04:49,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 878 states and 1299 transitions. [2021-10-13 01:04:49,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:49,277 INFO L681 BuchiCegarLoop]: Abstraction has 878 states and 1299 transitions. [2021-10-13 01:04:49,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 878 states and 1299 transitions. [2021-10-13 01:04:49,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 878 to 836. [2021-10-13 01:04:49,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 836 states, 836 states have (on average 1.4844497607655502) internal successors, (1241), 835 states have internal predecessors, (1241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 836 states to 836 states and 1241 transitions. [2021-10-13 01:04:49,301 INFO L704 BuchiCegarLoop]: Abstraction has 836 states and 1241 transitions. [2021-10-13 01:04:49,301 INFO L587 BuchiCegarLoop]: Abstraction has 836 states and 1241 transitions. [2021-10-13 01:04:49,301 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-13 01:04:49,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 836 states and 1241 transitions. [2021-10-13 01:04:49,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 763 [2021-10-13 01:04:49,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:49,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:49,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,309 INFO L791 eck$LassoCheckResult]: Stem: 7669#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 7648#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7547#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7476#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 7477#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7564#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7565#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7491#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7403#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7404#L418-1 assume !(0 == ~M_E~0); 7636#L578-1 assume !(0 == ~T1_E~0); 7437#L583-1 assume !(0 == ~T2_E~0); 7366#L588-1 assume !(0 == ~T3_E~0); 7296#L593-1 assume !(0 == ~T4_E~0); 7288#L598-1 assume !(0 == ~T5_E~0); 7289#L603-1 assume !(0 == ~E_1~0); 7492#L608-1 assume !(0 == ~E_2~0); 7357#L613-1 assume !(0 == ~E_3~0); 7358#L618-1 assume !(0 == ~E_4~0); 7466#L623-1 assume !(0 == ~E_5~0); 7590#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7643#L271 assume !(1 == ~m_pc~0); 7609#L271-2 is_master_triggered_~__retres1~0 := 0; 7610#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7504#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7505#L712 assume !(0 != activate_threads_~tmp~1); 7585#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7586#L290 assume 1 == ~t1_pc~0; 7478#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7324#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7487#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7488#L720 assume !(0 != activate_threads_~tmp___0~0); 7563#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7662#L309 assume !(1 == ~t2_pc~0); 7471#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 7470#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7462#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7265#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7266#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7553#L328 assume 1 == ~t3_pc~0; 7644#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7361#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7362#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7424#L736 assume !(0 != activate_threads_~tmp___2~0); 7425#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7656#L347 assume !(1 == ~t4_pc~0); 7267#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 7193#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7194#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7569#L744 assume !(0 != activate_threads_~tmp___3~0); 7570#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7331#L366 assume 1 == ~t5_pc~0; 7332#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7311#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7630#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7600#L752 assume !(0 != activate_threads_~tmp___4~0); 7270#L752-2 assume !(1 == ~M_E~0); 7271#L641-1 assume !(1 == ~T1_E~0); 7285#L646-1 assume !(1 == ~T2_E~0); 7411#L651-1 assume !(1 == ~T3_E~0); 7639#L656-1 assume !(1 == ~T4_E~0); 7595#L661-1 assume !(1 == ~T5_E~0); 7596#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7571#L671-1 assume !(1 == ~E_2~0); 7375#L676-1 assume !(1 == ~E_3~0); 7376#L681-1 assume !(1 == ~E_4~0); 7500#L686-1 assume !(1 == ~E_5~0); 7286#L892-1 [2021-10-13 01:04:49,309 INFO L793 eck$LassoCheckResult]: Loop: 7286#L892-1 assume !false; 7287#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7475#L553 assume !false; 7257#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7258#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7371#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7649#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7367#L478 assume !(0 != eval_~tmp~0); 7368#L568 start_simulation_~kernel_st~0 := 2; 7432#L386-1 start_simulation_~kernel_st~0 := 3; 7353#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7354#L578-4 assume !(0 == ~T1_E~0); 7584#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7642#L588-3 assume !(0 == ~T3_E~0); 7522#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7523#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7621#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7566#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7524#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7525#L618-3 assume !(0 == ~E_4~0); 7575#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7233#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7234#L271-18 assume !(1 == ~m_pc~0); 7321#L271-20 is_master_triggered_~__retres1~0 := 0; 7322#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7659#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7312#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7313#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7568#L290-18 assume 1 == ~t1_pc~0; 7426#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7427#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7446#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7540#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7616#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7459#L309-18 assume 1 == ~t2_pc~0; 7396#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7308#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7309#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7364#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7365#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7658#L328-18 assume 1 == ~t3_pc~0; 7336#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7337#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7581#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7348#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7349#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7618#L347-18 assume 1 == ~t4_pc~0; 7429#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7430#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7592#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7458#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7293#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7294#L366-18 assume !(1 == ~t5_pc~0); 7250#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 7251#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7454#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7455#L752-18 assume !(0 != activate_threads_~tmp___4~0); 7384#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7255#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7256#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7261#L651-3 assume !(1 == ~T3_E~0); 7262#L656-3 assume !(1 == ~T4_E~0); 7450#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7660#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7640#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7494#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7495#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7546#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7451#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7377#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7326#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7221#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7222#L911 assume !(0 == start_simulation_~tmp~3); 7529#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7620#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7198#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7405#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 7387#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7388#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 7482#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7483#L924 assume !(0 != start_simulation_~tmp___0~1); 7286#L892-1 [2021-10-13 01:04:49,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,309 INFO L82 PathProgramCache]: Analyzing trace with hash -425643714, now seen corresponding path program 1 times [2021-10-13 01:04:49,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,310 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139196256] [2021-10-13 01:04:49,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,310 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,352 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139196256] [2021-10-13 01:04:49,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139196256] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,353 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:49,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174093555] [2021-10-13 01:04:49,353 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:49,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,354 INFO L82 PathProgramCache]: Analyzing trace with hash -798900511, now seen corresponding path program 1 times [2021-10-13 01:04:49,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,354 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895528129] [2021-10-13 01:04:49,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,355 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,406 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,408 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895528129] [2021-10-13 01:04:49,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895528129] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,414 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,414 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:49,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349963431] [2021-10-13 01:04:49,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:49,415 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:49,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:04:49,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:04:49,416 INFO L87 Difference]: Start difference. First operand 836 states and 1241 transitions. cyclomatic complexity: 407 Second operand has 4 states, 4 states have (on average 16.75) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:49,586 INFO L93 Difference]: Finished difference Result 1920 states and 2814 transitions. [2021-10-13 01:04:49,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:04:49,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2814 transitions. [2021-10-13 01:04:49,605 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1798 [2021-10-13 01:04:49,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1920 states and 2814 transitions. [2021-10-13 01:04:49,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1920 [2021-10-13 01:04:49,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1920 [2021-10-13 01:04:49,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1920 states and 2814 transitions. [2021-10-13 01:04:49,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:49,629 INFO L681 BuchiCegarLoop]: Abstraction has 1920 states and 2814 transitions. [2021-10-13 01:04:49,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1920 states and 2814 transitions. [2021-10-13 01:04:49,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1920 to 1499. [2021-10-13 01:04:49,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1499 states, 1499 states have (on average 1.475650433622415) internal successors, (2212), 1498 states have internal predecessors, (2212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2212 transitions. [2021-10-13 01:04:49,671 INFO L704 BuchiCegarLoop]: Abstraction has 1499 states and 2212 transitions. [2021-10-13 01:04:49,671 INFO L587 BuchiCegarLoop]: Abstraction has 1499 states and 2212 transitions. [2021-10-13 01:04:49,672 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-13 01:04:49,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2212 transitions. [2021-10-13 01:04:49,683 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1426 [2021-10-13 01:04:49,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:49,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:49,685 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,685 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:49,685 INFO L791 eck$LassoCheckResult]: Stem: 10454#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 10430#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 10313#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10243#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 10244#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10331#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10332#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10260#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10170#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10171#L418-1 assume !(0 == ~M_E~0); 10414#L578-1 assume !(0 == ~T1_E~0); 10203#L583-1 assume !(0 == ~T2_E~0); 10132#L588-1 assume !(0 == ~T3_E~0); 10061#L593-1 assume !(0 == ~T4_E~0); 10053#L598-1 assume !(0 == ~T5_E~0); 10054#L603-1 assume !(0 == ~E_1~0); 10261#L608-1 assume !(0 == ~E_2~0); 10123#L613-1 assume !(0 == ~E_3~0); 10124#L618-1 assume !(0 == ~E_4~0); 10233#L623-1 assume !(0 == ~E_5~0); 10363#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10425#L271 assume !(1 == ~m_pc~0); 10385#L271-2 is_master_triggered_~__retres1~0 := 0; 10386#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10271#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10272#L712 assume !(0 != activate_threads_~tmp~1); 10357#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10358#L290 assume !(1 == ~t1_pc~0); 10092#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 10093#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10253#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10254#L720 assume !(0 != activate_threads_~tmp___0~0); 10329#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10444#L309 assume !(1 == ~t2_pc~0); 10239#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 10238#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10232#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10031#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10032#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10320#L328 assume 1 == ~t3_pc~0; 10426#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10128#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10129#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10196#L736 assume !(0 != activate_threads_~tmp___2~0); 10197#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10438#L347 assume !(1 == ~t4_pc~0); 10033#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 9959#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9960#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10335#L744 assume !(0 != activate_threads_~tmp___3~0); 10336#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10099#L366 assume 1 == ~t5_pc~0; 10100#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10078#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10408#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10375#L752 assume !(0 != activate_threads_~tmp___4~0); 10036#L752-2 assume !(1 == ~M_E~0); 10037#L641-1 assume !(1 == ~T1_E~0); 10050#L646-1 assume !(1 == ~T2_E~0); 10180#L651-1 assume !(1 == ~T3_E~0); 10419#L656-1 assume !(1 == ~T4_E~0); 10370#L661-1 assume !(1 == ~T5_E~0); 10371#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10337#L671-1 assume !(1 == ~E_2~0); 10141#L676-1 assume !(1 == ~E_3~0); 10142#L681-1 assume !(1 == ~E_4~0); 10269#L686-1 assume !(1 == ~E_5~0); 10051#L892-1 [2021-10-13 01:04:49,685 INFO L793 eck$LassoCheckResult]: Loop: 10051#L892-1 assume !false; 10052#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10242#L553 assume !false; 10023#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10024#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10137#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10429#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 10133#L478 assume !(0 != eval_~tmp~0); 10134#L568 start_simulation_~kernel_st~0 := 2; 10198#L386-1 start_simulation_~kernel_st~0 := 3; 10119#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10120#L578-4 assume !(0 == ~T1_E~0); 10353#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10423#L588-3 assume !(0 == ~T3_E~0); 10291#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10292#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10396#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10330#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10293#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10294#L618-3 assume !(0 == ~E_4~0); 10342#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9999#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10000#L271-18 assume !(1 == ~m_pc~0); 10086#L271-20 is_master_triggered_~__retres1~0 := 0; 10087#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10441#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10075#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10076#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10334#L290-18 assume !(1 == ~t1_pc~0); 10356#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 10209#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10210#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10309#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10391#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10225#L309-18 assume 1 == ~t2_pc~0; 10162#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10073#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10074#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10130#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10131#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10440#L328-18 assume 1 == ~t3_pc~0; 10102#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10103#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10350#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10114#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10115#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10393#L347-18 assume 1 == ~t4_pc~0; 10193#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10194#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10364#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10224#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10058#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10059#L366-18 assume !(1 == ~t5_pc~0); 10016#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 10017#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10220#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10221#L752-18 assume !(0 != activate_threads_~tmp___4~0); 10150#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 10021#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10022#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10027#L651-3 assume !(1 == ~T3_E~0); 10028#L656-3 assume !(1 == ~T4_E~0); 10216#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10442#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10421#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10258#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10259#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10312#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10217#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10143#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10090#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9987#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 9988#L911 assume !(0 == start_simulation_~tmp~3); 10298#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10395#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9964#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10169#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 10153#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10154#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 10248#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 10249#L924 assume !(0 != start_simulation_~tmp___0~1); 10051#L892-1 [2021-10-13 01:04:49,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,686 INFO L82 PathProgramCache]: Analyzing trace with hash -25652515, now seen corresponding path program 1 times [2021-10-13 01:04:49,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,686 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563644165] [2021-10-13 01:04:49,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,686 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,740 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563644165] [2021-10-13 01:04:49,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563644165] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,741 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,741 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:04:49,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169639034] [2021-10-13 01:04:49,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:49,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:49,742 INFO L82 PathProgramCache]: Analyzing trace with hash -1072679006, now seen corresponding path program 1 times [2021-10-13 01:04:49,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:49,742 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204477160] [2021-10-13 01:04:49,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:49,743 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:49,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:49,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:49,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:49,767 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204477160] [2021-10-13 01:04:49,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204477160] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:49,767 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:49,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:49,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13300769] [2021-10-13 01:04:49,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:49,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:49,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:04:49,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:04:49,769 INFO L87 Difference]: Start difference. First operand 1499 states and 2212 transitions. cyclomatic complexity: 715 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:49,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:49,960 INFO L93 Difference]: Finished difference Result 3890 states and 5753 transitions. [2021-10-13 01:04:49,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:04:49,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3890 states and 5753 transitions. [2021-10-13 01:04:49,996 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3746 [2021-10-13 01:04:50,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3890 states to 3890 states and 5753 transitions. [2021-10-13 01:04:50,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3890 [2021-10-13 01:04:50,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3890 [2021-10-13 01:04:50,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3890 states and 5753 transitions. [2021-10-13 01:04:50,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:50,043 INFO L681 BuchiCegarLoop]: Abstraction has 3890 states and 5753 transitions. [2021-10-13 01:04:50,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3890 states and 5753 transitions. [2021-10-13 01:04:50,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3890 to 1574. [2021-10-13 01:04:50,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1574 states, 1574 states have (on average 1.4529860228716645) internal successors, (2287), 1573 states have internal predecessors, (2287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:50,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1574 states to 1574 states and 2287 transitions. [2021-10-13 01:04:50,088 INFO L704 BuchiCegarLoop]: Abstraction has 1574 states and 2287 transitions. [2021-10-13 01:04:50,088 INFO L587 BuchiCegarLoop]: Abstraction has 1574 states and 2287 transitions. [2021-10-13 01:04:50,088 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-13 01:04:50,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1574 states and 2287 transitions. [2021-10-13 01:04:50,098 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1498 [2021-10-13 01:04:50,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:50,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:50,099 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:50,099 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:50,099 INFO L791 eck$LassoCheckResult]: Stem: 15881#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15850#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15729#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15651#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 15652#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15748#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15749#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15667#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15574#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15575#L418-1 assume !(0 == ~M_E~0); 15837#L578-1 assume !(0 == ~T1_E~0); 15610#L583-1 assume !(0 == ~T2_E~0); 15535#L588-1 assume !(0 == ~T3_E~0); 15464#L593-1 assume !(0 == ~T4_E~0); 15456#L598-1 assume !(0 == ~T5_E~0); 15457#L603-1 assume !(0 == ~E_1~0); 15668#L608-1 assume !(0 == ~E_2~0); 15526#L613-1 assume !(0 == ~E_3~0); 15527#L618-1 assume !(0 == ~E_4~0); 15641#L623-1 assume !(0 == ~E_5~0); 15778#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15846#L271 assume !(1 == ~m_pc~0); 15800#L271-2 is_master_triggered_~__retres1~0 := 0; 15801#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15680#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15681#L712 assume !(0 != activate_threads_~tmp~1); 15773#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15774#L290 assume !(1 == ~t1_pc~0); 15491#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 15492#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15662#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15663#L720 assume !(0 != activate_threads_~tmp___0~0); 15747#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15866#L309 assume !(1 == ~t2_pc~0); 15646#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 15803#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15804#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15434#L728 assume !(0 != activate_threads_~tmp___1~0); 15435#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15737#L328 assume 1 == ~t3_pc~0; 15847#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15530#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15531#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15595#L736 assume !(0 != activate_threads_~tmp___2~0); 15596#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15854#L347 assume !(1 == ~t4_pc~0); 15436#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 15361#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15362#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15753#L744 assume !(0 != activate_threads_~tmp___3~0); 15754#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15499#L366 assume 1 == ~t5_pc~0; 15500#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15479#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15829#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15790#L752 assume !(0 != activate_threads_~tmp___4~0); 15439#L752-2 assume !(1 == ~M_E~0); 15440#L641-1 assume !(1 == ~T1_E~0); 15453#L646-1 assume !(1 == ~T2_E~0); 15582#L651-1 assume !(1 == ~T3_E~0); 15839#L656-1 assume !(1 == ~T4_E~0); 15785#L661-1 assume !(1 == ~T5_E~0); 15786#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15755#L671-1 assume !(1 == ~E_2~0); 15545#L676-1 assume !(1 == ~E_3~0); 15546#L681-1 assume !(1 == ~E_4~0); 15676#L686-1 assume !(1 == ~E_5~0); 15454#L892-1 [2021-10-13 01:04:50,100 INFO L793 eck$LassoCheckResult]: Loop: 15454#L892-1 assume !false; 15455#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 15650#L553 assume !false; 15426#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15427#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15540#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15851#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15536#L478 assume !(0 != eval_~tmp~0); 15537#L568 start_simulation_~kernel_st~0 := 2; 15712#L386-1 start_simulation_~kernel_st~0 := 3; 15522#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15523#L578-4 assume !(0 == ~T1_E~0); 15771#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15843#L588-3 assume !(0 == ~T3_E~0); 15700#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15701#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15818#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15831#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16803#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16802#L618-3 assume !(0 == ~E_4~0); 16801#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16800#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16799#L271-18 assume !(1 == ~m_pc~0); 16798#L271-20 is_master_triggered_~__retres1~0 := 0; 16797#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16796#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16794#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16792#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16790#L290-18 assume !(1 == ~t1_pc~0); 16325#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 16787#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16785#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16784#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16783#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16782#L309-18 assume 1 == ~t2_pc~0; 16780#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16778#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16776#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16774#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16773#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16772#L328-18 assume 1 == ~t3_pc~0; 16770#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16769#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16768#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16767#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16766#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16765#L347-18 assume !(1 == ~t4_pc~0); 16763#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 16728#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16635#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15632#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15461#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15462#L366-18 assume !(1 == ~t5_pc~0); 15419#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 15420#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15628#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15629#L752-18 assume !(0 != activate_threads_~tmp___4~0); 15554#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 15424#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15425#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15430#L651-3 assume !(1 == ~T3_E~0); 15431#L656-3 assume !(1 == ~T4_E~0); 15624#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15860#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15840#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15670#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15671#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15728#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15625#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15547#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15494#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15389#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 15390#L911 assume !(0 == start_simulation_~tmp~3); 15707#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15816#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15366#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15576#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 15557#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15558#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 15657#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 15658#L924 assume !(0 != start_simulation_~tmp___0~1); 15454#L892-1 [2021-10-13 01:04:50,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:50,100 INFO L82 PathProgramCache]: Analyzing trace with hash -3020261, now seen corresponding path program 1 times [2021-10-13 01:04:50,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:50,100 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882767738] [2021-10-13 01:04:50,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:50,101 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:50,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:50,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:50,138 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:50,139 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882767738] [2021-10-13 01:04:50,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882767738] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:50,139 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:50,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:50,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128887773] [2021-10-13 01:04:50,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:50,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:50,141 INFO L82 PathProgramCache]: Analyzing trace with hash -21229917, now seen corresponding path program 1 times [2021-10-13 01:04:50,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:50,141 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279057831] [2021-10-13 01:04:50,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:50,141 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:50,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:50,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:50,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:50,172 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279057831] [2021-10-13 01:04:50,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1279057831] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:50,177 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:50,178 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:50,178 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489357685] [2021-10-13 01:04:50,178 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:50,178 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:50,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:04:50,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:04:50,179 INFO L87 Difference]: Start difference. First operand 1574 states and 2287 transitions. cyclomatic complexity: 715 Second operand has 4 states, 4 states have (on average 16.75) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:50,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:50,352 INFO L93 Difference]: Finished difference Result 3636 states and 5230 transitions. [2021-10-13 01:04:50,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:04:50,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3636 states and 5230 transitions. [2021-10-13 01:04:50,383 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3456 [2021-10-13 01:04:50,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3636 states to 3636 states and 5230 transitions. [2021-10-13 01:04:50,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3636 [2021-10-13 01:04:50,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3636 [2021-10-13 01:04:50,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3636 states and 5230 transitions. [2021-10-13 01:04:50,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:50,424 INFO L681 BuchiCegarLoop]: Abstraction has 3636 states and 5230 transitions. [2021-10-13 01:04:50,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3636 states and 5230 transitions. [2021-10-13 01:04:50,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3636 to 2865. [2021-10-13 01:04:50,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2865 states, 2865 states have (on average 1.4471204188481674) internal successors, (4146), 2864 states have internal predecessors, (4146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:50,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2865 states to 2865 states and 4146 transitions. [2021-10-13 01:04:50,495 INFO L704 BuchiCegarLoop]: Abstraction has 2865 states and 4146 transitions. [2021-10-13 01:04:50,495 INFO L587 BuchiCegarLoop]: Abstraction has 2865 states and 4146 transitions. [2021-10-13 01:04:50,495 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-13 01:04:50,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2865 states and 4146 transitions. [2021-10-13 01:04:50,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2788 [2021-10-13 01:04:50,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:50,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:50,511 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:50,511 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:50,512 INFO L791 eck$LassoCheckResult]: Stem: 21114#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 21074#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 20950#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20873#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 20874#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20969#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20970#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20888#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20793#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20794#L418-1 assume !(0 == ~M_E~0); 21058#L578-1 assume !(0 == ~T1_E~0); 20831#L583-1 assume !(0 == ~T2_E~0); 20755#L588-1 assume !(0 == ~T3_E~0); 20685#L593-1 assume !(0 == ~T4_E~0); 20676#L598-1 assume !(0 == ~T5_E~0); 20677#L603-1 assume !(0 == ~E_1~0); 20889#L608-1 assume !(0 == ~E_2~0); 20746#L613-1 assume !(0 == ~E_3~0); 20747#L618-1 assume !(0 == ~E_4~0); 20861#L623-1 assume !(0 == ~E_5~0); 21001#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21070#L271 assume !(1 == ~m_pc~0); 21025#L271-2 is_master_triggered_~__retres1~0 := 0; 21026#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20902#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20903#L712 assume !(0 != activate_threads_~tmp~1); 20996#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20997#L290 assume !(1 == ~t1_pc~0); 20713#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 20714#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20884#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20885#L720 assume !(0 != activate_threads_~tmp___0~0); 20968#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21095#L309 assume !(1 == ~t2_pc~0); 20867#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 21124#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21125#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20652#L728 assume !(0 != activate_threads_~tmp___1~0); 20653#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20957#L328 assume !(1 == ~t3_pc~0); 21014#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 20750#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20751#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20814#L736 assume !(0 != activate_threads_~tmp___2~0); 20815#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21083#L347 assume !(1 == ~t4_pc~0); 20654#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 20580#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20581#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20974#L744 assume !(0 != activate_threads_~tmp___3~0); 20975#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20721#L366 assume 1 == ~t5_pc~0; 20722#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20700#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21050#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21015#L752 assume !(0 != activate_threads_~tmp___4~0); 20657#L752-2 assume !(1 == ~M_E~0); 20658#L641-1 assume !(1 == ~T1_E~0); 20673#L646-1 assume !(1 == ~T2_E~0); 20802#L651-1 assume !(1 == ~T3_E~0); 21064#L656-1 assume !(1 == ~T4_E~0); 21010#L661-1 assume !(1 == ~T5_E~0); 21011#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20976#L671-1 assume !(1 == ~E_2~0); 20764#L676-1 assume !(1 == ~E_3~0); 20765#L681-1 assume !(1 == ~E_4~0); 20897#L686-1 assume !(1 == ~E_5~0); 20898#L892-1 [2021-10-13 01:04:50,512 INFO L793 eck$LassoCheckResult]: Loop: 20898#L892-1 assume !false; 22743#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 22739#L553 assume !false; 20644#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 20645#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 20760#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 21075#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 20756#L478 assume !(0 != eval_~tmp~0); 20757#L568 start_simulation_~kernel_st~0 := 2; 20823#L386-1 start_simulation_~kernel_st~0 := 3; 20742#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20743#L578-4 assume !(0 == ~T1_E~0); 20995#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21068#L588-3 assume !(0 == ~T3_E~0); 20920#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20921#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21040#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21052#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23331#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23330#L618-3 assume !(0 == ~E_4~0); 23329#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23327#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23325#L271-18 assume !(1 == ~m_pc~0); 23323#L271-20 is_master_triggered_~__retres1~0 := 0; 23321#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23318#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23316#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23314#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21119#L290-18 assume !(1 == ~t1_pc~0); 21120#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 22890#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22888#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22886#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22884#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22879#L309-18 assume 1 == ~t2_pc~0; 22880#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22881#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22895#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22869#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22867#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22865#L328-18 assume !(1 == ~t3_pc~0); 21266#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 22861#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22859#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22857#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22855#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22853#L347-18 assume !(1 == ~t4_pc~0); 22850#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 22848#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22846#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22844#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22842#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22840#L366-18 assume 1 == ~t5_pc~0; 22837#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22835#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22834#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22833#L752-18 assume !(0 != activate_threads_~tmp___4~0); 22831#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 22830#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22829#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22828#L651-3 assume !(1 == ~T3_E~0); 22827#L656-3 assume !(1 == ~T4_E~0); 22826#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22824#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22822#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22820#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22818#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22817#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22813#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22808#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22801#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22799#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22796#L911 assume !(0 == start_simulation_~tmp~3); 22794#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22785#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22780#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22778#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 22776#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22774#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 22772#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 22770#L924 assume !(0 != start_simulation_~tmp___0~1); 20898#L892-1 [2021-10-13 01:04:50,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:50,512 INFO L82 PathProgramCache]: Analyzing trace with hash -311459270, now seen corresponding path program 1 times [2021-10-13 01:04:50,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:50,513 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529119567] [2021-10-13 01:04:50,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:50,513 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:50,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:50,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:50,548 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:50,548 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529119567] [2021-10-13 01:04:50,548 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529119567] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:50,548 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:50,548 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:50,548 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068296991] [2021-10-13 01:04:50,549 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:50,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:50,549 INFO L82 PathProgramCache]: Analyzing trace with hash 465270051, now seen corresponding path program 1 times [2021-10-13 01:04:50,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:50,550 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380231665] [2021-10-13 01:04:50,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:50,550 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:50,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:50,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:50,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:50,589 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380231665] [2021-10-13 01:04:50,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380231665] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:50,589 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:50,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:50,590 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264876119] [2021-10-13 01:04:50,590 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:50,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:50,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-13 01:04:50,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-13 01:04:50,591 INFO L87 Difference]: Start difference. First operand 2865 states and 4146 transitions. cyclomatic complexity: 1283 Second operand has 4 states, 4 states have (on average 16.75) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:50,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:50,757 INFO L93 Difference]: Finished difference Result 7042 states and 10057 transitions. [2021-10-13 01:04:50,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-13 01:04:50,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7042 states and 10057 transitions. [2021-10-13 01:04:50,814 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6758 [2021-10-13 01:04:50,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7042 states to 7042 states and 10057 transitions. [2021-10-13 01:04:50,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7042 [2021-10-13 01:04:50,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7042 [2021-10-13 01:04:50,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7042 states and 10057 transitions. [2021-10-13 01:04:50,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:50,892 INFO L681 BuchiCegarLoop]: Abstraction has 7042 states and 10057 transitions. [2021-10-13 01:04:50,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7042 states and 10057 transitions. [2021-10-13 01:04:51,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7042 to 5580. [2021-10-13 01:04:51,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5580 states, 5580 states have (on average 1.435663082437276) internal successors, (8011), 5579 states have internal predecessors, (8011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:51,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 8011 transitions. [2021-10-13 01:04:51,061 INFO L704 BuchiCegarLoop]: Abstraction has 5580 states and 8011 transitions. [2021-10-13 01:04:51,061 INFO L587 BuchiCegarLoop]: Abstraction has 5580 states and 8011 transitions. [2021-10-13 01:04:51,061 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-13 01:04:51,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 8011 transitions. [2021-10-13 01:04:51,086 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2021-10-13 01:04:51,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:51,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:51,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:51,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:51,088 INFO L791 eck$LassoCheckResult]: Stem: 31033#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 30994#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30863#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30788#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 30789#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30882#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30883#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30802#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30712#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30713#L418-1 assume !(0 == ~M_E~0); 30980#L578-1 assume !(0 == ~T1_E~0); 30750#L583-1 assume !(0 == ~T2_E~0); 30672#L588-1 assume !(0 == ~T3_E~0); 30601#L593-1 assume !(0 == ~T4_E~0); 30592#L598-1 assume !(0 == ~T5_E~0); 30593#L603-1 assume !(0 == ~E_1~0); 30803#L608-1 assume !(0 == ~E_2~0); 30663#L613-1 assume !(0 == ~E_3~0); 30664#L618-1 assume !(0 == ~E_4~0); 30778#L623-1 assume !(0 == ~E_5~0); 30919#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30991#L271 assume !(1 == ~m_pc~0); 30942#L271-2 is_master_triggered_~__retres1~0 := 0; 30943#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30816#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30817#L712 assume !(0 != activate_threads_~tmp~1); 30914#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30915#L290 assume !(1 == ~t1_pc~0); 30629#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 30630#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30798#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30799#L720 assume !(0 != activate_threads_~tmp___0~0); 30881#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31015#L309 assume !(1 == ~t2_pc~0); 30783#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 30945#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30775#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30569#L728 assume !(0 != activate_threads_~tmp___1~0); 30570#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30871#L328 assume !(1 == ~t3_pc~0); 30930#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 30667#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30668#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30733#L736 assume !(0 != activate_threads_~tmp___2~0); 30734#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31002#L347 assume !(1 == ~t4_pc~0); 30571#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 30497#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30498#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30889#L744 assume !(0 != activate_threads_~tmp___3~0); 30890#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30637#L366 assume !(1 == ~t5_pc~0); 30615#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 30616#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30973#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30931#L752 assume !(0 != activate_threads_~tmp___4~0); 30574#L752-2 assume !(1 == ~M_E~0); 30575#L641-1 assume !(1 == ~T1_E~0); 30589#L646-1 assume !(1 == ~T2_E~0); 30720#L651-1 assume !(1 == ~T3_E~0); 30986#L656-1 assume !(1 == ~T4_E~0); 30926#L661-1 assume !(1 == ~T5_E~0); 30927#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30891#L671-1 assume !(1 == ~E_2~0); 30681#L676-1 assume !(1 == ~E_3~0); 30682#L681-1 assume !(1 == ~E_4~0); 30812#L686-1 assume !(1 == ~E_5~0); 30590#L892-1 [2021-10-13 01:04:51,089 INFO L793 eck$LassoCheckResult]: Loop: 30590#L892-1 assume !false; 30591#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 30787#L553 assume !false; 30561#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 30562#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 30677#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 30995#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30673#L478 assume !(0 != eval_~tmp~0); 30674#L568 start_simulation_~kernel_st~0 := 2; 30742#L386-1 start_simulation_~kernel_st~0 := 3; 30658#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30659#L578-4 assume !(0 == ~T1_E~0); 30913#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30990#L588-3 assume !(0 == ~T3_E~0); 30834#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30835#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30963#L603-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30884#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30836#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30837#L618-3 assume !(0 == ~E_4~0); 30896#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35988#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35987#L271-18 assume !(1 == ~m_pc~0); 35986#L271-20 is_master_triggered_~__retres1~0 := 0; 35985#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35983#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35982#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35981#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31039#L290-18 assume !(1 == ~t1_pc~0); 31040#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 35803#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35802#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35801#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35800#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35799#L309-18 assume !(1 == ~t2_pc~0); 35797#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 35795#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35793#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35792#L728-18 assume !(0 != activate_threads_~tmp___1~0); 35790#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31005#L328-18 assume !(1 == ~t3_pc~0); 30981#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 30909#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30910#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30653#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30654#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30959#L347-18 assume 1 == ~t4_pc~0; 30738#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 30739#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30921#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30771#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30597#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30598#L366-18 assume !(1 == ~t5_pc~0); 30554#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 30555#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30767#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30768#L752-18 assume !(0 != activate_threads_~tmp___4~0); 30692#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 30559#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30560#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30565#L651-3 assume !(1 == ~T3_E~0); 30566#L656-3 assume !(1 == ~T4_E~0); 30762#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31010#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30988#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30805#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30806#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30862#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30763#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 30683#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 30632#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 30525#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 30526#L911 assume !(0 == start_simulation_~tmp~3); 30843#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 30961#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 30502#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 30714#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 30695#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30696#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 30793#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 30794#L924 assume !(0 != start_simulation_~tmp___0~1); 30590#L892-1 [2021-10-13 01:04:51,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:51,089 INFO L82 PathProgramCache]: Analyzing trace with hash 865145049, now seen corresponding path program 1 times [2021-10-13 01:04:51,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:51,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045246855] [2021-10-13 01:04:51,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:51,090 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:51,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:51,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:51,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:51,120 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045246855] [2021-10-13 01:04:51,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2045246855] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:51,120 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:51,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:04:51,122 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763977120] [2021-10-13 01:04:51,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:51,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:51,123 INFO L82 PathProgramCache]: Analyzing trace with hash -53721882, now seen corresponding path program 1 times [2021-10-13 01:04:51,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:51,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142229667] [2021-10-13 01:04:51,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:51,123 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:51,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:51,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:51,177 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:51,177 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142229667] [2021-10-13 01:04:51,178 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142229667] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:51,178 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:51,178 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:51,178 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458987360] [2021-10-13 01:04:51,178 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:51,179 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:51,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:51,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:51,179 INFO L87 Difference]: Start difference. First operand 5580 states and 8011 transitions. cyclomatic complexity: 2433 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 2 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:51,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:51,230 INFO L93 Difference]: Finished difference Result 5580 states and 7917 transitions. [2021-10-13 01:04:51,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:51,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5580 states and 7917 transitions. [2021-10-13 01:04:51,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2021-10-13 01:04:51,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5580 states to 5580 states and 7917 transitions. [2021-10-13 01:04:51,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5580 [2021-10-13 01:04:51,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5580 [2021-10-13 01:04:51,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5580 states and 7917 transitions. [2021-10-13 01:04:51,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:51,303 INFO L681 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2021-10-13 01:04:51,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5580 states and 7917 transitions. [2021-10-13 01:04:51,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5580 to 5580. [2021-10-13 01:04:51,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5580 states, 5580 states have (on average 1.4188172043010752) internal successors, (7917), 5579 states have internal predecessors, (7917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:51,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 7917 transitions. [2021-10-13 01:04:51,503 INFO L704 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2021-10-13 01:04:51,503 INFO L587 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2021-10-13 01:04:51,504 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-13 01:04:51,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 7917 transitions. [2021-10-13 01:04:51,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2021-10-13 01:04:51,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:51,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:51,531 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:51,531 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:51,532 INFO L791 eck$LassoCheckResult]: Stem: 42212#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 42178#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 42045#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41963#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 41964#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42065#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42066#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41979#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41887#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41888#L418-1 assume !(0 == ~M_E~0); 42164#L578-1 assume !(0 == ~T1_E~0); 41923#L583-1 assume !(0 == ~T2_E~0); 41844#L588-1 assume !(0 == ~T3_E~0); 41770#L593-1 assume !(0 == ~T4_E~0); 41760#L598-1 assume !(0 == ~T5_E~0); 41761#L603-1 assume !(0 == ~E_1~0); 41980#L608-1 assume !(0 == ~E_2~0); 41834#L613-1 assume !(0 == ~E_3~0); 41835#L618-1 assume !(0 == ~E_4~0); 41953#L623-1 assume !(0 == ~E_5~0); 42093#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42175#L271 assume !(1 == ~m_pc~0); 42120#L271-2 is_master_triggered_~__retres1~0 := 0; 42121#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41992#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41993#L712 assume !(0 != activate_threads_~tmp~1); 42088#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42089#L290 assume !(1 == ~t1_pc~0); 41801#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 41802#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41973#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41974#L720 assume !(0 != activate_threads_~tmp___0~0); 42064#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42201#L309 assume !(1 == ~t2_pc~0); 41958#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 42123#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41952#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41737#L728 assume !(0 != activate_threads_~tmp___1~0); 41738#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42052#L328 assume !(1 == ~t3_pc~0); 42106#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 41840#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41841#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 41908#L736 assume !(0 != activate_threads_~tmp___2~0); 41909#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42184#L347 assume !(1 == ~t4_pc~0); 41739#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 41664#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41665#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42070#L744 assume !(0 != activate_threads_~tmp___3~0); 42071#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41806#L366 assume !(1 == ~t5_pc~0); 41784#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 41785#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42157#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 42107#L752 assume !(0 != activate_threads_~tmp___4~0); 41742#L752-2 assume !(1 == ~M_E~0); 41743#L641-1 assume !(1 == ~T1_E~0); 41757#L646-1 assume !(1 == ~T2_E~0); 41894#L651-1 assume !(1 == ~T3_E~0); 42167#L656-1 assume !(1 == ~T4_E~0); 42101#L661-1 assume !(1 == ~T5_E~0); 42102#L666-1 assume !(1 == ~E_1~0); 42072#L671-1 assume !(1 == ~E_2~0); 41853#L676-1 assume !(1 == ~E_3~0); 41854#L681-1 assume !(1 == ~E_4~0); 41987#L686-1 assume !(1 == ~E_5~0); 41988#L892-1 [2021-10-13 01:04:51,532 INFO L793 eck$LassoCheckResult]: Loop: 41988#L892-1 assume !false; 43832#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 43827#L553 assume !false; 43826#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43817#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43813#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43806#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 43803#L478 assume !(0 != eval_~tmp~0); 43804#L568 start_simulation_~kernel_st~0 := 2; 47051#L386-1 start_simulation_~kernel_st~0 := 3; 47048#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 47046#L578-4 assume !(0 == ~T1_E~0); 47044#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47042#L588-3 assume !(0 == ~T3_E~0); 47040#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47039#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47038#L603-3 assume !(0 == ~E_1~0); 47036#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47034#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47032#L618-3 assume !(0 == ~E_4~0); 47030#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47028#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47027#L271-18 assume !(1 == ~m_pc~0); 47025#L271-20 is_master_triggered_~__retres1~0 := 0; 47023#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47021#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 47019#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 47018#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42217#L290-18 assume !(1 == ~t1_pc~0); 42218#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 46751#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46750#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 46748#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 46745#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46720#L309-18 assume 1 == ~t2_pc~0; 46716#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 46711#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46705#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46698#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 46683#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46055#L328-18 assume !(1 == ~t3_pc~0); 46053#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 46051#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46049#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 46047#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 46045#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46042#L347-18 assume !(1 == ~t4_pc~0); 46039#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 46037#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46036#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 46033#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 46031#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43956#L366-18 assume !(1 == ~t5_pc~0); 43954#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 43952#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43949#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 43948#L752-18 assume !(0 != activate_threads_~tmp___4~0); 43945#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 43943#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43941#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43939#L651-3 assume !(1 == ~T3_E~0); 43937#L656-3 assume !(1 == ~T4_E~0); 43935#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43933#L666-3 assume !(1 == ~E_1~0); 43931#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43929#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43927#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43925#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43923#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43909#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43903#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43901#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 43897#L911 assume !(0 == start_simulation_~tmp~3); 43894#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43886#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43882#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43880#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 43877#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43875#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 43873#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 43871#L924 assume !(0 != start_simulation_~tmp___0~1); 41988#L892-1 [2021-10-13 01:04:51,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:51,533 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 1 times [2021-10-13 01:04:51,533 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:51,535 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132681637] [2021-10-13 01:04:51,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:51,535 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:51,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:51,550 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:51,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:51,608 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:51,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:51,609 INFO L82 PathProgramCache]: Analyzing trace with hash 108238116, now seen corresponding path program 1 times [2021-10-13 01:04:51,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:51,609 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63915780] [2021-10-13 01:04:51,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:51,610 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:51,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:51,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:51,645 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:51,646 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63915780] [2021-10-13 01:04:51,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63915780] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:51,646 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:51,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:51,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023898910] [2021-10-13 01:04:51,647 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:51,647 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:51,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:51,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:51,648 INFO L87 Difference]: Start difference. First operand 5580 states and 7917 transitions. cyclomatic complexity: 2339 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:51,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:51,703 INFO L93 Difference]: Finished difference Result 6496 states and 9195 transitions. [2021-10-13 01:04:51,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:51,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6496 states and 9195 transitions. [2021-10-13 01:04:51,742 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6364 [2021-10-13 01:04:51,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6496 states to 6496 states and 9195 transitions. [2021-10-13 01:04:51,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6496 [2021-10-13 01:04:51,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6496 [2021-10-13 01:04:51,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6496 states and 9195 transitions. [2021-10-13 01:04:51,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:51,887 INFO L681 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2021-10-13 01:04:51,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6496 states and 9195 transitions. [2021-10-13 01:04:51,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6496 to 6496. [2021-10-13 01:04:52,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6496 states, 6496 states have (on average 1.4154864532019704) internal successors, (9195), 6495 states have internal predecessors, (9195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:52,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6496 states to 6496 states and 9195 transitions. [2021-10-13 01:04:52,032 INFO L704 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2021-10-13 01:04:52,032 INFO L587 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2021-10-13 01:04:52,032 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-13 01:04:52,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6496 states and 9195 transitions. [2021-10-13 01:04:52,061 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6364 [2021-10-13 01:04:52,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:52,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:52,065 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:52,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:52,066 INFO L791 eck$LassoCheckResult]: Stem: 54338#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 54283#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 54134#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 54044#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 54045#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54162#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54163#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54065#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53966#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53967#L418-1 assume !(0 == ~M_E~0); 54266#L578-1 assume !(0 == ~T1_E~0); 54001#L583-1 assume !(0 == ~T2_E~0); 53921#L588-1 assume !(0 == ~T3_E~0); 53849#L593-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53850#L598-1 assume !(0 == ~T5_E~0); 54323#L603-1 assume !(0 == ~E_1~0); 54324#L608-1 assume !(0 == ~E_2~0); 53912#L613-1 assume !(0 == ~E_3~0); 53913#L618-1 assume !(0 == ~E_4~0); 54198#L623-1 assume !(0 == ~E_5~0); 54199#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54277#L271 assume !(1 == ~m_pc~0); 54278#L271-2 is_master_triggered_~__retres1~0 := 0; 54261#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54262#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54299#L712 assume !(0 != activate_threads_~tmp~1); 54300#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 54253#L290 assume !(1 == ~t1_pc~0); 54254#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 54227#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54228#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 54159#L720 assume !(0 != activate_threads_~tmp___0~0); 54160#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 54318#L309 assume !(1 == ~t2_pc~0); 54040#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 54374#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54373#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 54370#L728 assume !(0 != activate_threads_~tmp___1~0); 54369#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54325#L328 assume !(1 == ~t3_pc~0); 54326#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 53917#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53918#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 54368#L736 assume !(0 != activate_threads_~tmp___2~0); 54290#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54291#L347 assume !(1 == ~t4_pc~0); 53820#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 53746#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53747#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 54167#L744 assume !(0 != activate_threads_~tmp___3~0); 54168#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53888#L366 assume !(1 == ~t5_pc~0); 53866#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 53867#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54257#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 54211#L752 assume !(0 != activate_threads_~tmp___4~0); 53823#L752-2 assume !(1 == ~M_E~0); 53824#L641-1 assume !(1 == ~T1_E~0); 53838#L646-1 assume !(1 == ~T2_E~0); 53976#L651-1 assume !(1 == ~T3_E~0); 54269#L656-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54205#L661-1 assume !(1 == ~T5_E~0); 54206#L666-1 assume !(1 == ~E_1~0); 54169#L671-1 assume !(1 == ~E_2~0); 53931#L676-1 assume !(1 == ~E_3~0); 53932#L681-1 assume !(1 == ~E_4~0); 54076#L686-1 assume !(1 == ~E_5~0); 54077#L892-1 [2021-10-13 01:04:52,066 INFO L793 eck$LassoCheckResult]: Loop: 54077#L892-1 assume !false; 56131#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 55941#L553 assume !false; 56127#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56058#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56049#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56044#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 56039#L478 assume !(0 != eval_~tmp~0); 56040#L568 start_simulation_~kernel_st~0 := 2; 59843#L386-1 start_simulation_~kernel_st~0 := 3; 59842#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 59841#L578-4 assume !(0 == ~T1_E~0); 59840#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59839#L588-3 assume !(0 == ~T3_E~0); 59838#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54241#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54242#L603-3 assume !(0 == ~E_1~0); 54161#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54103#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54104#L618-3 assume !(0 == ~E_4~0); 54175#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53786#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53787#L271-18 assume !(1 == ~m_pc~0); 54258#L271-20 is_master_triggered_~__retres1~0 := 0; 54304#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54305#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59853#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 59852#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56545#L290-18 assume !(1 == ~t1_pc~0); 56543#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 56541#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56539#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56537#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56535#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56532#L309-18 assume 1 == ~t2_pc~0; 56528#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 56524#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56520#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56517#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56515#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56514#L328-18 assume !(1 == ~t3_pc~0); 56433#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 56509#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56506#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 56503#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56500#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56495#L347-18 assume !(1 == ~t4_pc~0); 56488#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 56483#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56473#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56448#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 56439#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56200#L366-18 assume !(1 == ~t5_pc~0); 56198#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 56196#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56194#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56192#L752-18 assume !(0 != activate_threads_~tmp___4~0); 56190#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 56189#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56187#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56185#L651-3 assume !(1 == ~T3_E~0); 56183#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56180#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56178#L666-3 assume !(1 == ~E_1~0); 56176#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56174#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56172#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56170#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56168#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56163#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56157#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56155#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 56153#L911 assume !(0 == start_simulation_~tmp~3); 56151#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56147#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56144#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56142#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 56141#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56140#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 56136#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 56134#L924 assume !(0 != start_simulation_~tmp___0~1); 54077#L892-1 [2021-10-13 01:04:52,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:52,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1784034277, now seen corresponding path program 1 times [2021-10-13 01:04:52,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:52,067 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037345490] [2021-10-13 01:04:52,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:52,067 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:52,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:52,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:52,097 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:52,097 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037345490] [2021-10-13 01:04:52,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037345490] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:52,097 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:52,097 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:04:52,097 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740293897] [2021-10-13 01:04:52,098 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:52,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:52,098 INFO L82 PathProgramCache]: Analyzing trace with hash 925886566, now seen corresponding path program 1 times [2021-10-13 01:04:52,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:52,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942451884] [2021-10-13 01:04:52,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:52,099 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:52,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:52,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:52,138 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:52,138 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942451884] [2021-10-13 01:04:52,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942451884] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:52,139 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:52,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:04:52,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402400128] [2021-10-13 01:04:52,139 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:52,139 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:52,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:52,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:52,141 INFO L87 Difference]: Start difference. First operand 6496 states and 9195 transitions. cyclomatic complexity: 2701 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 2 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:52,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:52,181 INFO L93 Difference]: Finished difference Result 5580 states and 7867 transitions. [2021-10-13 01:04:52,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:52,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5580 states and 7867 transitions. [2021-10-13 01:04:52,209 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2021-10-13 01:04:52,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5580 states to 5580 states and 7867 transitions. [2021-10-13 01:04:52,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5580 [2021-10-13 01:04:52,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5580 [2021-10-13 01:04:52,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5580 states and 7867 transitions. [2021-10-13 01:04:52,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:52,315 INFO L681 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2021-10-13 01:04:52,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5580 states and 7867 transitions. [2021-10-13 01:04:52,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5580 to 5580. [2021-10-13 01:04:52,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5580 states, 5580 states have (on average 1.4098566308243727) internal successors, (7867), 5579 states have internal predecessors, (7867), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:52,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 7867 transitions. [2021-10-13 01:04:52,407 INFO L704 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2021-10-13 01:04:52,407 INFO L587 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2021-10-13 01:04:52,407 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-13 01:04:52,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 7867 transitions. [2021-10-13 01:04:52,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2021-10-13 01:04:52,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:52,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:52,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:52,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:52,426 INFO L791 eck$LassoCheckResult]: Stem: 66364#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 66329#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66199#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66123#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 66124#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66219#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66220#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66138#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66046#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66047#L418-1 assume !(0 == ~M_E~0); 66313#L578-1 assume !(0 == ~T1_E~0); 66083#L583-1 assume !(0 == ~T2_E~0); 66004#L588-1 assume !(0 == ~T3_E~0); 65933#L593-1 assume !(0 == ~T4_E~0); 65925#L598-1 assume !(0 == ~T5_E~0); 65926#L603-1 assume !(0 == ~E_1~0); 66139#L608-1 assume !(0 == ~E_2~0); 65995#L613-1 assume !(0 == ~E_3~0); 65996#L618-1 assume !(0 == ~E_4~0); 66112#L623-1 assume !(0 == ~E_5~0); 66250#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66326#L271 assume !(1 == ~m_pc~0); 66274#L271-2 is_master_triggered_~__retres1~0 := 0; 66275#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66153#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 66154#L712 assume !(0 != activate_threads_~tmp~1); 66245#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 66246#L290 assume !(1 == ~t1_pc~0); 65961#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 65962#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66133#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 66134#L720 assume !(0 != activate_threads_~tmp___0~0); 66218#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66352#L309 assume !(1 == ~t2_pc~0); 66117#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 66278#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66111#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 65903#L728 assume !(0 != activate_threads_~tmp___1~0); 65904#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66207#L328 assume !(1 == ~t3_pc~0); 66261#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 66000#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66001#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 66068#L736 assume !(0 != activate_threads_~tmp___2~0); 66069#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66336#L347 assume !(1 == ~t4_pc~0); 65905#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 65831#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65832#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66224#L744 assume !(0 != activate_threads_~tmp___3~0); 66225#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65969#L366 assume !(1 == ~t5_pc~0); 65947#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 65948#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66306#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 66262#L752 assume !(0 != activate_threads_~tmp___4~0); 65908#L752-2 assume !(1 == ~M_E~0); 65909#L641-1 assume !(1 == ~T1_E~0); 65922#L646-1 assume !(1 == ~T2_E~0); 66054#L651-1 assume !(1 == ~T3_E~0); 66317#L656-1 assume !(1 == ~T4_E~0); 66257#L661-1 assume !(1 == ~T5_E~0); 66258#L666-1 assume !(1 == ~E_1~0); 66226#L671-1 assume !(1 == ~E_2~0); 66015#L676-1 assume !(1 == ~E_3~0); 66016#L681-1 assume !(1 == ~E_4~0); 66148#L686-1 assume !(1 == ~E_5~0); 66149#L892-1 [2021-10-13 01:04:52,427 INFO L793 eck$LassoCheckResult]: Loop: 66149#L892-1 assume !false; 67772#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 67770#L553 assume !false; 67768#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67587#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67578#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67576#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 67573#L478 assume !(0 != eval_~tmp~0); 67574#L568 start_simulation_~kernel_st~0 := 2; 70636#L386-1 start_simulation_~kernel_st~0 := 3; 70634#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70632#L578-4 assume !(0 == ~T1_E~0); 70630#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70628#L588-3 assume !(0 == ~T3_E~0); 70626#L593-3 assume !(0 == ~T4_E~0); 70624#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70622#L603-3 assume !(0 == ~E_1~0); 70620#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70618#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70616#L618-3 assume !(0 == ~E_4~0); 70614#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70612#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70610#L271-18 assume !(1 == ~m_pc~0); 70608#L271-20 is_master_triggered_~__retres1~0 := 0; 70606#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70604#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 70602#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 70600#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70598#L290-18 assume !(1 == ~t1_pc~0); 70400#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 70399#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70397#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70395#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70393#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70388#L309-18 assume !(1 == ~t2_pc~0); 70385#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 70383#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70381#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 70378#L728-18 assume !(0 != activate_threads_~tmp___1~0); 70375#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66339#L328-18 assume !(1 == ~t3_pc~0); 66314#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 66239#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66240#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 65985#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65986#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66291#L347-18 assume 1 == ~t4_pc~0; 66072#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 66073#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 66252#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66105#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 65930#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65931#L366-18 assume !(1 == ~t5_pc~0); 68384#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 68382#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 68381#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 68380#L752-18 assume !(0 != activate_threads_~tmp___4~0); 68379#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 68378#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68371#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68369#L651-3 assume !(1 == ~T3_E~0); 68367#L656-3 assume !(1 == ~T4_E~0); 68365#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68363#L666-3 assume !(1 == ~E_1~0); 68362#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68355#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68345#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68337#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68329#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 68318#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 68309#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 68300#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 68293#L911 assume !(0 == start_simulation_~tmp~3); 68289#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 68280#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 68273#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 68270#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 68265#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68259#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 68253#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 68246#L924 assume !(0 != start_simulation_~tmp___0~1); 66149#L892-1 [2021-10-13 01:04:52,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:52,427 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 2 times [2021-10-13 01:04:52,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:52,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086577675] [2021-10-13 01:04:52,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:52,428 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:52,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:52,441 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:52,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:52,488 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:52,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:52,489 INFO L82 PathProgramCache]: Analyzing trace with hash -655232856, now seen corresponding path program 1 times [2021-10-13 01:04:52,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:52,489 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679920492] [2021-10-13 01:04:52,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:52,489 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:52,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:52,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:52,529 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:52,529 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679920492] [2021-10-13 01:04:52,529 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [679920492] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:52,529 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:52,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:04:52,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41619618] [2021-10-13 01:04:52,530 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:52,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:52,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:04:52,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:04:52,530 INFO L87 Difference]: Start difference. First operand 5580 states and 7867 transitions. cyclomatic complexity: 2289 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:52,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:52,657 INFO L93 Difference]: Finished difference Result 9904 states and 13771 transitions. [2021-10-13 01:04:52,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-13 01:04:52,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9904 states and 13771 transitions. [2021-10-13 01:04:52,781 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9816 [2021-10-13 01:04:52,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9904 states to 9904 states and 13771 transitions. [2021-10-13 01:04:52,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9904 [2021-10-13 01:04:52,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9904 [2021-10-13 01:04:52,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9904 states and 13771 transitions. [2021-10-13 01:04:52,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:52,841 INFO L681 BuchiCegarLoop]: Abstraction has 9904 states and 13771 transitions. [2021-10-13 01:04:52,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9904 states and 13771 transitions. [2021-10-13 01:04:52,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9904 to 5628. [2021-10-13 01:04:52,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5628 states, 5628 states have (on average 1.40636105188344) internal successors, (7915), 5627 states have internal predecessors, (7915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:52,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5628 states to 5628 states and 7915 transitions. [2021-10-13 01:04:52,953 INFO L704 BuchiCegarLoop]: Abstraction has 5628 states and 7915 transitions. [2021-10-13 01:04:52,954 INFO L587 BuchiCegarLoop]: Abstraction has 5628 states and 7915 transitions. [2021-10-13 01:04:52,954 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-13 01:04:52,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5628 states and 7915 transitions. [2021-10-13 01:04:52,971 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5548 [2021-10-13 01:04:52,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:52,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:53,012 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:53,012 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:53,012 INFO L791 eck$LassoCheckResult]: Stem: 81895#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 81852#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81707#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81625#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 81626#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81726#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81727#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81640#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81547#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81548#L418-1 assume !(0 == ~M_E~0); 81834#L578-1 assume !(0 == ~T1_E~0); 81584#L583-1 assume !(0 == ~T2_E~0); 81505#L588-1 assume !(0 == ~T3_E~0); 81435#L593-1 assume !(0 == ~T4_E~0); 81426#L598-1 assume !(0 == ~T5_E~0); 81427#L603-1 assume !(0 == ~E_1~0); 81641#L608-1 assume !(0 == ~E_2~0); 81496#L613-1 assume !(0 == ~E_3~0); 81497#L618-1 assume !(0 == ~E_4~0); 81614#L623-1 assume !(0 == ~E_5~0); 81767#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81849#L271 assume !(1 == ~m_pc~0); 81791#L271-2 is_master_triggered_~__retres1~0 := 0; 81792#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81655#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 81656#L712 assume !(0 != activate_threads_~tmp~1); 81762#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81763#L290 assume !(1 == ~t1_pc~0); 81463#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 81464#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81636#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81637#L720 assume !(0 != activate_threads_~tmp___0~0); 81725#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81878#L309 assume !(1 == ~t2_pc~0); 81619#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 81795#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81611#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81403#L728 assume !(0 != activate_threads_~tmp___1~0); 81404#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81715#L328 assume !(1 == ~t3_pc~0); 81778#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 81500#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81501#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 81567#L736 assume !(0 != activate_threads_~tmp___2~0); 81568#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81861#L347 assume !(1 == ~t4_pc~0); 81405#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 81331#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81332#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81733#L744 assume !(0 != activate_threads_~tmp___3~0); 81734#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81471#L366 assume !(1 == ~t5_pc~0); 81449#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 81450#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81825#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81779#L752 assume !(0 != activate_threads_~tmp___4~0); 81408#L752-2 assume !(1 == ~M_E~0); 81409#L641-1 assume !(1 == ~T1_E~0); 81423#L646-1 assume !(1 == ~T2_E~0); 81555#L651-1 assume !(1 == ~T3_E~0); 81841#L656-1 assume !(1 == ~T4_E~0); 81774#L661-1 assume !(1 == ~T5_E~0); 81775#L666-1 assume !(1 == ~E_1~0); 81735#L671-1 assume !(1 == ~E_2~0); 81515#L676-1 assume !(1 == ~E_3~0); 81516#L681-1 assume !(1 == ~E_4~0); 81650#L686-1 assume !(1 == ~E_5~0); 81651#L892-1 [2021-10-13 01:04:53,013 INFO L793 eck$LassoCheckResult]: Loop: 81651#L892-1 assume !false; 86265#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 86261#L553 assume !false; 86164#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86156#L431 assume !(0 == ~m_st~0); 86157#L435 assume !(0 == ~t1_st~0); 86159#L439 assume !(0 == ~t2_st~0); 86154#L443 assume !(0 == ~t3_st~0); 86155#L447 assume !(0 == ~t4_st~0); 86158#L451 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 86160#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 84931#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 84932#L478 assume !(0 != eval_~tmp~0); 86149#L568 start_simulation_~kernel_st~0 := 2; 81575#L386-1 start_simulation_~kernel_st~0 := 3; 81576#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 81758#L578-4 assume !(0 == ~T1_E~0); 81759#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81847#L588-3 assume !(0 == ~T3_E~0); 81674#L593-3 assume !(0 == ~T4_E~0); 81675#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81812#L603-3 assume !(0 == ~E_1~0); 86487#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86486#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81741#L618-3 assume !(0 == ~E_4~0); 81742#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86485#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81826#L271-18 assume !(1 == ~m_pc~0); 81827#L271-20 is_master_triggered_~__retres1~0 := 0; 81866#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81867#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 81893#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86483#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81901#L290-18 assume !(1 == ~t1_pc~0); 81902#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 81593#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81594#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81700#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 81846#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81608#L309-18 assume 1 == ~t2_pc~0; 81539#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 81540#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84727#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 84728#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 81874#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81875#L328-18 assume !(1 == ~t3_pc~0); 81937#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 86476#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86475#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 86474#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86473#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86472#L347-18 assume 1 == ~t4_pc~0; 86471#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 86469#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86468#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 86467#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 86466#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86465#L366-18 assume !(1 == ~t5_pc~0); 85774#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 86464#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86463#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 86462#L752-18 assume !(0 != activate_threads_~tmp___4~0); 86461#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 86460#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86459#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86458#L651-3 assume !(1 == ~T3_E~0); 86457#L656-3 assume !(1 == ~T4_E~0); 86456#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86455#L666-3 assume !(1 == ~E_1~0); 86454#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86453#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86452#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86451#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86450#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86448#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86440#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86435#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 86404#L911 assume !(0 == start_simulation_~tmp~3); 86301#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86297#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86292#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86290#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 86288#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86286#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 86284#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 86282#L924 assume !(0 != start_simulation_~tmp___0~1); 81651#L892-1 [2021-10-13 01:04:53,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:53,013 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 3 times [2021-10-13 01:04:53,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:53,014 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178063071] [2021-10-13 01:04:53,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:53,014 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:53,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:53,026 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:53,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:53,061 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:53,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:53,061 INFO L82 PathProgramCache]: Analyzing trace with hash 43048842, now seen corresponding path program 1 times [2021-10-13 01:04:53,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:53,062 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454296738] [2021-10-13 01:04:53,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:53,063 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:53,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:53,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:53,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:53,132 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454296738] [2021-10-13 01:04:53,132 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454296738] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:53,133 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:53,133 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-13 01:04:53,133 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048289577] [2021-10-13 01:04:53,133 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:53,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:53,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-13 01:04:53,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-13 01:04:53,134 INFO L87 Difference]: Start difference. First operand 5628 states and 7915 transitions. cyclomatic complexity: 2289 Second operand has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:53,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:53,338 INFO L93 Difference]: Finished difference Result 11188 states and 15622 transitions. [2021-10-13 01:04:53,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-13 01:04:53,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11188 states and 15622 transitions. [2021-10-13 01:04:53,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11108 [2021-10-13 01:04:53,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11188 states to 11188 states and 15622 transitions. [2021-10-13 01:04:53,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11188 [2021-10-13 01:04:53,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11188 [2021-10-13 01:04:53,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11188 states and 15622 transitions. [2021-10-13 01:04:53,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:53,469 INFO L681 BuchiCegarLoop]: Abstraction has 11188 states and 15622 transitions. [2021-10-13 01:04:53,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11188 states and 15622 transitions. [2021-10-13 01:04:53,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11188 to 5772. [2021-10-13 01:04:53,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5772 states, 5772 states have (on average 1.389119889119889) internal successors, (8018), 5771 states have internal predecessors, (8018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:53,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5772 states to 5772 states and 8018 transitions. [2021-10-13 01:04:53,614 INFO L704 BuchiCegarLoop]: Abstraction has 5772 states and 8018 transitions. [2021-10-13 01:04:53,614 INFO L587 BuchiCegarLoop]: Abstraction has 5772 states and 8018 transitions. [2021-10-13 01:04:53,614 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-13 01:04:53,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5772 states and 8018 transitions. [2021-10-13 01:04:53,635 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5692 [2021-10-13 01:04:53,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:53,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:53,637 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:53,638 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:53,638 INFO L791 eck$LassoCheckResult]: Stem: 98714#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 98669#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98530#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98455#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 98456#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98553#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98554#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98469#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98377#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98378#L418-1 assume !(0 == ~M_E~0); 98653#L578-1 assume !(0 == ~T1_E~0); 98415#L583-1 assume !(0 == ~T2_E~0); 98335#L588-1 assume !(0 == ~T3_E~0); 98262#L593-1 assume !(0 == ~T4_E~0); 98254#L598-1 assume !(0 == ~T5_E~0); 98255#L603-1 assume !(0 == ~E_1~0); 98470#L608-1 assume !(0 == ~E_2~0); 98326#L613-1 assume !(0 == ~E_3~0); 98327#L618-1 assume !(0 == ~E_4~0); 98445#L623-1 assume !(0 == ~E_5~0); 98589#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98663#L271 assume !(1 == ~m_pc~0); 98614#L271-2 is_master_triggered_~__retres1~0 := 0; 98615#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98483#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98484#L712 assume !(0 != activate_threads_~tmp~1); 98584#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98585#L290 assume !(1 == ~t1_pc~0); 98292#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 98293#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98464#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 98465#L720 assume !(0 != activate_threads_~tmp___0~0); 98552#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98699#L309 assume !(1 == ~t2_pc~0); 98451#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 98618#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98442#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 98232#L728 assume !(0 != activate_threads_~tmp___1~0); 98233#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98538#L328 assume !(1 == ~t3_pc~0); 98600#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 98330#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98331#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 98399#L736 assume !(0 != activate_threads_~tmp___2~0); 98400#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98680#L347 assume !(1 == ~t4_pc~0); 98234#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 98160#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98161#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 98560#L744 assume !(0 != activate_threads_~tmp___3~0); 98561#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98300#L366 assume !(1 == ~t5_pc~0); 98276#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 98277#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98645#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 98601#L752 assume !(0 != activate_threads_~tmp___4~0); 98237#L752-2 assume !(1 == ~M_E~0); 98238#L641-1 assume !(1 == ~T1_E~0); 98251#L646-1 assume !(1 == ~T2_E~0); 98385#L651-1 assume !(1 == ~T3_E~0); 98657#L656-1 assume !(1 == ~T4_E~0); 98596#L661-1 assume !(1 == ~T5_E~0); 98597#L666-1 assume !(1 == ~E_1~0); 98562#L671-1 assume !(1 == ~E_2~0); 98345#L676-1 assume !(1 == ~E_3~0); 98346#L681-1 assume !(1 == ~E_4~0); 98478#L686-1 assume !(1 == ~E_5~0); 98479#L892-1 [2021-10-13 01:04:53,638 INFO L793 eck$LassoCheckResult]: Loop: 98479#L892-1 assume !false; 101135#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 100579#L553 assume !false; 101133#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101096#L431 assume !(0 == ~m_st~0); 101097#L435 assume !(0 == ~t1_st~0); 101099#L439 assume !(0 == ~t2_st~0); 101094#L443 assume !(0 == ~t3_st~0); 101095#L447 assume !(0 == ~t4_st~0); 101098#L451 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 101100#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101034#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 101035#L478 assume !(0 != eval_~tmp~0); 101359#L568 start_simulation_~kernel_st~0 := 2; 101358#L386-1 start_simulation_~kernel_st~0 := 3; 101357#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 101356#L578-4 assume !(0 == ~T1_E~0); 101355#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 101354#L588-3 assume !(0 == ~T3_E~0); 101353#L593-3 assume !(0 == ~T4_E~0); 101352#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101351#L603-3 assume !(0 == ~E_1~0); 101350#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 101349#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101348#L618-3 assume !(0 == ~E_4~0); 101347#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98200#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98201#L271-18 assume !(1 == ~m_pc~0); 98646#L271-20 is_master_triggered_~__retres1~0 := 0; 101274#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 101273#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 101272#L712-18 assume !(0 != activate_threads_~tmp~1); 101271#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 101269#L290-18 assume !(1 == ~t1_pc~0); 100928#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 101266#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 101264#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 101262#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 101260#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 101258#L309-18 assume !(1 == ~t2_pc~0); 101257#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 101254#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 101251#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 101248#L728-18 assume !(0 != activate_threads_~tmp___1~0); 101245#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 101243#L328-18 assume !(1 == ~t3_pc~0); 100179#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 101238#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 101235#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 101232#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 101230#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101228#L347-18 assume 1 == ~t4_pc~0; 101227#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 101224#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 101222#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 101220#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 101218#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 101215#L366-18 assume !(1 == ~t5_pc~0); 100713#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 101211#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 101209#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 101207#L752-18 assume !(0 != activate_threads_~tmp___4~0); 101205#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 101203#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101201#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101198#L651-3 assume !(1 == ~T3_E~0); 101195#L656-3 assume !(1 == ~T4_E~0); 101192#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101189#L666-3 assume !(1 == ~E_1~0); 101186#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 101183#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101178#L681-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101174#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101172#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101166#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 101159#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101156#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 101152#L911 assume !(0 == start_simulation_~tmp~3); 101149#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101145#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 101142#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101141#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 101140#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 101139#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 101138#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 101137#L924 assume !(0 != start_simulation_~tmp___0~1); 98479#L892-1 [2021-10-13 01:04:53,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:53,639 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 4 times [2021-10-13 01:04:53,639 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:53,639 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240189562] [2021-10-13 01:04:53,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:53,640 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:53,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:53,653 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:53,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:53,687 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:53,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:53,688 INFO L82 PathProgramCache]: Analyzing trace with hash -1361001201, now seen corresponding path program 1 times [2021-10-13 01:04:53,689 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:53,689 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171590632] [2021-10-13 01:04:53,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:53,689 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:53,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:53,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:53,719 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:53,719 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171590632] [2021-10-13 01:04:53,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171590632] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:53,719 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:53,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:53,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50117392] [2021-10-13 01:04:53,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-13 01:04:53,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:53,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:53,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:53,721 INFO L87 Difference]: Start difference. First operand 5772 states and 8018 transitions. cyclomatic complexity: 2248 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:53,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:53,803 INFO L93 Difference]: Finished difference Result 9770 states and 13364 transitions. [2021-10-13 01:04:53,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:53,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9770 states and 13364 transitions. [2021-10-13 01:04:53,855 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9688 [2021-10-13 01:04:53,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9770 states to 9770 states and 13364 transitions. [2021-10-13 01:04:53,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9770 [2021-10-13 01:04:53,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9770 [2021-10-13 01:04:53,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9770 states and 13364 transitions. [2021-10-13 01:04:53,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:53,963 INFO L681 BuchiCegarLoop]: Abstraction has 9770 states and 13364 transitions. [2021-10-13 01:04:53,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9770 states and 13364 transitions. [2021-10-13 01:04:54,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9770 to 9454. [2021-10-13 01:04:54,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9454 states, 9454 states have (on average 1.370002115506664) internal successors, (12952), 9453 states have internal predecessors, (12952), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:54,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9454 states to 9454 states and 12952 transitions. [2021-10-13 01:04:54,100 INFO L704 BuchiCegarLoop]: Abstraction has 9454 states and 12952 transitions. [2021-10-13 01:04:54,100 INFO L587 BuchiCegarLoop]: Abstraction has 9454 states and 12952 transitions. [2021-10-13 01:04:54,101 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-13 01:04:54,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9454 states and 12952 transitions. [2021-10-13 01:04:54,130 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9372 [2021-10-13 01:04:54,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:54,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:54,132 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:54,132 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:54,132 INFO L791 eck$LassoCheckResult]: Stem: 114280#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 114236#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 114092#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 114014#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 114015#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114113#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114114#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114028#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113932#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 113933#L418-1 assume !(0 == ~M_E~0); 114223#L578-1 assume !(0 == ~T1_E~0); 113971#L583-1 assume !(0 == ~T2_E~0); 113888#L588-1 assume !(0 == ~T3_E~0); 113812#L593-1 assume !(0 == ~T4_E~0); 113803#L598-1 assume !(0 == ~T5_E~0); 113804#L603-1 assume !(0 == ~E_1~0); 114029#L608-1 assume !(0 == ~E_2~0); 113879#L613-1 assume !(0 == ~E_3~0); 113880#L618-1 assume !(0 == ~E_4~0); 114003#L623-1 assume !(0 == ~E_5~0); 114154#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 114233#L271 assume !(1 == ~m_pc~0); 114180#L271-2 is_master_triggered_~__retres1~0 := 0; 114181#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114043#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 114044#L712 assume !(0 != activate_threads_~tmp~1); 114149#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114150#L290 assume !(1 == ~t1_pc~0); 113842#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 113843#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114024#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 114025#L720 assume !(0 != activate_threads_~tmp___0~0); 114112#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114265#L309 assume !(1 == ~t2_pc~0); 114008#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 114183#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114000#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 113780#L728 assume !(0 != activate_threads_~tmp___1~0); 113781#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 114101#L328 assume !(1 == ~t3_pc~0); 114165#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 113883#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 113884#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 113954#L736 assume !(0 != activate_threads_~tmp___2~0); 113955#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114250#L347 assume !(1 == ~t4_pc~0); 113782#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 113708#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113709#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 114121#L744 assume !(0 != activate_threads_~tmp___3~0); 114122#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 113850#L366 assume !(1 == ~t5_pc~0); 113827#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 113828#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 114216#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 114166#L752 assume !(0 != activate_threads_~tmp___4~0); 113785#L752-2 assume !(1 == ~M_E~0); 113786#L641-1 assume !(1 == ~T1_E~0); 113800#L646-1 assume !(1 == ~T2_E~0); 113940#L651-1 assume !(1 == ~T3_E~0); 114229#L656-1 assume !(1 == ~T4_E~0); 114161#L661-1 assume !(1 == ~T5_E~0); 114162#L666-1 assume !(1 == ~E_1~0); 114123#L671-1 assume !(1 == ~E_2~0); 113898#L676-1 assume !(1 == ~E_3~0); 113899#L681-1 assume !(1 == ~E_4~0); 114038#L686-1 assume !(1 == ~E_5~0); 114039#L892-1 assume !false; 115259#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 115085#L553 [2021-10-13 01:04:54,132 INFO L793 eck$LassoCheckResult]: Loop: 115085#L553 assume !false; 115247#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 115245#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 115244#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 115242#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 115241#L478 assume 0 != eval_~tmp~0; 115239#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 115237#L486 assume !(0 != eval_~tmp_ndt_1~0); 115236#L483 assume !(0 == ~t1_st~0); 115234#L497 assume !(0 == ~t2_st~0); 115249#L511 assume !(0 == ~t3_st~0); 115100#L525 assume !(0 == ~t4_st~0); 115094#L539 assume !(0 == ~t5_st~0); 115085#L553 [2021-10-13 01:04:54,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:54,133 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 1 times [2021-10-13 01:04:54,133 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:54,133 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196761054] [2021-10-13 01:04:54,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:54,134 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:54,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:54,143 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:54,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:54,166 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:54,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:54,167 INFO L82 PathProgramCache]: Analyzing trace with hash 346179051, now seen corresponding path program 1 times [2021-10-13 01:04:54,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:54,167 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206943169] [2021-10-13 01:04:54,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:54,168 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:54,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:54,171 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:54,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:54,175 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:54,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:54,175 INFO L82 PathProgramCache]: Analyzing trace with hash -956602929, now seen corresponding path program 1 times [2021-10-13 01:04:54,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:54,176 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981397391] [2021-10-13 01:04:54,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:54,176 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:54,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:54,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:54,203 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:54,204 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981397391] [2021-10-13 01:04:54,204 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981397391] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:54,204 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:54,204 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:54,204 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290363352] [2021-10-13 01:04:54,318 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:54,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:54,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:54,319 INFO L87 Difference]: Start difference. First operand 9454 states and 12952 transitions. cyclomatic complexity: 3501 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:54,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:54,466 INFO L93 Difference]: Finished difference Result 17835 states and 24218 transitions. [2021-10-13 01:04:54,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:54,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17835 states and 24218 transitions. [2021-10-13 01:04:54,546 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17676 [2021-10-13 01:04:54,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17835 states to 17835 states and 24218 transitions. [2021-10-13 01:04:54,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17835 [2021-10-13 01:04:54,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17835 [2021-10-13 01:04:54,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17835 states and 24218 transitions. [2021-10-13 01:04:54,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:54,641 INFO L681 BuchiCegarLoop]: Abstraction has 17835 states and 24218 transitions. [2021-10-13 01:04:54,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17835 states and 24218 transitions. [2021-10-13 01:04:54,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17835 to 17307. [2021-10-13 01:04:54,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17307 states, 17307 states have (on average 1.3595654937308603) internal successors, (23530), 17306 states have internal predecessors, (23530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:55,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17307 states to 17307 states and 23530 transitions. [2021-10-13 01:04:55,129 INFO L704 BuchiCegarLoop]: Abstraction has 17307 states and 23530 transitions. [2021-10-13 01:04:55,129 INFO L587 BuchiCegarLoop]: Abstraction has 17307 states and 23530 transitions. [2021-10-13 01:04:55,129 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-13 01:04:55,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17307 states and 23530 transitions. [2021-10-13 01:04:55,289 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2021-10-13 01:04:55,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:55,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:55,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:55,291 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:55,291 INFO L791 eck$LassoCheckResult]: Stem: 141620#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 141565#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 141399#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 141312#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 141313#L393-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 141423#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141424#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141332#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141232#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141233#L418-1 assume !(0 == ~M_E~0); 141544#L578-1 assume !(0 == ~T1_E~0); 141270#L583-1 assume !(0 == ~T2_E~0); 141186#L588-1 assume !(0 == ~T3_E~0); 141110#L593-1 assume !(0 == ~T4_E~0); 141102#L598-1 assume !(0 == ~T5_E~0); 141103#L603-1 assume !(0 == ~E_1~0); 141333#L608-1 assume !(0 == ~E_2~0); 141176#L613-1 assume !(0 == ~E_3~0); 141177#L618-1 assume !(0 == ~E_4~0); 141301#L623-1 assume !(0 == ~E_5~0); 141464#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 141558#L271 assume !(1 == ~m_pc~0); 141492#L271-2 is_master_triggered_~__retres1~0 := 0; 141493#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 141346#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 141347#L712 assume !(0 != activate_threads_~tmp~1); 141459#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141460#L290 assume !(1 == ~t1_pc~0); 141142#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 141143#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 141325#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 141326#L720 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 141420#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148360#L309 assume !(1 == ~t2_pc~0); 148358#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 148357#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 148356#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 141078#L728 assume !(0 != activate_threads_~tmp___1~0); 141079#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 141410#L328 assume !(1 == ~t3_pc~0); 141477#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 141182#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141183#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 141257#L736 assume !(0 != activate_threads_~tmp___2~0); 141258#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 141578#L347 assume !(1 == ~t4_pc~0); 141080#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 141005#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 141006#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 141429#L744 assume !(0 != activate_threads_~tmp___3~0); 141430#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 141149#L366 assume !(1 == ~t5_pc~0); 141126#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 141127#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 141538#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 141478#L752 assume !(0 != activate_threads_~tmp___4~0); 141083#L752-2 assume !(1 == ~M_E~0); 141084#L641-1 assume !(1 == ~T1_E~0); 141099#L646-1 assume !(1 == ~T2_E~0); 141243#L651-1 assume !(1 == ~T3_E~0); 141549#L656-1 assume !(1 == ~T4_E~0); 141473#L661-1 assume !(1 == ~T5_E~0); 141474#L666-1 assume !(1 == ~E_1~0); 141431#L671-1 assume !(1 == ~E_2~0); 141196#L676-1 assume !(1 == ~E_3~0); 141197#L681-1 assume !(1 == ~E_4~0); 141342#L686-1 assume !(1 == ~E_5~0); 141343#L892-1 assume !false; 151902#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 151901#L553 [2021-10-13 01:04:55,291 INFO L793 eck$LassoCheckResult]: Loop: 151901#L553 assume !false; 151900#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 151899#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 151898#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 151896#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 151894#L478 assume 0 != eval_~tmp~0; 151892#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 151889#L486 assume !(0 != eval_~tmp_ndt_1~0); 151887#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 148300#L500 assume !(0 != eval_~tmp_ndt_2~0); 151881#L497 assume !(0 == ~t2_st~0); 151877#L511 assume !(0 == ~t3_st~0); 151876#L525 assume !(0 == ~t4_st~0); 151905#L539 assume !(0 == ~t5_st~0); 151901#L553 [2021-10-13 01:04:55,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:55,292 INFO L82 PathProgramCache]: Analyzing trace with hash -701066143, now seen corresponding path program 1 times [2021-10-13 01:04:55,292 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:55,292 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939394109] [2021-10-13 01:04:55,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:55,293 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:55,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:55,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:55,314 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:55,314 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939394109] [2021-10-13 01:04:55,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939394109] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:55,315 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:55,315 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:55,315 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777019854] [2021-10-13 01:04:55,316 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-13 01:04:55,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:55,317 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896484, now seen corresponding path program 1 times [2021-10-13 01:04:55,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:55,317 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928598694] [2021-10-13 01:04:55,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:55,317 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:55,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:55,321 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:55,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:55,326 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:55,464 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:55,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:55,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:55,465 INFO L87 Difference]: Start difference. First operand 17307 states and 23530 transitions. cyclomatic complexity: 6226 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:55,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:55,541 INFO L93 Difference]: Finished difference Result 17238 states and 23435 transitions. [2021-10-13 01:04:55,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:55,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17238 states and 23435 transitions. [2021-10-13 01:04:55,615 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2021-10-13 01:04:55,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17238 states to 17238 states and 23435 transitions. [2021-10-13 01:04:55,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17238 [2021-10-13 01:04:55,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17238 [2021-10-13 01:04:55,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17238 states and 23435 transitions. [2021-10-13 01:04:55,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:55,706 INFO L681 BuchiCegarLoop]: Abstraction has 17238 states and 23435 transitions. [2021-10-13 01:04:55,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17238 states and 23435 transitions. [2021-10-13 01:04:56,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17238 to 17238. [2021-10-13 01:04:56,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17238 states, 17238 states have (on average 1.359496461306416) internal successors, (23435), 17237 states have internal predecessors, (23435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:56,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17238 states to 17238 states and 23435 transitions. [2021-10-13 01:04:56,094 INFO L704 BuchiCegarLoop]: Abstraction has 17238 states and 23435 transitions. [2021-10-13 01:04:56,094 INFO L587 BuchiCegarLoop]: Abstraction has 17238 states and 23435 transitions. [2021-10-13 01:04:56,094 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-13 01:04:56,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17238 states and 23435 transitions. [2021-10-13 01:04:56,328 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2021-10-13 01:04:56,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:56,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:56,330 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:56,330 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:56,330 INFO L791 eck$LassoCheckResult]: Stem: 176116#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 176074#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 175937#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 175854#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 175855#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 175959#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 175960#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 175871#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 175779#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 175780#L418-1 assume !(0 == ~M_E~0); 176051#L578-1 assume !(0 == ~T1_E~0); 175815#L583-1 assume !(0 == ~T2_E~0); 175737#L588-1 assume !(0 == ~T3_E~0); 175661#L593-1 assume !(0 == ~T4_E~0); 175652#L598-1 assume !(0 == ~T5_E~0); 175653#L603-1 assume !(0 == ~E_1~0); 175872#L608-1 assume !(0 == ~E_2~0); 175728#L613-1 assume !(0 == ~E_3~0); 175729#L618-1 assume !(0 == ~E_4~0); 175844#L623-1 assume !(0 == ~E_5~0); 175994#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 176069#L271 assume !(1 == ~m_pc~0); 176019#L271-2 is_master_triggered_~__retres1~0 := 0; 176020#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 175884#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 175885#L712 assume !(0 != activate_threads_~tmp~1); 175988#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 175989#L290 assume !(1 == ~t1_pc~0); 175694#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 175695#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 175864#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 175865#L720 assume !(0 != activate_threads_~tmp___0~0); 175957#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 176099#L309 assume !(1 == ~t2_pc~0); 175850#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 176022#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 175843#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 175629#L728 assume !(0 != activate_threads_~tmp___1~0); 175630#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 175946#L328 assume !(1 == ~t3_pc~0); 176004#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 175733#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 175734#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 175804#L736 assume !(0 != activate_threads_~tmp___2~0); 175805#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 176083#L347 assume !(1 == ~t4_pc~0); 175631#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 175556#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 175557#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 175963#L744 assume !(0 != activate_threads_~tmp___3~0); 175964#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 175701#L366 assume !(1 == ~t5_pc~0); 175677#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 175678#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 176044#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 176005#L752 assume !(0 != activate_threads_~tmp___4~0); 175634#L752-2 assume !(1 == ~M_E~0); 175635#L641-1 assume !(1 == ~T1_E~0); 175649#L646-1 assume !(1 == ~T2_E~0); 175789#L651-1 assume !(1 == ~T3_E~0); 176056#L656-1 assume !(1 == ~T4_E~0); 176000#L661-1 assume !(1 == ~T5_E~0); 176001#L666-1 assume !(1 == ~E_1~0); 175965#L671-1 assume !(1 == ~E_2~0); 175747#L676-1 assume !(1 == ~E_3~0); 175748#L681-1 assume !(1 == ~E_4~0); 175880#L686-1 assume !(1 == ~E_5~0); 175881#L892-1 assume !false; 183548#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 183192#L553 [2021-10-13 01:04:56,330 INFO L793 eck$LassoCheckResult]: Loop: 183192#L553 assume !false; 183543#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 183540#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 183538#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 183536#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 183534#L478 assume 0 != eval_~tmp~0; 183533#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 183529#L486 assume !(0 != eval_~tmp_ndt_1~0); 183527#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 182756#L500 assume !(0 != eval_~tmp_ndt_2~0); 183526#L497 assume !(0 == ~t2_st~0); 183520#L511 assume !(0 == ~t3_st~0); 183200#L525 assume !(0 == ~t4_st~0); 183194#L539 assume !(0 == ~t5_st~0); 183192#L553 [2021-10-13 01:04:56,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:56,331 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 2 times [2021-10-13 01:04:56,331 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:56,331 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486692635] [2021-10-13 01:04:56,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:56,332 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:56,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:56,341 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:56,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:56,365 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:56,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:56,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896484, now seen corresponding path program 2 times [2021-10-13 01:04:56,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:56,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491704541] [2021-10-13 01:04:56,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:56,367 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:56,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:56,370 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:56,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:56,375 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:56,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:56,377 INFO L82 PathProgramCache]: Analyzing trace with hash -478639232, now seen corresponding path program 1 times [2021-10-13 01:04:56,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:56,377 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025814646] [2021-10-13 01:04:56,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:56,378 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:56,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:56,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:56,408 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:56,409 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025814646] [2021-10-13 01:04:56,409 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025814646] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:56,409 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:56,409 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:56,409 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339460984] [2021-10-13 01:04:56,525 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:56,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:56,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:56,525 INFO L87 Difference]: Start difference. First operand 17238 states and 23435 transitions. cyclomatic complexity: 6200 Second operand has 3 states, 3 states have (on average 27.666666666666668) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:56,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:56,676 INFO L93 Difference]: Finished difference Result 31478 states and 42667 transitions. [2021-10-13 01:04:56,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:56,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31478 states and 42667 transitions. [2021-10-13 01:04:56,956 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31372 [2021-10-13 01:04:57,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31478 states to 31478 states and 42667 transitions. [2021-10-13 01:04:57,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31478 [2021-10-13 01:04:57,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31478 [2021-10-13 01:04:57,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31478 states and 42667 transitions. [2021-10-13 01:04:57,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:57,125 INFO L681 BuchiCegarLoop]: Abstraction has 31478 states and 42667 transitions. [2021-10-13 01:04:57,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31478 states and 42667 transitions. [2021-10-13 01:04:57,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31478 to 30006. [2021-10-13 01:04:57,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30006 states, 30006 states have (on average 1.3579617409851363) internal successors, (40747), 30005 states have internal predecessors, (40747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:57,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30006 states to 30006 states and 40747 transitions. [2021-10-13 01:04:57,699 INFO L704 BuchiCegarLoop]: Abstraction has 30006 states and 40747 transitions. [2021-10-13 01:04:57,699 INFO L587 BuchiCegarLoop]: Abstraction has 30006 states and 40747 transitions. [2021-10-13 01:04:57,699 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-13 01:04:57,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30006 states and 40747 transitions. [2021-10-13 01:04:57,785 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 29900 [2021-10-13 01:04:57,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:04:57,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:04:57,787 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:57,787 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:04:57,787 INFO L791 eck$LassoCheckResult]: Stem: 224882#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 224837#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 224672#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 224583#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 224584#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224694#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224695#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224601#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224504#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224505#L418-1 assume !(0 == ~M_E~0); 224812#L578-1 assume !(0 == ~T1_E~0); 224541#L583-1 assume !(0 == ~T2_E~0); 224456#L588-1 assume !(0 == ~T3_E~0); 224385#L593-1 assume !(0 == ~T4_E~0); 224377#L598-1 assume !(0 == ~T5_E~0); 224378#L603-1 assume !(0 == ~E_1~0); 224602#L608-1 assume !(0 == ~E_2~0); 224447#L613-1 assume !(0 == ~E_3~0); 224448#L618-1 assume !(0 == ~E_4~0); 224571#L623-1 assume !(0 == ~E_5~0); 224737#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 224830#L271 assume !(1 == ~m_pc~0); 224765#L271-2 is_master_triggered_~__retres1~0 := 0; 224766#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 224615#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 224616#L712 assume !(0 != activate_threads_~tmp~1); 224728#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 224729#L290 assume !(1 == ~t1_pc~0); 224416#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 224417#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 224594#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 224595#L720 assume !(0 != activate_threads_~tmp___0~0); 224692#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224866#L309 assume !(1 == ~t2_pc~0); 224578#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 224768#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 224570#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 224353#L728 assume !(0 != activate_threads_~tmp___1~0); 224354#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 224682#L328 assume !(1 == ~t3_pc~0); 224748#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 224452#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224453#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 224528#L736 assume !(0 != activate_threads_~tmp___2~0); 224529#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 224849#L347 assume !(1 == ~t4_pc~0); 224355#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 224280#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 224281#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 224700#L744 assume !(0 != activate_threads_~tmp___3~0); 224701#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 224423#L366 assume !(1 == ~t5_pc~0); 224401#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 224402#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 224800#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 224749#L752 assume !(0 != activate_threads_~tmp___4~0); 224358#L752-2 assume !(1 == ~M_E~0); 224359#L641-1 assume !(1 == ~T1_E~0); 224374#L646-1 assume !(1 == ~T2_E~0); 224514#L651-1 assume !(1 == ~T3_E~0); 224818#L656-1 assume !(1 == ~T4_E~0); 224744#L661-1 assume !(1 == ~T5_E~0); 224745#L666-1 assume !(1 == ~E_1~0); 224702#L671-1 assume !(1 == ~E_2~0); 224467#L676-1 assume !(1 == ~E_3~0); 224468#L681-1 assume !(1 == ~E_4~0); 224611#L686-1 assume !(1 == ~E_5~0); 224612#L892-1 assume !false; 236253#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 236251#L553 [2021-10-13 01:04:57,787 INFO L793 eck$LassoCheckResult]: Loop: 236251#L553 assume !false; 236249#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 236246#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 236241#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 236239#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 236237#L478 assume 0 != eval_~tmp~0; 236234#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 236230#L486 assume !(0 != eval_~tmp_ndt_1~0); 229698#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 229697#L500 assume !(0 != eval_~tmp_ndt_2~0); 229696#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 229101#L514 assume !(0 != eval_~tmp_ndt_3~0); 229695#L511 assume !(0 == ~t3_st~0); 234667#L525 assume !(0 == ~t4_st~0); 236256#L539 assume !(0 == ~t5_st~0); 236251#L553 [2021-10-13 01:04:57,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:57,788 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 3 times [2021-10-13 01:04:57,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:57,788 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45094079] [2021-10-13 01:04:57,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:57,789 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:57,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:57,798 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:57,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:57,823 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:57,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:57,824 INFO L82 PathProgramCache]: Analyzing trace with hash 17875238, now seen corresponding path program 1 times [2021-10-13 01:04:57,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:57,824 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969236777] [2021-10-13 01:04:57,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:57,824 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:57,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:57,828 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:04:57,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:04:57,832 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:04:57,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:04:57,833 INFO L82 PathProgramCache]: Analyzing trace with hash -2120124406, now seen corresponding path program 1 times [2021-10-13 01:04:57,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:04:57,833 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856427245] [2021-10-13 01:04:57,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:04:57,834 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:04:57,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:04:57,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:04:57,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:04:57,864 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [856427245] [2021-10-13 01:04:57,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [856427245] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:04:57,864 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:04:57,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:04:57,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560220233] [2021-10-13 01:04:58,004 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:04:58,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:04:58,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:04:58,005 INFO L87 Difference]: Start difference. First operand 30006 states and 40747 transitions. cyclomatic complexity: 10744 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:04:58,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:04:58,436 INFO L93 Difference]: Finished difference Result 55798 states and 75547 transitions. [2021-10-13 01:04:58,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:04:58,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55798 states and 75547 transitions. [2021-10-13 01:04:58,682 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 55660 [2021-10-13 01:04:58,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55798 states to 55798 states and 75547 transitions. [2021-10-13 01:04:58,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55798 [2021-10-13 01:04:59,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55798 [2021-10-13 01:04:59,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55798 states and 75547 transitions. [2021-10-13 01:04:59,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:04:59,064 INFO L681 BuchiCegarLoop]: Abstraction has 55798 states and 75547 transitions. [2021-10-13 01:04:59,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55798 states and 75547 transitions. [2021-10-13 01:04:59,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55798 to 54742. [2021-10-13 01:04:59,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54742 states, 54742 states have (on average 1.3549194402835119) internal successors, (74171), 54741 states have internal predecessors, (74171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:05:00,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54742 states to 54742 states and 74171 transitions. [2021-10-13 01:05:00,027 INFO L704 BuchiCegarLoop]: Abstraction has 54742 states and 74171 transitions. [2021-10-13 01:05:00,027 INFO L587 BuchiCegarLoop]: Abstraction has 54742 states and 74171 transitions. [2021-10-13 01:05:00,027 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-13 01:05:00,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54742 states and 74171 transitions. [2021-10-13 01:05:00,189 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 54604 [2021-10-13 01:05:00,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:05:00,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:05:00,191 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:00,192 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:00,192 INFO L791 eck$LassoCheckResult]: Stem: 310707#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 310648#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 310484#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 310399#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 310400#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 310506#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 310507#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 310417#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 310320#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 310321#L418-1 assume !(0 == ~M_E~0); 310622#L578-1 assume !(0 == ~T1_E~0); 310357#L583-1 assume !(0 == ~T2_E~0); 310274#L588-1 assume !(0 == ~T3_E~0); 310196#L593-1 assume !(0 == ~T4_E~0); 310187#L598-1 assume !(0 == ~T5_E~0); 310188#L603-1 assume !(0 == ~E_1~0); 310418#L608-1 assume !(0 == ~E_2~0); 310265#L613-1 assume !(0 == ~E_3~0); 310266#L618-1 assume !(0 == ~E_4~0); 310387#L623-1 assume !(0 == ~E_5~0); 310542#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 310642#L271 assume !(1 == ~m_pc~0); 310570#L271-2 is_master_triggered_~__retres1~0 := 0; 310571#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 310432#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 310433#L712 assume !(0 != activate_threads_~tmp~1); 310533#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 310534#L290 assume !(1 == ~t1_pc~0); 310226#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 310227#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 310410#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 310411#L720 assume !(0 != activate_threads_~tmp___0~0); 310504#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 310686#L309 assume !(1 == ~t2_pc~0); 310392#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 310573#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 310386#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 310163#L728 assume !(0 != activate_threads_~tmp___1~0); 310164#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 310494#L328 assume !(1 == ~t3_pc~0); 310555#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 310270#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 310271#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 310347#L736 assume !(0 != activate_threads_~tmp___2~0); 310348#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 310663#L347 assume !(1 == ~t4_pc~0); 310165#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 310092#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 310093#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 310513#L744 assume !(0 != activate_threads_~tmp___3~0); 310514#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 310235#L366 assume !(1 == ~t5_pc~0); 310212#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 310213#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 310611#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 310556#L752 assume !(0 != activate_threads_~tmp___4~0); 310168#L752-2 assume !(1 == ~M_E~0); 310169#L641-1 assume !(1 == ~T1_E~0); 310184#L646-1 assume !(1 == ~T2_E~0); 310331#L651-1 assume !(1 == ~T3_E~0); 310628#L656-1 assume !(1 == ~T4_E~0); 310550#L661-1 assume !(1 == ~T5_E~0); 310551#L666-1 assume !(1 == ~E_1~0); 310515#L671-1 assume !(1 == ~E_2~0); 310284#L676-1 assume !(1 == ~E_3~0); 310285#L681-1 assume !(1 == ~E_4~0); 310428#L686-1 assume !(1 == ~E_5~0); 310429#L892-1 assume !false; 344155#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 327197#L553 [2021-10-13 01:05:00,192 INFO L793 eck$LassoCheckResult]: Loop: 327197#L553 assume !false; 344152#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 344151#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 344150#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 344149#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 344148#L478 assume 0 != eval_~tmp~0; 344142#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 344139#L486 assume !(0 != eval_~tmp_ndt_1~0); 344065#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 344062#L500 assume !(0 != eval_~tmp_ndt_2~0); 344060#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 344044#L514 assume !(0 != eval_~tmp_ndt_3~0); 327247#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 327245#L528 assume !(0 != eval_~tmp_ndt_4~0); 327204#L525 assume !(0 == ~t4_st~0); 327200#L539 assume !(0 == ~t5_st~0); 327197#L553 [2021-10-13 01:05:00,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:00,193 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 4 times [2021-10-13 01:05:00,193 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:00,193 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013023435] [2021-10-13 01:05:00,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:00,194 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:00,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:00,203 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:00,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:00,227 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:00,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:00,228 INFO L82 PathProgramCache]: Analyzing trace with hash 548744105, now seen corresponding path program 1 times [2021-10-13 01:05:00,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:00,228 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318500011] [2021-10-13 01:05:00,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:00,228 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:00,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:00,232 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:00,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:00,236 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:00,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:00,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1304735419, now seen corresponding path program 1 times [2021-10-13 01:05:00,237 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:00,237 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162802055] [2021-10-13 01:05:00,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:00,238 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:00,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:05:00,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:05:00,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:05:00,268 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162802055] [2021-10-13 01:05:00,268 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162802055] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:05:00,268 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:05:00,268 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-13 01:05:00,268 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188541750] [2021-10-13 01:05:00,430 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:05:00,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:05:00,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:05:00,431 INFO L87 Difference]: Start difference. First operand 54742 states and 74171 transitions. cyclomatic complexity: 19432 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:05:00,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:05:00,801 INFO L93 Difference]: Finished difference Result 95878 states and 129659 transitions. [2021-10-13 01:05:00,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:05:00,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95878 states and 129659 transitions. [2021-10-13 01:05:01,455 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 95676 [2021-10-13 01:05:01,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95878 states to 95878 states and 129659 transitions. [2021-10-13 01:05:01,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95878 [2021-10-13 01:05:01,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95878 [2021-10-13 01:05:01,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95878 states and 129659 transitions. [2021-10-13 01:05:01,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:05:01,809 INFO L681 BuchiCegarLoop]: Abstraction has 95878 states and 129659 transitions. [2021-10-13 01:05:01,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95878 states and 129659 transitions. [2021-10-13 01:05:02,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95878 to 93446. [2021-10-13 01:05:02,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93446 states, 93446 states have (on average 1.3560237998416198) internal successors, (126715), 93445 states have internal predecessors, (126715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:05:03,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93446 states to 93446 states and 126715 transitions. [2021-10-13 01:05:03,192 INFO L704 BuchiCegarLoop]: Abstraction has 93446 states and 126715 transitions. [2021-10-13 01:05:03,192 INFO L587 BuchiCegarLoop]: Abstraction has 93446 states and 126715 transitions. [2021-10-13 01:05:03,192 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-13 01:05:03,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93446 states and 126715 transitions. [2021-10-13 01:05:03,410 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 93244 [2021-10-13 01:05:03,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:05:03,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:05:03,411 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:03,412 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:03,412 INFO L791 eck$LassoCheckResult]: Stem: 461345#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 461286#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 461119#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 461026#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 461027#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 461145#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 461146#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 461047#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 460945#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 460946#L418-1 assume !(0 == ~M_E~0); 461264#L578-1 assume !(0 == ~T1_E~0); 460983#L583-1 assume !(0 == ~T2_E~0); 460900#L588-1 assume !(0 == ~T3_E~0); 460825#L593-1 assume !(0 == ~T4_E~0); 460815#L598-1 assume !(0 == ~T5_E~0); 460816#L603-1 assume !(0 == ~E_1~0); 461048#L608-1 assume !(0 == ~E_2~0); 460891#L613-1 assume !(0 == ~E_3~0); 460892#L618-1 assume !(0 == ~E_4~0); 461013#L623-1 assume !(0 == ~E_5~0); 461187#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 461280#L271 assume !(1 == ~m_pc~0); 461216#L271-2 is_master_triggered_~__retres1~0 := 0; 461217#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 461064#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 461065#L712 assume !(0 != activate_threads_~tmp~1); 461178#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 461179#L290 assume !(1 == ~t1_pc~0); 460856#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 460857#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 461039#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 461040#L720 assume !(0 != activate_threads_~tmp___0~0); 461142#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 461323#L309 assume !(1 == ~t2_pc~0); 461019#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 461220#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 461012#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 460791#L728 assume !(0 != activate_threads_~tmp___1~0); 460792#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 461130#L328 assume !(1 == ~t3_pc~0); 461197#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 460896#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 460897#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 460971#L736 assume !(0 != activate_threads_~tmp___2~0); 460972#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 461300#L347 assume !(1 == ~t4_pc~0); 460793#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 460720#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 460721#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 461152#L744 assume !(0 != activate_threads_~tmp___3~0); 461153#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 460864#L366 assume !(1 == ~t5_pc~0); 460842#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 460843#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 461251#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 461200#L752 assume !(0 != activate_threads_~tmp___4~0); 460796#L752-2 assume !(1 == ~M_E~0); 460797#L641-1 assume !(1 == ~T1_E~0); 460812#L646-1 assume !(1 == ~T2_E~0); 460955#L651-1 assume !(1 == ~T3_E~0); 461272#L656-1 assume !(1 == ~T4_E~0); 461193#L661-1 assume !(1 == ~T5_E~0); 461194#L666-1 assume !(1 == ~E_1~0); 461154#L671-1 assume !(1 == ~E_2~0); 460910#L676-1 assume !(1 == ~E_3~0); 460911#L681-1 assume !(1 == ~E_4~0); 461060#L686-1 assume !(1 == ~E_5~0); 461061#L892-1 assume !false; 479850#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 479849#L553 [2021-10-13 01:05:03,412 INFO L793 eck$LassoCheckResult]: Loop: 479849#L553 assume !false; 479848#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 479846#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 479845#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 479844#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 479843#L478 assume 0 != eval_~tmp~0; 479841#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 479839#L486 assume !(0 != eval_~tmp_ndt_1~0); 479838#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 478318#L500 assume !(0 != eval_~tmp_ndt_2~0); 479836#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 478821#L514 assume !(0 != eval_~tmp_ndt_3~0); 479834#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 478444#L528 assume !(0 != eval_~tmp_ndt_4~0); 479833#L525 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 479854#L542 assume !(0 != eval_~tmp_ndt_5~0); 479853#L539 assume !(0 == ~t5_st~0); 479849#L553 [2021-10-13 01:05:03,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:03,413 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 5 times [2021-10-13 01:05:03,413 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:03,413 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234277883] [2021-10-13 01:05:03,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:03,414 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:03,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:03,422 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:03,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:03,446 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:03,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:03,447 INFO L82 PathProgramCache]: Analyzing trace with hash -168970143, now seen corresponding path program 1 times [2021-10-13 01:05:03,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:03,447 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278424182] [2021-10-13 01:05:03,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:03,447 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:03,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:03,451 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:03,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:03,455 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:03,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:03,456 INFO L82 PathProgramCache]: Analyzing trace with hash -1792260539, now seen corresponding path program 1 times [2021-10-13 01:05:03,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:03,456 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003565055] [2021-10-13 01:05:03,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:03,456 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:03,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-13 01:05:03,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-13 01:05:03,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-13 01:05:03,482 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003565055] [2021-10-13 01:05:03,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003565055] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-13 01:05:03,483 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-13 01:05:03,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-13 01:05:03,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403163194] [2021-10-13 01:05:03,667 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-13 01:05:03,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-13 01:05:03,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-13 01:05:03,668 INFO L87 Difference]: Start difference. First operand 93446 states and 126715 transitions. cyclomatic complexity: 33272 Second operand has 3 states, 2 states have (on average 43.0) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:05:04,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-13 01:05:04,686 INFO L93 Difference]: Finished difference Result 179750 states and 243051 transitions. [2021-10-13 01:05:04,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-13 01:05:04,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179750 states and 243051 transitions. [2021-10-13 01:05:05,896 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 179420 [2021-10-13 01:05:06,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179750 states to 179750 states and 243051 transitions. [2021-10-13 01:05:06,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179750 [2021-10-13 01:05:06,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179750 [2021-10-13 01:05:06,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179750 states and 243051 transitions. [2021-10-13 01:05:06,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-13 01:05:06,416 INFO L681 BuchiCegarLoop]: Abstraction has 179750 states and 243051 transitions. [2021-10-13 01:05:06,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179750 states and 243051 transitions. [2021-10-13 01:05:08,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179750 to 179750. [2021-10-13 01:05:08,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179750 states, 179750 states have (on average 1.3521613351877608) internal successors, (243051), 179749 states have internal predecessors, (243051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-13 01:05:08,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179750 states to 179750 states and 243051 transitions. [2021-10-13 01:05:08,990 INFO L704 BuchiCegarLoop]: Abstraction has 179750 states and 243051 transitions. [2021-10-13 01:05:08,991 INFO L587 BuchiCegarLoop]: Abstraction has 179750 states and 243051 transitions. [2021-10-13 01:05:08,991 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-13 01:05:08,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179750 states and 243051 transitions. [2021-10-13 01:05:09,418 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 179420 [2021-10-13 01:05:09,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-13 01:05:09,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-13 01:05:09,419 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:09,419 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-13 01:05:09,419 INFO L791 eck$LassoCheckResult]: Stem: 734579#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 734514#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 734330#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 734237#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 734238#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 734355#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 734356#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 734256#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 734150#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 734151#L418-1 assume !(0 == ~M_E~0); 734485#L578-1 assume !(0 == ~T1_E~0); 734188#L583-1 assume !(0 == ~T2_E~0); 734106#L588-1 assume !(0 == ~T3_E~0); 734029#L593-1 assume !(0 == ~T4_E~0); 734020#L598-1 assume !(0 == ~T5_E~0); 734021#L603-1 assume !(0 == ~E_1~0); 734257#L608-1 assume !(0 == ~E_2~0); 734097#L613-1 assume !(0 == ~E_3~0); 734098#L618-1 assume !(0 == ~E_4~0); 734225#L623-1 assume !(0 == ~E_5~0); 734401#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 734506#L271 assume !(1 == ~m_pc~0); 734432#L271-2 is_master_triggered_~__retres1~0 := 0; 734433#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 734277#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 734278#L712 assume !(0 != activate_threads_~tmp~1); 734394#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 734395#L290 assume !(1 == ~t1_pc~0); 734058#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 734059#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 734250#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 734251#L720 assume !(0 != activate_threads_~tmp___0~0); 734354#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 734557#L309 assume !(1 == ~t2_pc~0); 734229#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 734435#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 734222#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 733997#L728 assume !(0 != activate_threads_~tmp___1~0); 733998#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 734343#L328 assume !(1 == ~t3_pc~0); 734414#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 734101#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 734102#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 734172#L736 assume !(0 != activate_threads_~tmp___2~0); 734173#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 734526#L347 assume !(1 == ~t4_pc~0); 733999#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 733924#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 733925#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 734362#L744 assume !(0 != activate_threads_~tmp___3~0); 734363#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 734066#L366 assume !(1 == ~t5_pc~0); 734043#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 734044#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 734472#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 734417#L752 assume !(0 != activate_threads_~tmp___4~0); 734002#L752-2 assume !(1 == ~M_E~0); 734003#L641-1 assume !(1 == ~T1_E~0); 734017#L646-1 assume !(1 == ~T2_E~0); 734158#L651-1 assume !(1 == ~T3_E~0); 734491#L656-1 assume !(1 == ~T4_E~0); 734410#L661-1 assume !(1 == ~T5_E~0); 734411#L666-1 assume !(1 == ~E_1~0); 734364#L671-1 assume !(1 == ~E_2~0); 734116#L676-1 assume !(1 == ~E_3~0); 734117#L681-1 assume !(1 == ~E_4~0); 734272#L686-1 assume !(1 == ~E_5~0); 734273#L892-1 assume !false; 767417#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 767416#L553 [2021-10-13 01:05:09,419 INFO L793 eck$LassoCheckResult]: Loop: 767416#L553 assume !false; 767415#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 767413#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 767412#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 767237#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 767236#L478 assume 0 != eval_~tmp~0; 767231#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 767228#L486 assume !(0 != eval_~tmp_ndt_1~0); 767195#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 767192#L500 assume !(0 != eval_~tmp_ndt_2~0); 766470#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 765750#L514 assume !(0 != eval_~tmp_ndt_3~0); 765748#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 765745#L528 assume !(0 != eval_~tmp_ndt_4~0); 765746#L525 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 767419#L542 assume !(0 != eval_~tmp_ndt_5~0); 767418#L539 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 764432#L556 assume !(0 != eval_~tmp_ndt_6~0); 767416#L553 [2021-10-13 01:05:09,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:09,420 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 6 times [2021-10-13 01:05:09,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:09,420 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122764848] [2021-10-13 01:05:09,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:09,421 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:09,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,428 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:09,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,448 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:09,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:09,449 INFO L82 PathProgramCache]: Analyzing trace with hash -943106962, now seen corresponding path program 1 times [2021-10-13 01:05:09,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:09,449 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127902681] [2021-10-13 01:05:09,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:09,450 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:09,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,453 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:09,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,457 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:09,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-13 01:05:09,457 INFO L82 PathProgramCache]: Analyzing trace with hash 274498314, now seen corresponding path program 1 times [2021-10-13 01:05:09,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-13 01:05:09,457 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418074964] [2021-10-13 01:05:09,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-13 01:05:09,458 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-13 01:05:09,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,466 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-13 01:05:09,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-13 01:05:09,493 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-13 01:05:12,421 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.10 01:05:12 BoogieIcfgContainer [2021-10-13 01:05:12,421 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-13 01:05:12,422 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-13 01:05:12,422 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-13 01:05:12,422 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-13 01:05:12,423 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 01:04:47" (3/4) ... [2021-10-13 01:05:12,425 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-13 01:05:12,504 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/witness.graphml [2021-10-13 01:05:12,504 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-13 01:05:12,506 INFO L168 Benchmark]: Toolchain (without parser) took 26876.82 ms. Allocated memory was 151.0 MB in the beginning and 12.7 GB in the end (delta: 12.5 GB). Free memory was 109.4 MB in the beginning and 10.8 GB in the end (delta: -10.7 GB). Peak memory consumption was 1.8 GB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,506 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 151.0 MB. Free memory is still 126.2 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-13 01:05:12,507 INFO L168 Benchmark]: CACSL2BoogieTranslator took 390.63 ms. Allocated memory is still 151.0 MB. Free memory was 109.1 MB in the beginning and 119.4 MB in the end (delta: -10.2 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,507 INFO L168 Benchmark]: Boogie Procedure Inliner took 118.21 ms. Allocated memory is still 151.0 MB. Free memory was 119.4 MB in the beginning and 114.7 MB in the end (delta: 4.7 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,508 INFO L168 Benchmark]: Boogie Preprocessor took 106.86 ms. Allocated memory is still 151.0 MB. Free memory was 114.7 MB in the beginning and 110.5 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,508 INFO L168 Benchmark]: RCFGBuilder took 1151.33 ms. Allocated memory is still 151.0 MB. Free memory was 110.0 MB in the beginning and 66.9 MB in the end (delta: 43.1 MB). Peak memory consumption was 44.0 MB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,508 INFO L168 Benchmark]: BuchiAutomizer took 25017.91 ms. Allocated memory was 151.0 MB in the beginning and 12.7 GB in the end (delta: 12.5 GB). Free memory was 66.9 MB in the beginning and 10.8 GB in the end (delta: -10.7 GB). Peak memory consumption was 2.1 GB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,509 INFO L168 Benchmark]: Witness Printer took 82.50 ms. Allocated memory is still 12.7 GB. Free memory was 10.8 GB in the beginning and 10.8 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-13 01:05:12,511 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 151.0 MB. Free memory is still 126.2 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 390.63 ms. Allocated memory is still 151.0 MB. Free memory was 109.1 MB in the beginning and 119.4 MB in the end (delta: -10.2 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 118.21 ms. Allocated memory is still 151.0 MB. Free memory was 119.4 MB in the beginning and 114.7 MB in the end (delta: 4.7 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 106.86 ms. Allocated memory is still 151.0 MB. Free memory was 114.7 MB in the beginning and 110.5 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1151.33 ms. Allocated memory is still 151.0 MB. Free memory was 110.0 MB in the beginning and 66.9 MB in the end (delta: 43.1 MB). Peak memory consumption was 44.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 25017.91 ms. Allocated memory was 151.0 MB in the beginning and 12.7 GB in the end (delta: 12.5 GB). Free memory was 66.9 MB in the beginning and 10.8 GB in the end (delta: -10.7 GB). Peak memory consumption was 2.1 GB. Max. memory is 16.1 GB. * Witness Printer took 82.50 ms. Allocated memory is still 12.7 GB. Free memory was 10.8 GB in the beginning and 10.8 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 179750 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 24.9s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 6.2s. Construction of modules took 0.6s. Büchi inclusion checks took 3.0s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 7672.3ms AutomataMinimizationTime, 23 MinimizatonAttempts, 20508 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 4.7s Buchi closure took 0.2s. Biggest automaton had 179750 states and ocurred in iteration 23. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 16835 SDtfs, 20965 SDslu, 16997 SDs, 0 SdLazy, 639 SolverSat, 302 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 671.8ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 473]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=12157} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=12157, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a28b5f6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39110d7a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@90b1ca3=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30f9ff73=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1a30d089=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fd77506=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e6fef82=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@656c796e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d4994ae=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@650bd8ac=0, NULL=12158, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f674360=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dc459c0=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, NULL=12160, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=12159, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2db31c3d=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f72b22f=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@53c98c75=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 473]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int t5_pc = 0; [L23] int m_st ; [L24] int t1_st ; [L25] int t2_st ; [L26] int t3_st ; [L27] int t4_st ; [L28] int t5_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L937] int __retres1 ; [L848] m_i = 1 [L849] t1_i = 1 [L850] t2_i = 1 [L851] t3_i = 1 [L852] t4_i = 1 [L853] t5_i = 1 [L878] int kernel_st ; [L879] int tmp ; [L880] int tmp___0 ; [L884] kernel_st = 0 [L393] COND TRUE m_i == 1 [L394] m_st = 0 [L398] COND TRUE t1_i == 1 [L399] t1_st = 0 [L403] COND TRUE t2_i == 1 [L404] t2_st = 0 [L408] COND TRUE t3_i == 1 [L409] t3_st = 0 [L413] COND TRUE t4_i == 1 [L414] t4_st = 0 [L418] COND TRUE t5_i == 1 [L419] t5_st = 0 [L578] COND FALSE !(M_E == 0) [L583] COND FALSE !(T1_E == 0) [L588] COND FALSE !(T2_E == 0) [L593] COND FALSE !(T3_E == 0) [L598] COND FALSE !(T4_E == 0) [L603] COND FALSE !(T5_E == 0) [L608] COND FALSE !(E_1 == 0) [L613] COND FALSE !(E_2 == 0) [L618] COND FALSE !(E_3 == 0) [L623] COND FALSE !(E_4 == 0) [L628] COND FALSE !(E_5 == 0) [L701] int tmp ; [L702] int tmp___0 ; [L703] int tmp___1 ; [L704] int tmp___2 ; [L705] int tmp___3 ; [L706] int tmp___4 ; [L268] int __retres1 ; [L271] COND FALSE !(m_pc == 1) [L281] __retres1 = 0 [L283] return (__retres1); [L710] tmp = is_master_triggered() [L712] COND FALSE !(\read(tmp)) [L287] int __retres1 ; [L290] COND FALSE !(t1_pc == 1) [L300] __retres1 = 0 [L302] return (__retres1); [L718] tmp___0 = is_transmit1_triggered() [L720] COND FALSE !(\read(tmp___0)) [L306] int __retres1 ; [L309] COND FALSE !(t2_pc == 1) [L319] __retres1 = 0 [L321] return (__retres1); [L726] tmp___1 = is_transmit2_triggered() [L728] COND FALSE !(\read(tmp___1)) [L325] int __retres1 ; [L328] COND FALSE !(t3_pc == 1) [L338] __retres1 = 0 [L340] return (__retres1); [L734] tmp___2 = is_transmit3_triggered() [L736] COND FALSE !(\read(tmp___2)) [L344] int __retres1 ; [L347] COND FALSE !(t4_pc == 1) [L357] __retres1 = 0 [L359] return (__retres1); [L742] tmp___3 = is_transmit4_triggered() [L744] COND FALSE !(\read(tmp___3)) [L363] int __retres1 ; [L366] COND FALSE !(t5_pc == 1) [L376] __retres1 = 0 [L378] return (__retres1); [L750] tmp___4 = is_transmit5_triggered() [L752] COND FALSE !(\read(tmp___4)) [L641] COND FALSE !(M_E == 1) [L646] COND FALSE !(T1_E == 1) [L651] COND FALSE !(T2_E == 1) [L656] COND FALSE !(T3_E == 1) [L661] COND FALSE !(T4_E == 1) [L666] COND FALSE !(T5_E == 1) [L671] COND FALSE !(E_1 == 1) [L676] COND FALSE !(E_2 == 1) [L681] COND FALSE !(E_3 == 1) [L686] COND FALSE !(E_4 == 1) [L691] COND FALSE !(E_5 == 1) [L892] COND TRUE 1 [L895] kernel_st = 1 [L469] int tmp ; Loop: [L473] COND TRUE 1 [L428] int __retres1 ; [L431] COND TRUE m_st == 0 [L432] __retres1 = 1 [L464] return (__retres1); [L476] tmp = exists_runnable_thread() [L478] COND TRUE \read(tmp) [L483] COND TRUE m_st == 0 [L484] int tmp_ndt_1; [L485] tmp_ndt_1 = __VERIFIER_nondet_int() [L486] COND FALSE !(\read(tmp_ndt_1)) [L497] COND TRUE t1_st == 0 [L498] int tmp_ndt_2; [L499] tmp_ndt_2 = __VERIFIER_nondet_int() [L500] COND FALSE !(\read(tmp_ndt_2)) [L511] COND TRUE t2_st == 0 [L512] int tmp_ndt_3; [L513] tmp_ndt_3 = __VERIFIER_nondet_int() [L514] COND FALSE !(\read(tmp_ndt_3)) [L525] COND TRUE t3_st == 0 [L526] int tmp_ndt_4; [L527] tmp_ndt_4 = __VERIFIER_nondet_int() [L528] COND FALSE !(\read(tmp_ndt_4)) [L539] COND TRUE t4_st == 0 [L540] int tmp_ndt_5; [L541] tmp_ndt_5 = __VERIFIER_nondet_int() [L542] COND FALSE !(\read(tmp_ndt_5)) [L553] COND TRUE t5_st == 0 [L554] int tmp_ndt_6; [L555] tmp_ndt_6 = __VERIFIER_nondet_int() [L556] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-13 01:05:12,579 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c2079e1c-c1dc-4916-a96c-dec6bda1075b/bin/uautomizer-WNIpwEf4Nt/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...