./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 57096758 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a08b839794d511e255b2cbb9b4715d014c32f56d .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-5709675 [2021-10-15 20:16:14,240 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-15 20:16:14,244 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-15 20:16:14,288 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-15 20:16:14,289 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-15 20:16:14,294 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-15 20:16:14,295 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-15 20:16:14,298 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-15 20:16:14,300 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-15 20:16:14,301 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-15 20:16:14,302 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-15 20:16:14,303 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-15 20:16:14,306 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-15 20:16:14,314 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-15 20:16:14,317 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-15 20:16:14,322 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-15 20:16:14,325 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-15 20:16:14,327 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-15 20:16:14,332 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-15 20:16:14,334 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-15 20:16:14,336 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-15 20:16:14,341 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-15 20:16:14,344 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-15 20:16:14,345 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-15 20:16:14,352 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-15 20:16:14,353 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-15 20:16:14,353 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-15 20:16:14,354 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-15 20:16:14,355 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-15 20:16:14,356 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-15 20:16:14,356 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-15 20:16:14,357 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-15 20:16:14,358 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-15 20:16:14,359 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-15 20:16:14,360 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-15 20:16:14,360 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-15 20:16:14,361 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-15 20:16:14,361 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-15 20:16:14,361 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-15 20:16:14,362 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-15 20:16:14,363 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-15 20:16:14,363 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-15 20:16:14,389 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-15 20:16:14,390 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-15 20:16:14,390 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-15 20:16:14,390 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-15 20:16:14,391 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-15 20:16:14,392 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-15 20:16:14,392 INFO L138 SettingsManager]: * Use SBE=true [2021-10-15 20:16:14,392 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-15 20:16:14,392 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-15 20:16:14,392 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-15 20:16:14,393 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-15 20:16:14,393 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-15 20:16:14,393 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-15 20:16:14,393 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-15 20:16:14,393 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-15 20:16:14,394 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-15 20:16:14,394 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-15 20:16:14,394 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-15 20:16:14,394 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-15 20:16:14,395 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-15 20:16:14,395 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-15 20:16:14,395 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-15 20:16:14,395 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-15 20:16:14,395 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-15 20:16:14,396 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-15 20:16:14,396 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-15 20:16:14,396 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-15 20:16:14,396 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-15 20:16:14,397 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-15 20:16:14,397 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-15 20:16:14,397 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-15 20:16:14,397 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-15 20:16:14,398 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-15 20:16:14,398 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a08b839794d511e255b2cbb9b4715d014c32f56d [2021-10-15 20:16:14,632 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-15 20:16:14,661 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-15 20:16:14,663 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-15 20:16:14,664 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-15 20:16:14,665 INFO L275 PluginConnector]: CDTParser initialized [2021-10-15 20:16:14,666 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-10-15 20:16:14,734 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/data/8bdaa0a98/b2e08187b54144a4938f05114c873433/FLAG3899eeba5 [2021-10-15 20:16:15,190 INFO L306 CDTParser]: Found 1 translation units. [2021-10-15 20:16:15,191 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-10-15 20:16:15,213 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/data/8bdaa0a98/b2e08187b54144a4938f05114c873433/FLAG3899eeba5 [2021-10-15 20:16:15,572 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/data/8bdaa0a98/b2e08187b54144a4938f05114c873433 [2021-10-15 20:16:15,574 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-15 20:16:15,576 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-15 20:16:15,593 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-15 20:16:15,594 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-15 20:16:15,596 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-15 20:16:15,596 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:15,597 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52bf0e4e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15, skipping insertion in model container [2021-10-15 20:16:15,597 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:15,603 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-15 20:16:15,631 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-15 20:16:15,801 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[366,379] [2021-10-15 20:16:15,859 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-15 20:16:15,876 INFO L203 MainTranslator]: Completed pre-run [2021-10-15 20:16:15,886 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[366,379] [2021-10-15 20:16:15,915 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-15 20:16:15,938 INFO L208 MainTranslator]: Completed translation [2021-10-15 20:16:15,939 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15 WrapperNode [2021-10-15 20:16:15,940 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-15 20:16:15,941 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-15 20:16:15,941 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-15 20:16:15,941 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-15 20:16:15,949 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:15,975 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,035 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-15 20:16:16,037 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-15 20:16:16,037 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-15 20:16:16,037 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-15 20:16:16,045 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,045 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,054 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,054 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,065 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,075 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,079 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,085 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-15 20:16:16,086 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-15 20:16:16,086 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-15 20:16:16,086 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-15 20:16:16,087 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (1/1) ... [2021-10-15 20:16:16,111 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-15 20:16:16,124 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/z3 [2021-10-15 20:16:16,135 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-15 20:16:16,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-15 20:16:16,178 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-15 20:16:16,178 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-15 20:16:16,178 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-15 20:16:16,178 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-15 20:16:16,929 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-15 20:16:16,929 INFO L299 CfgBuilder]: Removed 105 assume(true) statements. [2021-10-15 20:16:16,932 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 08:16:16 BoogieIcfgContainer [2021-10-15 20:16:16,932 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-15 20:16:16,933 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-15 20:16:16,933 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-15 20:16:16,951 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-15 20:16:16,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 20:16:16,952 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.10 08:16:15" (1/3) ... [2021-10-15 20:16:16,956 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18cd1f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 08:16:16, skipping insertion in model container [2021-10-15 20:16:16,956 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 20:16:16,956 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 08:16:15" (2/3) ... [2021-10-15 20:16:16,957 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18cd1f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 08:16:16, skipping insertion in model container [2021-10-15 20:16:16,957 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 20:16:16,957 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 08:16:16" (3/3) ... [2021-10-15 20:16:16,958 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2021-10-15 20:16:17,009 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-15 20:16:17,009 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-15 20:16:17,009 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-15 20:16:17,009 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-15 20:16:17,009 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-15 20:16:17,009 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-15 20:16:17,010 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-15 20:16:17,010 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-15 20:16:17,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 223 states, 222 states have (on average 1.5765765765765767) internal successors, (350), 222 states have internal predecessors, (350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 180 [2021-10-15 20:16:17,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:17,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:17,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,076 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-15 20:16:17,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 223 states, 222 states have (on average 1.5765765765765767) internal successors, (350), 222 states have internal predecessors, (350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 180 [2021-10-15 20:16:17,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:17,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:17,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,102 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,112 INFO L791 eck$LassoCheckResult]: Stem: 212#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 150#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 152#L520true havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 72#L228true assume !(1 == ~m_i~0);~m_st~0 := 2; 30#L235-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 98#L240-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 138#L245-1true assume !(0 == ~M_E~0); 189#L348-1true assume !(0 == ~T1_E~0); 106#L353-1true assume !(0 == ~T2_E~0); 158#L358-1true assume !(0 == ~E_M~0); 43#L363-1true assume !(0 == ~E_1~0); 200#L368-1true assume !(0 == ~E_2~0); 133#L373-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 166#L170true assume 1 == ~m_pc~0; 207#L171true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 80#L181true is_master_triggered_#res := is_master_triggered_~__retres1~0; 196#L182true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 175#L429true assume !(0 != activate_threads_~tmp~1); 42#L429-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74#L189true assume 1 == ~t1_pc~0; 162#L190true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 88#L200true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 164#L201true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 121#L437true assume !(0 != activate_threads_~tmp___0~0); 34#L437-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203#L208true assume !(1 == ~t2_pc~0); 204#L208-2true is_transmit2_triggered_~__retres1~2 := 0; 220#L219true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52#L220true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 31#L445true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 179#L445-2true assume !(1 == ~M_E~0); 151#L386-1true assume !(1 == ~T1_E~0); 107#L391-1true assume !(1 == ~T2_E~0); 24#L396-1true assume !(1 == ~E_M~0); 93#L401-1true assume 1 == ~E_1~0;~E_1~0 := 2; 100#L406-1true assume !(1 == ~E_2~0); 64#L557-1true [2021-10-15 20:16:17,122 INFO L793 eck$LassoCheckResult]: Loop: 64#L557-1true assume !false; 112#L558true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7#L323true assume false; 46#L338true start_simulation_~kernel_st~0 := 2; 49#L228-1true start_simulation_~kernel_st~0 := 3; 17#L348-2true assume 0 == ~M_E~0;~M_E~0 := 1; 214#L348-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 123#L353-3true assume !(0 == ~T2_E~0); 81#L358-3true assume 0 == ~E_M~0;~E_M~0 := 1; 120#L363-3true assume 0 == ~E_1~0;~E_1~0 := 1; 78#L368-3true assume 0 == ~E_2~0;~E_2~0 := 1; 60#L373-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 153#L170-12true assume 1 == ~m_pc~0; 183#L171-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 71#L181-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 68#L182-4true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 155#L429-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 217#L429-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32#L189-12true assume 1 == ~t1_pc~0; 145#L190-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 149#L200-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96#L201-4true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 182#L437-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 92#L437-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77#L208-12true assume 1 == ~t2_pc~0; 205#L209-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8#L219-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28#L220-4true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6#L445-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 54#L445-14true assume !(1 == ~M_E~0); 142#L386-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 225#L391-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 202#L396-3true assume 1 == ~E_M~0;~E_M~0 := 2; 201#L401-3true assume 1 == ~E_1~0;~E_1~0 := 2; 73#L406-3true assume 1 == ~E_2~0;~E_2~0 := 2; 139#L411-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15#L258-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 216#L275-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 148#L276-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 184#L576true assume !(0 == start_simulation_~tmp~3); 129#L576-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 171#L258-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 211#L275-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 90#L276-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 33#L531true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 94#L538true stop_simulation_#res := stop_simulation_~__retres2~0; 45#L539true start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 126#L589true assume !(0 != start_simulation_~tmp___0~1); 64#L557-1true [2021-10-15 20:16:17,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2021-10-15 20:16:17,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,138 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612012286] [2021-10-15 20:16:17,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,141 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,367 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612012286] [2021-10-15 20:16:17,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612012286] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,369 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:17,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845861818] [2021-10-15 20:16:17,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:17,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,383 INFO L82 PathProgramCache]: Analyzing trace with hash -2131780757, now seen corresponding path program 1 times [2021-10-15 20:16:17,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,384 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151028933] [2021-10-15 20:16:17,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,434 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151028933] [2021-10-15 20:16:17,435 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151028933] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,435 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 20:16:17,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348321660] [2021-10-15 20:16:17,437 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:17,444 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:17,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:17,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:17,462 INFO L87 Difference]: Start difference. First operand has 223 states, 222 states have (on average 1.5765765765765767) internal successors, (350), 222 states have internal predecessors, (350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:17,505 INFO L93 Difference]: Finished difference Result 223 states and 337 transitions. [2021-10-15 20:16:17,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:17,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 337 transitions. [2021-10-15 20:16:17,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2021-10-15 20:16:17,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 217 states and 331 transitions. [2021-10-15 20:16:17,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2021-10-15 20:16:17,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2021-10-15 20:16:17,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 331 transitions. [2021-10-15 20:16:17,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:17,529 INFO L681 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2021-10-15 20:16:17,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 331 transitions. [2021-10-15 20:16:17,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2021-10-15 20:16:17,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217 states, 217 states have (on average 1.5253456221198156) internal successors, (331), 216 states have internal predecessors, (331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 331 transitions. [2021-10-15 20:16:17,569 INFO L704 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2021-10-15 20:16:17,569 INFO L587 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2021-10-15 20:16:17,569 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-15 20:16:17,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 331 transitions. [2021-10-15 20:16:17,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2021-10-15 20:16:17,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:17,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:17,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,577 INFO L791 eck$LassoCheckResult]: Stem: 671#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 645#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 646#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 575#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 503#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 504#L240-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 604#L245-1 assume !(0 == ~M_E~0); 638#L348-1 assume !(0 == ~T1_E~0); 611#L353-1 assume !(0 == ~T2_E~0); 612#L358-1 assume !(0 == ~E_M~0); 528#L363-1 assume !(0 == ~E_1~0); 529#L368-1 assume !(0 == ~E_2~0); 633#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 634#L170 assume 1 == ~m_pc~0; 655#L171 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 585#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 586#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 659#L429 assume !(0 != activate_threads_~tmp~1); 526#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 527#L189 assume 1 == ~t1_pc~0; 578#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 523#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 596#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 625#L437 assume !(0 != activate_threads_~tmp___0~0); 512#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 513#L208 assume !(1 == ~t2_pc~0); 667#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 669#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 545#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 505#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 506#L445-2 assume !(1 == ~M_E~0); 647#L386-1 assume !(1 == ~T1_E~0); 613#L391-1 assume !(1 == ~T2_E~0); 495#L396-1 assume !(1 == ~E_M~0); 496#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 599#L406-1 assume !(1 == ~E_2~0); 564#L557-1 [2021-10-15 20:16:17,577 INFO L793 eck$LassoCheckResult]: Loop: 564#L557-1 assume !false; 565#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 464#L323 assume !false; 465#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 568#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 484#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 460#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 461#L290 assume !(0 != eval_~tmp~0); 534#L338 start_simulation_~kernel_st~0 := 2; 535#L228-1 start_simulation_~kernel_st~0 := 3; 485#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 486#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 626#L353-3 assume !(0 == ~T2_E~0); 587#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 588#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 582#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 557#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 558#L170-12 assume !(1 == ~m_pc~0); 632#L170-14 is_master_triggered_~__retres1~0 := 0; 574#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 569#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 570#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 651#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 507#L189-12 assume 1 == ~t1_pc~0; 508#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 635#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 602#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 603#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 598#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 579#L208-12 assume 1 == ~t2_pc~0; 580#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 466#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 467#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 462#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 463#L445-14 assume !(1 == ~M_E~0); 547#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 639#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 666#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 665#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 576#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 577#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 480#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 481#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 643#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 644#L576 assume !(0 == start_simulation_~tmp~3); 520#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 630#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 622#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 597#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 510#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 511#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 532#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 533#L589 assume !(0 != start_simulation_~tmp___0~1); 564#L557-1 [2021-10-15 20:16:17,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,578 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2021-10-15 20:16:17,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,578 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613051973] [2021-10-15 20:16:17,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,579 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,644 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,655 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613051973] [2021-10-15 20:16:17,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613051973] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,655 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:17,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745216084] [2021-10-15 20:16:17,656 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:17,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,656 INFO L82 PathProgramCache]: Analyzing trace with hash 1447847017, now seen corresponding path program 1 times [2021-10-15 20:16:17,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,657 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516179236] [2021-10-15 20:16:17,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,657 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,714 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516179236] [2021-10-15 20:16:17,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516179236] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,715 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,715 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:17,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522717807] [2021-10-15 20:16:17,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:17,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:17,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:17,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:17,717 INFO L87 Difference]: Start difference. First operand 217 states and 331 transitions. cyclomatic complexity: 115 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:17,736 INFO L93 Difference]: Finished difference Result 217 states and 330 transitions. [2021-10-15 20:16:17,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:17,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 330 transitions. [2021-10-15 20:16:17,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2021-10-15 20:16:17,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 217 states and 330 transitions. [2021-10-15 20:16:17,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2021-10-15 20:16:17,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2021-10-15 20:16:17,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 330 transitions. [2021-10-15 20:16:17,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:17,746 INFO L681 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2021-10-15 20:16:17,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 330 transitions. [2021-10-15 20:16:17,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2021-10-15 20:16:17,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217 states, 217 states have (on average 1.5207373271889402) internal successors, (330), 216 states have internal predecessors, (330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 330 transitions. [2021-10-15 20:16:17,758 INFO L704 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2021-10-15 20:16:17,759 INFO L587 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2021-10-15 20:16:17,759 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-15 20:16:17,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 330 transitions. [2021-10-15 20:16:17,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2021-10-15 20:16:17,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:17,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:17,763 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,763 INFO L791 eck$LassoCheckResult]: Stem: 1112#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1086#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1087#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1016#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 944#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 945#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1045#L245-1 assume !(0 == ~M_E~0); 1079#L348-1 assume !(0 == ~T1_E~0); 1052#L353-1 assume !(0 == ~T2_E~0); 1053#L358-1 assume !(0 == ~E_M~0); 969#L363-1 assume !(0 == ~E_1~0); 970#L368-1 assume !(0 == ~E_2~0); 1074#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1075#L170 assume 1 == ~m_pc~0; 1096#L171 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1026#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1027#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1100#L429 assume !(0 != activate_threads_~tmp~1); 967#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 968#L189 assume 1 == ~t1_pc~0; 1019#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 964#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1037#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1066#L437 assume !(0 != activate_threads_~tmp___0~0); 953#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 954#L208 assume !(1 == ~t2_pc~0); 1108#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 1110#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 986#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 946#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 947#L445-2 assume !(1 == ~M_E~0); 1088#L386-1 assume !(1 == ~T1_E~0); 1054#L391-1 assume !(1 == ~T2_E~0); 936#L396-1 assume !(1 == ~E_M~0); 937#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1040#L406-1 assume !(1 == ~E_2~0); 1005#L557-1 [2021-10-15 20:16:17,764 INFO L793 eck$LassoCheckResult]: Loop: 1005#L557-1 assume !false; 1006#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 905#L323 assume !false; 906#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1009#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 925#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 901#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 902#L290 assume !(0 != eval_~tmp~0); 975#L338 start_simulation_~kernel_st~0 := 2; 976#L228-1 start_simulation_~kernel_st~0 := 3; 926#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 927#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1067#L353-3 assume !(0 == ~T2_E~0); 1028#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1029#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1023#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 998#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 999#L170-12 assume !(1 == ~m_pc~0); 1073#L170-14 is_master_triggered_~__retres1~0 := 0; 1015#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1010#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1011#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1092#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 948#L189-12 assume 1 == ~t1_pc~0; 949#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1076#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1043#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1044#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1039#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1020#L208-12 assume 1 == ~t2_pc~0; 1021#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 907#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 908#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 903#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 904#L445-14 assume !(1 == ~M_E~0); 988#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1080#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1107#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1106#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1017#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1018#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 921#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 922#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1084#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1085#L576 assume !(0 == start_simulation_~tmp~3); 961#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1071#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1063#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1038#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 951#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 952#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 973#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 974#L589 assume !(0 != start_simulation_~tmp___0~1); 1005#L557-1 [2021-10-15 20:16:17,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2021-10-15 20:16:17,765 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,765 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156271289] [2021-10-15 20:16:17,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,765 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,811 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,811 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156271289] [2021-10-15 20:16:17,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156271289] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,812 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,812 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 20:16:17,812 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014404111] [2021-10-15 20:16:17,813 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:17,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,813 INFO L82 PathProgramCache]: Analyzing trace with hash 1447847017, now seen corresponding path program 2 times [2021-10-15 20:16:17,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,814 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297551617] [2021-10-15 20:16:17,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,814 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:17,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:17,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:17,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297551617] [2021-10-15 20:16:17,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297551617] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:17,857 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:17,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:17,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812216231] [2021-10-15 20:16:17,858 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:17,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:17,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:17,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:17,859 INFO L87 Difference]: Start difference. First operand 217 states and 330 transitions. cyclomatic complexity: 114 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:17,915 INFO L93 Difference]: Finished difference Result 382 states and 568 transitions. [2021-10-15 20:16:17,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:17,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 382 states and 568 transitions. [2021-10-15 20:16:17,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 343 [2021-10-15 20:16:17,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 382 states to 382 states and 568 transitions. [2021-10-15 20:16:17,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 382 [2021-10-15 20:16:17,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 382 [2021-10-15 20:16:17,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 382 states and 568 transitions. [2021-10-15 20:16:17,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:17,928 INFO L681 BuchiCegarLoop]: Abstraction has 382 states and 568 transitions. [2021-10-15 20:16:17,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states and 568 transitions. [2021-10-15 20:16:17,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 363. [2021-10-15 20:16:17,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 363 states, 363 states have (on average 1.4931129476584022) internal successors, (542), 362 states have internal predecessors, (542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:17,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 542 transitions. [2021-10-15 20:16:17,950 INFO L704 BuchiCegarLoop]: Abstraction has 363 states and 542 transitions. [2021-10-15 20:16:17,950 INFO L587 BuchiCegarLoop]: Abstraction has 363 states and 542 transitions. [2021-10-15 20:16:17,950 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-15 20:16:17,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 363 states and 542 transitions. [2021-10-15 20:16:17,953 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 324 [2021-10-15 20:16:17,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:17,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:17,955 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:17,956 INFO L791 eck$LassoCheckResult]: Stem: 1731#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1701#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1702#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1624#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 1550#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1551#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1653#L245-1 assume !(0 == ~M_E~0); 1694#L348-1 assume !(0 == ~T1_E~0); 1661#L353-1 assume !(0 == ~T2_E~0); 1662#L358-1 assume !(0 == ~E_M~0); 1575#L363-1 assume !(0 == ~E_1~0); 1576#L368-1 assume !(0 == ~E_2~0); 1686#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1687#L170 assume !(1 == ~m_pc~0); 1707#L170-2 is_master_triggered_~__retres1~0 := 0; 1634#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1635#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1713#L429 assume !(0 != activate_threads_~tmp~1); 1573#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1574#L189 assume 1 == ~t1_pc~0; 1627#L190 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1570#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1645#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1677#L437 assume !(0 != activate_threads_~tmp___0~0); 1559#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1560#L208 assume !(1 == ~t2_pc~0); 1727#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 1729#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1592#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1552#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1553#L445-2 assume !(1 == ~M_E~0); 1703#L386-1 assume !(1 == ~T1_E~0); 1663#L391-1 assume !(1 == ~T2_E~0); 1542#L396-1 assume !(1 == ~E_M~0); 1543#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1648#L406-1 assume !(1 == ~E_2~0); 1655#L557-1 [2021-10-15 20:16:17,956 INFO L793 eck$LassoCheckResult]: Loop: 1655#L557-1 assume !false; 1786#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1693#L323 assume !false; 1783#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1776#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1774#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1772#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1770#L290 assume !(0 != eval_~tmp~0); 1581#L338 start_simulation_~kernel_st~0 := 2; 1582#L228-1 start_simulation_~kernel_st~0 := 3; 1532#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1533#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1678#L353-3 assume !(0 == ~T2_E~0); 1636#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1637#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1631#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1605#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1606#L170-12 assume !(1 == ~m_pc~0); 1685#L170-14 is_master_triggered_~__retres1~0 := 0; 1623#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1618#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1619#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1706#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1554#L189-12 assume 1 == ~t1_pc~0; 1555#L190-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1688#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1651#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1652#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1647#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1628#L208-12 assume 1 == ~t2_pc~0; 1629#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1513#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1514#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1509#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1510#L445-14 assume !(1 == ~M_E~0); 1594#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1695#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1726#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1725#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1625#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1626#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1527#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1528#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1699#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1700#L576 assume !(0 == start_simulation_~tmp~3); 1716#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1822#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1820#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1818#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1816#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1814#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 1812#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1810#L589 assume !(0 != start_simulation_~tmp___0~1); 1655#L557-1 [2021-10-15 20:16:17,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:17,956 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2021-10-15 20:16:17,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:17,957 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633181342] [2021-10-15 20:16:17,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:17,957 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:17,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,045 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,045 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633181342] [2021-10-15 20:16:18,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633181342] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,046 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,046 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,046 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115081035] [2021-10-15 20:16:18,047 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:18,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,047 INFO L82 PathProgramCache]: Analyzing trace with hash 1447847017, now seen corresponding path program 3 times [2021-10-15 20:16:18,047 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,048 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153863238] [2021-10-15 20:16:18,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,048 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,081 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,081 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153863238] [2021-10-15 20:16:18,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153863238] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,081 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445819143] [2021-10-15 20:16:18,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:18,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:18,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-15 20:16:18,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-15 20:16:18,083 INFO L87 Difference]: Start difference. First operand 363 states and 542 transitions. cyclomatic complexity: 181 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:18,223 INFO L93 Difference]: Finished difference Result 802 states and 1173 transitions. [2021-10-15 20:16:18,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-15 20:16:18,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 802 states and 1173 transitions. [2021-10-15 20:16:18,233 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 737 [2021-10-15 20:16:18,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 802 states to 802 states and 1173 transitions. [2021-10-15 20:16:18,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 802 [2021-10-15 20:16:18,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 802 [2021-10-15 20:16:18,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 802 states and 1173 transitions. [2021-10-15 20:16:18,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:18,245 INFO L681 BuchiCegarLoop]: Abstraction has 802 states and 1173 transitions. [2021-10-15 20:16:18,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802 states and 1173 transitions. [2021-10-15 20:16:18,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802 to 633. [2021-10-15 20:16:18,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4802527646129542) internal successors, (937), 632 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 937 transitions. [2021-10-15 20:16:18,264 INFO L704 BuchiCegarLoop]: Abstraction has 633 states and 937 transitions. [2021-10-15 20:16:18,264 INFO L587 BuchiCegarLoop]: Abstraction has 633 states and 937 transitions. [2021-10-15 20:16:18,264 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-15 20:16:18,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 937 transitions. [2021-10-15 20:16:18,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 594 [2021-10-15 20:16:18,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:18,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:18,272 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,272 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,272 INFO L791 eck$LassoCheckResult]: Stem: 2918#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2879#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2880#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2798#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 2724#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2725#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2828#L245-1 assume !(0 == ~M_E~0); 2867#L348-1 assume !(0 == ~T1_E~0); 2835#L353-1 assume !(0 == ~T2_E~0); 2836#L358-1 assume !(0 == ~E_M~0); 2751#L363-1 assume !(0 == ~E_1~0); 2752#L368-1 assume !(0 == ~E_2~0); 2860#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2861#L170 assume !(1 == ~m_pc~0); 2886#L170-2 is_master_triggered_~__retres1~0 := 0; 2808#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2809#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2893#L429 assume !(0 != activate_threads_~tmp~1); 2747#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2748#L189 assume !(1 == ~t1_pc~0); 2743#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 2744#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2819#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2852#L437 assume !(0 != activate_threads_~tmp___0~0); 2732#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2733#L208 assume !(1 == ~t2_pc~0); 2913#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 2915#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2766#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2726#L445 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2727#L445-2 assume !(1 == ~M_E~0); 2881#L386-1 assume !(1 == ~T1_E~0); 2837#L391-1 assume !(1 == ~T2_E~0); 2718#L396-1 assume !(1 == ~E_M~0); 2719#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2822#L406-1 assume !(1 == ~E_2~0); 2787#L557-1 [2021-10-15 20:16:18,272 INFO L793 eck$LassoCheckResult]: Loop: 2787#L557-1 assume !false; 2788#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2685#L323 assume !false; 2686#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2789#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2705#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2683#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2684#L290 assume !(0 != eval_~tmp~0); 2755#L338 start_simulation_~kernel_st~0 := 2; 2756#L228-1 start_simulation_~kernel_st~0 := 3; 2708#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2709#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2853#L353-3 assume !(0 == ~T2_E~0); 2812#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2813#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2805#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2778#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2779#L170-12 assume !(1 == ~m_pc~0); 2859#L170-14 is_master_triggered_~__retres1~0 := 0; 2795#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2791#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2792#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2884#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2728#L189-12 assume !(1 == ~t1_pc~0); 2729#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 2862#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2826#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2827#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2821#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2802#L208-12 assume 1 == ~t2_pc~0; 2803#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2687#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2688#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2681#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2682#L445-14 assume !(1 == ~M_E~0); 2768#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2868#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2912#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2911#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2796#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2797#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2701#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2702#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2877#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2878#L576 assume !(0 == start_simulation_~tmp~3); 2740#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2857#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2848#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2820#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2730#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2731#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 2753#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2754#L589 assume !(0 != start_simulation_~tmp___0~1); 2787#L557-1 [2021-10-15 20:16:18,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,273 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2021-10-15 20:16:18,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,274 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811626410] [2021-10-15 20:16:18,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,274 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,319 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811626410] [2021-10-15 20:16:18,320 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811626410] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,320 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 20:16:18,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187980367] [2021-10-15 20:16:18,321 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:18,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1390702792, now seen corresponding path program 1 times [2021-10-15 20:16:18,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,322 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335854863] [2021-10-15 20:16:18,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,322 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,353 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335854863] [2021-10-15 20:16:18,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335854863] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,354 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,354 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700060618] [2021-10-15 20:16:18,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:18,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:18,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 20:16:18,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 20:16:18,356 INFO L87 Difference]: Start difference. First operand 633 states and 937 transitions. cyclomatic complexity: 306 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:18,473 INFO L93 Difference]: Finished difference Result 1484 states and 2208 transitions. [2021-10-15 20:16:18,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-15 20:16:18,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1484 states and 2208 transitions. [2021-10-15 20:16:18,491 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1426 [2021-10-15 20:16:18,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1484 states to 1484 states and 2208 transitions. [2021-10-15 20:16:18,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1484 [2021-10-15 20:16:18,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1484 [2021-10-15 20:16:18,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1484 states and 2208 transitions. [2021-10-15 20:16:18,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:18,509 INFO L681 BuchiCegarLoop]: Abstraction has 1484 states and 2208 transitions. [2021-10-15 20:16:18,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1484 states and 2208 transitions. [2021-10-15 20:16:18,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1484 to 684. [2021-10-15 20:16:18,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 684 states, 684 states have (on average 1.4444444444444444) internal successors, (988), 683 states have internal predecessors, (988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 988 transitions. [2021-10-15 20:16:18,550 INFO L704 BuchiCegarLoop]: Abstraction has 684 states and 988 transitions. [2021-10-15 20:16:18,550 INFO L587 BuchiCegarLoop]: Abstraction has 684 states and 988 transitions. [2021-10-15 20:16:18,550 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-15 20:16:18,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 684 states and 988 transitions. [2021-10-15 20:16:18,555 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2021-10-15 20:16:18,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:18,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:18,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,557 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,559 INFO L791 eck$LassoCheckResult]: Stem: 5068#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5016#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5017#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4931#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 4854#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4855#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4963#L245-1 assume !(0 == ~M_E~0); 5007#L348-1 assume !(0 == ~T1_E~0); 4972#L353-1 assume !(0 == ~T2_E~0); 4973#L358-1 assume !(0 == ~E_M~0); 4881#L363-1 assume !(0 == ~E_1~0); 4882#L368-1 assume !(0 == ~E_2~0); 4999#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5000#L170 assume !(1 == ~m_pc~0); 5024#L170-2 is_master_triggered_~__retres1~0 := 0; 4942#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4943#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5036#L429 assume !(0 != activate_threads_~tmp~1); 4877#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4878#L189 assume !(1 == ~t1_pc~0); 4873#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 4874#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4954#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4990#L437 assume !(0 != activate_threads_~tmp___0~0); 4862#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4863#L208 assume !(1 == ~t2_pc~0); 5062#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 5064#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5070#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4856#L445 assume !(0 != activate_threads_~tmp___1~0); 4857#L445-2 assume !(1 == ~M_E~0); 5018#L386-1 assume !(1 == ~T1_E~0); 4974#L391-1 assume !(1 == ~T2_E~0); 4847#L396-1 assume !(1 == ~E_M~0); 4848#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4958#L406-1 assume !(1 == ~E_2~0); 4965#L557-1 [2021-10-15 20:16:18,560 INFO L793 eck$LassoCheckResult]: Loop: 4965#L557-1 assume !false; 5213#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5142#L323 assume !false; 5186#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5178#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5170#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5167#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5163#L290 assume !(0 != eval_~tmp~0); 5164#L338 start_simulation_~kernel_st~0 := 2; 5433#L228-1 start_simulation_~kernel_st~0 := 3; 5431#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5429#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5427#L353-3 assume !(0 == ~T2_E~0); 5425#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5423#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5422#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5418#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5417#L170-12 assume !(1 == ~m_pc~0); 5416#L170-14 is_master_triggered_~__retres1~0 := 0; 5415#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5414#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5022#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5023#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4858#L189-12 assume !(1 == ~t1_pc~0); 4859#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 5447#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5446#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5445#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5444#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4935#L208-12 assume 1 == ~t2_pc~0; 4936#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4817#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4818#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5471#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4812#L445-14 assume !(1 == ~M_E~0); 4899#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5008#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5061#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5060#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4929#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4930#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4830#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4831#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5014#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5015#L576 assume !(0 == start_simulation_~tmp~3); 4870#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4994#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5284#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5280#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 5246#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5240#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 5231#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 5217#L589 assume !(0 != start_simulation_~tmp___0~1); 4965#L557-1 [2021-10-15 20:16:18,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,560 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330394, now seen corresponding path program 1 times [2021-10-15 20:16:18,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,561 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139439655] [2021-10-15 20:16:18,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,561 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,638 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,638 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139439655] [2021-10-15 20:16:18,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139439655] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,639 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,639 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,639 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519227682] [2021-10-15 20:16:18,640 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:18,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,640 INFO L82 PathProgramCache]: Analyzing trace with hash 1390702792, now seen corresponding path program 2 times [2021-10-15 20:16:18,640 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,641 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529698841] [2021-10-15 20:16:18,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,643 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,678 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,678 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529698841] [2021-10-15 20:16:18,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529698841] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,678 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,678 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,679 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941091710] [2021-10-15 20:16:18,679 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:18,679 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:18,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-15 20:16:18,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-15 20:16:18,680 INFO L87 Difference]: Start difference. First operand 684 states and 988 transitions. cyclomatic complexity: 306 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:18,800 INFO L93 Difference]: Finished difference Result 1112 states and 1576 transitions. [2021-10-15 20:16:18,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-15 20:16:18,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1112 states and 1576 transitions. [2021-10-15 20:16:18,810 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1004 [2021-10-15 20:16:18,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1112 states to 1112 states and 1576 transitions. [2021-10-15 20:16:18,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1112 [2021-10-15 20:16:18,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1112 [2021-10-15 20:16:18,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1112 states and 1576 transitions. [2021-10-15 20:16:18,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:18,837 INFO L681 BuchiCegarLoop]: Abstraction has 1112 states and 1576 transitions. [2021-10-15 20:16:18,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1112 states and 1576 transitions. [2021-10-15 20:16:18,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1112 to 1090. [2021-10-15 20:16:18,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1090 states, 1090 states have (on average 1.4220183486238531) internal successors, (1550), 1089 states have internal predecessors, (1550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1090 states to 1090 states and 1550 transitions. [2021-10-15 20:16:18,861 INFO L704 BuchiCegarLoop]: Abstraction has 1090 states and 1550 transitions. [2021-10-15 20:16:18,861 INFO L587 BuchiCegarLoop]: Abstraction has 1090 states and 1550 transitions. [2021-10-15 20:16:18,861 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-15 20:16:18,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1090 states and 1550 transitions. [2021-10-15 20:16:18,868 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 990 [2021-10-15 20:16:18,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:18,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:18,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,871 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:18,871 INFO L791 eck$LassoCheckResult]: Stem: 6890#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6829#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6830#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6736#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 6660#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6661#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6769#L245-1 assume !(0 == ~M_E~0); 6818#L348-1 assume !(0 == ~T1_E~0); 6778#L353-1 assume !(0 == ~T2_E~0); 6779#L358-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6839#L363-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6687#L368-1 assume !(0 == ~E_2~0); 7263#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7262#L170 assume !(1 == ~m_pc~0); 7261#L170-2 is_master_triggered_~__retres1~0 := 0; 7260#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7259#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7256#L429 assume !(0 != activate_threads_~tmp~1); 7252#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7249#L189 assume !(1 == ~t1_pc~0); 7246#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 7242#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7237#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7233#L437 assume !(0 != activate_threads_~tmp___0~0); 7220#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7216#L208 assume !(1 == ~t2_pc~0); 7210#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 7205#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7200#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7184#L445 assume !(0 != activate_threads_~tmp___1~0); 7182#L445-2 assume !(1 == ~M_E~0); 7180#L386-1 assume !(1 == ~T1_E~0); 7178#L391-1 assume !(1 == ~T2_E~0); 7173#L396-1 assume !(1 == ~E_M~0); 7168#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6763#L406-1 assume !(1 == ~E_2~0); 6771#L557-1 [2021-10-15 20:16:18,872 INFO L793 eck$LassoCheckResult]: Loop: 6771#L557-1 assume !false; 7322#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7284#L323 assume !false; 6726#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6727#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7311#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7309#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7307#L290 assume !(0 != eval_~tmp~0); 7308#L338 start_simulation_~kernel_st~0 := 2; 7691#L228-1 start_simulation_~kernel_st~0 := 3; 7690#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7689#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7688#L353-3 assume !(0 == ~T2_E~0); 7687#L358-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6749#L363-3 assume !(0 == ~E_1~0); 7686#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7684#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7683#L170-12 assume !(1 == ~m_pc~0); 7682#L170-14 is_master_triggered_~__retres1~0 := 0; 7681#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7679#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7677#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6891#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6892#L189-12 assume !(1 == ~t1_pc~0); 7457#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 7455#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7453#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7451#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7450#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7449#L208-12 assume !(1 == ~t2_pc~0); 7447#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 7445#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7443#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7442#L445-12 assume !(0 != activate_threads_~tmp___1~0); 7440#L445-14 assume !(1 == ~M_E~0); 7439#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7438#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7437#L396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7436#L401-3 assume !(1 == ~E_1~0); 7349#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7435#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7429#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7426#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7424#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7422#L576 assume !(0 == start_simulation_~tmp~3); 7333#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7331#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7329#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7328#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 7327#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7326#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 7325#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7324#L589 assume !(0 != start_simulation_~tmp___0~1); 6771#L557-1 [2021-10-15 20:16:18,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,872 INFO L82 PathProgramCache]: Analyzing trace with hash 335369254, now seen corresponding path program 1 times [2021-10-15 20:16:18,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,873 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083258286] [2021-10-15 20:16:18,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,874 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,906 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,906 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083258286] [2021-10-15 20:16:18,906 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083258286] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,906 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 20:16:18,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561668193] [2021-10-15 20:16:18,907 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:18,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:18,908 INFO L82 PathProgramCache]: Analyzing trace with hash 152395817, now seen corresponding path program 1 times [2021-10-15 20:16:18,908 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:18,908 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598335863] [2021-10-15 20:16:18,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:18,909 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:18,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:18,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:18,955 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:18,955 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598335863] [2021-10-15 20:16:18,955 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598335863] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:18,955 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:18,956 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:18,956 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977847791] [2021-10-15 20:16:18,956 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:18,956 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:18,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:18,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:18,957 INFO L87 Difference]: Start difference. First operand 1090 states and 1550 transitions. cyclomatic complexity: 463 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:18,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:18,985 INFO L93 Difference]: Finished difference Result 1061 states and 1481 transitions. [2021-10-15 20:16:18,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:18,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1061 states and 1481 transitions. [2021-10-15 20:16:18,994 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 990 [2021-10-15 20:16:19,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1061 states to 1061 states and 1481 transitions. [2021-10-15 20:16:19,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1061 [2021-10-15 20:16:19,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1061 [2021-10-15 20:16:19,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1061 states and 1481 transitions. [2021-10-15 20:16:19,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,006 INFO L681 BuchiCegarLoop]: Abstraction has 1061 states and 1481 transitions. [2021-10-15 20:16:19,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1061 states and 1481 transitions. [2021-10-15 20:16:19,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1061 to 826. [2021-10-15 20:16:19,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 826 states, 826 states have (on average 1.3898305084745763) internal successors, (1148), 825 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 826 states to 826 states and 1148 transitions. [2021-10-15 20:16:19,024 INFO L704 BuchiCegarLoop]: Abstraction has 826 states and 1148 transitions. [2021-10-15 20:16:19,024 INFO L587 BuchiCegarLoop]: Abstraction has 826 states and 1148 transitions. [2021-10-15 20:16:19,024 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-15 20:16:19,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 826 states and 1148 transitions. [2021-10-15 20:16:19,044 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 756 [2021-10-15 20:16:19,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,046 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,046 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,048 INFO L791 eck$LassoCheckResult]: Stem: 9014#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8974#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8975#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8893#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 8820#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8821#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8922#L245-1 assume !(0 == ~M_E~0); 8963#L348-1 assume !(0 == ~T1_E~0); 8930#L353-1 assume !(0 == ~T2_E~0); 8931#L358-1 assume !(0 == ~E_M~0); 8846#L363-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8847#L368-1 assume !(0 == ~E_2~0); 9264#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9260#L170 assume !(1 == ~m_pc~0); 9258#L170-2 is_master_triggered_~__retres1~0 := 0; 9256#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9254#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9251#L429 assume !(0 != activate_threads_~tmp~1); 9249#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9247#L189 assume !(1 == ~t1_pc~0); 9245#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 9243#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9242#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9241#L437 assume !(0 != activate_threads_~tmp___0~0); 9240#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9238#L208 assume !(1 == ~t2_pc~0); 9236#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 9239#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9237#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9230#L445 assume !(0 != activate_threads_~tmp___1~0); 9229#L445-2 assume !(1 == ~M_E~0); 9228#L386-1 assume !(1 == ~T1_E~0); 9227#L391-1 assume !(1 == ~T2_E~0); 9226#L396-1 assume !(1 == ~E_M~0); 9225#L401-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8916#L406-1 assume !(1 == ~E_2~0); 8924#L557-1 [2021-10-15 20:16:19,048 INFO L793 eck$LassoCheckResult]: Loop: 8924#L557-1 assume !false; 9323#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9322#L323 assume !false; 9321#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9316#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9315#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8777#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 8778#L290 assume !(0 != eval_~tmp~0); 8851#L338 start_simulation_~kernel_st~0 := 2; 8852#L228-1 start_simulation_~kernel_st~0 := 3; 8800#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8801#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8948#L353-3 assume !(0 == ~T2_E~0); 8903#L358-3 assume !(0 == ~E_M~0); 8904#L363-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8946#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9586#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9585#L170-12 assume !(1 == ~m_pc~0); 9584#L170-14 is_master_triggered_~__retres1~0 := 0; 9583#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9582#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9581#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9580#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8824#L189-12 assume !(1 == ~t1_pc~0); 8825#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 9441#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9437#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9433#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9426#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9424#L208-12 assume 1 == ~t2_pc~0; 9422#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9420#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9418#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9415#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9401#L445-14 assume !(1 == ~M_E~0); 9400#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9399#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9398#L396-3 assume !(1 == ~E_M~0); 9361#L401-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9359#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9358#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9356#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9353#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9351#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9348#L576 assume !(0 == start_simulation_~tmp~3); 9346#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9344#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9342#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9338#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 9337#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9335#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 9333#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 9332#L589 assume !(0 != start_simulation_~tmp___0~1); 8924#L557-1 [2021-10-15 20:16:19,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,048 INFO L82 PathProgramCache]: Analyzing trace with hash -2036370008, now seen corresponding path program 1 times [2021-10-15 20:16:19,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,049 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133226698] [2021-10-15 20:16:19,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,049 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,105 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133226698] [2021-10-15 20:16:19,106 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133226698] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,106 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,106 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:19,106 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641094307] [2021-10-15 20:16:19,106 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:19,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,107 INFO L82 PathProgramCache]: Analyzing trace with hash -1002172860, now seen corresponding path program 1 times [2021-10-15 20:16:19,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418887982] [2021-10-15 20:16:19,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,108 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,135 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418887982] [2021-10-15 20:16:19,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418887982] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,142 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:19,142 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411758148] [2021-10-15 20:16:19,143 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,143 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-15 20:16:19,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-15 20:16:19,145 INFO L87 Difference]: Start difference. First operand 826 states and 1148 transitions. cyclomatic complexity: 324 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:19,209 INFO L93 Difference]: Finished difference Result 926 states and 1282 transitions. [2021-10-15 20:16:19,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-15 20:16:19,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 926 states and 1282 transitions. [2021-10-15 20:16:19,217 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 876 [2021-10-15 20:16:19,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 926 states to 926 states and 1282 transitions. [2021-10-15 20:16:19,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 926 [2021-10-15 20:16:19,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 926 [2021-10-15 20:16:19,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 926 states and 1282 transitions. [2021-10-15 20:16:19,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,232 INFO L681 BuchiCegarLoop]: Abstraction has 926 states and 1282 transitions. [2021-10-15 20:16:19,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 926 states and 1282 transitions. [2021-10-15 20:16:19,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 926 to 684. [2021-10-15 20:16:19,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 684 states, 684 states have (on average 1.381578947368421) internal successors, (945), 683 states have internal predecessors, (945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 945 transitions. [2021-10-15 20:16:19,248 INFO L704 BuchiCegarLoop]: Abstraction has 684 states and 945 transitions. [2021-10-15 20:16:19,248 INFO L587 BuchiCegarLoop]: Abstraction has 684 states and 945 transitions. [2021-10-15 20:16:19,248 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-15 20:16:19,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 684 states and 945 transitions. [2021-10-15 20:16:19,252 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2021-10-15 20:16:19,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,253 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,253 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,253 INFO L791 eck$LassoCheckResult]: Stem: 10778#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10741#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10742#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10655#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 10581#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10582#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10683#L245-1 assume !(0 == ~M_E~0); 10729#L348-1 assume !(0 == ~T1_E~0); 10692#L353-1 assume !(0 == ~T2_E~0); 10693#L358-1 assume !(0 == ~E_M~0); 10607#L363-1 assume !(0 == ~E_1~0); 10608#L368-1 assume !(0 == ~E_2~0); 10719#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10720#L170 assume !(1 == ~m_pc~0); 10748#L170-2 is_master_triggered_~__retres1~0 := 0; 10663#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10664#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10755#L429 assume !(0 != activate_threads_~tmp~1); 10603#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10604#L189 assume !(1 == ~t1_pc~0); 10599#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 10600#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10675#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10710#L437 assume !(0 != activate_threads_~tmp___0~0); 10589#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10590#L208 assume !(1 == ~t2_pc~0); 10772#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 10774#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10622#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10583#L445 assume !(0 != activate_threads_~tmp___1~0); 10584#L445-2 assume !(1 == ~M_E~0); 10743#L386-1 assume !(1 == ~T1_E~0); 10694#L391-1 assume !(1 == ~T2_E~0); 10572#L396-1 assume !(1 == ~E_M~0); 10573#L401-1 assume !(1 == ~E_1~0); 10678#L406-1 assume !(1 == ~E_2~0); 10642#L557-1 [2021-10-15 20:16:19,253 INFO L793 eck$LassoCheckResult]: Loop: 10642#L557-1 assume !false; 10643#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10541#L323 assume !false; 10542#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10646#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10560#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10539#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 10540#L290 assume !(0 != eval_~tmp~0); 10696#L338 start_simulation_~kernel_st~0 := 2; 11172#L228-1 start_simulation_~kernel_st~0 := 3; 11168#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11166#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11164#L353-3 assume !(0 == ~T2_E~0); 11162#L358-3 assume !(0 == ~E_M~0); 11160#L363-3 assume !(0 == ~E_1~0); 11159#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11156#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11154#L170-12 assume !(1 == ~m_pc~0); 11152#L170-14 is_master_triggered_~__retres1~0 := 0; 11149#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11146#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10746#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10747#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10585#L189-12 assume !(1 == ~t1_pc~0); 10586#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 11210#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11209#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11208#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11207#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11206#L208-12 assume !(1 == ~t2_pc~0); 11204#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 11202#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11200#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11199#L445-12 assume !(0 != activate_threads_~tmp___1~0); 11197#L445-14 assume !(1 == ~M_E~0); 11196#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11195#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11194#L396-3 assume !(1 == ~E_M~0); 11193#L401-3 assume !(1 == ~E_1~0); 11192#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11191#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10556#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10557#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10739#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 10740#L576 assume !(0 == start_simulation_~tmp~3); 10597#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10714#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10704#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10676#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 10587#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10588#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 10609#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10610#L589 assume !(0 != start_simulation_~tmp___0~1); 10642#L557-1 [2021-10-15 20:16:19,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,254 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2021-10-15 20:16:19,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,254 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829387967] [2021-10-15 20:16:19,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,254 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,271 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:19,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,319 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:19,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,320 INFO L82 PathProgramCache]: Analyzing trace with hash 2054487461, now seen corresponding path program 1 times [2021-10-15 20:16:19,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175940663] [2021-10-15 20:16:19,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,321 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175940663] [2021-10-15 20:16:19,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175940663] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,343 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,343 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:19,344 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139398261] [2021-10-15 20:16:19,344 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,344 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:19,345 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:19,345 INFO L87 Difference]: Start difference. First operand 684 states and 945 transitions. cyclomatic complexity: 263 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:19,365 INFO L93 Difference]: Finished difference Result 828 states and 1129 transitions. [2021-10-15 20:16:19,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:19,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 828 states and 1129 transitions. [2021-10-15 20:16:19,372 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 758 [2021-10-15 20:16:19,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 828 states to 828 states and 1129 transitions. [2021-10-15 20:16:19,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 828 [2021-10-15 20:16:19,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 828 [2021-10-15 20:16:19,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 828 states and 1129 transitions. [2021-10-15 20:16:19,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,381 INFO L681 BuchiCegarLoop]: Abstraction has 828 states and 1129 transitions. [2021-10-15 20:16:19,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 828 states and 1129 transitions. [2021-10-15 20:16:19,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 828 to 828. [2021-10-15 20:16:19,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 828 states, 828 states have (on average 1.3635265700483092) internal successors, (1129), 827 states have internal predecessors, (1129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 828 states to 828 states and 1129 transitions. [2021-10-15 20:16:19,396 INFO L704 BuchiCegarLoop]: Abstraction has 828 states and 1129 transitions. [2021-10-15 20:16:19,397 INFO L587 BuchiCegarLoop]: Abstraction has 828 states and 1129 transitions. [2021-10-15 20:16:19,397 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-15 20:16:19,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 828 states and 1129 transitions. [2021-10-15 20:16:19,401 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 758 [2021-10-15 20:16:19,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,402 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,403 INFO L791 eck$LassoCheckResult]: Stem: 12292#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12254#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12255#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12171#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 12100#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12101#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12201#L245-1 assume 0 == ~M_E~0;~M_E~0 := 1; 12243#L348-1 assume !(0 == ~T1_E~0); 12209#L353-1 assume !(0 == ~T2_E~0); 12210#L358-1 assume !(0 == ~E_M~0); 12124#L363-1 assume !(0 == ~E_1~0); 12125#L368-1 assume !(0 == ~E_2~0); 12235#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12236#L170 assume !(1 == ~m_pc~0); 12261#L170-2 is_master_triggered_~__retres1~0 := 0; 12181#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12182#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12269#L429 assume !(0 != activate_threads_~tmp~1); 12122#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12123#L189 assume !(1 == ~t1_pc~0); 12118#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 12119#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12193#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12227#L437 assume !(0 != activate_threads_~tmp___0~0); 12108#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12109#L208 assume !(1 == ~t2_pc~0); 12286#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 12288#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12141#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12102#L445 assume !(0 != activate_threads_~tmp___1~0); 12103#L445-2 assume 1 == ~M_E~0;~M_E~0 := 2; 12256#L386-1 assume !(1 == ~T1_E~0); 12211#L391-1 assume !(1 == ~T2_E~0); 12091#L396-1 assume !(1 == ~E_M~0); 12092#L401-1 assume !(1 == ~E_1~0); 12196#L406-1 assume !(1 == ~E_2~0); 12160#L557-1 [2021-10-15 20:16:19,403 INFO L793 eck$LassoCheckResult]: Loop: 12160#L557-1 assume !false; 12161#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12059#L323 assume !false; 12060#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12164#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12078#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12055#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12056#L290 assume !(0 != eval_~tmp~0); 12213#L338 start_simulation_~kernel_st~0 := 2; 12852#L228-1 start_simulation_~kernel_st~0 := 3; 12849#L348-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12850#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12876#L353-3 assume !(0 == ~T2_E~0); 12875#L358-3 assume !(0 == ~E_M~0); 12868#L363-3 assume !(0 == ~E_1~0); 12178#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12154#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12155#L170-12 assume !(1 == ~m_pc~0); 12257#L170-14 is_master_triggered_~__retres1~0 := 0; 12872#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12871#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12870#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12869#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12701#L189-12 assume !(1 == ~t1_pc~0); 12697#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 12695#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12693#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12691#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12688#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12687#L208-12 assume !(1 == ~t2_pc~0); 12685#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 12683#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12681#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12680#L445-12 assume !(0 != activate_threads_~tmp___1~0); 12678#L445-14 assume 1 == ~M_E~0;~M_E~0 := 2; 12675#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12673#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12671#L396-3 assume !(1 == ~E_M~0); 12669#L401-3 assume !(1 == ~E_1~0); 12664#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12657#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12652#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12646#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12641#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12634#L576 assume !(0 == start_simulation_~tmp~3); 12630#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12595#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12291#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12194#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 12106#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12107#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 12128#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 12129#L589 assume !(0 != start_simulation_~tmp___0~1); 12160#L557-1 [2021-10-15 20:16:19,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,404 INFO L82 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2021-10-15 20:16:19,404 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,404 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120610463] [2021-10-15 20:16:19,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,405 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,423 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120610463] [2021-10-15 20:16:19,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [120610463] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,423 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 20:16:19,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578988486] [2021-10-15 20:16:19,424 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:19,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,424 INFO L82 PathProgramCache]: Analyzing trace with hash -551536093, now seen corresponding path program 1 times [2021-10-15 20:16:19,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162714091] [2021-10-15 20:16:19,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,425 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,463 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162714091] [2021-10-15 20:16:19,464 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162714091] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,464 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,464 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 20:16:19,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868277180] [2021-10-15 20:16:19,465 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,465 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:19,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:19,466 INFO L87 Difference]: Start difference. First operand 828 states and 1129 transitions. cyclomatic complexity: 303 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:19,497 INFO L93 Difference]: Finished difference Result 684 states and 931 transitions. [2021-10-15 20:16:19,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:19,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 684 states and 931 transitions. [2021-10-15 20:16:19,502 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2021-10-15 20:16:19,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 684 states to 684 states and 931 transitions. [2021-10-15 20:16:19,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 684 [2021-10-15 20:16:19,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 684 [2021-10-15 20:16:19,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 684 states and 931 transitions. [2021-10-15 20:16:19,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,509 INFO L681 BuchiCegarLoop]: Abstraction has 684 states and 931 transitions. [2021-10-15 20:16:19,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 684 states and 931 transitions. [2021-10-15 20:16:19,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 684 to 684. [2021-10-15 20:16:19,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 684 states, 684 states have (on average 1.3611111111111112) internal successors, (931), 683 states have internal predecessors, (931), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 931 transitions. [2021-10-15 20:16:19,522 INFO L704 BuchiCegarLoop]: Abstraction has 684 states and 931 transitions. [2021-10-15 20:16:19,522 INFO L587 BuchiCegarLoop]: Abstraction has 684 states and 931 transitions. [2021-10-15 20:16:19,523 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-15 20:16:19,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 684 states and 931 transitions. [2021-10-15 20:16:19,526 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2021-10-15 20:16:19,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,527 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,528 INFO L791 eck$LassoCheckResult]: Stem: 13819#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13776#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13777#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13693#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 13619#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13620#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13721#L245-1 assume !(0 == ~M_E~0); 13765#L348-1 assume !(0 == ~T1_E~0); 13729#L353-1 assume !(0 == ~T2_E~0); 13730#L358-1 assume !(0 == ~E_M~0); 13645#L363-1 assume !(0 == ~E_1~0); 13646#L368-1 assume !(0 == ~E_2~0); 13756#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13757#L170 assume !(1 == ~m_pc~0); 13782#L170-2 is_master_triggered_~__retres1~0 := 0; 13702#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13703#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13791#L429 assume !(0 != activate_threads_~tmp~1); 13641#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13642#L189 assume !(1 == ~t1_pc~0); 13637#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 13638#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13713#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13746#L437 assume !(0 != activate_threads_~tmp___0~0); 13627#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13628#L208 assume !(1 == ~t2_pc~0); 13813#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 13815#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13660#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13621#L445 assume !(0 != activate_threads_~tmp___1~0); 13622#L445-2 assume !(1 == ~M_E~0); 13778#L386-1 assume !(1 == ~T1_E~0); 13731#L391-1 assume !(1 == ~T2_E~0); 13611#L396-1 assume !(1 == ~E_M~0); 13612#L401-1 assume !(1 == ~E_1~0); 13716#L406-1 assume !(1 == ~E_2~0); 13679#L557-1 [2021-10-15 20:16:19,528 INFO L793 eck$LassoCheckResult]: Loop: 13679#L557-1 assume !false; 13680#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13580#L323 assume !false; 13581#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 14118#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 14117#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 14116#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 14115#L290 assume !(0 != eval_~tmp~0); 13649#L338 start_simulation_~kernel_st~0 := 2; 13650#L228-1 start_simulation_~kernel_st~0 := 3; 13601#L348-2 assume !(0 == ~M_E~0); 13602#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13747#L353-3 assume !(0 == ~T2_E~0); 13707#L358-3 assume !(0 == ~E_M~0); 13708#L363-3 assume !(0 == ~E_1~0); 13699#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13673#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13674#L170-12 assume !(1 == ~m_pc~0); 13755#L170-14 is_master_triggered_~__retres1~0 := 0; 13690#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13685#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13686#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13781#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13623#L189-12 assume !(1 == ~t1_pc~0); 13624#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 14209#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14208#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14207#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14206#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14205#L208-12 assume !(1 == ~t2_pc~0); 14203#L208-14 is_transmit2_triggered_~__retres1~2 := 0; 14201#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14198#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14197#L445-12 assume !(0 != activate_threads_~tmp___1~0); 14195#L445-14 assume !(1 == ~M_E~0); 14190#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13821#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13822#L396-3 assume !(1 == ~E_M~0); 14122#L401-3 assume !(1 == ~E_1~0); 14121#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13764#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13596#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13597#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13774#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 13775#L576 assume !(0 == start_simulation_~tmp~3); 13796#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13787#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13740#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13714#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 13625#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13626#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 13647#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13648#L589 assume !(0 != start_simulation_~tmp___0~1); 13679#L557-1 [2021-10-15 20:16:19,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,529 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2021-10-15 20:16:19,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,529 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832044262] [2021-10-15 20:16:19,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,529 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,537 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:19,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,551 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:19,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1157094183, now seen corresponding path program 1 times [2021-10-15 20:16:19,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,552 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051792982] [2021-10-15 20:16:19,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,553 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,580 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051792982] [2021-10-15 20:16:19,580 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051792982] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,580 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 20:16:19,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284419145] [2021-10-15 20:16:19,581 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,581 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 20:16:19,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 20:16:19,582 INFO L87 Difference]: Start difference. First operand 684 states and 931 transitions. cyclomatic complexity: 249 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:19,666 INFO L93 Difference]: Finished difference Result 1176 states and 1582 transitions. [2021-10-15 20:16:19,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-15 20:16:19,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1176 states and 1582 transitions. [2021-10-15 20:16:19,675 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1132 [2021-10-15 20:16:19,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1176 states to 1176 states and 1582 transitions. [2021-10-15 20:16:19,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1176 [2021-10-15 20:16:19,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1176 [2021-10-15 20:16:19,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1176 states and 1582 transitions. [2021-10-15 20:16:19,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,687 INFO L681 BuchiCegarLoop]: Abstraction has 1176 states and 1582 transitions. [2021-10-15 20:16:19,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1176 states and 1582 transitions. [2021-10-15 20:16:19,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1176 to 696. [2021-10-15 20:16:19,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 696 states, 696 states have (on average 1.3548850574712643) internal successors, (943), 695 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 696 states to 696 states and 943 transitions. [2021-10-15 20:16:19,703 INFO L704 BuchiCegarLoop]: Abstraction has 696 states and 943 transitions. [2021-10-15 20:16:19,703 INFO L587 BuchiCegarLoop]: Abstraction has 696 states and 943 transitions. [2021-10-15 20:16:19,703 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-15 20:16:19,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 696 states and 943 transitions. [2021-10-15 20:16:19,707 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2021-10-15 20:16:19,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,708 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,708 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,708 INFO L791 eck$LassoCheckResult]: Stem: 15698#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 15656#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15657#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15571#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 15497#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15498#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15601#L245-1 assume !(0 == ~M_E~0); 15644#L348-1 assume !(0 == ~T1_E~0); 15609#L353-1 assume !(0 == ~T2_E~0); 15610#L358-1 assume !(0 == ~E_M~0); 15524#L363-1 assume !(0 == ~E_1~0); 15525#L368-1 assume !(0 == ~E_2~0); 15635#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15636#L170 assume !(1 == ~m_pc~0); 15662#L170-2 is_master_triggered_~__retres1~0 := 0; 15580#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15581#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15671#L429 assume !(0 != activate_threads_~tmp~1); 15520#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15521#L189 assume !(1 == ~t1_pc~0); 15516#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 15517#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15593#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15626#L437 assume !(0 != activate_threads_~tmp___0~0); 15505#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15506#L208 assume !(1 == ~t2_pc~0); 15691#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 15693#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15539#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15499#L445 assume !(0 != activate_threads_~tmp___1~0); 15500#L445-2 assume !(1 == ~M_E~0); 15658#L386-1 assume !(1 == ~T1_E~0); 15611#L391-1 assume !(1 == ~T2_E~0); 15490#L396-1 assume !(1 == ~E_M~0); 15491#L401-1 assume !(1 == ~E_1~0); 15596#L406-1 assume !(1 == ~E_2~0); 15559#L557-1 [2021-10-15 20:16:19,709 INFO L793 eck$LassoCheckResult]: Loop: 15559#L557-1 assume !false; 15560#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15456#L323 assume !false; 15457#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15561#L258 assume !(0 == ~m_st~0); 15647#L262 assume !(0 == ~t1_st~0); 15474#L266 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 15476#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15807#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 15806#L290 assume !(0 != eval_~tmp~0); 15528#L338 start_simulation_~kernel_st~0 := 2; 15529#L228-1 start_simulation_~kernel_st~0 := 3; 15477#L348-2 assume !(0 == ~M_E~0); 15478#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15627#L353-3 assume !(0 == ~T2_E~0); 15582#L358-3 assume !(0 == ~E_M~0); 15583#L363-3 assume !(0 == ~E_1~0); 15577#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15551#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15552#L170-12 assume !(1 == ~m_pc~0); 15633#L170-14 is_master_triggered_~__retres1~0 := 0; 15634#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15562#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15563#L429-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15661#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15501#L189-12 assume !(1 == ~t1_pc~0); 15502#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 15654#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15655#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16087#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15595#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15574#L208-12 assume 1 == ~t2_pc~0; 15575#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15458#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15459#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15495#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15455#L445-14 assume !(1 == ~M_E~0); 15541#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15700#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15701#L396-3 assume !(1 == ~E_M~0); 16076#L401-3 assume !(1 == ~E_1~0); 15569#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15570#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16074#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16071#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16068#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 16065#L576 assume !(0 == start_simulation_~tmp~3); 16066#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15666#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15623#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15594#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 15503#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15504#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 15526#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 15527#L589 assume !(0 != start_simulation_~tmp___0~1); 15559#L557-1 [2021-10-15 20:16:19,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,709 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2021-10-15 20:16:19,710 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,710 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655608195] [2021-10-15 20:16:19,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,710 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,719 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:19,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,737 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:19,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,738 INFO L82 PathProgramCache]: Analyzing trace with hash -572996015, now seen corresponding path program 1 times [2021-10-15 20:16:19,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,738 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014508376] [2021-10-15 20:16:19,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,738 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,798 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014508376] [2021-10-15 20:16:19,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014508376] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,798 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 20:16:19,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091709760] [2021-10-15 20:16:19,799 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,799 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 20:16:19,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 20:16:19,800 INFO L87 Difference]: Start difference. First operand 696 states and 943 transitions. cyclomatic complexity: 249 Second operand has 5 states, 5 states have (on average 11.0) internal successors, (55), 5 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:19,885 INFO L93 Difference]: Finished difference Result 958 states and 1298 transitions. [2021-10-15 20:16:19,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-15 20:16:19,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 958 states and 1298 transitions. [2021-10-15 20:16:19,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 916 [2021-10-15 20:16:19,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 958 states to 958 states and 1298 transitions. [2021-10-15 20:16:19,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 958 [2021-10-15 20:16:19,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 958 [2021-10-15 20:16:19,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 958 states and 1298 transitions. [2021-10-15 20:16:19,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:19,916 INFO L681 BuchiCegarLoop]: Abstraction has 958 states and 1298 transitions. [2021-10-15 20:16:19,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 958 states and 1298 transitions. [2021-10-15 20:16:19,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 958 to 702. [2021-10-15 20:16:19,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 702 states, 702 states have (on average 1.3304843304843306) internal successors, (934), 701 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:19,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 702 states to 702 states and 934 transitions. [2021-10-15 20:16:19,934 INFO L704 BuchiCegarLoop]: Abstraction has 702 states and 934 transitions. [2021-10-15 20:16:19,934 INFO L587 BuchiCegarLoop]: Abstraction has 702 states and 934 transitions. [2021-10-15 20:16:19,934 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-15 20:16:19,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 702 states and 934 transitions. [2021-10-15 20:16:19,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 660 [2021-10-15 20:16:19,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:19,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:19,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:19,939 INFO L791 eck$LassoCheckResult]: Stem: 17400#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17341#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17342#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17242#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 17167#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17168#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17275#L245-1 assume !(0 == ~M_E~0); 17329#L348-1 assume !(0 == ~T1_E~0); 17287#L353-1 assume !(0 == ~T2_E~0); 17288#L358-1 assume !(0 == ~E_M~0); 17195#L363-1 assume !(0 == ~E_1~0); 17196#L368-1 assume !(0 == ~E_2~0); 17321#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17322#L170 assume !(1 == ~m_pc~0); 17349#L170-2 is_master_triggered_~__retres1~0 := 0; 17250#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17251#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17366#L429 assume !(0 != activate_threads_~tmp~1); 17191#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17192#L189 assume !(1 == ~t1_pc~0); 17187#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 17188#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17262#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17307#L437 assume !(0 != activate_threads_~tmp___0~0); 17175#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17176#L208 assume !(1 == ~t2_pc~0); 17390#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 17392#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17210#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17169#L445 assume !(0 != activate_threads_~tmp___1~0); 17170#L445-2 assume !(1 == ~M_E~0); 17343#L386-1 assume !(1 == ~T1_E~0); 17289#L391-1 assume !(1 == ~T2_E~0); 17159#L396-1 assume !(1 == ~E_M~0); 17160#L401-1 assume !(1 == ~E_1~0); 17270#L406-1 assume !(1 == ~E_2~0); 17279#L557-1 [2021-10-15 20:16:19,940 INFO L793 eck$LassoCheckResult]: Loop: 17279#L557-1 assume !false; 17714#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 17439#L323 assume !false; 17713#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17709#L258 assume !(0 == ~m_st~0); 17710#L262 assume !(0 == ~t1_st~0); 17711#L266 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 17712#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17770#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 17769#L290 assume !(0 != eval_~tmp~0); 17768#L338 start_simulation_~kernel_st~0 := 2; 17767#L228-1 start_simulation_~kernel_st~0 := 3; 17766#L348-2 assume !(0 == ~M_E~0); 17577#L348-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17576#L353-3 assume !(0 == ~T2_E~0); 17574#L358-3 assume !(0 == ~E_M~0); 17572#L363-3 assume !(0 == ~E_1~0); 17571#L368-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17569#L373-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17344#L170-12 assume !(1 == ~m_pc~0); 17320#L170-14 is_master_triggered_~__retres1~0 := 0; 17239#L181-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17235#L182-4 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17236#L429-12 assume !(0 != activate_threads_~tmp~1); 17347#L429-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17171#L189-12 assume !(1 == ~t1_pc~0); 17172#L189-14 is_transmit1_triggered_~__retres1~1 := 0; 17556#L200-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17553#L201-4 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17550#L437-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17547#L437-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17545#L208-12 assume 1 == ~t2_pc~0; 17542#L209-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17540#L219-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17538#L220-4 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17527#L445-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17524#L445-14 assume !(1 == ~M_E~0); 17522#L386-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17520#L391-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17389#L396-3 assume !(1 == ~E_M~0); 17388#L401-3 assume !(1 == ~E_1~0); 17240#L406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17241#L411-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17139#L258-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17140#L275-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17339#L276-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 17340#L576 assume !(0 == start_simulation_~tmp~3); 17372#L576-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17733#L258-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17730#L275-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17727#L276-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 17724#L531 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17721#L538 stop_simulation_#res := stop_simulation_~__retres2~0; 17718#L539 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 17716#L589 assume !(0 != start_simulation_~tmp___0~1); 17279#L557-1 [2021-10-15 20:16:19,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,940 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2021-10-15 20:16:19,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804199606] [2021-10-15 20:16:19,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,941 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,949 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:19,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:19,963 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:19,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:19,964 INFO L82 PathProgramCache]: Analyzing trace with hash -298236401, now seen corresponding path program 1 times [2021-10-15 20:16:19,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:19,964 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983345554] [2021-10-15 20:16:19,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:19,964 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:19,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:19,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:19,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:19,987 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983345554] [2021-10-15 20:16:19,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983345554] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:19,987 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:19,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:19,987 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204908501] [2021-10-15 20:16:19,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 20:16:19,988 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:19,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:19,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:19,990 INFO L87 Difference]: Start difference. First operand 702 states and 934 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 18.333333333333332) internal successors, (55), 3 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:20,013 INFO L93 Difference]: Finished difference Result 927 states and 1216 transitions. [2021-10-15 20:16:20,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:20,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 927 states and 1216 transitions. [2021-10-15 20:16:20,023 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 883 [2021-10-15 20:16:20,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 927 states to 927 states and 1216 transitions. [2021-10-15 20:16:20,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 927 [2021-10-15 20:16:20,031 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 927 [2021-10-15 20:16:20,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 927 states and 1216 transitions. [2021-10-15 20:16:20,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:20,033 INFO L681 BuchiCegarLoop]: Abstraction has 927 states and 1216 transitions. [2021-10-15 20:16:20,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states and 1216 transitions. [2021-10-15 20:16:20,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 927. [2021-10-15 20:16:20,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 927 states, 927 states have (on average 1.3117583603020497) internal successors, (1216), 926 states have internal predecessors, (1216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 927 states and 1216 transitions. [2021-10-15 20:16:20,055 INFO L704 BuchiCegarLoop]: Abstraction has 927 states and 1216 transitions. [2021-10-15 20:16:20,055 INFO L587 BuchiCegarLoop]: Abstraction has 927 states and 1216 transitions. [2021-10-15 20:16:20,055 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-15 20:16:20,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 927 states and 1216 transitions. [2021-10-15 20:16:20,062 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 883 [2021-10-15 20:16:20,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:20,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:20,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,064 INFO L791 eck$LassoCheckResult]: Stem: 19009#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18960#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18961#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18872#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 18797#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18798#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18904#L245-1 assume !(0 == ~M_E~0); 18948#L348-1 assume !(0 == ~T1_E~0); 18913#L353-1 assume !(0 == ~T2_E~0); 18914#L358-1 assume !(0 == ~E_M~0); 18824#L363-1 assume !(0 == ~E_1~0); 18825#L368-1 assume !(0 == ~E_2~0); 18941#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18942#L170 assume !(1 == ~m_pc~0); 18967#L170-2 is_master_triggered_~__retres1~0 := 0; 18882#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18883#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18977#L429 assume !(0 != activate_threads_~tmp~1); 18820#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18821#L189 assume !(1 == ~t1_pc~0); 18816#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 18817#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18894#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18930#L437 assume !(0 != activate_threads_~tmp___0~0); 18805#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18806#L208 assume !(1 == ~t2_pc~0); 19000#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 19002#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18839#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18799#L445 assume !(0 != activate_threads_~tmp___1~0); 18800#L445-2 assume !(1 == ~M_E~0); 18962#L386-1 assume !(1 == ~T1_E~0); 18915#L391-1 assume !(1 == ~T2_E~0); 18790#L396-1 assume !(1 == ~E_M~0); 18791#L401-1 assume !(1 == ~E_1~0); 18898#L406-1 assume !(1 == ~E_2~0); 18907#L557-1 assume !false; 19458#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19456#L323 [2021-10-15 20:16:20,064 INFO L793 eck$LassoCheckResult]: Loop: 19456#L323 assume !false; 19454#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19450#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19448#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 19445#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 19442#L290 assume 0 != eval_~tmp~0; 19437#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 18949#L298 assume !(0 != eval_~tmp_ndt_1~0); 18950#L295 assume !(0 == ~t1_st~0); 19196#L309 assume !(0 == ~t2_st~0); 19456#L323 [2021-10-15 20:16:20,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,065 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2021-10-15 20:16:20,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,067 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286071377] [2021-10-15 20:16:20,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,067 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,086 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,110 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1924934063, now seen corresponding path program 1 times [2021-10-15 20:16:20,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,111 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675518576] [2021-10-15 20:16:20,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,111 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,116 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,122 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,123 INFO L82 PathProgramCache]: Analyzing trace with hash -460292778, now seen corresponding path program 1 times [2021-10-15 20:16:20,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673834998] [2021-10-15 20:16:20,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,124 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:20,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:20,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:20,149 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673834998] [2021-10-15 20:16:20,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673834998] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:20,149 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:20,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:20,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386983644] [2021-10-15 20:16:20,237 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:20,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:20,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:20,238 INFO L87 Difference]: Start difference. First operand 927 states and 1216 transitions. cyclomatic complexity: 292 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:20,301 INFO L93 Difference]: Finished difference Result 1663 states and 2154 transitions. [2021-10-15 20:16:20,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:20,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1663 states and 2154 transitions. [2021-10-15 20:16:20,311 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1580 [2021-10-15 20:16:20,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1663 states to 1663 states and 2154 transitions. [2021-10-15 20:16:20,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1663 [2021-10-15 20:16:20,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1663 [2021-10-15 20:16:20,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1663 states and 2154 transitions. [2021-10-15 20:16:20,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:20,327 INFO L681 BuchiCegarLoop]: Abstraction has 1663 states and 2154 transitions. [2021-10-15 20:16:20,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1663 states and 2154 transitions. [2021-10-15 20:16:20,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1663 to 1611. [2021-10-15 20:16:20,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1611 states, 1611 states have (on average 1.2973308504034762) internal successors, (2090), 1610 states have internal predecessors, (2090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1611 states to 1611 states and 2090 transitions. [2021-10-15 20:16:20,372 INFO L704 BuchiCegarLoop]: Abstraction has 1611 states and 2090 transitions. [2021-10-15 20:16:20,372 INFO L587 BuchiCegarLoop]: Abstraction has 1611 states and 2090 transitions. [2021-10-15 20:16:20,372 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-15 20:16:20,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1611 states and 2090 transitions. [2021-10-15 20:16:20,377 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1528 [2021-10-15 20:16:20,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:20,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:20,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,379 INFO L791 eck$LassoCheckResult]: Stem: 21604#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21562#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21563#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21471#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 21394#L235-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 21395#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22138#L245-1 assume !(0 == ~M_E~0); 22137#L348-1 assume !(0 == ~T1_E~0); 22136#L353-1 assume !(0 == ~T2_E~0); 22135#L358-1 assume !(0 == ~E_M~0); 22134#L363-1 assume !(0 == ~E_1~0); 22133#L368-1 assume !(0 == ~E_2~0); 22132#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22131#L170 assume !(1 == ~m_pc~0); 22130#L170-2 is_master_triggered_~__retres1~0 := 0; 22129#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22128#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22127#L429 assume !(0 != activate_threads_~tmp~1); 22126#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22125#L189 assume !(1 == ~t1_pc~0); 22124#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 22123#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22122#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22121#L437 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21403#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21404#L208 assume !(1 == ~t2_pc~0); 21598#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 21600#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21436#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21397#L445 assume !(0 != activate_threads_~tmp___1~0); 21398#L445-2 assume !(1 == ~M_E~0); 21564#L386-1 assume !(1 == ~T1_E~0); 21510#L391-1 assume !(1 == ~T2_E~0); 21388#L396-1 assume !(1 == ~E_M~0); 21389#L401-1 assume !(1 == ~E_1~0); 21495#L406-1 assume !(1 == ~E_2~0); 21503#L557-1 assume !false; 22853#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22845#L323 [2021-10-15 20:16:20,379 INFO L793 eck$LassoCheckResult]: Loop: 22845#L323 assume !false; 22844#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22843#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22842#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22840#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 22838#L290 assume 0 != eval_~tmp~0; 22697#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 21549#L298 assume !(0 != eval_~tmp_ndt_1~0); 21550#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 22071#L312 assume !(0 != eval_~tmp_ndt_2~0); 22774#L309 assume !(0 == ~t2_st~0); 22845#L323 [2021-10-15 20:16:20,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,379 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2021-10-15 20:16:20,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816233268] [2021-10-15 20:16:20,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,380 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:20,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:20,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:20,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816233268] [2021-10-15 20:16:20,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816233268] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:20,442 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:20,442 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 20:16:20,442 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856026066] [2021-10-15 20:16:20,443 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 20:16:20,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,443 INFO L82 PathProgramCache]: Analyzing trace with hash 456481406, now seen corresponding path program 1 times [2021-10-15 20:16:20,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,443 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333677533] [2021-10-15 20:16:20,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,444 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,446 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,449 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,549 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:20,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:20,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:20,550 INFO L87 Difference]: Start difference. First operand 1611 states and 2090 transitions. cyclomatic complexity: 482 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:20,563 INFO L93 Difference]: Finished difference Result 1574 states and 2042 transitions. [2021-10-15 20:16:20,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:20,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1574 states and 2042 transitions. [2021-10-15 20:16:20,571 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1528 [2021-10-15 20:16:20,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1574 states to 1574 states and 2042 transitions. [2021-10-15 20:16:20,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1574 [2021-10-15 20:16:20,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1574 [2021-10-15 20:16:20,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1574 states and 2042 transitions. [2021-10-15 20:16:20,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:20,587 INFO L681 BuchiCegarLoop]: Abstraction has 1574 states and 2042 transitions. [2021-10-15 20:16:20,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1574 states and 2042 transitions. [2021-10-15 20:16:20,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1574 to 1574. [2021-10-15 20:16:20,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1574 states, 1574 states have (on average 1.2973316391359593) internal successors, (2042), 1573 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1574 states to 1574 states and 2042 transitions. [2021-10-15 20:16:20,626 INFO L704 BuchiCegarLoop]: Abstraction has 1574 states and 2042 transitions. [2021-10-15 20:16:20,626 INFO L587 BuchiCegarLoop]: Abstraction has 1574 states and 2042 transitions. [2021-10-15 20:16:20,626 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-15 20:16:20,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1574 states and 2042 transitions. [2021-10-15 20:16:20,632 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1528 [2021-10-15 20:16:20,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:20,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:20,633 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,633 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,633 INFO L791 eck$LassoCheckResult]: Stem: 24803#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24750#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24751#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24659#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 24587#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24588#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24693#L245-1 assume !(0 == ~M_E~0); 24735#L348-1 assume !(0 == ~T1_E~0); 24700#L353-1 assume !(0 == ~T2_E~0); 24701#L358-1 assume !(0 == ~E_M~0); 24611#L363-1 assume !(0 == ~E_1~0); 24612#L368-1 assume !(0 == ~E_2~0); 24727#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24728#L170 assume !(1 == ~m_pc~0); 24758#L170-2 is_master_triggered_~__retres1~0 := 0; 24670#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24671#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 24769#L429 assume !(0 != activate_threads_~tmp~1); 24609#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24610#L189 assume !(1 == ~t1_pc~0); 24605#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 24606#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24683#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 24717#L437 assume !(0 != activate_threads_~tmp___0~0); 24595#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24596#L208 assume !(1 == ~t2_pc~0); 24797#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 24799#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24628#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 24589#L445 assume !(0 != activate_threads_~tmp___1~0); 24590#L445-2 assume !(1 == ~M_E~0); 24752#L386-1 assume !(1 == ~T1_E~0); 24702#L391-1 assume !(1 == ~T2_E~0); 24579#L396-1 assume !(1 == ~E_M~0); 24580#L401-1 assume !(1 == ~E_1~0); 24687#L406-1 assume !(1 == ~E_2~0); 24695#L557-1 assume !false; 25833#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 25827#L323 [2021-10-15 20:16:20,633 INFO L793 eck$LassoCheckResult]: Loop: 25827#L323 assume !false; 25822#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25817#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25812#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25807#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 25801#L290 assume 0 != eval_~tmp~0; 25794#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 24738#L298 assume !(0 != eval_~tmp_ndt_1~0); 24739#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 25051#L312 assume !(0 != eval_~tmp_ndt_2~0); 25837#L309 assume !(0 == ~t2_st~0); 25827#L323 [2021-10-15 20:16:20,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2021-10-15 20:16:20,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286331857] [2021-10-15 20:16:20,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,634 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,641 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,651 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,652 INFO L82 PathProgramCache]: Analyzing trace with hash 456481406, now seen corresponding path program 2 times [2021-10-15 20:16:20,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,652 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821639774] [2021-10-15 20:16:20,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,653 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,655 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,658 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,659 INFO L82 PathProgramCache]: Analyzing trace with hash -1384279015, now seen corresponding path program 1 times [2021-10-15 20:16:20,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,659 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402046276] [2021-10-15 20:16:20,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,659 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 20:16:20,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 20:16:20,680 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 20:16:20,681 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402046276] [2021-10-15 20:16:20,681 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402046276] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 20:16:20,681 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 20:16:20,681 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 20:16:20,681 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468394149] [2021-10-15 20:16:20,760 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 20:16:20,760 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 20:16:20,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 20:16:20,760 INFO L87 Difference]: Start difference. First operand 1574 states and 2042 transitions. cyclomatic complexity: 471 Second operand has 3 states, 2 states have (on average 24.5) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 20:16:20,799 INFO L93 Difference]: Finished difference Result 2478 states and 3184 transitions. [2021-10-15 20:16:20,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 20:16:20,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2478 states and 3184 transitions. [2021-10-15 20:16:20,813 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2428 [2021-10-15 20:16:20,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2478 states to 2478 states and 3184 transitions. [2021-10-15 20:16:20,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2478 [2021-10-15 20:16:20,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2478 [2021-10-15 20:16:20,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2478 states and 3184 transitions. [2021-10-15 20:16:20,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 20:16:20,843 INFO L681 BuchiCegarLoop]: Abstraction has 2478 states and 3184 transitions. [2021-10-15 20:16:20,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2478 states and 3184 transitions. [2021-10-15 20:16:20,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2478 to 2430. [2021-10-15 20:16:20,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2430 states, 2430 states have (on average 1.2905349794238683) internal successors, (3136), 2429 states have internal predecessors, (3136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 20:16:20,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2430 states to 2430 states and 3136 transitions. [2021-10-15 20:16:20,892 INFO L704 BuchiCegarLoop]: Abstraction has 2430 states and 3136 transitions. [2021-10-15 20:16:20,892 INFO L587 BuchiCegarLoop]: Abstraction has 2430 states and 3136 transitions. [2021-10-15 20:16:20,892 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-15 20:16:20,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2430 states and 3136 transitions. [2021-10-15 20:16:20,900 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2380 [2021-10-15 20:16:20,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 20:16:20,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 20:16:20,901 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 20:16:20,902 INFO L791 eck$LassoCheckResult]: Stem: 28871#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 28820#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28821#L520 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28723#L228 assume 1 == ~m_i~0;~m_st~0 := 0; 28647#L235-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28648#L240-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28757#L245-1 assume !(0 == ~M_E~0); 28804#L348-1 assume !(0 == ~T1_E~0); 28765#L353-1 assume !(0 == ~T2_E~0); 28766#L358-1 assume !(0 == ~E_M~0); 28671#L363-1 assume !(0 == ~E_1~0); 28672#L368-1 assume !(0 == ~E_2~0); 28797#L373-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28798#L170 assume !(1 == ~m_pc~0); 28829#L170-2 is_master_triggered_~__retres1~0 := 0; 28737#L181 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28738#L182 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28843#L429 assume !(0 != activate_threads_~tmp~1); 28669#L429-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28670#L189 assume !(1 == ~t1_pc~0); 28665#L189-2 is_transmit1_triggered_~__retres1~1 := 0; 28666#L200 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28748#L201 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28784#L437 assume !(0 != activate_threads_~tmp___0~0); 28655#L437-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28656#L208 assume !(1 == ~t2_pc~0); 28863#L208-2 is_transmit2_triggered_~__retres1~2 := 0; 28865#L219 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28690#L220 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28649#L445 assume !(0 != activate_threads_~tmp___1~0); 28650#L445-2 assume !(1 == ~M_E~0); 28822#L386-1 assume !(1 == ~T1_E~0); 28767#L391-1 assume !(1 == ~T2_E~0); 28637#L396-1 assume !(1 == ~E_M~0); 28638#L401-1 assume !(1 == ~E_1~0); 28752#L406-1 assume !(1 == ~E_2~0); 28759#L557-1 assume !false; 29911#L558 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29908#L323 [2021-10-15 20:16:20,902 INFO L793 eck$LassoCheckResult]: Loop: 29908#L323 assume !false; 29903#L286 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29902#L258 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29901#L275 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29898#L276 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 29672#L290 assume 0 != eval_~tmp~0; 29673#L290-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 29850#L298 assume !(0 != eval_~tmp_ndt_1~0); 29582#L295 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 29577#L312 assume !(0 != eval_~tmp_ndt_2~0); 29578#L309 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 29709#L326 assume !(0 != eval_~tmp_ndt_3~0); 29908#L323 [2021-10-15 20:16:20,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2021-10-15 20:16:20,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506432229] [2021-10-15 20:16:20,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,904 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,913 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,933 INFO L82 PathProgramCache]: Analyzing trace with hash 1266018993, now seen corresponding path program 1 times [2021-10-15 20:16:20,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496756265] [2021-10-15 20:16:20,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,933 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,937 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,940 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:20,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 20:16:20,941 INFO L82 PathProgramCache]: Analyzing trace with hash 37020790, now seen corresponding path program 1 times [2021-10-15 20:16:20,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 20:16:20,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960940327] [2021-10-15 20:16:20,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 20:16:20,942 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 20:16:20,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,952 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 20:16:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 20:16:20,970 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 20:16:22,199 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 15.10 08:16:22 BoogieIcfgContainer [2021-10-15 20:16:22,200 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-15 20:16:22,200 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-15 20:16:22,200 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-15 20:16:22,201 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-15 20:16:22,201 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 08:16:16" (3/4) ... [2021-10-15 20:16:22,203 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-15 20:16:22,248 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/witness.graphml [2021-10-15 20:16:22,248 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-15 20:16:22,250 INFO L168 Benchmark]: Toolchain (without parser) took 6672.97 ms. Allocated memory was 83.9 MB in the beginning and 165.7 MB in the end (delta: 81.8 MB). Free memory was 48.6 MB in the beginning and 54.0 MB in the end (delta: -5.4 MB). Peak memory consumption was 75.3 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,250 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 83.9 MB. Free memory is still 65.5 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-15 20:16:22,251 INFO L168 Benchmark]: CACSL2BoogieTranslator took 346.90 ms. Allocated memory was 83.9 MB in the beginning and 109.1 MB in the end (delta: 25.2 MB). Free memory was 48.4 MB in the beginning and 84.0 MB in the end (delta: -35.6 MB). Peak memory consumption was 7.8 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,251 INFO L168 Benchmark]: Boogie Procedure Inliner took 94.51 ms. Allocated memory is still 109.1 MB. Free memory was 84.0 MB in the beginning and 80.9 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,251 INFO L168 Benchmark]: Boogie Preprocessor took 48.31 ms. Allocated memory is still 109.1 MB. Free memory was 80.9 MB in the beginning and 78.3 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,252 INFO L168 Benchmark]: RCFGBuilder took 846.49 ms. Allocated memory is still 109.1 MB. Free memory was 78.3 MB in the beginning and 81.8 MB in the end (delta: -3.5 MB). Peak memory consumption was 24.6 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,252 INFO L168 Benchmark]: BuchiAutomizer took 5266.97 ms. Allocated memory was 109.1 MB in the beginning and 165.7 MB in the end (delta: 56.6 MB). Free memory was 81.8 MB in the beginning and 57.1 MB in the end (delta: 24.8 MB). Peak memory consumption was 104.2 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,253 INFO L168 Benchmark]: Witness Printer took 48.09 ms. Allocated memory is still 165.7 MB. Free memory was 57.1 MB in the beginning and 54.0 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-15 20:16:22,255 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 83.9 MB. Free memory is still 65.5 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 346.90 ms. Allocated memory was 83.9 MB in the beginning and 109.1 MB in the end (delta: 25.2 MB). Free memory was 48.4 MB in the beginning and 84.0 MB in the end (delta: -35.6 MB). Peak memory consumption was 7.8 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 94.51 ms. Allocated memory is still 109.1 MB. Free memory was 84.0 MB in the beginning and 80.9 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 48.31 ms. Allocated memory is still 109.1 MB. Free memory was 80.9 MB in the beginning and 78.3 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 846.49 ms. Allocated memory is still 109.1 MB. Free memory was 78.3 MB in the beginning and 81.8 MB in the end (delta: -3.5 MB). Peak memory consumption was 24.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 5266.97 ms. Allocated memory was 109.1 MB in the beginning and 165.7 MB in the end (delta: 56.6 MB). Free memory was 81.8 MB in the beginning and 57.1 MB in the end (delta: 24.8 MB). Peak memory consumption was 104.2 MB. Max. memory is 16.1 GB. * Witness Printer took 48.09 ms. Allocated memory is still 165.7 MB. Free memory was 57.1 MB in the beginning and 54.0 MB in the end (delta: 3.0 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2430 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.1s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.4s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 392.8ms AutomataMinimizationTime, 16 MinimizatonAttempts, 2323 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 2430 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5377 SDtfs, 6323 SDslu, 5031 SDs, 0 SdLazy, 453 SolverSat, 162 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 451.8ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=29509} State at position 1 is {NULL=0, token=0, NULL=29509, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51b295b7=0, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@74befa21=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d965815=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4693bd07=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2bea2b77=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@36b6e09=0, NULL=29511, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3209fa5d=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=29510, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=29512, t2_i=1, m_i=1, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@913d639=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27195749=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int M_E = 2; [L26] int T1_E = 2; [L27] int T2_E = 2; [L28] int E_M = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L35] int token ; [L37] int local ; [L602] int __retres1 ; [L516] m_i = 1 [L517] t1_i = 1 [L518] t2_i = 1 [L543] int kernel_st ; [L544] int tmp ; [L545] int tmp___0 ; [L549] kernel_st = 0 [L235] COND TRUE m_i == 1 [L236] m_st = 0 [L240] COND TRUE t1_i == 1 [L241] t1_st = 0 [L245] COND TRUE t2_i == 1 [L246] t2_st = 0 [L348] COND FALSE !(M_E == 0) [L353] COND FALSE !(T1_E == 0) [L358] COND FALSE !(T2_E == 0) [L363] COND FALSE !(E_M == 0) [L368] COND FALSE !(E_1 == 0) [L373] COND FALSE !(E_2 == 0) [L421] int tmp ; [L422] int tmp___0 ; [L423] int tmp___1 ; [L167] int __retres1 ; [L170] COND FALSE !(m_pc == 1) [L180] __retres1 = 0 [L182] return (__retres1); [L427] tmp = is_master_triggered() [L429] COND FALSE !(\read(tmp)) [L186] int __retres1 ; [L189] COND FALSE !(t1_pc == 1) [L199] __retres1 = 0 [L201] return (__retres1); [L435] tmp___0 = is_transmit1_triggered() [L437] COND FALSE !(\read(tmp___0)) [L205] int __retres1 ; [L208] COND FALSE !(t2_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L443] tmp___1 = is_transmit2_triggered() [L445] COND FALSE !(\read(tmp___1)) [L386] COND FALSE !(M_E == 1) [L391] COND FALSE !(T1_E == 1) [L396] COND FALSE !(T2_E == 1) [L401] COND FALSE !(E_M == 1) [L406] COND FALSE !(E_1 == 1) [L411] COND FALSE !(E_2 == 1) [L557] COND TRUE 1 [L560] kernel_st = 1 [L281] int tmp ; Loop: [L285] COND TRUE 1 [L255] int __retres1 ; [L258] COND TRUE m_st == 0 [L259] __retres1 = 1 [L276] return (__retres1); [L288] tmp = exists_runnable_thread() [L290] COND TRUE \read(tmp) [L295] COND TRUE m_st == 0 [L296] int tmp_ndt_1; [L297] tmp_ndt_1 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_1)) [L309] COND TRUE t1_st == 0 [L310] int tmp_ndt_2; [L311] tmp_ndt_2 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_2)) [L323] COND TRUE t2_st == 0 [L324] int tmp_ndt_3; [L325] tmp_ndt_3 = __VERIFIER_nondet_int() [L326] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-15 20:16:22,314 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c3b97702-7a5d-4807-94a5-881128fe604f/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...