./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 57096758 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5937481bc19468f59d919de13c534d2ea0f2da0e ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-5709675 [2021-10-15 19:08:53,401 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-15 19:08:53,404 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-15 19:08:53,454 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-15 19:08:53,457 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-15 19:08:53,463 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-15 19:08:53,467 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-15 19:08:53,472 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-15 19:08:53,476 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-15 19:08:53,484 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-15 19:08:53,486 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-15 19:08:53,488 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-15 19:08:53,489 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-15 19:08:53,492 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-15 19:08:53,495 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-15 19:08:53,498 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-15 19:08:53,500 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-15 19:08:53,502 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-15 19:08:53,508 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-15 19:08:53,520 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-15 19:08:53,523 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-15 19:08:53,525 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-15 19:08:53,529 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-15 19:08:53,531 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-15 19:08:53,535 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-15 19:08:53,536 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-15 19:08:53,536 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-15 19:08:53,539 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-15 19:08:53,539 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-15 19:08:53,541 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-15 19:08:53,542 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-15 19:08:53,544 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-15 19:08:53,546 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-15 19:08:53,548 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-15 19:08:53,550 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-15 19:08:53,550 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-15 19:08:53,551 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-15 19:08:53,551 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-15 19:08:53,552 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-15 19:08:53,553 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-15 19:08:53,554 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-15 19:08:53,555 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-15 19:08:53,618 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-15 19:08:53,623 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-15 19:08:53,624 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-15 19:08:53,625 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-15 19:08:53,626 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-15 19:08:53,627 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-15 19:08:53,627 INFO L138 SettingsManager]: * Use SBE=true [2021-10-15 19:08:53,627 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-15 19:08:53,627 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-15 19:08:53,628 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-15 19:08:53,629 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-15 19:08:53,629 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-15 19:08:53,630 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-15 19:08:53,630 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-15 19:08:53,630 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-15 19:08:53,630 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-15 19:08:53,631 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-15 19:08:53,631 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-15 19:08:53,631 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-15 19:08:53,631 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-15 19:08:53,632 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-15 19:08:53,632 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-15 19:08:53,632 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-15 19:08:53,632 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-15 19:08:53,633 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-15 19:08:53,633 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-15 19:08:53,635 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-15 19:08:53,635 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-15 19:08:53,635 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-15 19:08:53,636 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-15 19:08:53,636 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-15 19:08:53,637 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-15 19:08:53,638 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-15 19:08:53,638 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5937481bc19468f59d919de13c534d2ea0f2da0e [2021-10-15 19:08:54,035 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-15 19:08:54,066 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-15 19:08:54,070 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-15 19:08:54,071 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-15 19:08:54,073 INFO L275 PluginConnector]: CDTParser initialized [2021-10-15 19:08:54,074 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-10-15 19:08:54,202 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/data/d6a09bec7/5bae689f95cb4c4ab60f59e058b1665a/FLAG1e7871c70 [2021-10-15 19:08:54,812 INFO L306 CDTParser]: Found 1 translation units. [2021-10-15 19:08:54,812 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-10-15 19:08:54,840 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/data/d6a09bec7/5bae689f95cb4c4ab60f59e058b1665a/FLAG1e7871c70 [2021-10-15 19:08:55,142 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/data/d6a09bec7/5bae689f95cb4c4ab60f59e058b1665a [2021-10-15 19:08:55,145 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-15 19:08:55,149 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-15 19:08:55,153 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-15 19:08:55,154 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-15 19:08:55,167 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-15 19:08:55,169 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,170 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2870243b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55, skipping insertion in model container [2021-10-15 19:08:55,171 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,180 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-15 19:08:55,236 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-15 19:08:55,442 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[366,379] [2021-10-15 19:08:55,530 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-15 19:08:55,542 INFO L203 MainTranslator]: Completed pre-run [2021-10-15 19:08:55,568 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[366,379] [2021-10-15 19:08:55,621 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-15 19:08:55,648 INFO L208 MainTranslator]: Completed translation [2021-10-15 19:08:55,648 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55 WrapperNode [2021-10-15 19:08:55,649 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-15 19:08:55,650 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-15 19:08:55,650 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-15 19:08:55,651 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-15 19:08:55,660 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,674 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,744 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-15 19:08:55,745 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-15 19:08:55,745 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-15 19:08:55,745 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-15 19:08:55,756 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,758 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,783 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,783 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,824 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,884 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,888 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,899 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-15 19:08:55,900 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-15 19:08:55,901 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-15 19:08:55,902 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-15 19:08:55,904 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (1/1) ... [2021-10-15 19:08:55,913 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-15 19:08:55,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/z3 [2021-10-15 19:08:55,942 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-15 19:08:55,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-15 19:08:56,007 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-15 19:08:56,008 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-15 19:08:56,008 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-15 19:08:56,008 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-15 19:08:57,373 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-15 19:08:57,373 INFO L299 CfgBuilder]: Removed 198 assume(true) statements. [2021-10-15 19:08:57,377 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 07:08:57 BoogieIcfgContainer [2021-10-15 19:08:57,378 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-15 19:08:57,379 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-15 19:08:57,379 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-15 19:08:57,383 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-15 19:08:57,384 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 19:08:57,384 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.10 07:08:55" (1/3) ... [2021-10-15 19:08:57,386 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a6c42c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 07:08:57, skipping insertion in model container [2021-10-15 19:08:57,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 19:08:57,387 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 07:08:55" (2/3) ... [2021-10-15 19:08:57,387 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a6c42c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.10 07:08:57, skipping insertion in model container [2021-10-15 19:08:57,387 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-15 19:08:57,387 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 07:08:57" (3/3) ... [2021-10-15 19:08:57,389 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2021-10-15 19:08:57,453 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-15 19:08:57,453 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-15 19:08:57,453 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-15 19:08:57,453 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-15 19:08:57,453 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-15 19:08:57,453 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-15 19:08:57,454 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-15 19:08:57,454 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-15 19:08:57,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:57,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-10-15 19:08:57,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:57,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:57,591 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:57,591 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:57,592 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-15 19:08:57,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:57,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-10-15 19:08:57,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:57,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:57,651 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:57,651 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:57,661 INFO L791 eck$LassoCheckResult]: Stem: 527#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 446#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 346#L895true havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 463#L411true assume !(1 == ~m_i~0);~m_st~0 := 2; 402#L418-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 468#L423-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 202#L428-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 188#L433-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 170#L438-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 98#L443-1true assume !(0 == ~M_E~0); 505#L603-1true assume !(0 == ~T1_E~0); 216#L608-1true assume !(0 == ~T2_E~0); 113#L613-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 196#L618-1true assume !(0 == ~T4_E~0); 330#L623-1true assume !(0 == ~T5_E~0); 494#L628-1true assume !(0 == ~E_M~0); 472#L633-1true assume !(0 == ~E_1~0); 313#L638-1true assume !(0 == ~E_2~0); 363#L643-1true assume !(0 == ~E_3~0); 361#L648-1true assume !(0 == ~E_4~0); 459#L653-1true assume 0 == ~E_5~0;~E_5~0 := 1; 400#L658-1true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61#L296true assume 1 == ~m_pc~0; 30#L297true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 206#L307true is_master_triggered_#res := is_master_triggered_~__retres1~0; 132#L308true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 136#L747true assume !(0 != activate_threads_~tmp~1); 314#L747-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47#L315true assume !(1 == ~t1_pc~0); 487#L315-2true is_transmit1_triggered_~__retres1~1 := 0; 430#L326true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 417#L327true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22#L755true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 530#L755-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31#L334true assume 1 == ~t2_pc~0; 285#L335true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 384#L345true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50#L346true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 473#L763true assume !(0 != activate_threads_~tmp___1~0); 482#L763-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87#L353true assume !(1 == ~t3_pc~0); 369#L353-2true is_transmit3_triggered_~__retres1~3 := 0; 254#L364true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62#L365true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 508#L771true assume !(0 != activate_threads_~tmp___2~0); 331#L771-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 437#L372true assume 1 == ~t4_pc~0; 109#L373true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 177#L383true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 393#L384true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 403#L779true assume !(0 != activate_threads_~tmp___3~0); 36#L779-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 355#L391true assume !(1 == ~t5_pc~0); 4#L391-2true is_transmit5_triggered_~__retres1~5 := 0; 84#L402true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 178#L403true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 241#L787true assume !(0 != activate_threads_~tmp___4~0); 497#L787-2true assume !(1 == ~M_E~0); 307#L671-1true assume !(1 == ~T1_E~0); 125#L676-1true assume !(1 == ~T2_E~0); 380#L681-1true assume !(1 == ~T3_E~0); 220#L686-1true assume !(1 == ~T4_E~0); 392#L691-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 374#L696-1true assume !(1 == ~E_M~0); 421#L701-1true assume !(1 == ~E_1~0); 444#L706-1true assume !(1 == ~E_2~0); 231#L711-1true assume !(1 == ~E_3~0); 105#L716-1true assume !(1 == ~E_4~0); 462#L721-1true assume !(1 == ~E_5~0); 533#L932-1true [2021-10-15 19:08:57,663 INFO L793 eck$LassoCheckResult]: Loop: 533#L932-1true assume !false; 418#L933true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 450#L578true assume !true; 344#L593true start_simulation_~kernel_st~0 := 2; 438#L411-1true start_simulation_~kernel_st~0 := 3; 123#L603-2true assume 0 == ~M_E~0;~M_E~0 := 1; 127#L603-4true assume !(0 == ~T1_E~0); 297#L608-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 239#L613-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 316#L618-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 518#L623-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 41#L628-3true assume 0 == ~E_M~0;~E_M~0 := 1; 413#L633-3true assume 0 == ~E_1~0;~E_1~0 := 1; 63#L638-3true assume 0 == ~E_2~0;~E_2~0 := 1; 337#L643-3true assume !(0 == ~E_3~0); 72#L648-3true assume 0 == ~E_4~0;~E_4~0 := 1; 76#L653-3true assume 0 == ~E_5~0;~E_5~0 := 1; 227#L658-3true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 267#L296-21true assume !(1 == ~m_pc~0); 338#L296-23true is_master_triggered_~__retres1~0 := 0; 515#L307-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 353#L308-7true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 238#L747-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 298#L747-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 251#L315-21true assume 1 == ~t1_pc~0; 485#L316-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 465#L326-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 514#L327-7true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 167#L755-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 179#L755-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 111#L334-21true assume !(1 == ~t2_pc~0); 540#L334-23true is_transmit2_triggered_~__retres1~2 := 0; 293#L345-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 445#L346-7true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 373#L763-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 390#L763-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7#L353-21true assume 1 == ~t3_pc~0; 371#L354-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 475#L364-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 481#L365-7true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 332#L771-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 69#L771-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 257#L372-21true assume !(1 == ~t4_pc~0); 190#L372-23true is_transmit4_triggered_~__retres1~4 := 0; 194#L383-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 269#L384-7true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 153#L779-21true assume !(0 != activate_threads_~tmp___3~0); 24#L779-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 538#L391-21true assume !(1 == ~t5_pc~0); 211#L391-23true is_transmit5_triggered_~__retres1~5 := 0; 49#L402-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 486#L403-7true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 318#L787-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 243#L787-23true assume 1 == ~M_E~0;~M_E~0 := 2; 412#L671-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 217#L676-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 324#L681-3true assume !(1 == ~T3_E~0); 276#L686-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 184#L691-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 120#L696-3true assume 1 == ~E_M~0;~E_M~0 := 2; 163#L701-3true assume 1 == ~E_1~0;~E_1~0 := 2; 524#L706-3true assume 1 == ~E_2~0;~E_2~0 := 2; 431#L711-3true assume 1 == ~E_3~0;~E_3~0 := 2; 420#L716-3true assume 1 == ~E_4~0;~E_4~0 := 2; 244#L721-3true assume !(1 == ~E_5~0); 144#L726-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 501#L456-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 130#L488-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 228#L489-1true start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 165#L951true assume !(0 == start_simulation_~tmp~3); 290#L951-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 457#L456-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 308#L488-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 452#L489-2true stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 226#L906true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 110#L913true stop_simulation_#res := stop_simulation_~__retres2~0; 349#L914true start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 73#L964true assume !(0 != start_simulation_~tmp___0~1); 533#L932-1true [2021-10-15 19:08:57,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:57,671 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-10-15 19:08:57,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:57,683 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641529606] [2021-10-15 19:08:57,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:57,684 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:57,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:57,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:57,911 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:57,911 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641529606] [2021-10-15 19:08:57,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641529606] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:57,912 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:57,913 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:57,915 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044280860] [2021-10-15 19:08:57,921 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:57,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:57,922 INFO L82 PathProgramCache]: Analyzing trace with hash -44876897, now seen corresponding path program 1 times [2021-10-15 19:08:57,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:57,923 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015010456] [2021-10-15 19:08:57,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:57,923 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:57,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:57,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:57,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:57,960 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015010456] [2021-10-15 19:08:57,960 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015010456] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:57,961 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:57,961 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:08:57,961 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277331358] [2021-10-15 19:08:57,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:57,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:57,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:57,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:57,985 INFO L87 Difference]: Start difference. First operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:58,048 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2021-10-15 19:08:58,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:58,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2021-10-15 19:08:58,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2021-10-15 19:08:58,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:58,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:58,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2021-10-15 19:08:58,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:58,105 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-10-15 19:08:58,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2021-10-15 19:08:58,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:58,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.518796992481203) internal successors, (808), 531 states have internal predecessors, (808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2021-10-15 19:08:58,199 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-10-15 19:08:58,200 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-10-15 19:08:58,200 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-15 19:08:58,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2021-10-15 19:08:58,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:58,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:58,219 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,220 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,221 INFO L791 eck$LassoCheckResult]: Stem: 1615#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1604#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1553#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1554#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 1585#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1586#L423-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1430#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1415#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1395#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1277#L443-1 assume !(0 == ~M_E~0); 1278#L603-1 assume !(0 == ~T1_E~0); 1436#L608-1 assume !(0 == ~T2_E~0); 1304#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1305#L618-1 assume !(0 == ~T4_E~0); 1424#L623-1 assume !(0 == ~T5_E~0); 1543#L628-1 assume !(0 == ~E_M~0); 1609#L633-1 assume !(0 == ~E_1~0); 1529#L638-1 assume !(0 == ~E_2~0); 1530#L643-1 assume !(0 == ~E_3~0); 1562#L648-1 assume !(0 == ~E_4~0); 1563#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1583#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1208#L296 assume 1 == ~m_pc~0; 1146#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1147#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1334#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1335#L747 assume !(0 != activate_threads_~tmp~1); 1342#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1181#L315 assume !(1 == ~t1_pc~0); 1182#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 1602#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1593#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1126#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1127#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1149#L334 assume 1 == ~t2_pc~0; 1150#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1407#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1188#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1189#L763 assume !(0 != activate_threads_~tmp___1~0); 1610#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1253#L353 assume !(1 == ~t3_pc~0); 1254#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 1480#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1209#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1210#L771 assume !(0 != activate_threads_~tmp___2~0); 1544#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1545#L372 assume 1 == ~t4_pc~0; 1295#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1296#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1405#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1578#L779 assume !(0 != activate_threads_~tmp___3~0); 1160#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1161#L391 assume !(1 == ~t5_pc~0); 1087#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 1088#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1247#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1406#L787 assume !(0 != activate_threads_~tmp___4~0); 1464#L787-2 assume !(1 == ~M_E~0); 1523#L671-1 assume !(1 == ~T1_E~0); 1322#L676-1 assume !(1 == ~T2_E~0); 1323#L681-1 assume !(1 == ~T3_E~0); 1443#L686-1 assume !(1 == ~T4_E~0); 1444#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1570#L696-1 assume !(1 == ~E_M~0); 1571#L701-1 assume !(1 == ~E_1~0); 1597#L706-1 assume !(1 == ~E_2~0); 1452#L711-1 assume !(1 == ~E_3~0); 1286#L716-1 assume !(1 == ~E_4~0); 1287#L721-1 assume !(1 == ~E_5~0); 1232#L932-1 [2021-10-15 19:08:58,222 INFO L793 eck$LassoCheckResult]: Loop: 1232#L932-1 assume !false; 1594#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1099#L578 assume !false; 1184#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1185#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1281#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1458#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1459#L503 assume !(0 != eval_~tmp~0); 1551#L593 start_simulation_~kernel_st~0 := 2; 1552#L411-1 start_simulation_~kernel_st~0 := 3; 1319#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1320#L603-4 assume !(0 == ~T1_E~0); 1327#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1462#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1463#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1532#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1170#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1171#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1211#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1212#L643-3 assume !(0 == ~E_3~0); 1229#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1230#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1236#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1450#L296-21 assume 1 == ~m_pc~0; 1490#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1547#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1558#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1460#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1461#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1476#L315-21 assume 1 == ~t1_pc~0; 1477#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1352#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1606#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1391#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1392#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1300#L334-21 assume 1 == ~t2_pc~0; 1301#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1503#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1511#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1568#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1569#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1093#L353-21 assume 1 == ~t3_pc~0; 1094#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1566#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1611#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1546#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1223#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1224#L372-21 assume !(1 == ~t4_pc~0); 1418#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 1419#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1423#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1371#L779-21 assume !(0 != activate_threads_~tmp___3~0); 1130#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1131#L391-21 assume !(1 == ~t5_pc~0); 1435#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 1186#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1187#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1534#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1466#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1467#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1437#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1438#L681-3 assume !(1 == ~T3_E~0); 1495#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1410#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1315#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1316#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1385#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1603#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1595#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1468#L721-3 assume !(1 == ~E_5~0); 1354#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1355#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1144#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1330#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1388#L951 assume !(0 == start_simulation_~tmp~3); 1389#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1506#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1376#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1524#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 1448#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1298#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 1299#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 1231#L964 assume !(0 != start_simulation_~tmp___0~1); 1232#L932-1 [2021-10-15 19:08:58,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,223 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-10-15 19:08:58,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,224 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480357766] [2021-10-15 19:08:58,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,225 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,362 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,363 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480357766] [2021-10-15 19:08:58,363 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480357766] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:58,363 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:58,363 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:58,364 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361074700] [2021-10-15 19:08:58,364 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:58,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1357373672, now seen corresponding path program 1 times [2021-10-15 19:08:58,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427866821] [2021-10-15 19:08:58,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,366 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,481 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427866821] [2021-10-15 19:08:58,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427866821] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:58,482 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:58,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:58,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802780464] [2021-10-15 19:08:58,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:58,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:58,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:58,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:58,485 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:58,515 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2021-10-15 19:08:58,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:58,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2021-10-15 19:08:58,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2021-10-15 19:08:58,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:58,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:58,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2021-10-15 19:08:58,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:58,563 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-10-15 19:08:58,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2021-10-15 19:08:58,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:58,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5169172932330828) internal successors, (807), 531 states have internal predecessors, (807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2021-10-15 19:08:58,585 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-10-15 19:08:58,585 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-10-15 19:08:58,586 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-15 19:08:58,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2021-10-15 19:08:58,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:58,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:58,597 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,597 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,597 INFO L791 eck$LassoCheckResult]: Stem: 2686#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2675#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2624#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2625#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 2656#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2657#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2501#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2486#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2466#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2348#L443-1 assume !(0 == ~M_E~0); 2349#L603-1 assume !(0 == ~T1_E~0); 2509#L608-1 assume !(0 == ~T2_E~0); 2375#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2376#L618-1 assume !(0 == ~T4_E~0); 2495#L623-1 assume !(0 == ~T5_E~0); 2614#L628-1 assume !(0 == ~E_M~0); 2680#L633-1 assume !(0 == ~E_1~0); 2600#L638-1 assume !(0 == ~E_2~0); 2601#L643-1 assume !(0 == ~E_3~0); 2633#L648-1 assume !(0 == ~E_4~0); 2634#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2654#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2279#L296 assume 1 == ~m_pc~0; 2217#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2218#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2405#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2406#L747 assume !(0 != activate_threads_~tmp~1); 2413#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2254#L315 assume !(1 == ~t1_pc~0); 2255#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 2674#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2664#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2199#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2200#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2220#L334 assume 1 == ~t2_pc~0; 2221#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2478#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2259#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2260#L763 assume !(0 != activate_threads_~tmp___1~0); 2681#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2324#L353 assume !(1 == ~t3_pc~0); 2325#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 2551#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2280#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2281#L771 assume !(0 != activate_threads_~tmp___2~0); 2615#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2616#L372 assume 1 == ~t4_pc~0; 2366#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2367#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2476#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2649#L779 assume !(0 != activate_threads_~tmp___3~0); 2232#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2233#L391 assume !(1 == ~t5_pc~0); 2160#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 2161#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2318#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2477#L787 assume !(0 != activate_threads_~tmp___4~0); 2535#L787-2 assume !(1 == ~M_E~0); 2594#L671-1 assume !(1 == ~T1_E~0); 2393#L676-1 assume !(1 == ~T2_E~0); 2394#L681-1 assume !(1 == ~T3_E~0); 2514#L686-1 assume !(1 == ~T4_E~0); 2515#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2641#L696-1 assume !(1 == ~E_M~0); 2642#L701-1 assume !(1 == ~E_1~0); 2668#L706-1 assume !(1 == ~E_2~0); 2523#L711-1 assume !(1 == ~E_3~0); 2357#L716-1 assume !(1 == ~E_4~0); 2358#L721-1 assume !(1 == ~E_5~0); 2303#L932-1 [2021-10-15 19:08:58,601 INFO L793 eck$LassoCheckResult]: Loop: 2303#L932-1 assume !false; 2665#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2170#L578 assume !false; 2257#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2258#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2352#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2529#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2530#L503 assume !(0 != eval_~tmp~0); 2622#L593 start_simulation_~kernel_st~0 := 2; 2623#L411-1 start_simulation_~kernel_st~0 := 3; 2390#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2391#L603-4 assume !(0 == ~T1_E~0); 2398#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2533#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2534#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2603#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2241#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2242#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2282#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2283#L643-3 assume !(0 == ~E_3~0); 2300#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2301#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2307#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2521#L296-21 assume 1 == ~m_pc~0; 2561#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2618#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2629#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2531#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2532#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2547#L315-21 assume 1 == ~t1_pc~0; 2548#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2423#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2677#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2462#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2463#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2371#L334-21 assume 1 == ~t2_pc~0; 2372#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2574#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2582#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2639#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2640#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2164#L353-21 assume 1 == ~t3_pc~0; 2165#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2637#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2682#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2617#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2294#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2295#L372-21 assume !(1 == ~t4_pc~0); 2489#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 2490#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2494#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2440#L779-21 assume !(0 != activate_threads_~tmp___3~0); 2197#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2198#L391-21 assume !(1 == ~t5_pc~0); 2506#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 2252#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2253#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2604#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2537#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2538#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2507#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2508#L681-3 assume !(1 == ~T3_E~0); 2566#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2481#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2386#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2387#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2454#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2673#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2666#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2539#L721-3 assume !(1 == ~E_5~0); 2425#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2426#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2212#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2401#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2459#L951 assume !(0 == start_simulation_~tmp~3); 2460#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2577#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2445#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2595#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 2519#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2369#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 2370#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 2302#L964 assume !(0 != start_simulation_~tmp___0~1); 2303#L932-1 [2021-10-15 19:08:58,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,602 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-10-15 19:08:58,602 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,603 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494114564] [2021-10-15 19:08:58,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,603 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,659 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494114564] [2021-10-15 19:08:58,659 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494114564] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:58,659 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:58,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:58,660 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780015367] [2021-10-15 19:08:58,660 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:58,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,661 INFO L82 PathProgramCache]: Analyzing trace with hash -1357373672, now seen corresponding path program 2 times [2021-10-15 19:08:58,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,662 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052508584] [2021-10-15 19:08:58,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,662 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,760 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052508584] [2021-10-15 19:08:58,760 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052508584] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:58,761 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:58,761 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:58,761 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075862214] [2021-10-15 19:08:58,766 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:58,766 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:58,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:58,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:58,768 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:58,787 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2021-10-15 19:08:58,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:58,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2021-10-15 19:08:58,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2021-10-15 19:08:58,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:58,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:58,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2021-10-15 19:08:58,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:58,806 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-10-15 19:08:58,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2021-10-15 19:08:58,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:58,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5150375939849625) internal successors, (806), 531 states have internal predecessors, (806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:58,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2021-10-15 19:08:58,822 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-10-15 19:08:58,822 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-10-15 19:08:58,822 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-15 19:08:58,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2021-10-15 19:08:58,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:58,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:58,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:58,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:58,830 INFO L791 eck$LassoCheckResult]: Stem: 3757#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3746#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3695#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3696#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 3727#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3728#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3572#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3557#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3537#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3419#L443-1 assume !(0 == ~M_E~0); 3420#L603-1 assume !(0 == ~T1_E~0); 3580#L608-1 assume !(0 == ~T2_E~0); 3446#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3447#L618-1 assume !(0 == ~T4_E~0); 3566#L623-1 assume !(0 == ~T5_E~0); 3685#L628-1 assume !(0 == ~E_M~0); 3751#L633-1 assume !(0 == ~E_1~0); 3671#L638-1 assume !(0 == ~E_2~0); 3672#L643-1 assume !(0 == ~E_3~0); 3704#L648-1 assume !(0 == ~E_4~0); 3705#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3725#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3350#L296 assume 1 == ~m_pc~0; 3288#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3289#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3476#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3477#L747 assume !(0 != activate_threads_~tmp~1); 3484#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3325#L315 assume !(1 == ~t1_pc~0); 3326#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 3745#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3735#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3270#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3271#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3291#L334 assume 1 == ~t2_pc~0; 3292#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3549#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3330#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3331#L763 assume !(0 != activate_threads_~tmp___1~0); 3752#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3395#L353 assume !(1 == ~t3_pc~0); 3396#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 3622#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3351#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3352#L771 assume !(0 != activate_threads_~tmp___2~0); 3686#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3687#L372 assume 1 == ~t4_pc~0; 3437#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3438#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3547#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3720#L779 assume !(0 != activate_threads_~tmp___3~0); 3303#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3304#L391 assume !(1 == ~t5_pc~0); 3231#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 3232#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3389#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3548#L787 assume !(0 != activate_threads_~tmp___4~0); 3606#L787-2 assume !(1 == ~M_E~0); 3665#L671-1 assume !(1 == ~T1_E~0); 3464#L676-1 assume !(1 == ~T2_E~0); 3465#L681-1 assume !(1 == ~T3_E~0); 3585#L686-1 assume !(1 == ~T4_E~0); 3586#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3712#L696-1 assume !(1 == ~E_M~0); 3713#L701-1 assume !(1 == ~E_1~0); 3739#L706-1 assume !(1 == ~E_2~0); 3594#L711-1 assume !(1 == ~E_3~0); 3428#L716-1 assume !(1 == ~E_4~0); 3429#L721-1 assume !(1 == ~E_5~0); 3374#L932-1 [2021-10-15 19:08:58,830 INFO L793 eck$LassoCheckResult]: Loop: 3374#L932-1 assume !false; 3736#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3241#L578 assume !false; 3328#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3329#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3423#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3600#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3601#L503 assume !(0 != eval_~tmp~0); 3693#L593 start_simulation_~kernel_st~0 := 2; 3694#L411-1 start_simulation_~kernel_st~0 := 3; 3461#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3462#L603-4 assume !(0 == ~T1_E~0); 3469#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3604#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3605#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3674#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3312#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3313#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3353#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3354#L643-3 assume !(0 == ~E_3~0); 3371#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3372#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3378#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3592#L296-21 assume 1 == ~m_pc~0; 3632#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3689#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3700#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3602#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3603#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3618#L315-21 assume 1 == ~t1_pc~0; 3619#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3495#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3748#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3533#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3534#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3442#L334-21 assume 1 == ~t2_pc~0; 3443#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3645#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3653#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3710#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3711#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3235#L353-21 assume 1 == ~t3_pc~0; 3236#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3708#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3753#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3688#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3365#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3366#L372-21 assume !(1 == ~t4_pc~0); 3560#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 3561#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3563#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3511#L779-21 assume !(0 != activate_threads_~tmp___3~0); 3268#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3269#L391-21 assume !(1 == ~t5_pc~0); 3577#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 3323#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3324#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3675#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3608#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3609#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3578#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3579#L681-3 assume !(1 == ~T3_E~0); 3637#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3552#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3457#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3458#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3525#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3744#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3737#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3610#L721-3 assume !(1 == ~E_5~0); 3496#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3497#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3283#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3472#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3530#L951 assume !(0 == start_simulation_~tmp~3); 3531#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3648#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3516#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3666#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 3590#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3440#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 3441#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 3373#L964 assume !(0 != start_simulation_~tmp___0~1); 3374#L932-1 [2021-10-15 19:08:58,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-10-15 19:08:58,831 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,832 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726350520] [2021-10-15 19:08:58,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,832 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,913 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726350520] [2021-10-15 19:08:58,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726350520] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:58,914 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:58,915 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:58,916 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070038350] [2021-10-15 19:08:58,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:58,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:58,918 INFO L82 PathProgramCache]: Analyzing trace with hash -1357373672, now seen corresponding path program 3 times [2021-10-15 19:08:58,919 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:58,919 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108866672] [2021-10-15 19:08:58,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:58,920 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:58,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:58,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:58,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:58,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108866672] [2021-10-15 19:08:58,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108866672] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,000 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:59,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479068075] [2021-10-15 19:08:59,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:59,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:59,009 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:59,025 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2021-10-15 19:08:59,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:59,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2021-10-15 19:08:59,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2021-10-15 19:08:59,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:59,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:59,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2021-10-15 19:08:59,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:59,040 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-10-15 19:08:59,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2021-10-15 19:08:59,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:59,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.513157894736842) internal successors, (805), 531 states have internal predecessors, (805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2021-10-15 19:08:59,080 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-10-15 19:08:59,081 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-10-15 19:08:59,081 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-15 19:08:59,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2021-10-15 19:08:59,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:59,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:59,093 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,094 INFO L791 eck$LassoCheckResult]: Stem: 4828#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4817#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4766#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4767#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 4798#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4799#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4643#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4628#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4608#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4490#L443-1 assume !(0 == ~M_E~0); 4491#L603-1 assume !(0 == ~T1_E~0); 4651#L608-1 assume !(0 == ~T2_E~0); 4517#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4518#L618-1 assume !(0 == ~T4_E~0); 4637#L623-1 assume !(0 == ~T5_E~0); 4756#L628-1 assume !(0 == ~E_M~0); 4822#L633-1 assume !(0 == ~E_1~0); 4742#L638-1 assume !(0 == ~E_2~0); 4743#L643-1 assume !(0 == ~E_3~0); 4775#L648-1 assume !(0 == ~E_4~0); 4776#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4796#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4421#L296 assume 1 == ~m_pc~0; 4359#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4360#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4547#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4548#L747 assume !(0 != activate_threads_~tmp~1); 4555#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4396#L315 assume !(1 == ~t1_pc~0); 4397#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 4816#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4806#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4343#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4344#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4362#L334 assume 1 == ~t2_pc~0; 4363#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4620#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4401#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4402#L763 assume !(0 != activate_threads_~tmp___1~0); 4823#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4466#L353 assume !(1 == ~t3_pc~0); 4467#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 4693#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4422#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4423#L771 assume !(0 != activate_threads_~tmp___2~0); 4757#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4758#L372 assume 1 == ~t4_pc~0; 4508#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4509#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4618#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4791#L779 assume !(0 != activate_threads_~tmp___3~0); 4374#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4375#L391 assume !(1 == ~t5_pc~0); 4302#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 4303#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4460#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4619#L787 assume !(0 != activate_threads_~tmp___4~0); 4677#L787-2 assume !(1 == ~M_E~0); 4736#L671-1 assume !(1 == ~T1_E~0); 4535#L676-1 assume !(1 == ~T2_E~0); 4536#L681-1 assume !(1 == ~T3_E~0); 4656#L686-1 assume !(1 == ~T4_E~0); 4657#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4783#L696-1 assume !(1 == ~E_M~0); 4784#L701-1 assume !(1 == ~E_1~0); 4810#L706-1 assume !(1 == ~E_2~0); 4665#L711-1 assume !(1 == ~E_3~0); 4499#L716-1 assume !(1 == ~E_4~0); 4500#L721-1 assume !(1 == ~E_5~0); 4445#L932-1 [2021-10-15 19:08:59,094 INFO L793 eck$LassoCheckResult]: Loop: 4445#L932-1 assume !false; 4807#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4312#L578 assume !false; 4399#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4400#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4494#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4671#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4672#L503 assume !(0 != eval_~tmp~0); 4764#L593 start_simulation_~kernel_st~0 := 2; 4765#L411-1 start_simulation_~kernel_st~0 := 3; 4532#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4533#L603-4 assume !(0 == ~T1_E~0); 4540#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4675#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4676#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4745#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4383#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4384#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4424#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4425#L643-3 assume !(0 == ~E_3~0); 4442#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4443#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4449#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4663#L296-21 assume !(1 == ~m_pc~0); 4704#L296-23 is_master_triggered_~__retres1~0 := 0; 4760#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4771#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4673#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4674#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4689#L315-21 assume 1 == ~t1_pc~0; 4690#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4566#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4819#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4604#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4605#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4513#L334-21 assume 1 == ~t2_pc~0; 4514#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4716#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4724#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4781#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4782#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4304#L353-21 assume 1 == ~t3_pc~0; 4305#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4779#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4824#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4759#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4436#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4437#L372-21 assume !(1 == ~t4_pc~0); 4631#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 4632#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4634#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4582#L779-21 assume !(0 != activate_threads_~tmp___3~0); 4341#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4342#L391-21 assume !(1 == ~t5_pc~0); 4648#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 4394#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4395#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4746#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4679#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4680#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4649#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4650#L681-3 assume !(1 == ~T3_E~0); 4708#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4623#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4528#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4529#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4596#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4815#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4808#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4681#L721-3 assume !(1 == ~E_5~0); 4567#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4568#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4354#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4543#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4601#L951 assume !(0 == start_simulation_~tmp~3); 4602#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4719#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4587#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4737#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 4661#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4511#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 4512#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 4444#L964 assume !(0 != start_simulation_~tmp___0~1); 4445#L932-1 [2021-10-15 19:08:59,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,095 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-10-15 19:08:59,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,096 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278780492] [2021-10-15 19:08:59,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,096 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,129 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278780492] [2021-10-15 19:08:59,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278780492] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,129 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:59,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1478249768] [2021-10-15 19:08:59,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:59,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1031109431, now seen corresponding path program 1 times [2021-10-15 19:08:59,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,132 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521029530] [2021-10-15 19:08:59,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,132 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,167 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521029530] [2021-10-15 19:08:59,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521029530] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,168 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,168 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:59,168 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851999958] [2021-10-15 19:08:59,169 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:59,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:59,170 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:59,186 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-10-15 19:08:59,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:59,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-10-15 19:08:59,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2021-10-15 19:08:59,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:59,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:59,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2021-10-15 19:08:59,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:59,202 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-10-15 19:08:59,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2021-10-15 19:08:59,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:59,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5112781954887218) internal successors, (804), 531 states have internal predecessors, (804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2021-10-15 19:08:59,220 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-10-15 19:08:59,220 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-10-15 19:08:59,220 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-15 19:08:59,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2021-10-15 19:08:59,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:59,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:59,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,228 INFO L791 eck$LassoCheckResult]: Stem: 5899#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5888#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5837#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5838#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 5869#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5870#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5714#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5699#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5679#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5561#L443-1 assume !(0 == ~M_E~0); 5562#L603-1 assume !(0 == ~T1_E~0); 5722#L608-1 assume !(0 == ~T2_E~0); 5588#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5589#L618-1 assume !(0 == ~T4_E~0); 5708#L623-1 assume !(0 == ~T5_E~0); 5827#L628-1 assume !(0 == ~E_M~0); 5893#L633-1 assume !(0 == ~E_1~0); 5813#L638-1 assume !(0 == ~E_2~0); 5814#L643-1 assume !(0 == ~E_3~0); 5846#L648-1 assume !(0 == ~E_4~0); 5847#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5867#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5492#L296 assume 1 == ~m_pc~0; 5430#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5431#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5618#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5619#L747 assume !(0 != activate_threads_~tmp~1); 5626#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5467#L315 assume !(1 == ~t1_pc~0); 5468#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 5887#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5877#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5414#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5415#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5433#L334 assume 1 == ~t2_pc~0; 5434#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5691#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5472#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5473#L763 assume !(0 != activate_threads_~tmp___1~0); 5894#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5537#L353 assume !(1 == ~t3_pc~0); 5538#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 5764#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5493#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5494#L771 assume !(0 != activate_threads_~tmp___2~0); 5828#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5829#L372 assume 1 == ~t4_pc~0; 5579#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5580#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5689#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5862#L779 assume !(0 != activate_threads_~tmp___3~0); 5445#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5446#L391 assume !(1 == ~t5_pc~0); 5373#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 5374#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5531#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5690#L787 assume !(0 != activate_threads_~tmp___4~0); 5748#L787-2 assume !(1 == ~M_E~0); 5807#L671-1 assume !(1 == ~T1_E~0); 5606#L676-1 assume !(1 == ~T2_E~0); 5607#L681-1 assume !(1 == ~T3_E~0); 5727#L686-1 assume !(1 == ~T4_E~0); 5728#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5854#L696-1 assume !(1 == ~E_M~0); 5855#L701-1 assume !(1 == ~E_1~0); 5881#L706-1 assume !(1 == ~E_2~0); 5736#L711-1 assume !(1 == ~E_3~0); 5570#L716-1 assume !(1 == ~E_4~0); 5571#L721-1 assume !(1 == ~E_5~0); 5516#L932-1 [2021-10-15 19:08:59,229 INFO L793 eck$LassoCheckResult]: Loop: 5516#L932-1 assume !false; 5878#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5383#L578 assume !false; 5470#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5471#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5565#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5742#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5743#L503 assume !(0 != eval_~tmp~0); 5835#L593 start_simulation_~kernel_st~0 := 2; 5836#L411-1 start_simulation_~kernel_st~0 := 3; 5603#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5604#L603-4 assume !(0 == ~T1_E~0); 5611#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5746#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5747#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5816#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5454#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5455#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5495#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5496#L643-3 assume !(0 == ~E_3~0); 5513#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5514#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5521#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5734#L296-21 assume 1 == ~m_pc~0; 5774#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5831#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5842#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5744#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5745#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5760#L315-21 assume 1 == ~t1_pc~0; 5761#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5637#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5890#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5675#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5676#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5584#L334-21 assume 1 == ~t2_pc~0; 5585#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5787#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5795#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5852#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5853#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5375#L353-21 assume 1 == ~t3_pc~0; 5376#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5850#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5895#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5830#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5507#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5508#L372-21 assume !(1 == ~t4_pc~0); 5702#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 5703#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5705#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5653#L779-21 assume !(0 != activate_threads_~tmp___3~0); 5412#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5413#L391-21 assume !(1 == ~t5_pc~0); 5719#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 5465#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5466#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5817#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5750#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5751#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5720#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5721#L681-3 assume !(1 == ~T3_E~0); 5779#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5694#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5599#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5600#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5667#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5886#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5879#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5752#L721-3 assume !(1 == ~E_5~0); 5638#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5639#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5425#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5614#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5672#L951 assume !(0 == start_simulation_~tmp~3); 5673#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5790#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5658#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5808#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 5732#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5582#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 5583#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 5515#L964 assume !(0 != start_simulation_~tmp___0~1); 5516#L932-1 [2021-10-15 19:08:59,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-10-15 19:08:59,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384418097] [2021-10-15 19:08:59,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,231 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,266 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384418097] [2021-10-15 19:08:59,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384418097] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,267 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:08:59,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644662856] [2021-10-15 19:08:59,269 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:59,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1357373672, now seen corresponding path program 4 times [2021-10-15 19:08:59,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,270 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398745163] [2021-10-15 19:08:59,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,270 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,306 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398745163] [2021-10-15 19:08:59,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398745163] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,306 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,306 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:59,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678138926] [2021-10-15 19:08:59,307 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,307 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:59,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:59,308 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:59,330 INFO L93 Difference]: Finished difference Result 532 states and 799 transitions. [2021-10-15 19:08:59,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:59,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 799 transitions. [2021-10-15 19:08:59,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 799 transitions. [2021-10-15 19:08:59,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:59,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:59,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 799 transitions. [2021-10-15 19:08:59,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:59,345 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-10-15 19:08:59,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 799 transitions. [2021-10-15 19:08:59,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:59,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5018796992481203) internal successors, (799), 531 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 799 transitions. [2021-10-15 19:08:59,362 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-10-15 19:08:59,362 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-10-15 19:08:59,363 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-15 19:08:59,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 799 transitions. [2021-10-15 19:08:59,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:59,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:59,373 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,374 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,374 INFO L791 eck$LassoCheckResult]: Stem: 6970#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6959#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6908#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6909#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 6940#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6941#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6785#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6770#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6750#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6632#L443-1 assume !(0 == ~M_E~0); 6633#L603-1 assume !(0 == ~T1_E~0); 6793#L608-1 assume !(0 == ~T2_E~0); 6659#L613-1 assume !(0 == ~T3_E~0); 6660#L618-1 assume !(0 == ~T4_E~0); 6781#L623-1 assume !(0 == ~T5_E~0); 6898#L628-1 assume !(0 == ~E_M~0); 6964#L633-1 assume !(0 == ~E_1~0); 6884#L638-1 assume !(0 == ~E_2~0); 6885#L643-1 assume !(0 == ~E_3~0); 6917#L648-1 assume !(0 == ~E_4~0); 6918#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6938#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6563#L296 assume 1 == ~m_pc~0; 6501#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6502#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6689#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6690#L747 assume !(0 != activate_threads_~tmp~1); 6697#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6538#L315 assume !(1 == ~t1_pc~0); 6539#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 6958#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6948#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6485#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6486#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6504#L334 assume 1 == ~t2_pc~0; 6505#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6763#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6543#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6544#L763 assume !(0 != activate_threads_~tmp___1~0); 6965#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6608#L353 assume !(1 == ~t3_pc~0); 6609#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 6835#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6564#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6565#L771 assume !(0 != activate_threads_~tmp___2~0); 6899#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6900#L372 assume 1 == ~t4_pc~0; 6650#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6651#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6760#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6933#L779 assume !(0 != activate_threads_~tmp___3~0); 6516#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6517#L391 assume !(1 == ~t5_pc~0); 6444#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 6445#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6602#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6761#L787 assume !(0 != activate_threads_~tmp___4~0); 6819#L787-2 assume !(1 == ~M_E~0); 6878#L671-1 assume !(1 == ~T1_E~0); 6677#L676-1 assume !(1 == ~T2_E~0); 6678#L681-1 assume !(1 == ~T3_E~0); 6798#L686-1 assume !(1 == ~T4_E~0); 6799#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6925#L696-1 assume !(1 == ~E_M~0); 6926#L701-1 assume !(1 == ~E_1~0); 6952#L706-1 assume !(1 == ~E_2~0); 6807#L711-1 assume !(1 == ~E_3~0); 6641#L716-1 assume !(1 == ~E_4~0); 6642#L721-1 assume !(1 == ~E_5~0); 6587#L932-1 [2021-10-15 19:08:59,375 INFO L793 eck$LassoCheckResult]: Loop: 6587#L932-1 assume !false; 6949#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6454#L578 assume !false; 6541#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6542#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6636#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6813#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 6814#L503 assume !(0 != eval_~tmp~0); 6906#L593 start_simulation_~kernel_st~0 := 2; 6907#L411-1 start_simulation_~kernel_st~0 := 3; 6674#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6675#L603-4 assume !(0 == ~T1_E~0); 6682#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6817#L613-3 assume !(0 == ~T3_E~0); 6818#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6887#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6525#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6526#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6566#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6567#L643-3 assume !(0 == ~E_3~0); 6584#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6585#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6592#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6805#L296-21 assume 1 == ~m_pc~0; 6845#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6902#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6911#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6815#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6816#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6831#L315-21 assume 1 == ~t1_pc~0; 6832#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6707#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6961#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6746#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6747#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6655#L334-21 assume 1 == ~t2_pc~0; 6656#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6858#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6866#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6923#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6924#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6448#L353-21 assume 1 == ~t3_pc~0; 6449#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6921#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6966#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6901#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6578#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6579#L372-21 assume !(1 == ~t4_pc~0); 6773#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 6774#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6776#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6724#L779-21 assume !(0 != activate_threads_~tmp___3~0); 6483#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6484#L391-21 assume !(1 == ~t5_pc~0); 6790#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 6536#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6537#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6889#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6821#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6822#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6791#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6792#L681-3 assume !(1 == ~T3_E~0); 6850#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6765#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6670#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6671#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6738#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6957#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6950#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6823#L721-3 assume !(1 == ~E_5~0); 6709#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6710#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6499#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6685#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6743#L951 assume !(0 == start_simulation_~tmp~3); 6744#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6861#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6729#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6879#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 6803#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6653#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 6654#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 6586#L964 assume !(0 != start_simulation_~tmp___0~1); 6587#L932-1 [2021-10-15 19:08:59,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,376 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2021-10-15 19:08:59,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,377 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843375831] [2021-10-15 19:08:59,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,378 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,417 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843375831] [2021-10-15 19:08:59,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843375831] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,417 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,417 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:08:59,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836935828] [2021-10-15 19:08:59,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:59,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,419 INFO L82 PathProgramCache]: Analyzing trace with hash 551084118, now seen corresponding path program 1 times [2021-10-15 19:08:59,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,419 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540416938] [2021-10-15 19:08:59,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,420 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,470 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540416938] [2021-10-15 19:08:59,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540416938] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,470 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:08:59,471 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411053615] [2021-10-15 19:08:59,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:59,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:59,472 INFO L87 Difference]: Start difference. First operand 532 states and 799 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:59,528 INFO L93 Difference]: Finished difference Result 532 states and 786 transitions. [2021-10-15 19:08:59,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:59,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 786 transitions. [2021-10-15 19:08:59,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 786 transitions. [2021-10-15 19:08:59,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-10-15 19:08:59,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-10-15 19:08:59,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 786 transitions. [2021-10-15 19:08:59,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:59,542 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-10-15 19:08:59,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 786 transitions. [2021-10-15 19:08:59,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-10-15 19:08:59,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.4774436090225564) internal successors, (786), 531 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 786 transitions. [2021-10-15 19:08:59,555 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-10-15 19:08:59,555 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-10-15 19:08:59,556 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-15 19:08:59,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 786 transitions. [2021-10-15 19:08:59,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-10-15 19:08:59,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:59,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:59,562 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,562 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,562 INFO L791 eck$LassoCheckResult]: Stem: 8041#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 8030#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7979#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7980#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 8011#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8012#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7854#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7839#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7818#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7702#L443-1 assume !(0 == ~M_E~0); 7703#L603-1 assume !(0 == ~T1_E~0); 7863#L608-1 assume !(0 == ~T2_E~0); 7729#L613-1 assume !(0 == ~T3_E~0); 7730#L618-1 assume !(0 == ~T4_E~0); 7850#L623-1 assume !(0 == ~T5_E~0); 7969#L628-1 assume !(0 == ~E_M~0); 8035#L633-1 assume !(0 == ~E_1~0); 7954#L638-1 assume !(0 == ~E_2~0); 7955#L643-1 assume !(0 == ~E_3~0); 7988#L648-1 assume !(0 == ~E_4~0); 7989#L653-1 assume !(0 == ~E_5~0); 8009#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7634#L296 assume 1 == ~m_pc~0; 7572#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7573#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7759#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7760#L747 assume !(0 != activate_threads_~tmp~1); 7766#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7609#L315 assume !(1 == ~t1_pc~0); 7610#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 8029#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8019#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7556#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7557#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7575#L334 assume 1 == ~t2_pc~0; 7576#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7832#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7614#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7615#L763 assume !(0 != activate_threads_~tmp___1~0); 8036#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7678#L353 assume !(1 == ~t3_pc~0); 7679#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 7905#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7635#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7636#L771 assume !(0 != activate_threads_~tmp___2~0); 7970#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7971#L372 assume 1 == ~t4_pc~0; 7720#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7721#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7829#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8004#L779 assume !(0 != activate_threads_~tmp___3~0); 7587#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7588#L391 assume !(1 == ~t5_pc~0); 7515#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 7516#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7673#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7830#L787 assume !(0 != activate_threads_~tmp___4~0); 7889#L787-2 assume !(1 == ~M_E~0); 7948#L671-1 assume !(1 == ~T1_E~0); 7747#L676-1 assume !(1 == ~T2_E~0); 7748#L681-1 assume !(1 == ~T3_E~0); 7868#L686-1 assume !(1 == ~T4_E~0); 7869#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7996#L696-1 assume !(1 == ~E_M~0); 7997#L701-1 assume !(1 == ~E_1~0); 8023#L706-1 assume !(1 == ~E_2~0); 7877#L711-1 assume !(1 == ~E_3~0); 7711#L716-1 assume !(1 == ~E_4~0); 7712#L721-1 assume !(1 == ~E_5~0); 7658#L932-1 [2021-10-15 19:08:59,563 INFO L793 eck$LassoCheckResult]: Loop: 7658#L932-1 assume !false; 8020#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7525#L578 assume !false; 7612#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7613#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7706#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7883#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7884#L503 assume !(0 != eval_~tmp~0); 7977#L593 start_simulation_~kernel_st~0 := 2; 7978#L411-1 start_simulation_~kernel_st~0 := 3; 7744#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7745#L603-4 assume !(0 == ~T1_E~0); 7752#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7887#L613-3 assume !(0 == ~T3_E~0); 7888#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7957#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7598#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7599#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7637#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7638#L643-3 assume !(0 == ~E_3~0); 7655#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7656#L653-3 assume !(0 == ~E_5~0); 7662#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7875#L296-21 assume 1 == ~m_pc~0; 7915#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7973#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7982#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7885#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7886#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7901#L315-21 assume 1 == ~t1_pc~0; 7902#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7776#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8032#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7814#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7815#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7725#L334-21 assume 1 == ~t2_pc~0; 7726#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7928#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7936#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7994#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7995#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7519#L353-21 assume 1 == ~t3_pc~0; 7520#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7992#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8037#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7972#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7649#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7650#L372-21 assume !(1 == ~t4_pc~0); 7842#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 7843#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7845#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7792#L779-21 assume !(0 != activate_threads_~tmp___3~0); 7554#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7555#L391-21 assume !(1 == ~t5_pc~0); 7859#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 7607#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7608#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7959#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7891#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7892#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7861#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7862#L681-3 assume !(1 == ~T3_E~0); 7920#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7740#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7741#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7806#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8028#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8021#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7893#L721-3 assume !(1 == ~E_5~0); 7777#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7778#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7570#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7755#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7811#L951 assume !(0 == start_simulation_~tmp~3); 7812#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7931#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7797#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7949#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 7873#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7723#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 7724#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 7657#L964 assume !(0 != start_simulation_~tmp___0~1); 7658#L932-1 [2021-10-15 19:08:59,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,564 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2021-10-15 19:08:59,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,565 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494305915] [2021-10-15 19:08:59,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,565 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,610 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494305915] [2021-10-15 19:08:59,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494305915] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,611 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:08:59,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560656907] [2021-10-15 19:08:59,612 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:59,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,613 INFO L82 PathProgramCache]: Analyzing trace with hash 1230356372, now seen corresponding path program 1 times [2021-10-15 19:08:59,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,613 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807507097] [2021-10-15 19:08:59,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,614 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,661 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807507097] [2021-10-15 19:08:59,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807507097] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,668 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,668 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:08:59,668 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526211019] [2021-10-15 19:08:59,669 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,669 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:08:59,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:08:59,670 INFO L87 Difference]: Start difference. First operand 532 states and 786 transitions. cyclomatic complexity: 255 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:08:59,744 INFO L93 Difference]: Finished difference Result 973 states and 1419 transitions. [2021-10-15 19:08:59,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:08:59,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1419 transitions. [2021-10-15 19:08:59,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 898 [2021-10-15 19:08:59,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1419 transitions. [2021-10-15 19:08:59,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-10-15 19:08:59,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-10-15 19:08:59,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1419 transitions. [2021-10-15 19:08:59,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:08:59,774 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1419 transitions. [2021-10-15 19:08:59,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1419 transitions. [2021-10-15 19:08:59,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 933. [2021-10-15 19:08:59,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4619506966773848) internal successors, (1364), 932 states have internal predecessors, (1364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:08:59,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1364 transitions. [2021-10-15 19:08:59,806 INFO L704 BuchiCegarLoop]: Abstraction has 933 states and 1364 transitions. [2021-10-15 19:08:59,807 INFO L587 BuchiCegarLoop]: Abstraction has 933 states and 1364 transitions. [2021-10-15 19:08:59,807 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-15 19:08:59,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1364 transitions. [2021-10-15 19:08:59,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 858 [2021-10-15 19:08:59,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:08:59,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:08:59,816 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,816 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:08:59,816 INFO L791 eck$LassoCheckResult]: Stem: 9574#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9561#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9499#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9500#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 9535#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9536#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9367#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9352#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9331#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9218#L443-1 assume !(0 == ~M_E~0); 9219#L603-1 assume !(0 == ~T1_E~0); 9381#L608-1 assume !(0 == ~T2_E~0); 9244#L613-1 assume !(0 == ~T3_E~0); 9245#L618-1 assume !(0 == ~T4_E~0); 9363#L623-1 assume !(0 == ~T5_E~0); 9488#L628-1 assume !(0 == ~E_M~0); 9566#L633-1 assume !(0 == ~E_1~0); 9473#L638-1 assume !(0 == ~E_2~0); 9474#L643-1 assume !(0 == ~E_3~0); 9508#L648-1 assume !(0 == ~E_4~0); 9509#L653-1 assume !(0 == ~E_5~0); 9533#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9145#L296 assume !(1 == ~m_pc~0); 9146#L296-2 is_master_triggered_~__retres1~0 := 0; 9370#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9273#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9274#L747 assume !(0 != activate_threads_~tmp~1); 9280#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9122#L315 assume !(1 == ~t1_pc~0); 9123#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 9555#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9543#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9070#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9071#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9086#L334 assume 1 == ~t2_pc~0; 9087#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9345#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9125#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9126#L763 assume !(0 != activate_threads_~tmp___1~0); 9567#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9192#L353 assume !(1 == ~t3_pc~0); 9193#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 9423#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9149#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9150#L771 assume !(0 != activate_threads_~tmp___2~0); 9489#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9490#L372 assume 1 == ~t4_pc~0; 9235#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9236#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9342#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9525#L779 assume !(0 != activate_threads_~tmp___3~0); 9098#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9099#L391 assume !(1 == ~t5_pc~0); 9029#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 9030#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9187#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9343#L787 assume !(0 != activate_threads_~tmp___4~0); 9409#L787-2 assume !(1 == ~M_E~0); 9466#L671-1 assume !(1 == ~T1_E~0); 9264#L676-1 assume !(1 == ~T2_E~0); 9265#L681-1 assume !(1 == ~T3_E~0); 9387#L686-1 assume !(1 == ~T4_E~0); 9388#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9517#L696-1 assume !(1 == ~E_M~0); 9518#L701-1 assume !(1 == ~E_1~0); 9547#L706-1 assume !(1 == ~E_2~0); 9396#L711-1 assume !(1 == ~E_3~0); 9226#L716-1 assume !(1 == ~E_4~0); 9227#L721-1 assume !(1 == ~E_5~0); 9170#L932-1 [2021-10-15 19:08:59,817 INFO L793 eck$LassoCheckResult]: Loop: 9170#L932-1 assume !false; 9544#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9039#L578 assume !false; 9118#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9119#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9220#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9402#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 9403#L503 assume !(0 != eval_~tmp~0); 9497#L593 start_simulation_~kernel_st~0 := 2; 9498#L411-1 start_simulation_~kernel_st~0 := 3; 9259#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9260#L603-4 assume !(0 == ~T1_E~0); 9266#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9406#L613-3 assume !(0 == ~T3_E~0); 9407#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9476#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9107#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9108#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9147#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9148#L643-3 assume !(0 == ~E_3~0); 9167#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9168#L653-3 assume !(0 == ~E_5~0); 9174#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9394#L296-21 assume !(1 == ~m_pc~0); 9434#L296-23 is_master_triggered_~__retres1~0 := 0; 9925#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9924#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9923#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9922#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9921#L315-21 assume 1 == ~t1_pc~0; 9920#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9918#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9917#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9916#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9915#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9914#L334-21 assume 1 == ~t2_pc~0; 9912#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9911#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9910#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9909#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9908#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9904#L353-21 assume !(1 == ~t3_pc~0); 9901#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 9899#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9897#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9895#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9893#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9891#L372-21 assume 1 == ~t4_pc~0; 9888#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9886#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9884#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9882#L779-21 assume !(0 != activate_threads_~tmp___3~0); 9880#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9878#L391-21 assume !(1 == ~t5_pc~0); 9876#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 9120#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9121#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9478#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9410#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9411#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9379#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9380#L681-3 assume !(1 == ~T3_E~0); 9438#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9347#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9255#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9256#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9321#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9554#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9545#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9412#L721-3 assume !(1 == ~E_5~0); 9290#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9291#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9084#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9269#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9324#L951 assume !(0 == start_simulation_~tmp~3); 9325#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9449#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9312#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9467#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 9393#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9238#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 9239#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 9169#L964 assume !(0 != start_simulation_~tmp___0~1); 9170#L932-1 [2021-10-15 19:08:59,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,818 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2021-10-15 19:08:59,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128325352] [2021-10-15 19:08:59,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,819 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,872 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128325352] [2021-10-15 19:08:59,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128325352] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,873 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:08:59,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298125489] [2021-10-15 19:08:59,874 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:08:59,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:08:59,875 INFO L82 PathProgramCache]: Analyzing trace with hash -1066825613, now seen corresponding path program 1 times [2021-10-15 19:08:59,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:08:59,875 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241614318] [2021-10-15 19:08:59,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:08:59,876 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:08:59,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:08:59,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:08:59,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:08:59,922 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241614318] [2021-10-15 19:08:59,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241614318] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:08:59,923 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:08:59,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:08:59,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682970323] [2021-10-15 19:08:59,924 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:08:59,924 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:08:59,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 19:08:59,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 19:08:59,925 INFO L87 Difference]: Start difference. First operand 933 states and 1364 transitions. cyclomatic complexity: 433 Second operand has 5 states, 5 states have (on average 13.8) internal successors, (69), 5 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:00,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:00,167 INFO L93 Difference]: Finished difference Result 2500 states and 3642 transitions. [2021-10-15 19:09:00,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-15 19:09:00,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2500 states and 3642 transitions. [2021-10-15 19:09:00,192 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2340 [2021-10-15 19:09:00,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2500 states to 2500 states and 3642 transitions. [2021-10-15 19:09:00,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2500 [2021-10-15 19:09:00,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2500 [2021-10-15 19:09:00,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2500 states and 3642 transitions. [2021-10-15 19:09:00,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:00,228 INFO L681 BuchiCegarLoop]: Abstraction has 2500 states and 3642 transitions. [2021-10-15 19:09:00,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2500 states and 3642 transitions. [2021-10-15 19:09:00,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2500 to 981. [2021-10-15 19:09:00,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4393476044852191) internal successors, (1412), 980 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:00,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1412 transitions. [2021-10-15 19:09:00,288 INFO L704 BuchiCegarLoop]: Abstraction has 981 states and 1412 transitions. [2021-10-15 19:09:00,288 INFO L587 BuchiCegarLoop]: Abstraction has 981 states and 1412 transitions. [2021-10-15 19:09:00,288 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-15 19:09:00,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1412 transitions. [2021-10-15 19:09:00,295 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 903 [2021-10-15 19:09:00,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:00,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:00,297 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:00,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:00,298 INFO L791 eck$LassoCheckResult]: Stem: 13062#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13038#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12970#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12971#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 13008#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13009#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12822#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12803#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12781#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12663#L443-1 assume !(0 == ~M_E~0); 12664#L603-1 assume !(0 == ~T1_E~0); 12832#L608-1 assume !(0 == ~T2_E~0); 12691#L613-1 assume !(0 == ~T3_E~0); 12692#L618-1 assume !(0 == ~T4_E~0); 12813#L623-1 assume !(0 == ~T5_E~0); 12956#L628-1 assume !(0 == ~E_M~0); 13044#L633-1 assume !(0 == ~E_1~0); 12939#L638-1 assume !(0 == ~E_2~0); 12940#L643-1 assume !(0 == ~E_3~0); 12980#L648-1 assume !(0 == ~E_4~0); 12981#L653-1 assume !(0 == ~E_5~0); 13006#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12594#L296 assume !(1 == ~m_pc~0); 12595#L296-2 is_master_triggered_~__retres1~0 := 0; 12825#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12720#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12721#L747 assume !(0 != activate_threads_~tmp~1); 12727#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12567#L315 assume !(1 == ~t1_pc~0); 12568#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 13029#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13030#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12514#L755 assume !(0 != activate_threads_~tmp___0~0); 12515#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12534#L334 assume 1 == ~t2_pc~0; 12535#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12794#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12574#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12575#L763 assume !(0 != activate_threads_~tmp___1~0); 13045#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12639#L353 assume !(1 == ~t3_pc~0); 12640#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 12885#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12596#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12597#L771 assume !(0 != activate_threads_~tmp___2~0); 12957#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12958#L372 assume 1 == ~t4_pc~0; 12681#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12682#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12792#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12998#L779 assume !(0 != activate_threads_~tmp___3~0); 12547#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12548#L391 assume !(1 == ~t5_pc~0); 12475#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 12476#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12634#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12793#L787 assume !(0 != activate_threads_~tmp___4~0); 12867#L787-2 assume !(1 == ~M_E~0); 12931#L671-1 assume !(1 == ~T1_E~0); 12709#L676-1 assume !(1 == ~T2_E~0); 12710#L681-1 assume !(1 == ~T3_E~0); 12840#L686-1 assume !(1 == ~T4_E~0); 12841#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12989#L696-1 assume !(1 == ~E_M~0); 12990#L701-1 assume !(1 == ~E_1~0); 13022#L706-1 assume !(1 == ~E_2~0); 12854#L711-1 assume !(1 == ~E_3~0); 12672#L716-1 assume !(1 == ~E_4~0); 12673#L721-1 assume !(1 == ~E_5~0); 12619#L932-1 [2021-10-15 19:09:00,298 INFO L793 eck$LassoCheckResult]: Loop: 12619#L932-1 assume !false; 13019#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12487#L578 assume !false; 12570#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12571#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12667#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12861#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12862#L503 assume !(0 != eval_~tmp~0); 13042#L593 start_simulation_~kernel_st~0 := 2; 13428#L411-1 start_simulation_~kernel_st~0 := 3; 13427#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13426#L603-4 assume !(0 == ~T1_E~0); 13425#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13424#L613-3 assume !(0 == ~T3_E~0); 13423#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13367#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13366#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13365#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13364#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13363#L643-3 assume !(0 == ~E_3~0); 13362#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13361#L653-3 assume !(0 == ~E_5~0); 12850#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12851#L296-21 assume !(1 == ~m_pc~0); 12895#L296-23 is_master_triggered_~__retres1~0 := 0; 13451#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13450#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13449#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13448#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12880#L315-21 assume !(1 == ~t1_pc~0); 12881#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 13447#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13445#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13443#L755-21 assume !(0 != activate_threads_~tmp___0~0); 13441#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13440#L334-21 assume 1 == ~t2_pc~0; 13438#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13437#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13436#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13435#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13434#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13433#L353-21 assume !(1 == ~t3_pc~0); 13431#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 13430#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13429#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12959#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12610#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12611#L372-21 assume !(1 == ~t4_pc~0); 12806#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 12807#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12812#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12756#L779-21 assume !(0 != activate_threads_~tmp___3~0); 12518#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12519#L391-21 assume !(1 == ~t5_pc~0); 12830#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 12572#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12573#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12944#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12869#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 12870#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12833#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12834#L681-3 assume !(1 == ~T3_E~0); 12899#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12798#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12702#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12703#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12770#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13031#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13020#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12871#L721-3 assume !(1 == ~E_5~0); 12738#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12739#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12532#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12716#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 12773#L951 assume !(0 == start_simulation_~tmp~3); 12774#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12912#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12759#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12932#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 12848#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12684#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 12685#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 12618#L964 assume !(0 != start_simulation_~tmp___0~1); 12619#L932-1 [2021-10-15 19:09:00,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:00,299 INFO L82 PathProgramCache]: Analyzing trace with hash -1507063107, now seen corresponding path program 1 times [2021-10-15 19:09:00,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:00,300 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395702486] [2021-10-15 19:09:00,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:00,300 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:00,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:00,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:00,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:00,355 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395702486] [2021-10-15 19:09:00,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395702486] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:00,356 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:00,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:00,356 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232670662] [2021-10-15 19:09:00,358 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:09:00,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:00,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1085046063, now seen corresponding path program 1 times [2021-10-15 19:09:00,359 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:00,359 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451985412] [2021-10-15 19:09:00,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:00,359 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:00,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:00,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:00,406 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:00,406 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451985412] [2021-10-15 19:09:00,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1451985412] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:00,413 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:00,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:09:00,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983604143] [2021-10-15 19:09:00,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:00,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:00,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-15 19:09:00,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-15 19:09:00,415 INFO L87 Difference]: Start difference. First operand 981 states and 1412 transitions. cyclomatic complexity: 433 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:00,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:00,600 INFO L93 Difference]: Finished difference Result 2246 states and 3192 transitions. [2021-10-15 19:09:00,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-15 19:09:00,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2246 states and 3192 transitions. [2021-10-15 19:09:00,624 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2118 [2021-10-15 19:09:00,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2246 states to 2246 states and 3192 transitions. [2021-10-15 19:09:00,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2246 [2021-10-15 19:09:00,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2246 [2021-10-15 19:09:00,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2246 states and 3192 transitions. [2021-10-15 19:09:00,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:00,655 INFO L681 BuchiCegarLoop]: Abstraction has 2246 states and 3192 transitions. [2021-10-15 19:09:00,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2246 states and 3192 transitions. [2021-10-15 19:09:00,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2246 to 1776. [2021-10-15 19:09:00,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1776 states, 1776 states have (on average 1.4301801801801801) internal successors, (2540), 1775 states have internal predecessors, (2540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:00,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 1776 states and 2540 transitions. [2021-10-15 19:09:00,704 INFO L704 BuchiCegarLoop]: Abstraction has 1776 states and 2540 transitions. [2021-10-15 19:09:00,704 INFO L587 BuchiCegarLoop]: Abstraction has 1776 states and 2540 transitions. [2021-10-15 19:09:00,704 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-15 19:09:00,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1776 states and 2540 transitions. [2021-10-15 19:09:00,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1698 [2021-10-15 19:09:00,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:00,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:00,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:00,720 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:00,721 INFO L791 eck$LassoCheckResult]: Stem: 16280#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16257#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16188#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16189#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 16230#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16231#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16054#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16036#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16015#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15899#L443-1 assume !(0 == ~M_E~0); 15900#L603-1 assume !(0 == ~T1_E~0); 16062#L608-1 assume !(0 == ~T2_E~0); 15927#L613-1 assume !(0 == ~T3_E~0); 15928#L618-1 assume !(0 == ~T4_E~0); 16046#L623-1 assume !(0 == ~T5_E~0); 16178#L628-1 assume !(0 == ~E_M~0); 16264#L633-1 assume !(0 == ~E_1~0); 16163#L638-1 assume !(0 == ~E_2~0); 16164#L643-1 assume !(0 == ~E_3~0); 16201#L648-1 assume !(0 == ~E_4~0); 16202#L653-1 assume !(0 == ~E_5~0); 16228#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15830#L296 assume !(1 == ~m_pc~0); 15831#L296-2 is_master_triggered_~__retres1~0 := 0; 16057#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15956#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15957#L747 assume !(0 != activate_threads_~tmp~1); 15963#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15803#L315 assume !(1 == ~t1_pc~0); 15804#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 16272#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16285#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15752#L755 assume !(0 != activate_threads_~tmp___0~0); 15753#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15772#L334 assume !(1 == ~t2_pc~0); 15773#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 16028#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15810#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15811#L763 assume !(0 != activate_threads_~tmp___1~0); 16265#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15875#L353 assume !(1 == ~t3_pc~0); 15876#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 16110#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15832#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15833#L771 assume !(0 != activate_threads_~tmp___2~0); 16179#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16180#L372 assume 1 == ~t4_pc~0; 15919#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15920#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16026#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16221#L779 assume !(0 != activate_threads_~tmp___3~0); 15782#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15783#L391 assume !(1 == ~t5_pc~0); 15714#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 15715#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15870#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16027#L787 assume !(0 != activate_threads_~tmp___4~0); 16094#L787-2 assume !(1 == ~M_E~0); 16156#L671-1 assume !(1 == ~T1_E~0); 15945#L676-1 assume !(1 == ~T2_E~0); 15946#L681-1 assume !(1 == ~T3_E~0); 16070#L686-1 assume !(1 == ~T4_E~0); 16071#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16212#L696-1 assume !(1 == ~E_M~0); 16213#L701-1 assume !(1 == ~E_1~0); 16241#L706-1 assume !(1 == ~E_2~0); 16079#L711-1 assume !(1 == ~E_3~0); 15910#L716-1 assume !(1 == ~E_4~0); 15911#L721-1 assume !(1 == ~E_5~0); 15855#L932-1 [2021-10-15 19:09:00,721 INFO L793 eck$LassoCheckResult]: Loop: 15855#L932-1 assume !false; 16239#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 15726#L578 assume !false; 15806#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15807#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15903#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16088#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16089#L503 assume !(0 != eval_~tmp~0); 16186#L593 start_simulation_~kernel_st~0 := 2; 16187#L411-1 start_simulation_~kernel_st~0 := 3; 15942#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15943#L603-4 assume !(0 == ~T1_E~0); 15949#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16092#L613-3 assume !(0 == ~T3_E~0); 16093#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16166#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15792#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15793#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15834#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15835#L643-3 assume !(0 == ~E_3~0); 15852#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15853#L653-3 assume !(0 == ~E_5~0); 15859#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16077#L296-21 assume !(1 == ~m_pc~0); 16120#L296-23 is_master_triggered_~__retres1~0 := 0; 16182#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16194#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16090#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16091#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16107#L315-21 assume !(1 == ~t1_pc~0); 15972#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 15973#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16261#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16011#L755-21 assume !(0 != activate_threads_~tmp___0~0); 16012#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15924#L334-21 assume !(1 == ~t2_pc~0); 15925#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 16143#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16144#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16210#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16211#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15718#L353-21 assume 1 == ~t3_pc~0; 15719#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16208#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16266#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16181#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15846#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15847#L372-21 assume 1 == ~t4_pc~0; 16113#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16040#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16045#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15988#L779-21 assume !(0 != activate_threads_~tmp___3~0); 15756#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15757#L391-21 assume !(1 == ~t5_pc~0); 16060#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 15808#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15809#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16168#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16096#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 16097#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16063#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16064#L681-3 assume !(1 == ~T3_E~0); 16124#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16031#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15938#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15939#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16004#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16251#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16240#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16098#L721-3 assume !(1 == ~E_5~0); 15974#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15975#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15770#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15952#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 16007#L951 assume !(0 == start_simulation_~tmp~3); 16008#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16138#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15995#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16157#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 16076#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15922#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 15923#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 15854#L964 assume !(0 != start_simulation_~tmp___0~1); 15855#L932-1 [2021-10-15 19:09:00,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:00,722 INFO L82 PathProgramCache]: Analyzing trace with hash -455614018, now seen corresponding path program 1 times [2021-10-15 19:09:00,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:00,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121485803] [2021-10-15 19:09:00,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:00,723 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:00,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:00,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:00,775 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:00,775 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121485803] [2021-10-15 19:09:00,775 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121485803] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:00,776 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:00,776 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:09:00,776 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884488794] [2021-10-15 19:09:00,776 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:09:00,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:00,777 INFO L82 PathProgramCache]: Analyzing trace with hash 2143244496, now seen corresponding path program 1 times [2021-10-15 19:09:00,777 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:00,778 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513958740] [2021-10-15 19:09:00,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:00,778 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:00,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:00,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:00,824 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:00,824 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513958740] [2021-10-15 19:09:00,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513958740] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:00,824 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:00,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:09:00,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002684767] [2021-10-15 19:09:00,825 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:00,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:00,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:00,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:00,826 INFO L87 Difference]: Start difference. First operand 1776 states and 2540 transitions. cyclomatic complexity: 766 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:00,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:00,950 INFO L93 Difference]: Finished difference Result 3271 states and 4647 transitions. [2021-10-15 19:09:00,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:00,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3271 states and 4647 transitions. [2021-10-15 19:09:00,986 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3184 [2021-10-15 19:09:01,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3271 states to 3271 states and 4647 transitions. [2021-10-15 19:09:01,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3271 [2021-10-15 19:09:01,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3271 [2021-10-15 19:09:01,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3271 states and 4647 transitions. [2021-10-15 19:09:01,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:01,032 INFO L681 BuchiCegarLoop]: Abstraction has 3271 states and 4647 transitions. [2021-10-15 19:09:01,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3271 states and 4647 transitions. [2021-10-15 19:09:01,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3271 to 3263. [2021-10-15 19:09:01,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3263 states, 3263 states have (on average 1.4216978240882623) internal successors, (4639), 3262 states have internal predecessors, (4639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:01,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3263 states to 3263 states and 4639 transitions. [2021-10-15 19:09:01,123 INFO L704 BuchiCegarLoop]: Abstraction has 3263 states and 4639 transitions. [2021-10-15 19:09:01,123 INFO L587 BuchiCegarLoop]: Abstraction has 3263 states and 4639 transitions. [2021-10-15 19:09:01,124 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-15 19:09:01,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3263 states and 4639 transitions. [2021-10-15 19:09:01,142 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-10-15 19:09:01,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:01,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:01,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:01,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:01,144 INFO L791 eck$LassoCheckResult]: Stem: 21376#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21343#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21265#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21266#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 21313#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21314#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21113#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21095#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21073#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20955#L443-1 assume !(0 == ~M_E~0); 20956#L603-1 assume !(0 == ~T1_E~0); 21126#L608-1 assume !(0 == ~T2_E~0); 20980#L613-1 assume !(0 == ~T3_E~0); 20981#L618-1 assume !(0 == ~T4_E~0); 21106#L623-1 assume !(0 == ~T5_E~0); 21251#L628-1 assume !(0 == ~E_M~0); 21356#L633-1 assume !(0 == ~E_1~0); 21235#L638-1 assume !(0 == ~E_2~0); 21236#L643-1 assume !(0 == ~E_3~0); 21282#L648-1 assume !(0 == ~E_4~0); 21283#L653-1 assume !(0 == ~E_5~0); 21311#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20886#L296 assume !(1 == ~m_pc~0); 20887#L296-2 is_master_triggered_~__retres1~0 := 0; 21116#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21011#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21012#L747 assume !(0 != activate_threads_~tmp~1); 21018#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20859#L315 assume !(1 == ~t1_pc~0); 20860#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 21367#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21382#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20808#L755 assume !(0 != activate_threads_~tmp___0~0); 20809#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20828#L334 assume !(1 == ~t2_pc~0); 20829#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 21087#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20866#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20867#L763 assume !(0 != activate_threads_~tmp___1~0); 21357#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20932#L353 assume !(1 == ~t3_pc~0); 20933#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 21175#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20888#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20889#L771 assume !(0 != activate_threads_~tmp___2~0); 21252#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21253#L372 assume !(1 == ~t4_pc~0); 20995#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 20996#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21084#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21305#L779 assume !(0 != activate_threads_~tmp___3~0); 20837#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20838#L391 assume !(1 == ~t5_pc~0); 20770#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 20771#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20927#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21085#L787 assume !(0 != activate_threads_~tmp___4~0); 21159#L787-2 assume !(1 == ~M_E~0); 21227#L671-1 assume !(1 == ~T1_E~0); 21000#L676-1 assume !(1 == ~T2_E~0); 21001#L681-1 assume !(1 == ~T3_E~0); 21134#L686-1 assume !(1 == ~T4_E~0); 21135#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21295#L696-1 assume !(1 == ~E_M~0); 21296#L701-1 assume !(1 == ~E_1~0); 21326#L706-1 assume !(1 == ~E_2~0); 21143#L711-1 assume !(1 == ~E_3~0); 20966#L716-1 assume !(1 == ~E_4~0); 20967#L721-1 assume !(1 == ~E_5~0); 20912#L932-1 [2021-10-15 19:09:01,144 INFO L793 eck$LassoCheckResult]: Loop: 20912#L932-1 assume !false; 21323#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 20782#L578 assume !false; 21345#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23447#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 23446#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23445#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 23443#L503 assume !(0 != eval_~tmp~0); 23444#L593 start_simulation_~kernel_st~0 := 2; 23727#L411-1 start_simulation_~kernel_st~0 := 3; 23726#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23725#L603-4 assume !(0 == ~T1_E~0); 23721#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23719#L613-3 assume !(0 == ~T3_E~0); 23717#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23715#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23712#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23710#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23708#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23707#L643-3 assume !(0 == ~E_3~0); 23706#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23705#L653-3 assume !(0 == ~E_5~0); 23704#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23703#L296-21 assume !(1 == ~m_pc~0); 23701#L296-23 is_master_triggered_~__retres1~0 := 0; 23700#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23699#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23698#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23697#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23694#L315-21 assume !(1 == ~t1_pc~0); 23693#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 23691#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23689#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23687#L755-21 assume !(0 != activate_threads_~tmp___0~0); 23684#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23681#L334-21 assume !(1 == ~t2_pc~0); 23679#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 23674#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23672#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 23670#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23668#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23666#L353-21 assume 1 == ~t3_pc~0; 21289#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 21290#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21358#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21254#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20903#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20904#L372-21 assume !(1 == ~t4_pc~0); 21098#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 21099#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21105#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21045#L779-21 assume !(0 != activate_threads_~tmp___3~0); 20812#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20813#L391-21 assume !(1 == ~t5_pc~0); 21123#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 20864#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20865#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21241#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21161#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 21162#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21127#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21128#L681-3 assume !(1 == ~T3_E~0); 21191#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21090#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20991#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20992#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21061#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21336#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21325#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21163#L721-3 assume !(1 == ~E_5~0); 21029#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 21030#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 20826#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 21007#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 21064#L951 assume !(0 == start_simulation_~tmp~3); 21065#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 21348#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 21052#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 21228#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 21140#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20975#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 20976#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 20911#L964 assume !(0 != start_simulation_~tmp___0~1); 20912#L932-1 [2021-10-15 19:09:01,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:01,145 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-10-15 19:09:01,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:01,146 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595441274] [2021-10-15 19:09:01,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:01,146 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:01,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:01,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:01,195 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:01,196 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595441274] [2021-10-15 19:09:01,196 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1595441274] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:01,196 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:01,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:09:01,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489964334] [2021-10-15 19:09:01,198 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:09:01,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:01,199 INFO L82 PathProgramCache]: Analyzing trace with hash 378427887, now seen corresponding path program 1 times [2021-10-15 19:09:01,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:01,200 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282705183] [2021-10-15 19:09:01,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:01,200 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:01,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:01,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:01,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:01,234 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1282705183] [2021-10-15 19:09:01,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1282705183] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:01,235 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:01,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:09:01,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591644592] [2021-10-15 19:09:01,236 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:01,236 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:01,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:01,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:01,237 INFO L87 Difference]: Start difference. First operand 3263 states and 4639 transitions. cyclomatic complexity: 1380 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:01,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:01,273 INFO L93 Difference]: Finished difference Result 3263 states and 4613 transitions. [2021-10-15 19:09:01,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:01,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3263 states and 4613 transitions. [2021-10-15 19:09:01,303 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-10-15 19:09:01,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3263 states to 3263 states and 4613 transitions. [2021-10-15 19:09:01,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3263 [2021-10-15 19:09:01,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3263 [2021-10-15 19:09:01,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3263 states and 4613 transitions. [2021-10-15 19:09:01,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:01,376 INFO L681 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-10-15 19:09:01,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3263 states and 4613 transitions. [2021-10-15 19:09:01,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3263 to 3263. [2021-10-15 19:09:01,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3263 states, 3263 states have (on average 1.4137296965982225) internal successors, (4613), 3262 states have internal predecessors, (4613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:01,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3263 states to 3263 states and 4613 transitions. [2021-10-15 19:09:01,486 INFO L704 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-10-15 19:09:01,486 INFO L587 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-10-15 19:09:01,486 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-15 19:09:01,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3263 states and 4613 transitions. [2021-10-15 19:09:01,509 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-10-15 19:09:01,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:01,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:01,512 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:01,512 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:01,512 INFO L791 eck$LassoCheckResult]: Stem: 27931#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 27897#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 27823#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27824#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 27864#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27865#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27662#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27641#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27615#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27491#L443-1 assume !(0 == ~M_E~0); 27492#L603-1 assume !(0 == ~T1_E~0); 27677#L608-1 assume !(0 == ~T2_E~0); 27517#L613-1 assume !(0 == ~T3_E~0); 27518#L618-1 assume !(0 == ~T4_E~0); 27654#L623-1 assume !(0 == ~T5_E~0); 27808#L628-1 assume !(0 == ~E_M~0); 27910#L633-1 assume !(0 == ~E_1~0); 27787#L638-1 assume !(0 == ~E_2~0); 27788#L643-1 assume !(0 == ~E_3~0); 27835#L648-1 assume !(0 == ~E_4~0); 27836#L653-1 assume !(0 == ~E_5~0); 27862#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27421#L296 assume !(1 == ~m_pc~0); 27422#L296-2 is_master_triggered_~__retres1~0 := 0; 27668#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27549#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27550#L747 assume !(0 != activate_threads_~tmp~1); 27556#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27398#L315 assume !(1 == ~t1_pc~0); 27399#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 27917#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27938#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27347#L755 assume !(0 != activate_threads_~tmp___0~0); 27348#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27363#L334 assume !(1 == ~t2_pc~0); 27364#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 27633#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27401#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27402#L763 assume !(0 != activate_threads_~tmp___1~0); 27911#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27466#L353 assume !(1 == ~t3_pc~0); 27467#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 27728#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27425#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27426#L771 assume !(0 != activate_threads_~tmp___2~0); 27809#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27810#L372 assume !(1 == ~t4_pc~0); 27532#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 27533#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27627#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27855#L779 assume !(0 != activate_threads_~tmp___3~0); 27374#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27375#L391 assume !(1 == ~t5_pc~0); 27307#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 27308#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27461#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 27630#L787 assume !(0 != activate_threads_~tmp___4~0); 27709#L787-2 assume !(1 == ~M_E~0); 27779#L671-1 assume !(1 == ~T1_E~0); 27539#L676-1 assume !(1 == ~T2_E~0); 27540#L681-1 assume !(1 == ~T3_E~0); 27681#L686-1 assume !(1 == ~T4_E~0); 27682#L691-1 assume !(1 == ~T5_E~0); 27845#L696-1 assume !(1 == ~E_M~0); 27846#L701-1 assume !(1 == ~E_1~0); 27879#L706-1 assume !(1 == ~E_2~0); 27691#L711-1 assume !(1 == ~E_3~0); 27502#L716-1 assume !(1 == ~E_4~0); 27503#L721-1 assume !(1 == ~E_5~0); 27904#L932-1 [2021-10-15 19:09:01,513 INFO L793 eck$LassoCheckResult]: Loop: 27904#L932-1 assume !false; 29249#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 29247#L578 assume !false; 29245#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 29231#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 29229#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 29227#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 29223#L503 assume !(0 != eval_~tmp~0); 29224#L593 start_simulation_~kernel_st~0 := 2; 30163#L411-1 start_simulation_~kernel_st~0 := 3; 30161#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30066#L603-4 assume !(0 == ~T1_E~0); 30065#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30064#L613-3 assume !(0 == ~T3_E~0); 30062#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30060#L623-3 assume !(0 == ~T5_E~0); 30058#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30056#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30054#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30052#L643-3 assume !(0 == ~E_3~0); 30050#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30047#L653-3 assume !(0 == ~E_5~0); 30045#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30043#L296-21 assume !(1 == ~m_pc~0); 30042#L296-23 is_master_triggered_~__retres1~0 := 0; 30039#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30038#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30037#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30036#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30035#L315-21 assume !(1 == ~t1_pc~0); 30033#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 30031#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30029#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30028#L755-21 assume !(0 != activate_threads_~tmp___0~0); 27628#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27629#L334-21 assume !(1 == ~t2_pc~0); 29601#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 29599#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29597#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 29595#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29592#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29590#L353-21 assume !(1 == ~t3_pc~0); 29587#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 29585#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29583#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 29581#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29579#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29577#L372-21 assume !(1 == ~t4_pc~0); 29575#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 29573#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29571#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 29570#L779-21 assume !(0 != activate_threads_~tmp___3~0); 29567#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29565#L391-21 assume !(1 == ~t5_pc~0); 29562#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 29560#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29558#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 29554#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29552#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 29551#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29550#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29549#L681-3 assume !(1 == ~T3_E~0); 29548#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29547#L691-3 assume !(1 == ~T5_E~0); 29546#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29545#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29544#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29543#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29542#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29541#L721-3 assume !(1 == ~E_5~0); 29539#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 29534#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 29528#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 29526#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 29439#L951 assume !(0 == start_simulation_~tmp~3); 29437#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 29430#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 29425#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 29423#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 29421#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29419#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 29417#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 29415#L964 assume !(0 != start_simulation_~tmp___0~1); 27904#L932-1 [2021-10-15 19:09:01,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:01,514 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-10-15 19:09:01,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:01,516 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458714818] [2021-10-15 19:09:01,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:01,517 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:01,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:01,535 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:01,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:01,617 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:01,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:01,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1640794806, now seen corresponding path program 1 times [2021-10-15 19:09:01,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:01,620 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407472992] [2021-10-15 19:09:01,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:01,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:01,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:01,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:01,665 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:01,666 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407472992] [2021-10-15 19:09:01,666 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407472992] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:01,666 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:01,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:09:01,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126546275] [2021-10-15 19:09:01,667 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:01,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:01,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 19:09:01,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 19:09:01,669 INFO L87 Difference]: Start difference. First operand 3263 states and 4613 transitions. cyclomatic complexity: 1354 Second operand has 5 states, 5 states have (on average 16.6) internal successors, (83), 5 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:01,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:01,807 INFO L93 Difference]: Finished difference Result 5839 states and 8149 transitions. [2021-10-15 19:09:01,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-15 19:09:01,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5839 states and 8149 transitions. [2021-10-15 19:09:01,849 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5740 [2021-10-15 19:09:01,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5839 states to 5839 states and 8149 transitions. [2021-10-15 19:09:01,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5839 [2021-10-15 19:09:01,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5839 [2021-10-15 19:09:01,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5839 states and 8149 transitions. [2021-10-15 19:09:01,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:01,914 INFO L681 BuchiCegarLoop]: Abstraction has 5839 states and 8149 transitions. [2021-10-15 19:09:01,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5839 states and 8149 transitions. [2021-10-15 19:09:02,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5839 to 3287. [2021-10-15 19:09:02,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3287 states, 3287 states have (on average 1.4107088530574992) internal successors, (4637), 3286 states have internal predecessors, (4637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:02,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3287 states to 3287 states and 4637 transitions. [2021-10-15 19:09:02,082 INFO L704 BuchiCegarLoop]: Abstraction has 3287 states and 4637 transitions. [2021-10-15 19:09:02,083 INFO L587 BuchiCegarLoop]: Abstraction has 3287 states and 4637 transitions. [2021-10-15 19:09:02,083 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-15 19:09:02,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3287 states and 4637 transitions. [2021-10-15 19:09:02,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3200 [2021-10-15 19:09:02,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:02,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:02,106 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:02,106 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:02,106 INFO L791 eck$LassoCheckResult]: Stem: 37046#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 37008#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36931#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36932#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 36977#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36978#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36771#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36753#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36730#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36610#L443-1 assume !(0 == ~M_E~0); 36611#L603-1 assume !(0 == ~T1_E~0); 36786#L608-1 assume !(0 == ~T2_E~0); 36634#L613-1 assume !(0 == ~T3_E~0); 36635#L618-1 assume !(0 == ~T4_E~0); 36766#L623-1 assume !(0 == ~T5_E~0); 36916#L628-1 assume !(0 == ~E_M~0); 37018#L633-1 assume !(0 == ~E_1~0); 36901#L638-1 assume !(0 == ~E_2~0); 36902#L643-1 assume !(0 == ~E_3~0); 36946#L648-1 assume !(0 == ~E_4~0); 36947#L653-1 assume !(0 == ~E_5~0); 36975#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36539#L296 assume !(1 == ~m_pc~0); 36540#L296-2 is_master_triggered_~__retres1~0 := 0; 36775#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36666#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36667#L747 assume !(0 != activate_threads_~tmp~1); 36673#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36516#L315 assume !(1 == ~t1_pc~0); 36517#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 37030#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37055#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36465#L755 assume !(0 != activate_threads_~tmp___0~0); 36466#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36481#L334 assume !(1 == ~t2_pc~0); 36482#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 36745#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36519#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36520#L763 assume !(0 != activate_threads_~tmp___1~0); 37019#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36585#L353 assume !(1 == ~t3_pc~0); 36586#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 36838#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36543#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36544#L771 assume !(0 != activate_threads_~tmp___2~0); 36917#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36918#L372 assume !(1 == ~t4_pc~0); 36649#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 36650#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36741#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36969#L779 assume !(0 != activate_threads_~tmp___3~0); 36492#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36493#L391 assume !(1 == ~t5_pc~0); 36425#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 36426#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36580#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 36743#L787 assume !(0 != activate_threads_~tmp___4~0); 36820#L787-2 assume !(1 == ~M_E~0); 36893#L671-1 assume !(1 == ~T1_E~0); 36656#L676-1 assume !(1 == ~T2_E~0); 36657#L681-1 assume !(1 == ~T3_E~0); 36793#L686-1 assume !(1 == ~T4_E~0); 36794#L691-1 assume !(1 == ~T5_E~0); 36958#L696-1 assume !(1 == ~E_M~0); 36959#L701-1 assume !(1 == ~E_1~0); 36993#L706-1 assume !(1 == ~E_2~0); 36804#L711-1 assume !(1 == ~E_3~0); 36620#L716-1 assume !(1 == ~E_4~0); 36621#L721-1 assume !(1 == ~E_5~0); 37012#L932-1 [2021-10-15 19:09:02,107 INFO L793 eck$LassoCheckResult]: Loop: 37012#L932-1 assume !false; 39319#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 39315#L578 assume !false; 39190#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39171#L456 assume !(0 == ~m_st~0); 39172#L460 assume !(0 == ~t1_st~0); 39175#L464 assume !(0 == ~t2_st~0); 39177#L468 assume !(0 == ~t3_st~0); 39173#L472 assume !(0 == ~t4_st~0); 39174#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 39176#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36813#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 36814#L503 assume !(0 != eval_~tmp~0); 39167#L593 start_simulation_~kernel_st~0 := 2; 37003#L411-1 start_simulation_~kernel_st~0 := 3; 37004#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36658#L603-4 assume !(0 == ~T1_E~0); 36659#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36882#L613-3 assume !(0 == ~T3_E~0); 39165#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39164#L623-3 assume !(0 == ~T5_E~0); 39163#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36983#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36984#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39162#L643-3 assume !(0 == ~E_3~0); 36562#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36563#L653-3 assume !(0 == ~E_5~0); 36569#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39160#L296-21 assume !(1 == ~m_pc~0); 39159#L296-23 is_master_triggered_~__retres1~0 := 0; 39158#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39157#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36815#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 36816#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36883#L315-21 assume 1 == ~t1_pc~0; 37028#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 37029#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37040#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37041#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36726#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36742#L334-21 assume !(1 == ~t2_pc~0); 37054#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 36877#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36878#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36956#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36957#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36968#L353-21 assume !(1 == ~t3_pc~0); 38967#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 37020#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37021#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 38966#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 38965#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36842#L372-21 assume !(1 == ~t4_pc~0); 36843#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 39626#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36852#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36700#L779-21 assume !(0 != activate_threads_~tmp___3~0); 36463#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36464#L391-21 assume !(1 == ~t5_pc~0); 36781#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 36514#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36515#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 39508#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39507#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 39505#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39503#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39501#L681-3 assume !(1 == ~T3_E~0); 39499#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39497#L691-3 assume !(1 == ~T5_E~0); 36645#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36646#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36717#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37045#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39482#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39480#L721-3 assume !(1 == ~E_5~0); 39478#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39471#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39465#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39463#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 39439#L951 assume !(0 == start_simulation_~tmp~3); 39437#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39434#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39430#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39429#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 39427#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39425#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 39423#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 39421#L964 assume !(0 != start_simulation_~tmp___0~1); 37012#L932-1 [2021-10-15 19:09:02,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:02,108 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-10-15 19:09:02,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:02,108 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342593949] [2021-10-15 19:09:02,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:02,109 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:02,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:02,124 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:02,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:02,182 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:02,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:02,185 INFO L82 PathProgramCache]: Analyzing trace with hash -1940300346, now seen corresponding path program 1 times [2021-10-15 19:09:02,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:02,186 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804578865] [2021-10-15 19:09:02,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:02,187 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:02,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:02,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:02,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:02,278 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804578865] [2021-10-15 19:09:02,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804578865] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:02,278 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:02,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-15 19:09:02,279 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785653164] [2021-10-15 19:09:02,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:02,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:02,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-15 19:09:02,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-15 19:09:02,281 INFO L87 Difference]: Start difference. First operand 3287 states and 4637 transitions. cyclomatic complexity: 1354 Second operand has 5 states, 5 states have (on average 17.6) internal successors, (88), 5 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:02,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:02,553 INFO L93 Difference]: Finished difference Result 6487 states and 9096 transitions. [2021-10-15 19:09:02,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-15 19:09:02,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6487 states and 9096 transitions. [2021-10-15 19:09:02,603 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6392 [2021-10-15 19:09:02,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6487 states to 6487 states and 9096 transitions. [2021-10-15 19:09:02,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6487 [2021-10-15 19:09:02,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6487 [2021-10-15 19:09:02,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6487 states and 9096 transitions. [2021-10-15 19:09:02,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:02,760 INFO L681 BuchiCegarLoop]: Abstraction has 6487 states and 9096 transitions. [2021-10-15 19:09:02,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6487 states and 9096 transitions. [2021-10-15 19:09:02,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6487 to 3371. [2021-10-15 19:09:02,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3371 states, 3371 states have (on average 1.3930584396321566) internal successors, (4696), 3370 states have internal predecessors, (4696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:02,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3371 states to 3371 states and 4696 transitions. [2021-10-15 19:09:02,864 INFO L704 BuchiCegarLoop]: Abstraction has 3371 states and 4696 transitions. [2021-10-15 19:09:02,864 INFO L587 BuchiCegarLoop]: Abstraction has 3371 states and 4696 transitions. [2021-10-15 19:09:02,865 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-15 19:09:02,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3371 states and 4696 transitions. [2021-10-15 19:09:02,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3284 [2021-10-15 19:09:02,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:02,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:02,883 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:02,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:02,884 INFO L791 eck$LassoCheckResult]: Stem: 46844#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 46816#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 46719#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 46720#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 46779#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46780#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46557#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46539#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46516#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46397#L443-1 assume !(0 == ~M_E~0); 46398#L603-1 assume !(0 == ~T1_E~0); 46570#L608-1 assume !(0 == ~T2_E~0); 46421#L613-1 assume !(0 == ~T3_E~0); 46422#L618-1 assume !(0 == ~T4_E~0); 46550#L623-1 assume !(0 == ~T5_E~0); 46705#L628-1 assume !(0 == ~E_M~0); 46828#L633-1 assume !(0 == ~E_1~0); 46688#L638-1 assume !(0 == ~E_2~0); 46689#L643-1 assume !(0 == ~E_3~0); 46736#L648-1 assume !(0 == ~E_4~0); 46737#L653-1 assume !(0 == ~E_5~0); 46776#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46327#L296 assume !(1 == ~m_pc~0); 46328#L296-2 is_master_triggered_~__retres1~0 := 0; 46562#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46452#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46453#L747 assume !(0 != activate_threads_~tmp~1); 46459#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46299#L315 assume !(1 == ~t1_pc~0); 46300#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 46835#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46856#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 46248#L755 assume !(0 != activate_threads_~tmp___0~0); 46249#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46268#L334 assume !(1 == ~t2_pc~0); 46269#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 46530#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46306#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 46307#L763 assume !(0 != activate_threads_~tmp___1~0); 46829#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46374#L353 assume !(1 == ~t3_pc~0); 46375#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 46625#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46329#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 46330#L771 assume !(0 != activate_threads_~tmp___2~0); 46706#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46707#L372 assume !(1 == ~t4_pc~0); 46436#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 46437#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46528#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 46767#L779 assume !(0 != activate_threads_~tmp___3~0); 46277#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46278#L391 assume !(1 == ~t5_pc~0); 46210#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 46211#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46369#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 46529#L787 assume !(0 != activate_threads_~tmp___4~0); 46605#L787-2 assume !(1 == ~M_E~0); 46680#L671-1 assume !(1 == ~T1_E~0); 46441#L676-1 assume !(1 == ~T2_E~0); 46442#L681-1 assume !(1 == ~T3_E~0); 46578#L686-1 assume !(1 == ~T4_E~0); 46579#L691-1 assume !(1 == ~T5_E~0); 46748#L696-1 assume !(1 == ~E_M~0); 46749#L701-1 assume !(1 == ~E_1~0); 46793#L706-1 assume !(1 == ~E_2~0); 46588#L711-1 assume !(1 == ~E_3~0); 46407#L716-1 assume !(1 == ~E_4~0); 46408#L721-1 assume !(1 == ~E_5~0); 46822#L932-1 [2021-10-15 19:09:02,884 INFO L793 eck$LassoCheckResult]: Loop: 46822#L932-1 assume !false; 48148#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 48147#L578 assume !false; 48146#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 48139#L456 assume !(0 == ~m_st~0); 48140#L460 assume !(0 == ~t1_st~0); 48143#L464 assume !(0 == ~t2_st~0); 48145#L468 assume !(0 == ~t3_st~0); 48141#L472 assume !(0 == ~t4_st~0); 48142#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 48144#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 48135#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 48136#L503 assume !(0 != eval_~tmp~0); 48338#L593 start_simulation_~kernel_st~0 := 2; 48337#L411-1 start_simulation_~kernel_st~0 := 3; 48336#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48335#L603-4 assume !(0 == ~T1_E~0); 48334#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48333#L613-3 assume !(0 == ~T3_E~0); 48332#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48331#L623-3 assume !(0 == ~T5_E~0); 48330#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48329#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48328#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48327#L643-3 assume !(0 == ~E_3~0); 48326#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48325#L653-3 assume !(0 == ~E_5~0); 48324#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48323#L296-21 assume !(1 == ~m_pc~0); 48322#L296-23 is_master_triggered_~__retres1~0 := 0; 48321#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48320#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 48319#L747-21 assume !(0 != activate_threads_~tmp~1); 48317#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48315#L315-21 assume 1 == ~t1_pc~0; 48312#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 48309#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48306#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 48303#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48301#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48298#L334-21 assume !(1 == ~t2_pc~0); 48094#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 48293#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48290#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 48288#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 48286#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48285#L353-21 assume !(1 == ~t3_pc~0); 48282#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 48280#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48278#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 48276#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48274#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48270#L372-21 assume !(1 == ~t4_pc~0); 48267#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 48264#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48261#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 48258#L779-21 assume !(0 != activate_threads_~tmp___3~0); 48255#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48252#L391-21 assume !(1 == ~t5_pc~0); 48247#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 48243#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48239#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 48235#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 48231#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 48228#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48226#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48223#L681-3 assume !(1 == ~T3_E~0); 48220#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48217#L691-3 assume !(1 == ~T5_E~0); 48214#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48211#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48207#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48204#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48201#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48198#L721-3 assume !(1 == ~E_5~0); 48195#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 48191#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 48184#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 48181#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 48177#L951 assume !(0 == start_simulation_~tmp~3); 48175#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 48171#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 48165#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 48163#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 48161#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 48159#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 48157#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 48153#L964 assume !(0 != start_simulation_~tmp___0~1); 46822#L932-1 [2021-10-15 19:09:02,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:02,885 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-10-15 19:09:02,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:02,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461010840] [2021-10-15 19:09:02,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:02,886 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:02,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:02,898 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:02,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:02,927 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:02,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:02,928 INFO L82 PathProgramCache]: Analyzing trace with hash -1899625596, now seen corresponding path program 1 times [2021-10-15 19:09:02,928 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:02,928 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717255802] [2021-10-15 19:09:02,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:02,929 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:02,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:02,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:02,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:02,962 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717255802] [2021-10-15 19:09:02,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717255802] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:02,963 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:02,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:02,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23624256] [2021-10-15 19:09:02,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-15 19:09:02,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:02,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:02,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:02,965 INFO L87 Difference]: Start difference. First operand 3371 states and 4696 transitions. cyclomatic complexity: 1329 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:03,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:03,037 INFO L93 Difference]: Finished difference Result 5773 states and 7922 transitions. [2021-10-15 19:09:03,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:03,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5773 states and 7922 transitions. [2021-10-15 19:09:03,119 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5676 [2021-10-15 19:09:03,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5773 states to 5773 states and 7922 transitions. [2021-10-15 19:09:03,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5773 [2021-10-15 19:09:03,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5773 [2021-10-15 19:09:03,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5773 states and 7922 transitions. [2021-10-15 19:09:03,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:03,154 INFO L681 BuchiCegarLoop]: Abstraction has 5773 states and 7922 transitions. [2021-10-15 19:09:03,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5773 states and 7922 transitions. [2021-10-15 19:09:03,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5773 to 5621. [2021-10-15 19:09:03,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5621 states, 5621 states have (on average 1.3737769080234834) internal successors, (7722), 5620 states have internal predecessors, (7722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:03,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5621 states to 5621 states and 7722 transitions. [2021-10-15 19:09:03,303 INFO L704 BuchiCegarLoop]: Abstraction has 5621 states and 7722 transitions. [2021-10-15 19:09:03,303 INFO L587 BuchiCegarLoop]: Abstraction has 5621 states and 7722 transitions. [2021-10-15 19:09:03,303 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-15 19:09:03,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5621 states and 7722 transitions. [2021-10-15 19:09:03,369 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5524 [2021-10-15 19:09:03,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:03,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:03,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:03,371 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:03,371 INFO L791 eck$LassoCheckResult]: Stem: 55992#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 55951#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 55863#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55864#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 55915#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55916#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55710#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55690#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55667#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55548#L443-1 assume !(0 == ~M_E~0); 55549#L603-1 assume !(0 == ~T1_E~0); 55723#L608-1 assume !(0 == ~T2_E~0); 55573#L613-1 assume !(0 == ~T3_E~0); 55574#L618-1 assume !(0 == ~T4_E~0); 55700#L623-1 assume !(0 == ~T5_E~0); 55850#L628-1 assume !(0 == ~E_M~0); 55965#L633-1 assume !(0 == ~E_1~0); 55833#L638-1 assume !(0 == ~E_2~0); 55834#L643-1 assume !(0 == ~E_3~0); 55878#L648-1 assume !(0 == ~E_4~0); 55879#L653-1 assume !(0 == ~E_5~0); 55913#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55476#L296 assume !(1 == ~m_pc~0); 55477#L296-2 is_master_triggered_~__retres1~0 := 0; 55714#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55605#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55606#L747 assume !(0 != activate_threads_~tmp~1); 55612#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55448#L315 assume !(1 == ~t1_pc~0); 55449#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 55973#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56003#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55398#L755 assume !(0 != activate_threads_~tmp___0~0); 55399#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55418#L334 assume !(1 == ~t2_pc~0); 55419#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 55681#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55455#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 55456#L763 assume !(0 != activate_threads_~tmp___1~0); 55966#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55525#L353 assume !(1 == ~t3_pc~0); 55526#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 55771#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55478#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 55479#L771 assume !(0 != activate_threads_~tmp___2~0); 55851#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55852#L372 assume !(1 == ~t4_pc~0); 55588#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 55589#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55679#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55906#L779 assume !(0 != activate_threads_~tmp___3~0); 55427#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55428#L391 assume !(1 == ~t5_pc~0); 55360#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 55361#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55520#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 55680#L787 assume !(0 != activate_threads_~tmp___4~0); 55754#L787-2 assume !(1 == ~M_E~0); 55822#L671-1 assume !(1 == ~T1_E~0); 55594#L676-1 assume !(1 == ~T2_E~0); 55595#L681-1 assume !(1 == ~T3_E~0); 55731#L686-1 assume !(1 == ~T4_E~0); 55732#L691-1 assume !(1 == ~T5_E~0); 55890#L696-1 assume !(1 == ~E_M~0); 55891#L701-1 assume !(1 == ~E_1~0); 55929#L706-1 assume !(1 == ~E_2~0); 55741#L711-1 assume !(1 == ~E_3~0); 55559#L716-1 assume !(1 == ~E_4~0); 55560#L721-1 assume !(1 == ~E_5~0); 55958#L932-1 assume !false; 59343#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 59339#L578 [2021-10-15 19:09:03,371 INFO L793 eck$LassoCheckResult]: Loop: 59339#L578 assume !false; 59336#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 59332#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 59329#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 59326#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 59321#L503 assume 0 != eval_~tmp~0; 59316#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 59313#L511 assume !(0 != eval_~tmp_ndt_1~0); 59306#L508 assume !(0 == ~t1_st~0); 59303#L522 assume !(0 == ~t2_st~0); 59300#L536 assume !(0 == ~t3_st~0); 59350#L550 assume !(0 == ~t4_st~0); 59347#L564 assume !(0 == ~t5_st~0); 59339#L578 [2021-10-15 19:09:03,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:03,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-10-15 19:09:03,372 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:03,372 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427767610] [2021-10-15 19:09:03,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:03,373 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:03,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:03,385 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:03,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:03,416 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:03,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:03,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 1 times [2021-10-15 19:09:03,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:03,418 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573414135] [2021-10-15 19:09:03,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:03,418 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:03,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:03,423 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:03,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:03,428 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:03,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:03,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1605223329, now seen corresponding path program 1 times [2021-10-15 19:09:03,429 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:03,430 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281174469] [2021-10-15 19:09:03,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:03,430 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:03,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:03,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:03,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:03,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281174469] [2021-10-15 19:09:03,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281174469] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:03,470 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:03,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:03,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987882397] [2021-10-15 19:09:03,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:03,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:03,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:03,593 INFO L87 Difference]: Start difference. First operand 5621 states and 7722 transitions. cyclomatic complexity: 2107 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:03,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:03,707 INFO L93 Difference]: Finished difference Result 10485 states and 14302 transitions. [2021-10-15 19:09:03,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:03,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10485 states and 14302 transitions. [2021-10-15 19:09:03,776 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10296 [2021-10-15 19:09:03,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10485 states to 10485 states and 14302 transitions. [2021-10-15 19:09:03,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10485 [2021-10-15 19:09:03,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10485 [2021-10-15 19:09:03,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10485 states and 14302 transitions. [2021-10-15 19:09:03,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:03,858 INFO L681 BuchiCegarLoop]: Abstraction has 10485 states and 14302 transitions. [2021-10-15 19:09:03,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10485 states and 14302 transitions. [2021-10-15 19:09:04,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10485 to 10005. [2021-10-15 19:09:04,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10005 states, 10005 states have (on average 1.3671164417791104) internal successors, (13678), 10004 states have internal predecessors, (13678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:04,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10005 states to 10005 states and 13678 transitions. [2021-10-15 19:09:04,171 INFO L704 BuchiCegarLoop]: Abstraction has 10005 states and 13678 transitions. [2021-10-15 19:09:04,171 INFO L587 BuchiCegarLoop]: Abstraction has 10005 states and 13678 transitions. [2021-10-15 19:09:04,171 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-15 19:09:04,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10005 states and 13678 transitions. [2021-10-15 19:09:04,211 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-10-15 19:09:04,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:04,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:04,213 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:04,213 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:04,214 INFO L791 eck$LassoCheckResult]: Stem: 72201#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 72130#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 72020#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 72021#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 72081#L418-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 72082#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72151#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71812#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71813#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71666#L443-1 assume !(0 == ~M_E~0); 71667#L603-1 assume !(0 == ~T1_E~0); 71856#L608-1 assume !(0 == ~T2_E~0); 71857#L613-1 assume !(0 == ~T3_E~0); 71824#L618-1 assume !(0 == ~T4_E~0); 71825#L623-1 assume !(0 == ~T5_E~0); 72175#L628-1 assume !(0 == ~E_M~0); 72176#L633-1 assume !(0 == ~E_1~0); 71985#L638-1 assume !(0 == ~E_2~0); 71986#L643-1 assume !(0 == ~E_3~0); 72036#L648-1 assume !(0 == ~E_4~0); 72037#L653-1 assume !(0 == ~E_5~0); 72078#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 72079#L296 assume !(1 == ~m_pc~0); 71973#L296-2 is_master_triggered_~__retres1~0 := 0; 71974#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71719#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 71720#L747 assume !(0 != activate_threads_~tmp~1); 71988#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71989#L315 assume !(1 == ~t1_pc~0); 72171#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 72172#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 72215#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 72216#L755 assume !(0 != activate_threads_~tmp___0~0); 72202#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 72203#L334 assume !(1 == ~t2_pc~0); 71803#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 71804#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 71570#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 71571#L763 assume !(0 != activate_threads_~tmp___1~0); 72168#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72169#L353 assume !(1 == ~t3_pc~0); 72047#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 72048#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 71595#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 71596#L771 assume !(0 != activate_threads_~tmp___2~0); 72007#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 72008#L372 assume !(1 == ~t4_pc~0); 71702#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 71703#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 72070#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 72071#L779 assume !(0 != activate_threads_~tmp___3~0); 71541#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 71542#L391 assume !(1 == ~t5_pc~0); 71476#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 71477#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 71799#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 71800#L787 assume !(0 != activate_threads_~tmp___4~0); 72177#L787-2 assume !(1 == ~M_E~0); 72178#L671-1 assume !(1 == ~T1_E~0); 71709#L676-1 assume !(1 == ~T2_E~0); 71710#L681-1 assume !(1 == ~T3_E~0); 71864#L686-1 assume !(1 == ~T4_E~0); 71865#L691-1 assume !(1 == ~T5_E~0); 72052#L696-1 assume !(1 == ~E_M~0); 72053#L701-1 assume !(1 == ~E_1~0); 72126#L706-1 assume !(1 == ~E_2~0); 72127#L711-1 assume !(1 == ~E_3~0); 71673#L716-1 assume !(1 == ~E_4~0); 71674#L721-1 assume !(1 == ~E_5~0); 72295#L932-1 assume !false; 79269#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 73621#L578 [2021-10-15 19:09:04,214 INFO L793 eck$LassoCheckResult]: Loop: 73621#L578 assume !false; 79268#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 79266#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 79267#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 80711#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 80710#L503 assume 0 != eval_~tmp~0; 80709#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 71830#L511 assume !(0 != eval_~tmp_ndt_1~0); 71832#L508 assume !(0 == ~t1_st~0); 73298#L522 assume !(0 == ~t2_st~0); 73291#L536 assume !(0 == ~t3_st~0); 73578#L550 assume !(0 == ~t4_st~0); 73570#L564 assume !(0 == ~t5_st~0); 73621#L578 [2021-10-15 19:09:04,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:04,215 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-10-15 19:09:04,215 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:04,215 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245838228] [2021-10-15 19:09:04,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:04,215 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:04,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:04,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:04,238 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:04,239 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245838228] [2021-10-15 19:09:04,239 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245838228] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:04,239 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:04,239 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:04,239 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420367027] [2021-10-15 19:09:04,240 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-15 19:09:04,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:04,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 2 times [2021-10-15 19:09:04,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:04,241 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251556669] [2021-10-15 19:09:04,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:04,241 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:04,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:04,245 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:04,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:04,251 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:04,362 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:04,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:04,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:04,363 INFO L87 Difference]: Start difference. First operand 10005 states and 13678 transitions. cyclomatic complexity: 3679 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:04,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:04,432 INFO L93 Difference]: Finished difference Result 9933 states and 13577 transitions. [2021-10-15 19:09:04,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:04,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9933 states and 13577 transitions. [2021-10-15 19:09:04,489 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-10-15 19:09:04,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9933 states to 9933 states and 13577 transitions. [2021-10-15 19:09:04,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9933 [2021-10-15 19:09:04,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9933 [2021-10-15 19:09:04,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9933 states and 13577 transitions. [2021-10-15 19:09:04,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:04,556 INFO L681 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-10-15 19:09:04,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9933 states and 13577 transitions. [2021-10-15 19:09:04,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9933 to 9933. [2021-10-15 19:09:04,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.366857948253297) internal successors, (13577), 9932 states have internal predecessors, (13577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:04,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 13577 transitions. [2021-10-15 19:09:04,938 INFO L704 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-10-15 19:09:04,938 INFO L587 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-10-15 19:09:04,938 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-15 19:09:04,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 13577 transitions. [2021-10-15 19:09:04,978 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-10-15 19:09:04,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:04,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:04,980 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:04,980 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:04,980 INFO L791 eck$LassoCheckResult]: Stem: 92034#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 92000#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 91921#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 91922#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 91968#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91969#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91766#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91747#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91725#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91608#L443-1 assume !(0 == ~M_E~0); 91609#L603-1 assume !(0 == ~T1_E~0); 91781#L608-1 assume !(0 == ~T2_E~0); 91631#L613-1 assume !(0 == ~T3_E~0); 91632#L618-1 assume !(0 == ~T4_E~0); 91759#L623-1 assume !(0 == ~T5_E~0); 91909#L628-1 assume !(0 == ~E_M~0); 92012#L633-1 assume !(0 == ~E_1~0); 91893#L638-1 assume !(0 == ~E_2~0); 91894#L643-1 assume !(0 == ~E_3~0); 91934#L648-1 assume !(0 == ~E_4~0); 91935#L653-1 assume !(0 == ~E_5~0); 91966#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91535#L296 assume !(1 == ~m_pc~0); 91536#L296-2 is_master_triggered_~__retres1~0 := 0; 91769#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91663#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91664#L747 assume !(0 != activate_threads_~tmp~1); 91670#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91511#L315 assume !(1 == ~t1_pc~0); 91512#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 92022#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92046#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91460#L755 assume !(0 != activate_threads_~tmp___0~0); 91461#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91475#L334 assume !(1 == ~t2_pc~0); 91476#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 91739#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91514#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 91515#L763 assume !(0 != activate_threads_~tmp___1~0); 92013#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91583#L353 assume !(1 == ~t3_pc~0); 91584#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 91830#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91539#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 91540#L771 assume !(0 != activate_threads_~tmp___2~0); 91910#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91911#L372 assume !(1 == ~t4_pc~0); 91646#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 91647#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91736#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 91958#L779 assume !(0 != activate_threads_~tmp___3~0); 91486#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91487#L391 assume !(1 == ~t5_pc~0); 91420#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 91421#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91578#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 91737#L787 assume !(0 != activate_threads_~tmp___4~0); 91814#L787-2 assume !(1 == ~M_E~0); 91883#L671-1 assume !(1 == ~T1_E~0); 91653#L676-1 assume !(1 == ~T2_E~0); 91654#L681-1 assume !(1 == ~T3_E~0); 91787#L686-1 assume !(1 == ~T4_E~0); 91788#L691-1 assume !(1 == ~T5_E~0); 91948#L696-1 assume !(1 == ~E_M~0); 91949#L701-1 assume !(1 == ~E_1~0); 91984#L706-1 assume !(1 == ~E_2~0); 91798#L711-1 assume !(1 == ~E_3~0); 91616#L716-1 assume !(1 == ~E_4~0); 91617#L721-1 assume !(1 == ~E_5~0); 92006#L932-1 assume !false; 95190#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 95188#L578 [2021-10-15 19:09:04,980 INFO L793 eck$LassoCheckResult]: Loop: 95188#L578 assume !false; 95186#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 95182#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 95180#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 95178#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 95176#L503 assume 0 != eval_~tmp~0; 95173#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 95170#L511 assume !(0 != eval_~tmp_ndt_1~0); 95167#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 95031#L525 assume !(0 != eval_~tmp_ndt_2~0); 95164#L522 assume !(0 == ~t2_st~0); 95162#L536 assume !(0 == ~t3_st~0); 95198#L550 assume !(0 == ~t4_st~0); 95194#L564 assume !(0 == ~t5_st~0); 95188#L578 [2021-10-15 19:09:04,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:04,981 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-10-15 19:09:04,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:04,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786658336] [2021-10-15 19:09:04,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:04,982 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:04,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:04,993 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:05,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:05,024 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:05,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:05,025 INFO L82 PathProgramCache]: Analyzing trace with hash -11527191, now seen corresponding path program 1 times [2021-10-15 19:09:05,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:05,025 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351424737] [2021-10-15 19:09:05,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:05,026 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:05,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:05,030 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:05,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:05,035 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:05,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:05,036 INFO L82 PathProgramCache]: Analyzing trace with hash 888960747, now seen corresponding path program 1 times [2021-10-15 19:09:05,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:05,036 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812270024] [2021-10-15 19:09:05,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:05,037 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:05,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:05,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:05,205 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:05,205 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812270024] [2021-10-15 19:09:05,206 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812270024] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:05,206 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:05,206 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:05,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866943747] [2021-10-15 19:09:05,382 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:05,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:05,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:05,383 INFO L87 Difference]: Start difference. First operand 9933 states and 13577 transitions. cyclomatic complexity: 3650 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:05,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:05,527 INFO L93 Difference]: Finished difference Result 18745 states and 25501 transitions. [2021-10-15 19:09:05,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:05,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18745 states and 25501 transitions. [2021-10-15 19:09:05,635 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18588 [2021-10-15 19:09:05,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18745 states to 18745 states and 25501 transitions. [2021-10-15 19:09:05,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18745 [2021-10-15 19:09:05,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18745 [2021-10-15 19:09:05,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18745 states and 25501 transitions. [2021-10-15 19:09:05,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:05,996 INFO L681 BuchiCegarLoop]: Abstraction has 18745 states and 25501 transitions. [2021-10-15 19:09:06,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18745 states and 25501 transitions. [2021-10-15 19:09:06,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18745 to 18369. [2021-10-15 19:09:06,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18369 states, 18369 states have (on average 1.3616963362186292) internal successors, (25013), 18368 states have internal predecessors, (25013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:06,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18369 states to 18369 states and 25013 transitions. [2021-10-15 19:09:06,648 INFO L704 BuchiCegarLoop]: Abstraction has 18369 states and 25013 transitions. [2021-10-15 19:09:06,649 INFO L587 BuchiCegarLoop]: Abstraction has 18369 states and 25013 transitions. [2021-10-15 19:09:06,649 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-15 19:09:06,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18369 states and 25013 transitions. [2021-10-15 19:09:06,723 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18212 [2021-10-15 19:09:06,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:06,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:06,725 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:06,725 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:06,725 INFO L791 eck$LassoCheckResult]: Stem: 120762#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 120721#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 120634#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 120635#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 120687#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 120688#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120459#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120439#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120413#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120291#L443-1 assume !(0 == ~M_E~0); 120292#L603-1 assume !(0 == ~T1_E~0); 120476#L608-1 assume !(0 == ~T2_E~0); 120316#L613-1 assume !(0 == ~T3_E~0); 120317#L618-1 assume !(0 == ~T4_E~0); 120450#L623-1 assume !(0 == ~T5_E~0); 120620#L628-1 assume !(0 == ~E_M~0); 120737#L633-1 assume !(0 == ~E_1~0); 120602#L638-1 assume !(0 == ~E_2~0); 120603#L643-1 assume !(0 == ~E_3~0); 120651#L648-1 assume !(0 == ~E_4~0); 120652#L653-1 assume !(0 == ~E_5~0); 120685#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120220#L296 assume !(1 == ~m_pc~0); 120221#L296-2 is_master_triggered_~__retres1~0 := 0; 120467#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 120348#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 120349#L747 assume !(0 != activate_threads_~tmp~1); 120355#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 120192#L315 assume !(1 == ~t1_pc~0); 120193#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 120746#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 120768#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 120142#L755 assume !(0 != activate_threads_~tmp___0~0); 120143#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120160#L334 assume !(1 == ~t2_pc~0); 120161#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 120428#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 120199#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 120200#L763 assume !(0 != activate_threads_~tmp___1~0); 120738#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 120267#L353 assume !(1 == ~t3_pc~0); 120268#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 120534#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 120222#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 120223#L771 assume !(0 != activate_threads_~tmp___2~0); 120621#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 120622#L372 assume !(1 == ~t4_pc~0); 120331#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 120332#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120425#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 120678#L779 assume !(0 != activate_threads_~tmp___3~0); 120169#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120170#L391 assume !(1 == ~t5_pc~0); 120104#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 120105#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 120262#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 120426#L787 assume !(0 != activate_threads_~tmp___4~0); 120515#L787-2 assume !(1 == ~M_E~0); 120591#L671-1 assume !(1 == ~T1_E~0); 120336#L676-1 assume !(1 == ~T2_E~0); 120337#L681-1 assume !(1 == ~T3_E~0); 120485#L686-1 assume !(1 == ~T4_E~0); 120486#L691-1 assume !(1 == ~T5_E~0); 120663#L696-1 assume !(1 == ~E_M~0); 120664#L701-1 assume !(1 == ~E_1~0); 120704#L706-1 assume !(1 == ~E_2~0); 120499#L711-1 assume !(1 == ~E_3~0); 120301#L716-1 assume !(1 == ~E_4~0); 120302#L721-1 assume !(1 == ~E_5~0); 120729#L932-1 assume !false; 124270#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 124266#L578 [2021-10-15 19:09:06,725 INFO L793 eck$LassoCheckResult]: Loop: 124266#L578 assume !false; 124110#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 124056#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 124045#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 124036#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 124027#L503 assume 0 != eval_~tmp~0; 124017#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 124006#L511 assume !(0 != eval_~tmp_ndt_1~0); 123995#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 123002#L525 assume !(0 != eval_~tmp_ndt_2~0); 121908#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 121901#L539 assume !(0 != eval_~tmp_ndt_3~0); 121902#L536 assume !(0 == ~t3_st~0); 123910#L550 assume !(0 == ~t4_st~0); 123903#L564 assume !(0 == ~t5_st~0); 124266#L578 [2021-10-15 19:09:06,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:06,726 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-10-15 19:09:06,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:06,727 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608341538] [2021-10-15 19:09:06,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:06,727 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:06,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:06,741 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:06,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:06,775 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:06,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:06,776 INFO L82 PathProgramCache]: Analyzing trace with hash -524557124, now seen corresponding path program 1 times [2021-10-15 19:09:06,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:06,777 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711702741] [2021-10-15 19:09:06,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:06,777 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:06,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:06,781 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:06,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:06,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:06,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:06,789 INFO L82 PathProgramCache]: Analyzing trace with hash 1620765178, now seen corresponding path program 1 times [2021-10-15 19:09:06,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:06,789 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279373266] [2021-10-15 19:09:06,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:06,789 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:06,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:06,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:06,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:06,826 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279373266] [2021-10-15 19:09:06,827 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279373266] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:06,827 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:06,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:06,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912018942] [2021-10-15 19:09:07,016 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:07,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:07,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:07,020 INFO L87 Difference]: Start difference. First operand 18369 states and 25013 transitions. cyclomatic complexity: 6650 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:07,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:07,425 INFO L93 Difference]: Finished difference Result 33593 states and 45597 transitions. [2021-10-15 19:09:07,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:07,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33593 states and 45597 transitions. [2021-10-15 19:09:07,611 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 33356 [2021-10-15 19:09:07,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33593 states to 33593 states and 45597 transitions. [2021-10-15 19:09:07,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33593 [2021-10-15 19:09:07,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33593 [2021-10-15 19:09:07,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33593 states and 45597 transitions. [2021-10-15 19:09:07,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:07,847 INFO L681 BuchiCegarLoop]: Abstraction has 33593 states and 45597 transitions. [2021-10-15 19:09:07,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33593 states and 45597 transitions. [2021-10-15 19:09:08,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33593 to 32537. [2021-10-15 19:09:08,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32537 states, 32537 states have (on average 1.3610658634785013) internal successors, (44285), 32536 states have internal predecessors, (44285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:08,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32537 states to 32537 states and 44285 transitions. [2021-10-15 19:09:08,748 INFO L704 BuchiCegarLoop]: Abstraction has 32537 states and 44285 transitions. [2021-10-15 19:09:08,748 INFO L587 BuchiCegarLoop]: Abstraction has 32537 states and 44285 transitions. [2021-10-15 19:09:08,748 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-15 19:09:08,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32537 states and 44285 transitions. [2021-10-15 19:09:08,871 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 32300 [2021-10-15 19:09:08,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:08,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:08,873 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:08,873 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:08,874 INFO L791 eck$LassoCheckResult]: Stem: 172742#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 172697#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 172611#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 172612#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 172661#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 172662#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172436#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172414#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172388#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 172263#L443-1 assume !(0 == ~M_E~0); 172264#L603-1 assume !(0 == ~T1_E~0); 172451#L608-1 assume !(0 == ~T2_E~0); 172290#L613-1 assume !(0 == ~T3_E~0); 172291#L618-1 assume !(0 == ~T4_E~0); 172425#L623-1 assume !(0 == ~T5_E~0); 172594#L628-1 assume !(0 == ~E_M~0); 172715#L633-1 assume !(0 == ~E_1~0); 172573#L638-1 assume !(0 == ~E_2~0); 172574#L643-1 assume !(0 == ~E_3~0); 172627#L648-1 assume !(0 == ~E_4~0); 172628#L653-1 assume !(0 == ~E_5~0); 172659#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 172190#L296 assume !(1 == ~m_pc~0); 172191#L296-2 is_master_triggered_~__retres1~0 := 0; 172440#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 172323#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 172324#L747 assume !(0 != activate_threads_~tmp~1); 172330#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 172163#L315 assume !(1 == ~t1_pc~0); 172164#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 172725#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 172751#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 172112#L755 assume !(0 != activate_threads_~tmp___0~0); 172113#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 172130#L334 assume !(1 == ~t2_pc~0); 172131#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 172403#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 172170#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 172171#L763 assume !(0 != activate_threads_~tmp___1~0); 172716#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 172240#L353 assume !(1 == ~t3_pc~0); 172241#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 172507#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 172192#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 172193#L771 assume !(0 != activate_threads_~tmp___2~0); 172595#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 172596#L372 assume !(1 == ~t4_pc~0); 172305#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 172306#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 172400#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 172651#L779 assume !(0 != activate_threads_~tmp___3~0); 172140#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 172141#L391 assume !(1 == ~t5_pc~0); 172074#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 172075#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 172235#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 172401#L787 assume !(0 != activate_threads_~tmp___4~0); 172485#L787-2 assume !(1 == ~M_E~0); 172563#L671-1 assume !(1 == ~T1_E~0); 172310#L676-1 assume !(1 == ~T2_E~0); 172311#L681-1 assume !(1 == ~T3_E~0); 172460#L686-1 assume !(1 == ~T4_E~0); 172461#L691-1 assume !(1 == ~T5_E~0); 172641#L696-1 assume !(1 == ~E_M~0); 172642#L701-1 assume !(1 == ~E_1~0); 172678#L706-1 assume !(1 == ~E_2~0); 172472#L711-1 assume !(1 == ~E_3~0); 172276#L716-1 assume !(1 == ~E_4~0); 172277#L721-1 assume !(1 == ~E_5~0); 172707#L932-1 assume !false; 177662#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 177660#L578 [2021-10-15 19:09:08,874 INFO L793 eck$LassoCheckResult]: Loop: 177660#L578 assume !false; 177658#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 177655#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 177653#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 177650#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 177648#L503 assume 0 != eval_~tmp~0; 177645#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 177642#L511 assume !(0 != eval_~tmp_ndt_1~0); 177640#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 177603#L525 assume !(0 != eval_~tmp_ndt_2~0); 176959#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 176957#L539 assume !(0 != eval_~tmp_ndt_3~0); 176955#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 175974#L553 assume !(0 != eval_~tmp_ndt_4~0); 176953#L550 assume !(0 == ~t4_st~0); 177666#L564 assume !(0 == ~t5_st~0); 177660#L578 [2021-10-15 19:09:08,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:08,875 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-10-15 19:09:08,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:08,875 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453565266] [2021-10-15 19:09:08,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:08,876 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:08,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:08,902 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:09,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:09,097 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:09,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:09,098 INFO L82 PathProgramCache]: Analyzing trace with hash 913205966, now seen corresponding path program 1 times [2021-10-15 19:09:09,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:09,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210609412] [2021-10-15 19:09:09,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:09,100 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:09,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:09,106 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:09,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:09,112 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:09,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:09,113 INFO L82 PathProgramCache]: Analyzing trace with hash -1301279408, now seen corresponding path program 1 times [2021-10-15 19:09:09,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:09,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25086063] [2021-10-15 19:09:09,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:09,114 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:09,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:09,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:09,158 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:09,158 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25086063] [2021-10-15 19:09:09,158 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25086063] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:09,159 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:09,159 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-15 19:09:09,159 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590487083] [2021-10-15 19:09:09,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:09,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:09,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:09,340 INFO L87 Difference]: Start difference. First operand 32537 states and 44285 transitions. cyclomatic complexity: 11754 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:09,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:09,589 INFO L93 Difference]: Finished difference Result 41835 states and 56779 transitions. [2021-10-15 19:09:09,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:09,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41835 states and 56779 transitions. [2021-10-15 19:09:10,006 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 41582 [2021-10-15 19:09:10,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41835 states to 41835 states and 56779 transitions. [2021-10-15 19:09:10,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41835 [2021-10-15 19:09:10,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41835 [2021-10-15 19:09:10,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41835 states and 56779 transitions. [2021-10-15 19:09:10,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:10,468 INFO L681 BuchiCegarLoop]: Abstraction has 41835 states and 56779 transitions. [2021-10-15 19:09:10,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41835 states and 56779 transitions. [2021-10-15 19:09:11,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41835 to 41195. [2021-10-15 19:09:11,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41195 states, 41195 states have (on average 1.3581017113727394) internal successors, (55947), 41194 states have internal predecessors, (55947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:11,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41195 states to 41195 states and 55947 transitions. [2021-10-15 19:09:11,536 INFO L704 BuchiCegarLoop]: Abstraction has 41195 states and 55947 transitions. [2021-10-15 19:09:11,536 INFO L587 BuchiCegarLoop]: Abstraction has 41195 states and 55947 transitions. [2021-10-15 19:09:11,537 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-15 19:09:11,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41195 states and 55947 transitions. [2021-10-15 19:09:11,677 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40942 [2021-10-15 19:09:11,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:11,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:11,678 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:11,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:11,679 INFO L791 eck$LassoCheckResult]: Stem: 247148#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 247096#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 247001#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 247002#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 247054#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247055#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246812#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246791#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246766#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246641#L443-1 assume !(0 == ~M_E~0); 246642#L603-1 assume !(0 == ~T1_E~0); 246828#L608-1 assume !(0 == ~T2_E~0); 246665#L613-1 assume !(0 == ~T3_E~0); 246666#L618-1 assume !(0 == ~T4_E~0); 246802#L623-1 assume !(0 == ~T5_E~0); 246983#L628-1 assume !(0 == ~E_M~0); 247117#L633-1 assume !(0 == ~E_1~0); 246960#L638-1 assume !(0 == ~E_2~0); 246961#L643-1 assume !(0 == ~E_3~0); 247017#L648-1 assume !(0 == ~E_4~0); 247018#L653-1 assume !(0 == ~E_5~0); 247052#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 246571#L296 assume !(1 == ~m_pc~0); 246572#L296-2 is_master_triggered_~__retres1~0 := 0; 246818#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 246697#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 246698#L747 assume !(0 != activate_threads_~tmp~1); 246704#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 246542#L315 assume !(1 == ~t1_pc~0); 246543#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 247126#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 247161#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 246492#L755 assume !(0 != activate_threads_~tmp___0~0); 246493#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 246510#L334 assume !(1 == ~t2_pc~0); 246511#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 246782#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 246549#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 246550#L763 assume !(0 != activate_threads_~tmp___1~0); 247118#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 246618#L353 assume !(1 == ~t3_pc~0); 246619#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 246882#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 246573#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 246574#L771 assume !(0 != activate_threads_~tmp___2~0); 246984#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 246985#L372 assume !(1 == ~t4_pc~0); 246680#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 246681#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 246779#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 247043#L779 assume !(0 != activate_threads_~tmp___3~0); 246519#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 246520#L391 assume !(1 == ~t5_pc~0); 246454#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 246455#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 246613#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 246780#L787 assume !(0 != activate_threads_~tmp___4~0); 246865#L787-2 assume !(1 == ~M_E~0); 246951#L671-1 assume !(1 == ~T1_E~0); 246685#L676-1 assume !(1 == ~T2_E~0); 246686#L681-1 assume !(1 == ~T3_E~0); 246837#L686-1 assume !(1 == ~T4_E~0); 246838#L691-1 assume !(1 == ~T5_E~0); 247032#L696-1 assume !(1 == ~E_M~0); 247033#L701-1 assume !(1 == ~E_1~0); 247076#L706-1 assume !(1 == ~E_2~0); 246849#L711-1 assume !(1 == ~E_3~0); 246651#L716-1 assume !(1 == ~E_4~0); 246652#L721-1 assume !(1 == ~E_5~0); 247110#L932-1 assume !false; 256155#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 256152#L578 [2021-10-15 19:09:11,679 INFO L793 eck$LassoCheckResult]: Loop: 256152#L578 assume !false; 256149#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 256145#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 256142#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 256138#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 256135#L503 assume 0 != eval_~tmp~0; 256131#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 256132#L511 assume !(0 != eval_~tmp_ndt_1~0); 262586#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 254293#L525 assume !(0 != eval_~tmp_ndt_2~0); 253637#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 253632#L539 assume !(0 != eval_~tmp_ndt_3~0); 253633#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 257479#L553 assume !(0 != eval_~tmp_ndt_4~0); 256166#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 256162#L567 assume !(0 != eval_~tmp_ndt_5~0); 256159#L564 assume !(0 == ~t5_st~0); 256152#L578 [2021-10-15 19:09:11,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:11,681 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-10-15 19:09:11,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:11,681 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812452983] [2021-10-15 19:09:11,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:11,682 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:11,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:11,694 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:11,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:11,724 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:11,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:11,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1755558441, now seen corresponding path program 1 times [2021-10-15 19:09:11,725 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:11,725 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814265896] [2021-10-15 19:09:11,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:11,726 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:11,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:11,730 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:11,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:11,736 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:11,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:11,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1685128299, now seen corresponding path program 1 times [2021-10-15 19:09:11,737 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:11,737 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137386076] [2021-10-15 19:09:11,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:11,737 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:11,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-15 19:09:11,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-15 19:09:11,773 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-15 19:09:11,773 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137386076] [2021-10-15 19:09:11,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137386076] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-15 19:09:11,773 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-15 19:09:11,773 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-15 19:09:11,774 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387924823] [2021-10-15 19:09:11,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-15 19:09:11,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-15 19:09:11,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-15 19:09:11,976 INFO L87 Difference]: Start difference. First operand 41195 states and 55947 transitions. cyclomatic complexity: 14758 Second operand has 3 states, 2 states have (on average 44.0) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:12,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-15 19:09:12,344 INFO L93 Difference]: Finished difference Result 71639 states and 97183 transitions. [2021-10-15 19:09:12,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-15 19:09:12,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71639 states and 97183 transitions. [2021-10-15 19:09:12,966 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 71210 [2021-10-15 19:09:13,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71639 states to 71639 states and 97183 transitions. [2021-10-15 19:09:13,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71639 [2021-10-15 19:09:13,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71639 [2021-10-15 19:09:13,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71639 states and 97183 transitions. [2021-10-15 19:09:13,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-15 19:09:13,619 INFO L681 BuchiCegarLoop]: Abstraction has 71639 states and 97183 transitions. [2021-10-15 19:09:13,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71639 states and 97183 transitions. [2021-10-15 19:09:14,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71639 to 71063. [2021-10-15 19:09:14,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71063 states, 71063 states have (on average 1.3594556942431364) internal successors, (96607), 71062 states have internal predecessors, (96607), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-15 19:09:14,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71063 states to 71063 states and 96607 transitions. [2021-10-15 19:09:14,677 INFO L704 BuchiCegarLoop]: Abstraction has 71063 states and 96607 transitions. [2021-10-15 19:09:14,677 INFO L587 BuchiCegarLoop]: Abstraction has 71063 states and 96607 transitions. [2021-10-15 19:09:14,677 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-15 19:09:14,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71063 states and 96607 transitions. [2021-10-15 19:09:14,932 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 70634 [2021-10-15 19:09:14,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-15 19:09:14,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-15 19:09:14,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:14,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-15 19:09:14,935 INFO L791 eck$LassoCheckResult]: Stem: 359987#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 359932#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 359842#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 359843#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 359891#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 359892#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 359658#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 359637#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 359613#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 359485#L443-1 assume !(0 == ~M_E~0); 359486#L603-1 assume !(0 == ~T1_E~0); 359674#L608-1 assume !(0 == ~T2_E~0); 359509#L613-1 assume !(0 == ~T3_E~0); 359510#L618-1 assume !(0 == ~T4_E~0); 359647#L623-1 assume !(0 == ~T5_E~0); 359822#L628-1 assume !(0 == ~E_M~0); 359953#L633-1 assume !(0 == ~E_1~0); 359800#L638-1 assume !(0 == ~E_2~0); 359801#L643-1 assume !(0 == ~E_3~0); 359855#L648-1 assume !(0 == ~E_4~0); 359856#L653-1 assume !(0 == ~E_5~0); 359889#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 359413#L296 assume !(1 == ~m_pc~0); 359414#L296-2 is_master_triggered_~__retres1~0 := 0; 359662#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 359544#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 359545#L747 assume !(0 != activate_threads_~tmp~1); 359551#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 359384#L315 assume !(1 == ~t1_pc~0); 359385#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 359966#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 359995#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 359333#L755 assume !(0 != activate_threads_~tmp___0~0); 359334#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 359351#L334 assume !(1 == ~t2_pc~0); 359352#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 359628#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 359391#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 359392#L763 assume !(0 != activate_threads_~tmp___1~0); 359954#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 359462#L353 assume !(1 == ~t3_pc~0); 359463#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 359730#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 359415#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 359416#L771 assume !(0 != activate_threads_~tmp___2~0); 359823#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 359824#L372 assume !(1 == ~t4_pc~0); 359525#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 359526#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 359625#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 359881#L779 assume !(0 != activate_threads_~tmp___3~0); 359361#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 359362#L391 assume !(1 == ~t5_pc~0); 359296#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 359297#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 359457#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 359626#L787 assume !(0 != activate_threads_~tmp___4~0); 359710#L787-2 assume !(1 == ~M_E~0); 359793#L671-1 assume !(1 == ~T1_E~0); 359530#L676-1 assume !(1 == ~T2_E~0); 359531#L681-1 assume !(1 == ~T3_E~0); 359682#L686-1 assume !(1 == ~T4_E~0); 359683#L691-1 assume !(1 == ~T5_E~0); 359870#L696-1 assume !(1 == ~E_M~0); 359871#L701-1 assume !(1 == ~E_1~0); 359911#L706-1 assume !(1 == ~E_2~0); 359696#L711-1 assume !(1 == ~E_3~0); 359495#L716-1 assume !(1 == ~E_4~0); 359496#L721-1 assume !(1 == ~E_5~0); 359942#L932-1 assume !false; 367074#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 364515#L578 [2021-10-15 19:09:14,935 INFO L793 eck$LassoCheckResult]: Loop: 364515#L578 assume !false; 367071#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 367068#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 367066#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 367062#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 367060#L503 assume 0 != eval_~tmp~0; 367057#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 367054#L511 assume !(0 != eval_~tmp_ndt_1~0); 367051#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 367007#L525 assume !(0 != eval_~tmp_ndt_2~0); 364996#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 364524#L539 assume !(0 != eval_~tmp_ndt_3~0); 364522#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 364520#L553 assume !(0 != eval_~tmp_ndt_4~0); 364519#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 364517#L567 assume !(0 != eval_~tmp_ndt_5~0); 364516#L564 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet15;havoc eval_#t~nondet15; 364279#L581 assume !(0 != eval_~tmp_ndt_6~0); 364515#L578 [2021-10-15 19:09:14,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:14,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-10-15 19:09:14,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:14,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403252989] [2021-10-15 19:09:14,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:14,937 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:14,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:14,950 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:14,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:14,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:14,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:14,985 INFO L82 PathProgramCache]: Analyzing trace with hash 1412259251, now seen corresponding path program 1 times [2021-10-15 19:09:14,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:14,986 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190993346] [2021-10-15 19:09:14,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:14,987 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:14,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:14,992 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:14,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:14,998 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:14,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-15 19:09:14,999 INFO L82 PathProgramCache]: Analyzing trace with hash -699373643, now seen corresponding path program 1 times [2021-10-15 19:09:15,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-15 19:09:15,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851803882] [2021-10-15 19:09:15,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-15 19:09:15,000 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-15 19:09:15,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:15,013 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-15 19:09:15,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-15 19:09:15,054 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-15 19:09:18,432 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 15.10 07:09:18 BoogieIcfgContainer [2021-10-15 19:09:18,432 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-15 19:09:18,433 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-15 19:09:18,433 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-15 19:09:18,433 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-15 19:09:18,434 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 07:08:57" (3/4) ... [2021-10-15 19:09:18,443 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-15 19:09:18,533 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/witness.graphml [2021-10-15 19:09:18,534 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-15 19:09:18,536 INFO L168 Benchmark]: Toolchain (without parser) took 23385.31 ms. Allocated memory was 100.7 MB in the beginning and 9.1 GB in the end (delta: 9.0 GB). Free memory was 67.9 MB in the beginning and 8.4 GB in the end (delta: -8.3 GB). Peak memory consumption was 694.6 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,536 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 100.7 MB. Free memory is still 54.1 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-15 19:09:18,537 INFO L168 Benchmark]: CACSL2BoogieTranslator took 495.85 ms. Allocated memory was 100.7 MB in the beginning and 121.6 MB in the end (delta: 21.0 MB). Free memory was 67.6 MB in the beginning and 91.0 MB in the end (delta: -23.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,537 INFO L168 Benchmark]: Boogie Procedure Inliner took 93.83 ms. Allocated memory is still 121.6 MB. Free memory was 91.0 MB in the beginning and 86.0 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,538 INFO L168 Benchmark]: Boogie Preprocessor took 154.79 ms. Allocated memory is still 121.6 MB. Free memory was 86.0 MB in the beginning and 81.4 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,538 INFO L168 Benchmark]: RCFGBuilder took 1477.53 ms. Allocated memory is still 121.6 MB. Free memory was 81.4 MB in the beginning and 65.5 MB in the end (delta: 15.8 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,539 INFO L168 Benchmark]: BuchiAutomizer took 21053.19 ms. Allocated memory was 121.6 MB in the beginning and 9.1 GB in the end (delta: 9.0 GB). Free memory was 65.5 MB in the beginning and 8.4 GB in the end (delta: -8.3 GB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,540 INFO L168 Benchmark]: Witness Printer took 101.10 ms. Allocated memory is still 9.1 GB. Free memory was 8.4 GB in the beginning and 8.4 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-15 19:09:18,542 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 100.7 MB. Free memory is still 54.1 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 495.85 ms. Allocated memory was 100.7 MB in the beginning and 121.6 MB in the end (delta: 21.0 MB). Free memory was 67.6 MB in the beginning and 91.0 MB in the end (delta: -23.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 93.83 ms. Allocated memory is still 121.6 MB. Free memory was 91.0 MB in the beginning and 86.0 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 154.79 ms. Allocated memory is still 121.6 MB. Free memory was 86.0 MB in the beginning and 81.4 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1477.53 ms. Allocated memory is still 121.6 MB. Free memory was 81.4 MB in the beginning and 65.5 MB in the end (delta: 15.8 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 21053.19 ms. Allocated memory was 121.6 MB in the beginning and 9.1 GB in the end (delta: 9.0 GB). Free memory was 65.5 MB in the beginning and 8.4 GB in the end (delta: -8.3 GB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. * Witness Printer took 101.10 ms. Allocated memory is still 9.1 GB. Free memory was 8.4 GB in the beginning and 8.4 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 71063 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 20.9s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 7.3s. Construction of modules took 0.7s. Büchi inclusion checks took 2.0s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 5336.6ms AutomataMinimizationTime, 21 MinimizatonAttempts, 10985 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 3.4s Buchi closure took 0.2s. Biggest automaton had 71063 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17322 SDtfs, 20056 SDslu, 15514 SDs, 0 SdLazy, 537 SolverSat, 285 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 760.1ms Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 498]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=16208} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=16208, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@232aaa57=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1150a4b1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65c4d290=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@131ba8a7=0, NULL=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@123658ef=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3eb953b8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@48373e2a=0, tmp=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ba425ee=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7dd46598=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5428e08e=0, NULL=16210, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40838363=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28ec8eae=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68ca94f=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55f36db7=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c85a6cc=0, T1_E=2, NULL=16211, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=16209, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 498]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L977] int __retres1 ; [L888] m_i = 1 [L889] t1_i = 1 [L890] t2_i = 1 [L891] t3_i = 1 [L892] t4_i = 1 [L893] t5_i = 1 [L918] int kernel_st ; [L919] int tmp ; [L920] int tmp___0 ; [L924] kernel_st = 0 [L418] COND TRUE m_i == 1 [L419] m_st = 0 [L423] COND TRUE t1_i == 1 [L424] t1_st = 0 [L428] COND TRUE t2_i == 1 [L429] t2_st = 0 [L433] COND TRUE t3_i == 1 [L434] t3_st = 0 [L438] COND TRUE t4_i == 1 [L439] t4_st = 0 [L443] COND TRUE t5_i == 1 [L444] t5_st = 0 [L603] COND FALSE !(M_E == 0) [L608] COND FALSE !(T1_E == 0) [L613] COND FALSE !(T2_E == 0) [L618] COND FALSE !(T3_E == 0) [L623] COND FALSE !(T4_E == 0) [L628] COND FALSE !(T5_E == 0) [L633] COND FALSE !(E_M == 0) [L638] COND FALSE !(E_1 == 0) [L643] COND FALSE !(E_2 == 0) [L648] COND FALSE !(E_3 == 0) [L653] COND FALSE !(E_4 == 0) [L658] COND FALSE !(E_5 == 0) [L736] int tmp ; [L737] int tmp___0 ; [L738] int tmp___1 ; [L739] int tmp___2 ; [L740] int tmp___3 ; [L741] int tmp___4 ; [L293] int __retres1 ; [L296] COND FALSE !(m_pc == 1) [L306] __retres1 = 0 [L308] return (__retres1); [L745] tmp = is_master_triggered() [L747] COND FALSE !(\read(tmp)) [L312] int __retres1 ; [L315] COND FALSE !(t1_pc == 1) [L325] __retres1 = 0 [L327] return (__retres1); [L753] tmp___0 = is_transmit1_triggered() [L755] COND FALSE !(\read(tmp___0)) [L331] int __retres1 ; [L334] COND FALSE !(t2_pc == 1) [L344] __retres1 = 0 [L346] return (__retres1); [L761] tmp___1 = is_transmit2_triggered() [L763] COND FALSE !(\read(tmp___1)) [L350] int __retres1 ; [L353] COND FALSE !(t3_pc == 1) [L363] __retres1 = 0 [L365] return (__retres1); [L769] tmp___2 = is_transmit3_triggered() [L771] COND FALSE !(\read(tmp___2)) [L369] int __retres1 ; [L372] COND FALSE !(t4_pc == 1) [L382] __retres1 = 0 [L384] return (__retres1); [L777] tmp___3 = is_transmit4_triggered() [L779] COND FALSE !(\read(tmp___3)) [L388] int __retres1 ; [L391] COND FALSE !(t5_pc == 1) [L401] __retres1 = 0 [L403] return (__retres1); [L785] tmp___4 = is_transmit5_triggered() [L787] COND FALSE !(\read(tmp___4)) [L671] COND FALSE !(M_E == 1) [L676] COND FALSE !(T1_E == 1) [L681] COND FALSE !(T2_E == 1) [L686] COND FALSE !(T3_E == 1) [L691] COND FALSE !(T4_E == 1) [L696] COND FALSE !(T5_E == 1) [L701] COND FALSE !(E_M == 1) [L706] COND FALSE !(E_1 == 1) [L711] COND FALSE !(E_2 == 1) [L716] COND FALSE !(E_3 == 1) [L721] COND FALSE !(E_4 == 1) [L726] COND FALSE !(E_5 == 1) [L932] COND TRUE 1 [L935] kernel_st = 1 [L494] int tmp ; Loop: [L498] COND TRUE 1 [L453] int __retres1 ; [L456] COND TRUE m_st == 0 [L457] __retres1 = 1 [L489] return (__retres1); [L501] tmp = exists_runnable_thread() [L503] COND TRUE \read(tmp) [L508] COND TRUE m_st == 0 [L509] int tmp_ndt_1; [L510] tmp_ndt_1 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_1)) [L522] COND TRUE t1_st == 0 [L523] int tmp_ndt_2; [L524] tmp_ndt_2 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_2)) [L536] COND TRUE t2_st == 0 [L537] int tmp_ndt_3; [L538] tmp_ndt_3 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_3)) [L550] COND TRUE t3_st == 0 [L551] int tmp_ndt_4; [L552] tmp_ndt_4 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_4)) [L564] COND TRUE t4_st == 0 [L565] int tmp_ndt_5; [L566] tmp_ndt_5 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_5)) [L578] COND TRUE t5_st == 0 [L579] int tmp_ndt_6; [L580] tmp_ndt_6 = __VERIFIER_nondet_int() [L581] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-15 19:09:18,623 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2d0c26bb-c081-4979-8873-5fa1d3f98778/bin/uautomizer-hJ6jxDFKc3/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...