./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NO_13.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e943c265 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NO_13.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash eeea679d58a502ae5881094604c1f31424fa081cb4c3d3de58dd4530f33f3571 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-e943c26 [2021-10-21 19:05:07,017 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-21 19:05:07,020 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-21 19:05:07,080 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-21 19:05:07,081 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-21 19:05:07,084 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-21 19:05:07,086 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-21 19:05:07,090 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-21 19:05:07,093 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-21 19:05:07,100 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-21 19:05:07,101 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-21 19:05:07,103 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-21 19:05:07,103 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-21 19:05:07,107 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-21 19:05:07,110 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-21 19:05:07,117 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-21 19:05:07,118 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-21 19:05:07,119 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-21 19:05:07,121 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-21 19:05:07,123 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-21 19:05:07,125 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-21 19:05:07,129 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-21 19:05:07,130 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-21 19:05:07,131 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-21 19:05:07,134 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-21 19:05:07,135 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-21 19:05:07,135 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-21 19:05:07,136 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-21 19:05:07,137 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-21 19:05:07,138 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-21 19:05:07,138 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-21 19:05:07,139 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-21 19:05:07,140 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-21 19:05:07,141 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-21 19:05:07,149 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-21 19:05:07,150 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-21 19:05:07,151 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-21 19:05:07,151 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-21 19:05:07,152 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-21 19:05:07,152 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-21 19:05:07,153 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-21 19:05:07,154 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-10-21 19:05:07,205 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-21 19:05:07,206 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-21 19:05:07,207 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-21 19:05:07,207 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-21 19:05:07,208 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-21 19:05:07,208 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-21 19:05:07,209 INFO L138 SettingsManager]: * Use SBE=true [2021-10-21 19:05:07,209 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-21 19:05:07,209 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-21 19:05:07,209 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-21 19:05:07,210 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-21 19:05:07,211 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-21 19:05:07,211 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-21 19:05:07,211 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-21 19:05:07,211 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-21 19:05:07,212 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-21 19:05:07,212 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-21 19:05:07,212 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-21 19:05:07,212 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-21 19:05:07,212 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-21 19:05:07,213 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-21 19:05:07,213 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-21 19:05:07,213 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-21 19:05:07,213 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-21 19:05:07,214 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-21 19:05:07,214 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-21 19:05:07,215 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-21 19:05:07,216 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-21 19:05:07,216 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-21 19:05:07,217 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-21 19:05:07,217 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> eeea679d58a502ae5881094604c1f31424fa081cb4c3d3de58dd4530f33f3571 [2021-10-21 19:05:07,481 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-21 19:05:07,509 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-21 19:05:07,512 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-21 19:05:07,513 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-21 19:05:07,514 INFO L275 PluginConnector]: CDTParser initialized [2021-10-21 19:05:07,515 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/../../sv-benchmarks/c/termination-restricted-15/NO_13.c [2021-10-21 19:05:07,598 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/data/0b3b1d4eb/fcda993fab41451297eca649e4a8919d/FLAGa42a5fe2f [2021-10-21 19:05:07,992 INFO L306 CDTParser]: Found 1 translation units. [2021-10-21 19:05:07,992 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/sv-benchmarks/c/termination-restricted-15/NO_13.c [2021-10-21 19:05:08,001 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/data/0b3b1d4eb/fcda993fab41451297eca649e4a8919d/FLAGa42a5fe2f [2021-10-21 19:05:08,391 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/data/0b3b1d4eb/fcda993fab41451297eca649e4a8919d [2021-10-21 19:05:08,394 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-21 19:05:08,409 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-21 19:05:08,411 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-21 19:05:08,411 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-21 19:05:08,415 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-21 19:05:08,416 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,417 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d9cd1de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08, skipping insertion in model container [2021-10-21 19:05:08,417 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,425 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-21 19:05:08,437 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-21 19:05:08,562 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-21 19:05:08,566 INFO L203 MainTranslator]: Completed pre-run [2021-10-21 19:05:08,597 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-21 19:05:08,622 INFO L208 MainTranslator]: Completed translation [2021-10-21 19:05:08,623 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08 WrapperNode [2021-10-21 19:05:08,623 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-21 19:05:08,624 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-21 19:05:08,624 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-21 19:05:08,625 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-21 19:05:08,633 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,640 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,661 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-21 19:05:08,662 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-21 19:05:08,662 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-21 19:05:08,662 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-21 19:05:08,671 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,672 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,673 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,673 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,682 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,687 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,688 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,689 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-21 19:05:08,691 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-21 19:05:08,692 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-21 19:05:08,692 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-21 19:05:08,693 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (1/1) ... [2021-10-21 19:05:08,703 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:08,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:08,733 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:08,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-21 19:05:08,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-21 19:05:08,786 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-21 19:05:08,935 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-21 19:05:08,935 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2021-10-21 19:05:08,939 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.10 07:05:08 BoogieIcfgContainer [2021-10-21 19:05:08,939 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-21 19:05:08,941 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-21 19:05:08,941 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-21 19:05:08,945 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-21 19:05:08,945 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-21 19:05:08,946 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.10 07:05:08" (1/3) ... [2021-10-21 19:05:08,949 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56eac278 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.10 07:05:08, skipping insertion in model container [2021-10-21 19:05:08,950 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-21 19:05:08,950 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.10 07:05:08" (2/3) ... [2021-10-21 19:05:08,951 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@56eac278 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.10 07:05:08, skipping insertion in model container [2021-10-21 19:05:08,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-21 19:05:08,951 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.10 07:05:08" (3/3) ... [2021-10-21 19:05:08,953 INFO L389 chiAutomizerObserver]: Analyzing ICFG NO_13.c [2021-10-21 19:05:09,002 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-21 19:05:09,002 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-21 19:05:09,002 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-21 19:05:09,003 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-21 19:05:09,003 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-21 19:05:09,003 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-21 19:05:09,003 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-21 19:05:09,003 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-21 19:05:09,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:09,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:09,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:09,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:09,040 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-21 19:05:09,040 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-21 19:05:09,040 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-21 19:05:09,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:09,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:09,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:09,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:09,042 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-21 19:05:09,042 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-21 19:05:09,048 INFO L791 eck$LassoCheckResult]: Stem: 6#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3#L12-2true [2021-10-21 19:05:09,048 INFO L793 eck$LassoCheckResult]: Loop: 3#L12-2true assume !!(main_~i~0 < main_~j~0); 8#L12true assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3#L12-2true [2021-10-21 19:05:09,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:09,054 INFO L82 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2021-10-21 19:05:09,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:09,062 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581890397] [2021-10-21 19:05:09,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:09,064 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:09,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,126 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:09,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,144 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:09,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:09,147 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 1 times [2021-10-21 19:05:09,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:09,148 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076353805] [2021-10-21 19:05:09,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:09,148 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:09,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,160 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:09,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,167 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:09,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:09,169 INFO L82 PathProgramCache]: Analyzing trace with hash 31075, now seen corresponding path program 1 times [2021-10-21 19:05:09,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:09,169 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510261544] [2021-10-21 19:05:09,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:09,170 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:09,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,179 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:09,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:09,186 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:09,260 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:09,261 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:09,261 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:09,261 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:09,261 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-21 19:05:09,262 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,262 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:09,262 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:09,262 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration1_Loop [2021-10-21 19:05:09,262 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:09,262 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:09,280 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,292 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,369 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:09,370 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-21 19:05:09,372 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,372 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,394 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,420 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:09,421 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:09,423 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-10-21 19:05:09,448 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-21 19:05:09,448 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-21 19:05:09,487 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2021-10-21 19:05:09,487 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,487 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,490 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,499 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:09,499 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:09,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-10-21 19:05:09,530 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-21 19:05:09,530 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-21 19:05:09,568 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:09,569 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,571 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,579 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:09,579 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:09,599 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-10-21 19:05:09,648 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:09,648 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,648 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,650 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,655 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-21 19:05:09,656 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:09,693 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-10-21 19:05:09,734 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-21 19:05:09,740 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:09,741 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:09,741 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:09,741 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:09,741 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:09,741 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-21 19:05:09,741 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,742 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:09,742 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:09,742 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration1_Loop [2021-10-21 19:05:09,742 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:09,742 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:09,744 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,753 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,760 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:09,858 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:09,865 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-21 19:05:09,867 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,874 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,876 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:09,886 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:09,886 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:09,886 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:09,887 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:09,895 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-21 19:05:09,895 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-21 19:05:09,910 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-10-21 19:05:09,926 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-21 19:05:09,961 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:09,961 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:09,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:09,963 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:09,970 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:09,980 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:09,980 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:09,980 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:09,981 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:09,989 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-21 19:05:09,989 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-21 19:05:09,997 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-10-21 19:05:10,009 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-21 19:05:10,046 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,047 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,048 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,054 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:10,063 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:10,064 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-21 19:05:10,064 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:10,064 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:10,065 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:10,067 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-21 19:05:10,067 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-21 19:05:10,071 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-10-21 19:05:10,089 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-21 19:05:10,094 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-21 19:05:10,095 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2021-10-21 19:05:10,096 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,098 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-10-21 19:05:10,110 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-21 19:05:10,110 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-21 19:05:10,111 INFO L513 LassoAnalysis]: Proved termination. [2021-10-21 19:05:10,111 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2021-10-21 19:05:10,142 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,145 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-21 19:05:10,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:10,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:10,177 INFO L263 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:10,178 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:10,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:10,187 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:10,188 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:10,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:10,211 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-21 19:05:10,212 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:10,280 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 23 states and 30 transitions. Complement of second has 6 states. [2021-10-21 19:05:10,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:10,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:10,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2021-10-21 19:05:10,290 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 2 letters. [2021-10-21 19:05:10,291 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:10,291 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 3 letters. Loop has 2 letters. [2021-10-21 19:05:10,291 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:10,291 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 4 letters. [2021-10-21 19:05:10,291 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:10,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 30 transitions. [2021-10-21 19:05:10,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:10,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 7 states and 10 transitions. [2021-10-21 19:05:10,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2021-10-21 19:05:10,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-21 19:05:10,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 10 transitions. [2021-10-21 19:05:10,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:10,340 INFO L681 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-21 19:05:10,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 10 transitions. [2021-10-21 19:05:10,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2021-10-21 19:05:10,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 6 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:10,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 10 transitions. [2021-10-21 19:05:10,363 INFO L704 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-21 19:05:10,363 INFO L587 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-21 19:05:10,363 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-21 19:05:10,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 10 transitions. [2021-10-21 19:05:10,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:10,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:10,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:10,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] [2021-10-21 19:05:10,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-21 19:05:10,365 INFO L791 eck$LassoCheckResult]: Stem: 68#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 69#L12-2 assume !!(main_~i~0 < main_~j~0); 67#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 63#L12-2 [2021-10-21 19:05:10,365 INFO L793 eck$LassoCheckResult]: Loop: 63#L12-2 assume !!(main_~i~0 < main_~j~0); 64#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 63#L12-2 [2021-10-21 19:05:10,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:10,366 INFO L82 PathProgramCache]: Analyzing trace with hash 31077, now seen corresponding path program 1 times [2021-10-21 19:05:10,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:10,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828536020] [2021-10-21 19:05:10,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:10,367 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:10,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:10,422 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-10-21 19:05:10,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:10,426 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:10,427 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828536020] [2021-10-21 19:05:10,427 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828536020] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-21 19:05:10,427 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-21 19:05:10,428 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2021-10-21 19:05:10,428 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633153724] [2021-10-21 19:05:10,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-21 19:05:10,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:10,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 2 times [2021-10-21 19:05:10,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:10,431 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586015568] [2021-10-21 19:05:10,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:10,432 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:10,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:10,437 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:10,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:10,459 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:10,503 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:10,504 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:10,504 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:10,504 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:10,504 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-21 19:05:10,504 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,504 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:10,504 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:10,504 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration2_Loop [2021-10-21 19:05:10,505 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:10,505 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:10,507 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,589 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:10,590 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-21 19:05:10,590 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,602 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-10-21 19:05:10,614 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:10,614 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:10,632 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-21 19:05:10,632 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-21 19:05:10,654 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,654 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,655 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,658 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-10-21 19:05:10,659 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:10,659 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:10,673 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-21 19:05:10,673 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-21 19:05:10,692 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,692 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,693 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,694 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-10-21 19:05:10,701 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:10,701 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:10,735 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,735 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,735 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,736 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-10-21 19:05:10,738 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-21 19:05:10,738 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:10,783 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-21 19:05:10,785 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,786 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:10,786 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:10,786 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:10,786 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:10,786 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-21 19:05:10,786 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,786 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:10,786 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:10,786 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration2_Loop [2021-10-21 19:05:10,786 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:10,786 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:10,788 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,792 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,802 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:10,852 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:10,852 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-21 19:05:10,852 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,852 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,853 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,862 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:10,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:10,872 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:10,872 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:10,872 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:10,875 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-21 19:05:10,875 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-21 19:05:10,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-10-21 19:05:10,901 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-21 19:05:10,938 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:10,938 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,938 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,940 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,945 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:10,954 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:10,955 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-21 19:05:10,955 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:10,955 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:10,955 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:10,957 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-21 19:05:10,957 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-21 19:05:10,960 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-10-21 19:05:10,983 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-21 19:05:10,987 INFO L443 ModelExtractionUtils]: Simplification made 2 calls to the SMT solver. [2021-10-21 19:05:10,987 INFO L444 ModelExtractionUtils]: 2 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-21 19:05:10,988 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:10,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:10,989 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:10,994 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-21 19:05:10,994 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-21 19:05:10,995 INFO L513 LassoAnalysis]: Proved termination. [2021-10-21 19:05:10,995 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2021-10-21 19:05:11,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-10-21 19:05:11,018 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:11,019 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-21 19:05:11,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,044 INFO L263 TraceCheckSpWp]: Trace formula consists of 12 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,057 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,062 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,077 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-21 19:05:11,078 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,098 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 16 transitions. Complement of second has 5 states. [2021-10-21 19:05:11,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:11,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-21 19:05:11,101 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 2 letters. [2021-10-21 19:05:11,102 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,102 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 5 letters. Loop has 2 letters. [2021-10-21 19:05:11,102 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,102 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 4 letters. [2021-10-21 19:05:11,102 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 16 transitions. [2021-10-21 19:05:11,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:11,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 16 transitions. [2021-10-21 19:05:11,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-10-21 19:05:11,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-21 19:05:11,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 16 transitions. [2021-10-21 19:05:11,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:11,105 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2021-10-21 19:05:11,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 16 transitions. [2021-10-21 19:05:11,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2021-10-21 19:05:11,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 10 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 16 transitions. [2021-10-21 19:05:11,113 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2021-10-21 19:05:11,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:11,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-21 19:05:11,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-21 19:05:11,119 INFO L87 Difference]: Start difference. First operand 11 states and 16 transitions. Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:11,132 INFO L93 Difference]: Finished difference Result 13 states and 17 transitions. [2021-10-21 19:05:11,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-21 19:05:11,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 17 transitions. [2021-10-21 19:05:11,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:11,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 16 transitions. [2021-10-21 19:05:11,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-10-21 19:05:11,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-21 19:05:11,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 16 transitions. [2021-10-21 19:05:11,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:11,137 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-10-21 19:05:11,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 16 transitions. [2021-10-21 19:05:11,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2021-10-21 19:05:11,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2021-10-21 19:05:11,140 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2021-10-21 19:05:11,140 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2021-10-21 19:05:11,141 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-21 19:05:11,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2021-10-21 19:05:11,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-21 19:05:11,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:11,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:11,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1, 1] [2021-10-21 19:05:11,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-21 19:05:11,146 INFO L791 eck$LassoCheckResult]: Stem: 144#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 139#L12-2 assume !!(main_~i~0 < main_~j~0); 140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 149#L12-2 assume !!(main_~i~0 < main_~j~0); 148#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 146#L12-2 assume !!(main_~i~0 < main_~j~0); 142#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 145#L12-2 [2021-10-21 19:05:11,146 INFO L793 eck$LassoCheckResult]: Loop: 145#L12-2 assume !!(main_~i~0 < main_~j~0); 147#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 145#L12-2 [2021-10-21 19:05:11,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1366043347, now seen corresponding path program 1 times [2021-10-21 19:05:11,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:11,151 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037098063] [2021-10-21 19:05:11,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:11,152 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:11,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,205 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,205 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:11,205 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037098063] [2021-10-21 19:05:11,206 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037098063] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:11,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1909827399] [2021-10-21 19:05:11,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:11,207 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:11,207 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:11,212 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:11,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-10-21 19:05:11,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,257 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 3 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,258 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,323 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1909827399] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:11,323 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:11,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2021-10-21 19:05:11,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621571351] [2021-10-21 19:05:11,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-21 19:05:11,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,325 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 3 times [2021-10-21 19:05:11,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:11,325 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885816474] [2021-10-21 19:05:11,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:11,325 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:11,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:11,330 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:11,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:11,334 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:11,358 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:11,359 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:11,359 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:11,359 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:11,359 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-21 19:05:11,359 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,359 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:11,360 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:11,360 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration3_Loop [2021-10-21 19:05:11,360 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:11,360 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:11,361 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,373 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,416 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:11,416 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-21 19:05:11,417 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:11,423 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:11,427 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:11,427 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:11,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-10-21 19:05:11,471 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:11,471 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:11,472 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:11,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2021-10-21 19:05:11,477 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-21 19:05:11,477 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:11,534 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-21 19:05:11,537 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:11,538 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:11,538 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:11,538 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:11,538 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:11,538 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-21 19:05:11,538 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,538 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:11,538 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:11,538 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration3_Loop [2021-10-21 19:05:11,538 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:11,538 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:11,540 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,553 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:11,599 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:11,599 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-21 19:05:11,599 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:11,600 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:11,618 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:11,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2021-10-21 19:05:11,627 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:11,627 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-21 19:05:11,628 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:11,628 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:11,628 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:11,634 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-21 19:05:11,634 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-21 19:05:11,652 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-21 19:05:11,656 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-21 19:05:11,657 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2021-10-21 19:05:11,657 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:11,657 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:11,663 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:11,666 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-21 19:05:11,666 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-21 19:05:11,666 INFO L513 LassoAnalysis]: Proved termination. [2021-10-21 19:05:11,667 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2021-10-21 19:05:11,693 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2021-10-21 19:05:11,704 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:11,704 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-21 19:05:11,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,730 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,731 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,766 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,767 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,774 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-21 19:05:11,774 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,816 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 13 states and 19 transitions. Complement of second has 5 states. [2021-10-21 19:05:11,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:11,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-21 19:05:11,818 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-21 19:05:11,818 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,818 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-21 19:05:11,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,837 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,881 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,882 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,890 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-21 19:05:11,890 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,899 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 13 states and 19 transitions. Complement of second has 5 states. [2021-10-21 19:05:11,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:11,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-21 19:05:11,901 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-21 19:05:11,901 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,901 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-21 19:05:11,904 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:11,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:11,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,928 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,929 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:11,957 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:11,957 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:11,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:11,967 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-21 19:05:11,967 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,978 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 15 states and 22 transitions. Complement of second has 4 states. [2021-10-21 19:05:11,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:11,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 7 transitions. [2021-10-21 19:05:11,979 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-21 19:05:11,980 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,980 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 9 letters. Loop has 2 letters. [2021-10-21 19:05:11,980 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,980 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 4 letters. [2021-10-21 19:05:11,980 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:11,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 22 transitions. [2021-10-21 19:05:11,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-21 19:05:11,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 13 states and 18 transitions. [2021-10-21 19:05:11,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-21 19:05:11,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-21 19:05:11,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 18 transitions. [2021-10-21 19:05:11,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:11,983 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 18 transitions. [2021-10-21 19:05:11,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 18 transitions. [2021-10-21 19:05:11,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 6. [2021-10-21 19:05:11,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.3333333333333333) internal successors, (8), 5 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 8 transitions. [2021-10-21 19:05:11,985 INFO L704 BuchiCegarLoop]: Abstraction has 6 states and 8 transitions. [2021-10-21 19:05:11,985 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:11,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-21 19:05:11,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-21 19:05:11,986 INFO L87 Difference]: Start difference. First operand 6 states and 8 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:11,994 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:12,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:12,000 INFO L93 Difference]: Finished difference Result 10 states and 12 transitions. [2021-10-21 19:05:12,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-21 19:05:12,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 12 transitions. [2021-10-21 19:05:12,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-21 19:05:12,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 9 states and 11 transitions. [2021-10-21 19:05:12,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2021-10-21 19:05:12,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4 [2021-10-21 19:05:12,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2021-10-21 19:05:12,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:12,002 INFO L681 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-10-21 19:05:12,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2021-10-21 19:05:12,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2021-10-21 19:05:12,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.25) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 10 transitions. [2021-10-21 19:05:12,004 INFO L704 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-10-21 19:05:12,004 INFO L587 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-10-21 19:05:12,004 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-21 19:05:12,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 10 transitions. [2021-10-21 19:05:12,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-21 19:05:12,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:12,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:12,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1] [2021-10-21 19:05:12,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-21 19:05:12,006 INFO L791 eck$LassoCheckResult]: Stem: 339#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 335#L12-2 assume !!(main_~i~0 < main_~j~0); 336#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 337#L12-2 assume !!(main_~i~0 < main_~j~0); 338#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 342#L12-2 assume !!(main_~i~0 < main_~j~0); 340#L12 [2021-10-21 19:05:12,006 INFO L793 eck$LassoCheckResult]: Loop: 340#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 341#L12-2 assume !!(main_~i~0 < main_~j~0); 340#L12 [2021-10-21 19:05:12,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,006 INFO L82 PathProgramCache]: Analyzing trace with hash 925765348, now seen corresponding path program 2 times [2021-10-21 19:05:12,006 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,007 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088520399] [2021-10-21 19:05:12,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,007 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,015 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:12,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,022 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:12,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1436, now seen corresponding path program 1 times [2021-10-21 19:05:12,022 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,023 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602465874] [2021-10-21 19:05:12,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,023 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,027 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:12,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,031 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:12,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,032 INFO L82 PathProgramCache]: Analyzing trace with hash 602269631, now seen corresponding path program 2 times [2021-10-21 19:05:12,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,032 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956750827] [2021-10-21 19:05:12,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,032 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,065 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:12,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:12,065 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956750827] [2021-10-21 19:05:12,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956750827] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:12,066 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846261125] [2021-10-21 19:05:12,066 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:12,066 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:12,066 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,067 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-10-21 19:05:12,121 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:12,121 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:12,122 INFO L263 TraceCheckSpWp]: Trace formula consists of 25 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,123 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,160 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:12,160 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1846261125] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:12,161 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:12,161 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2021-10-21 19:05:12,161 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877926788] [2021-10-21 19:05:12,193 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:12,193 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:12,193 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:12,193 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:12,193 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-21 19:05:12,193 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,194 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:12,194 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:12,194 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration4_Loop [2021-10-21 19:05:12,194 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:12,194 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:12,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,199 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,207 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,265 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:12,265 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-21 19:05:12,265 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,266 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,267 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,268 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:12,269 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:12,284 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-10-21 19:05:12,290 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-21 19:05:12,290 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_7=1} Honda state: {v_rep~unnamed0~0~true_7=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-21 19:05:12,310 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:12,310 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,310 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,311 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-10-21 19:05:12,312 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-21 19:05:12,312 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:12,351 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:12,351 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,351 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,352 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,353 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2021-10-21 19:05:12,353 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-21 19:05:12,353 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-21 19:05:12,394 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-21 19:05:12,398 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2021-10-21 19:05:12,398 INFO L210 LassoAnalysis]: Preferences: [2021-10-21 19:05:12,398 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-21 19:05:12,398 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-21 19:05:12,398 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-21 19:05:12,399 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-21 19:05:12,399 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,399 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-21 19:05:12,399 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-21 19:05:12,399 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration4_Loop [2021-10-21 19:05:12,399 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-21 19:05:12,399 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-21 19:05:12,400 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,410 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,412 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-21 19:05:12,452 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-21 19:05:12,452 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-21 19:05:12,452 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,453 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,453 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,462 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-21 19:05:12,471 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-21 19:05:12,471 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-21 19:05:12,472 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-21 19:05:12,472 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-21 19:05:12,472 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-21 19:05:12,473 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-21 19:05:12,473 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-21 19:05:12,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2021-10-21 19:05:12,489 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-21 19:05:12,492 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-21 19:05:12,493 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-21 19:05:12,493 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-21 19:05:12,493 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,494 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,496 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-21 19:05:12,496 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-21 19:05:12,496 INFO L513 LassoAnalysis]: Proved termination. [2021-10-21 19:05:12,496 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = -2*ULTIMATE.start_main_~j~0 + 103 Supporting invariants [] [2021-10-21 19:05:12,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2021-10-21 19:05:12,533 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:12,533 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-21 19:05:12,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,552 INFO L263 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,580 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,581 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:12,613 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-21 19:05:12,614 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,617 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 8 states and 10 transitions. Complement of second has 3 states. [2021-10-21 19:05:12,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:12,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2021-10-21 19:05:12,618 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-21 19:05:12,619 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:12,619 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-21 19:05:12,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,633 INFO L263 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,633 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,651 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:12,683 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-21 19:05:12,684 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,691 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 8 states and 10 transitions. Complement of second has 3 states. [2021-10-21 19:05:12,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:12,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2021-10-21 19:05:12,693 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-21 19:05:12,693 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:12,693 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-21 19:05:12,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,711 INFO L263 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,712 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,730 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,730 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:12,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-21 19:05:12,763 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-21 19:05:12,763 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,775 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 12 states and 14 transitions. Complement of second has 4 states. [2021-10-21 19:05:12,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-21 19:05:12,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2021-10-21 19:05:12,777 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-21 19:05:12,777 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:12,777 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 8 letters. Loop has 2 letters. [2021-10-21 19:05:12,777 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:12,778 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 4 letters. [2021-10-21 19:05:12,778 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-21 19:05:12,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 14 transitions. [2021-10-21 19:05:12,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2021-10-21 19:05:12,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 10 states and 12 transitions. [2021-10-21 19:05:12,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:12,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:12,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 12 transitions. [2021-10-21 19:05:12,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:12,782 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2021-10-21 19:05:12,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 12 transitions. [2021-10-21 19:05:12,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 9. [2021-10-21 19:05:12,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2021-10-21 19:05:12,784 INFO L704 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-10-21 19:05:12,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:12,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-21 19:05:12,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-10-21 19:05:12,787 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. Second operand has 5 states, 5 states have (on average 1.6) internal successors, (8), 4 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:12,799 INFO L93 Difference]: Finished difference Result 13 states and 15 transitions. [2021-10-21 19:05:12,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-21 19:05:12,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 15 transitions. [2021-10-21 19:05:12,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:12,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 14 transitions. [2021-10-21 19:05:12,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:12,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:12,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 14 transitions. [2021-10-21 19:05:12,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:12,805 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 14 transitions. [2021-10-21 19:05:12,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 14 transitions. [2021-10-21 19:05:12,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2021-10-21 19:05:12,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.1818181818181819) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:12,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 13 transitions. [2021-10-21 19:05:12,808 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2021-10-21 19:05:12,808 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2021-10-21 19:05:12,808 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-21 19:05:12,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 13 transitions. [2021-10-21 19:05:12,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:12,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:12,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:12,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 1] [2021-10-21 19:05:12,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:12,811 INFO L791 eck$LassoCheckResult]: Stem: 519#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 515#L12-2 assume !!(main_~i~0 < main_~j~0); 516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 517#L12-2 assume !!(main_~i~0 < main_~j~0); 518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 525#L12-2 assume !!(main_~i~0 < main_~j~0); 524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 523#L12-2 assume !!(main_~i~0 < main_~j~0); 520#L12 [2021-10-21 19:05:12,811 INFO L793 eck$LassoCheckResult]: Loop: 520#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 521#L12-2 assume !!(main_~i~0 < main_~j~0); 524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 523#L12-2 assume !!(main_~i~0 < main_~j~0); 520#L12 [2021-10-21 19:05:12,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,813 INFO L82 PathProgramCache]: Analyzing trace with hash 602269569, now seen corresponding path program 3 times [2021-10-21 19:05:12,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,813 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290126394] [2021-10-21 19:05:12,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,814 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,843 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:12,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,856 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:12,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 1 times [2021-10-21 19:05:12,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,859 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054663807] [2021-10-21 19:05:12,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,860 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,867 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:12,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:12,873 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:12,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:12,876 INFO L82 PathProgramCache]: Analyzing trace with hash 1740322745, now seen corresponding path program 3 times [2021-10-21 19:05:12,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:12,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909359290] [2021-10-21 19:05:12,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:12,881 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:12,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:12,933 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:12,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:12,934 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909359290] [2021-10-21 19:05:12,934 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1909359290] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:12,934 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1855559413] [2021-10-21 19:05:12,934 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:12,934 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:12,935 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:12,935 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:12,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-10-21 19:05:12,977 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2021-10-21 19:05:12,985 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2021-10-21 19:05:12,986 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:12,986 INFO L263 TraceCheckSpWp]: Trace formula consists of 37 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-21 19:05:12,987 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:13,027 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,028 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1855559413] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,028 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:13,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2021-10-21 19:05:13,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650881494] [2021-10-21 19:05:13,090 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:13,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-21 19:05:13,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-10-21 19:05:13,091 INFO L87 Difference]: Start difference. First operand 11 states and 13 transitions. cyclomatic complexity: 3 Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:13,113 INFO L93 Difference]: Finished difference Result 15 states and 17 transitions. [2021-10-21 19:05:13,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-21 19:05:13,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 17 transitions. [2021-10-21 19:05:13,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 14 states and 16 transitions. [2021-10-21 19:05:13,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:13,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:13,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2021-10-21 19:05:13,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:13,118 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 16 transitions. [2021-10-21 19:05:13,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2021-10-21 19:05:13,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2021-10-21 19:05:13,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.1538461538461537) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2021-10-21 19:05:13,121 INFO L704 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2021-10-21 19:05:13,121 INFO L587 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2021-10-21 19:05:13,121 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-21 19:05:13,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2021-10-21 19:05:13,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:13,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:13,123 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 1] [2021-10-21 19:05:13,123 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:13,124 INFO L791 eck$LassoCheckResult]: Stem: 589#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 585#L12-2 assume !!(main_~i~0 < main_~j~0); 586#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 587#L12-2 assume !!(main_~i~0 < main_~j~0); 588#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 597#L12-2 assume !!(main_~i~0 < main_~j~0); 596#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 595#L12-2 assume !!(main_~i~0 < main_~j~0); 594#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 593#L12-2 assume !!(main_~i~0 < main_~j~0); 590#L12 [2021-10-21 19:05:13,124 INFO L793 eck$LassoCheckResult]: Loop: 590#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 591#L12-2 assume !!(main_~i~0 < main_~j~0); 594#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 593#L12-2 assume !!(main_~i~0 < main_~j~0); 590#L12 [2021-10-21 19:05:13,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,124 INFO L82 PathProgramCache]: Analyzing trace with hash -1039528738, now seen corresponding path program 4 times [2021-10-21 19:05:13,125 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,125 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781830204] [2021-10-21 19:05:13,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,125 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,142 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,167 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 2 times [2021-10-21 19:05:13,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,173 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014443855] [2021-10-21 19:05:13,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,173 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,182 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,188 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1650681494, now seen corresponding path program 4 times [2021-10-21 19:05:13,191 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,192 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114322590] [2021-10-21 19:05:13,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,192 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:13,252 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:13,252 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114322590] [2021-10-21 19:05:13,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114322590] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,253 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2001776300] [2021-10-21 19:05:13,253 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:13,253 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:13,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:13,254 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:13,270 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-10-21 19:05:13,308 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:13,308 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:13,309 INFO L263 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-21 19:05:13,310 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:13,350 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2001776300] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,350 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:13,350 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2021-10-21 19:05:13,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352758582] [2021-10-21 19:05:13,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:13,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-21 19:05:13,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-10-21 19:05:13,412 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:13,438 INFO L93 Difference]: Finished difference Result 17 states and 19 transitions. [2021-10-21 19:05:13,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-21 19:05:13,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 19 transitions. [2021-10-21 19:05:13,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 16 states and 18 transitions. [2021-10-21 19:05:13,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:13,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:13,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 18 transitions. [2021-10-21 19:05:13,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:13,441 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2021-10-21 19:05:13,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 18 transitions. [2021-10-21 19:05:13,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2021-10-21 19:05:13,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.1333333333333333) internal successors, (17), 14 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 17 transitions. [2021-10-21 19:05:13,443 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2021-10-21 19:05:13,443 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2021-10-21 19:05:13,443 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-21 19:05:13,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 17 transitions. [2021-10-21 19:05:13,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:13,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:13,444 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 1] [2021-10-21 19:05:13,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:13,445 INFO L791 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 666#L12-2 assume !!(main_~i~0 < main_~j~0); 667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 668#L12-2 assume !!(main_~i~0 < main_~j~0); 669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 680#L12-2 assume !!(main_~i~0 < main_~j~0); 679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 678#L12-2 assume !!(main_~i~0 < main_~j~0); 676#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 675#L12-2 assume !!(main_~i~0 < main_~j~0); 674#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 673#L12-2 assume !!(main_~i~0 < main_~j~0); 671#L12 [2021-10-21 19:05:13,445 INFO L793 eck$LassoCheckResult]: Loop: 671#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 672#L12-2 assume !!(main_~i~0 < main_~j~0); 674#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 673#L12-2 assume !!(main_~i~0 < main_~j~0); 671#L12 [2021-10-21 19:05:13,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,445 INFO L82 PathProgramCache]: Analyzing trace with hash 1740263163, now seen corresponding path program 5 times [2021-10-21 19:05:13,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,446 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463825509] [2021-10-21 19:05:13,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,446 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,453 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,461 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 3 times [2021-10-21 19:05:13,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,462 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441650364] [2021-10-21 19:05:13,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,462 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,466 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,469 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,470 INFO L82 PathProgramCache]: Analyzing trace with hash 1404785203, now seen corresponding path program 5 times [2021-10-21 19:05:13,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,470 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748646659] [2021-10-21 19:05:13,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,471 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:13,528 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:13,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748646659] [2021-10-21 19:05:13,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748646659] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [905851750] [2021-10-21 19:05:13,529 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:13,529 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:13,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:13,541 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:13,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-10-21 19:05:13,611 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-10-21 19:05:13,611 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:13,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 7 conjunts are in the unsatisfiable core [2021-10-21 19:05:13,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:13,666 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [905851750] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,667 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:13,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2021-10-21 19:05:13,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574713963] [2021-10-21 19:05:13,713 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:13,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-10-21 19:05:13,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-10-21 19:05:13,715 INFO L87 Difference]: Start difference. First operand 15 states and 17 transitions. cyclomatic complexity: 3 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:13,736 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2021-10-21 19:05:13,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-10-21 19:05:13,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2021-10-21 19:05:13,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 18 states and 20 transitions. [2021-10-21 19:05:13,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:13,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:13,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 20 transitions. [2021-10-21 19:05:13,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:13,740 INFO L681 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2021-10-21 19:05:13,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 20 transitions. [2021-10-21 19:05:13,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 17. [2021-10-21 19:05:13,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.1176470588235294) internal successors, (19), 16 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:13,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 19 transitions. [2021-10-21 19:05:13,746 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2021-10-21 19:05:13,746 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2021-10-21 19:05:13,746 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-21 19:05:13,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 19 transitions. [2021-10-21 19:05:13,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:13,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:13,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:13,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 1] [2021-10-21 19:05:13,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:13,752 INFO L791 eck$LassoCheckResult]: Stem: 762#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 758#L12-2 assume !!(main_~i~0 < main_~j~0); 759#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 760#L12-2 assume !!(main_~i~0 < main_~j~0); 761#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 765#L12-2 assume !!(main_~i~0 < main_~j~0); 774#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 773#L12-2 assume !!(main_~i~0 < main_~j~0); 772#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 771#L12-2 assume !!(main_~i~0 < main_~j~0); 769#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 768#L12-2 assume !!(main_~i~0 < main_~j~0); 767#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 766#L12-2 assume !!(main_~i~0 < main_~j~0); 763#L12 [2021-10-21 19:05:13,752 INFO L793 eck$LassoCheckResult]: Loop: 763#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 764#L12-2 assume !!(main_~i~0 < main_~j~0); 767#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 766#L12-2 assume !!(main_~i~0 < main_~j~0); 763#L12 [2021-10-21 19:05:13,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1650621912, now seen corresponding path program 6 times [2021-10-21 19:05:13,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,753 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233904139] [2021-10-21 19:05:13,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,753 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,769 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 4 times [2021-10-21 19:05:13,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,788 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174069767] [2021-10-21 19:05:13,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,788 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,792 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:13,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:13,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:13,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:13,795 INFO L82 PathProgramCache]: Analyzing trace with hash 1321650832, now seen corresponding path program 6 times [2021-10-21 19:05:13,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:13,796 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318698879] [2021-10-21 19:05:13,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:13,796 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:13,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:13,856 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:13,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:13,857 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318698879] [2021-10-21 19:05:13,859 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318698879] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:13,860 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [52180378] [2021-10-21 19:05:13,860 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:13,860 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:13,860 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:13,864 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:13,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-10-21 19:05:13,957 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2021-10-21 19:05:13,957 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:13,958 INFO L263 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 8 conjunts are in the unsatisfiable core [2021-10-21 19:05:13,959 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:14,013 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [52180378] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,014 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:14,014 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2021-10-21 19:05:14,015 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481823601] [2021-10-21 19:05:14,059 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:14,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-10-21 19:05:14,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-10-21 19:05:14,060 INFO L87 Difference]: Start difference. First operand 17 states and 19 transitions. cyclomatic complexity: 3 Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:14,086 INFO L93 Difference]: Finished difference Result 21 states and 23 transitions. [2021-10-21 19:05:14,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-10-21 19:05:14,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 23 transitions. [2021-10-21 19:05:14,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 20 states and 22 transitions. [2021-10-21 19:05:14,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:14,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:14,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 22 transitions. [2021-10-21 19:05:14,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:14,094 INFO L681 BuchiCegarLoop]: Abstraction has 20 states and 22 transitions. [2021-10-21 19:05:14,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 22 transitions. [2021-10-21 19:05:14,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 19. [2021-10-21 19:05:14,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2021-10-21 19:05:14,099 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2021-10-21 19:05:14,099 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2021-10-21 19:05:14,099 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-21 19:05:14,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2021-10-21 19:05:14,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:14,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:14,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 1] [2021-10-21 19:05:14,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:14,100 INFO L791 eck$LassoCheckResult]: Stem: 865#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 861#L12-2 assume !!(main_~i~0 < main_~j~0); 862#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 863#L12-2 assume !!(main_~i~0 < main_~j~0); 864#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 868#L12-2 assume !!(main_~i~0 < main_~j~0); 879#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 878#L12-2 assume !!(main_~i~0 < main_~j~0); 877#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 876#L12-2 assume !!(main_~i~0 < main_~j~0); 875#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 874#L12-2 assume !!(main_~i~0 < main_~j~0); 872#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 871#L12-2 assume !!(main_~i~0 < main_~j~0); 870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 869#L12-2 assume !!(main_~i~0 < main_~j~0); 866#L12 [2021-10-21 19:05:14,100 INFO L793 eck$LassoCheckResult]: Loop: 866#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 867#L12-2 assume !!(main_~i~0 < main_~j~0); 870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 869#L12-2 assume !!(main_~i~0 < main_~j~0); 866#L12 [2021-10-21 19:05:14,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1404725621, now seen corresponding path program 7 times [2021-10-21 19:05:14,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,101 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501733035] [2021-10-21 19:05:14,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,101 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,108 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,115 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,116 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 5 times [2021-10-21 19:05:14,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900403967] [2021-10-21 19:05:14,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,117 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,123 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,126 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,127 INFO L82 PathProgramCache]: Analyzing trace with hash -1261068371, now seen corresponding path program 7 times [2021-10-21 19:05:14,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356027071] [2021-10-21 19:05:14,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,128 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:14,216 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,216 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:14,216 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356027071] [2021-10-21 19:05:14,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356027071] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,217 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2138934393] [2021-10-21 19:05:14,217 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:14,217 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:14,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:14,223 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:14,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-10-21 19:05:14,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:14,298 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 9 conjunts are in the unsatisfiable core [2021-10-21 19:05:14,299 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:14,363 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2138934393] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,364 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:14,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2021-10-21 19:05:14,364 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026218052] [2021-10-21 19:05:14,407 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:14,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-10-21 19:05:14,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-10-21 19:05:14,408 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 3 Second operand has 10 states, 10 states have (on average 1.9) internal successors, (19), 9 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:14,438 INFO L93 Difference]: Finished difference Result 23 states and 25 transitions. [2021-10-21 19:05:14,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-21 19:05:14,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 25 transitions. [2021-10-21 19:05:14,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 22 states and 24 transitions. [2021-10-21 19:05:14,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:14,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:14,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 24 transitions. [2021-10-21 19:05:14,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:14,440 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 24 transitions. [2021-10-21 19:05:14,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 24 transitions. [2021-10-21 19:05:14,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2021-10-21 19:05:14,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.0952380952380953) internal successors, (23), 20 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 23 transitions. [2021-10-21 19:05:14,443 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-21 19:05:14,443 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-21 19:05:14,443 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-21 19:05:14,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 23 transitions. [2021-10-21 19:05:14,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:14,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:14,444 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 1] [2021-10-21 19:05:14,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:14,445 INFO L791 eck$LassoCheckResult]: Stem: 979#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 975#L12-2 assume !!(main_~i~0 < main_~j~0); 976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 977#L12-2 assume !!(main_~i~0 < main_~j~0); 978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 982#L12-2 assume !!(main_~i~0 < main_~j~0); 995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 994#L12-2 assume !!(main_~i~0 < main_~j~0); 993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 992#L12-2 assume !!(main_~i~0 < main_~j~0); 991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 990#L12-2 assume !!(main_~i~0 < main_~j~0); 989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 988#L12-2 assume !!(main_~i~0 < main_~j~0); 986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 985#L12-2 assume !!(main_~i~0 < main_~j~0); 984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 983#L12-2 assume !!(main_~i~0 < main_~j~0); 980#L12 [2021-10-21 19:05:14,445 INFO L793 eck$LassoCheckResult]: Loop: 980#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 981#L12-2 assume !!(main_~i~0 < main_~j~0); 984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 983#L12-2 assume !!(main_~i~0 < main_~j~0); 980#L12 [2021-10-21 19:05:14,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,445 INFO L82 PathProgramCache]: Analyzing trace with hash 1321591250, now seen corresponding path program 8 times [2021-10-21 19:05:14,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,446 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644900773] [2021-10-21 19:05:14,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,446 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,453 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,459 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,460 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 6 times [2021-10-21 19:05:14,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,460 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388130152] [2021-10-21 19:05:14,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,461 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,464 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,467 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,467 INFO L82 PathProgramCache]: Analyzing trace with hash -763125366, now seen corresponding path program 8 times [2021-10-21 19:05:14,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087736933] [2021-10-21 19:05:14,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,468 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:14,539 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:14,539 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087736933] [2021-10-21 19:05:14,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087736933] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,540 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [555865568] [2021-10-21 19:05:14,540 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:14,540 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:14,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:14,542 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:14,563 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-10-21 19:05:14,627 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:14,627 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:14,628 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-21 19:05:14,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:14,695 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,695 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [555865568] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:14,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2021-10-21 19:05:14,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256902167] [2021-10-21 19:05:14,738 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:14,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-10-21 19:05:14,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-10-21 19:05:14,739 INFO L87 Difference]: Start difference. First operand 21 states and 23 transitions. cyclomatic complexity: 3 Second operand has 11 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:14,775 INFO L93 Difference]: Finished difference Result 25 states and 27 transitions. [2021-10-21 19:05:14,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-21 19:05:14,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 27 transitions. [2021-10-21 19:05:14,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 24 states and 26 transitions. [2021-10-21 19:05:14,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:14,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:14,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 26 transitions. [2021-10-21 19:05:14,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:14,779 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2021-10-21 19:05:14,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 26 transitions. [2021-10-21 19:05:14,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 23. [2021-10-21 19:05:14,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.0869565217391304) internal successors, (25), 22 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:14,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2021-10-21 19:05:14,784 INFO L704 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2021-10-21 19:05:14,784 INFO L587 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2021-10-21 19:05:14,784 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-21 19:05:14,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 25 transitions. [2021-10-21 19:05:14,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:14,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:14,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:14,787 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 1] [2021-10-21 19:05:14,787 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:14,787 INFO L791 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1100#L12-2 assume !!(main_~i~0 < main_~j~0); 1101#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1102#L12-2 assume !!(main_~i~0 < main_~j~0); 1103#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1107#L12-2 assume !!(main_~i~0 < main_~j~0); 1122#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1121#L12-2 assume !!(main_~i~0 < main_~j~0); 1120#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1119#L12-2 assume !!(main_~i~0 < main_~j~0); 1118#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1117#L12-2 assume !!(main_~i~0 < main_~j~0); 1116#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1115#L12-2 assume !!(main_~i~0 < main_~j~0); 1114#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1113#L12-2 assume !!(main_~i~0 < main_~j~0); 1111#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1110#L12-2 assume !!(main_~i~0 < main_~j~0); 1109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1108#L12-2 assume !!(main_~i~0 < main_~j~0); 1105#L12 [2021-10-21 19:05:14,787 INFO L793 eck$LassoCheckResult]: Loop: 1105#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1106#L12-2 assume !!(main_~i~0 < main_~j~0); 1109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1108#L12-2 assume !!(main_~i~0 < main_~j~0); 1105#L12 [2021-10-21 19:05:14,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,788 INFO L82 PathProgramCache]: Analyzing trace with hash -1261127953, now seen corresponding path program 9 times [2021-10-21 19:05:14,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,788 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394144914] [2021-10-21 19:05:14,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,788 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,801 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,818 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,823 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 7 times [2021-10-21 19:05:14,823 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,823 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272847400] [2021-10-21 19:05:14,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,824 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,827 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:14,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:14,848 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:14,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:14,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1018732583, now seen corresponding path program 9 times [2021-10-21 19:05:14,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:14,849 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210550776] [2021-10-21 19:05:14,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:14,849 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:14,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:14,957 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:14,958 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:14,958 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210550776] [2021-10-21 19:05:14,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210550776] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:14,958 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [755949685] [2021-10-21 19:05:14,959 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:14,959 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:14,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:14,961 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:14,979 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-10-21 19:05:15,051 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2021-10-21 19:05:15,051 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:15,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 11 conjunts are in the unsatisfiable core [2021-10-21 19:05:15,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:15,143 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:15,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [755949685] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:15,144 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:15,144 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2021-10-21 19:05:15,144 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609164714] [2021-10-21 19:05:15,192 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:15,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-10-21 19:05:15,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-10-21 19:05:15,193 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. cyclomatic complexity: 3 Second operand has 12 states, 12 states have (on average 1.9166666666666667) internal successors, (23), 11 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:15,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:15,229 INFO L93 Difference]: Finished difference Result 27 states and 29 transitions. [2021-10-21 19:05:15,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-10-21 19:05:15,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 29 transitions. [2021-10-21 19:05:15,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:15,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 26 states and 28 transitions. [2021-10-21 19:05:15,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:15,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:15,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 28 transitions. [2021-10-21 19:05:15,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:15,236 INFO L681 BuchiCegarLoop]: Abstraction has 26 states and 28 transitions. [2021-10-21 19:05:15,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 28 transitions. [2021-10-21 19:05:15,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2021-10-21 19:05:15,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.08) internal successors, (27), 24 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:15,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 27 transitions. [2021-10-21 19:05:15,242 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2021-10-21 19:05:15,242 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2021-10-21 19:05:15,242 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-21 19:05:15,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 27 transitions. [2021-10-21 19:05:15,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:15,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:15,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:15,244 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 10, 1] [2021-10-21 19:05:15,244 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:15,245 INFO L791 eck$LassoCheckResult]: Stem: 1240#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1236#L12-2 assume !!(main_~i~0 < main_~j~0); 1237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1238#L12-2 assume !!(main_~i~0 < main_~j~0); 1239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1243#L12-2 assume !!(main_~i~0 < main_~j~0); 1260#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1259#L12-2 assume !!(main_~i~0 < main_~j~0); 1258#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1257#L12-2 assume !!(main_~i~0 < main_~j~0); 1256#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1255#L12-2 assume !!(main_~i~0 < main_~j~0); 1254#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1253#L12-2 assume !!(main_~i~0 < main_~j~0); 1252#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1251#L12-2 assume !!(main_~i~0 < main_~j~0); 1250#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1249#L12-2 assume !!(main_~i~0 < main_~j~0); 1247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1246#L12-2 assume !!(main_~i~0 < main_~j~0); 1245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1244#L12-2 assume !!(main_~i~0 < main_~j~0); 1241#L12 [2021-10-21 19:05:15,245 INFO L793 eck$LassoCheckResult]: Loop: 1241#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1242#L12-2 assume !!(main_~i~0 < main_~j~0); 1245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1244#L12-2 assume !!(main_~i~0 < main_~j~0); 1241#L12 [2021-10-21 19:05:15,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,245 INFO L82 PathProgramCache]: Analyzing trace with hash -763184948, now seen corresponding path program 10 times [2021-10-21 19:05:15,245 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,246 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44867390] [2021-10-21 19:05:15,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,246 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,255 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:15,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,264 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:15,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 8 times [2021-10-21 19:05:15,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627048930] [2021-10-21 19:05:15,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,266 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,269 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:15,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,272 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:15,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,272 INFO L82 PathProgramCache]: Analyzing trace with hash -307729532, now seen corresponding path program 10 times [2021-10-21 19:05:15,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738229026] [2021-10-21 19:05:15,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,274 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:15,388 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:15,388 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:15,388 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738229026] [2021-10-21 19:05:15,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738229026] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:15,389 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [818301705] [2021-10-21 19:05:15,389 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:15,389 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:15,389 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:15,390 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:15,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-10-21 19:05:15,480 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:15,480 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:15,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 12 conjunts are in the unsatisfiable core [2021-10-21 19:05:15,482 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:15,571 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:15,571 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [818301705] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:15,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:15,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2021-10-21 19:05:15,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311238443] [2021-10-21 19:05:15,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:15,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-10-21 19:05:15,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-10-21 19:05:15,618 INFO L87 Difference]: Start difference. First operand 25 states and 27 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 12 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:15,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:15,652 INFO L93 Difference]: Finished difference Result 29 states and 31 transitions. [2021-10-21 19:05:15,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-10-21 19:05:15,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 31 transitions. [2021-10-21 19:05:15,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:15,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 28 states and 30 transitions. [2021-10-21 19:05:15,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:15,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:15,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 30 transitions. [2021-10-21 19:05:15,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:15,655 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2021-10-21 19:05:15,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 30 transitions. [2021-10-21 19:05:15,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2021-10-21 19:05:15,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.0740740740740742) internal successors, (29), 26 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:15,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 29 transitions. [2021-10-21 19:05:15,657 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-21 19:05:15,657 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-21 19:05:15,657 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-21 19:05:15,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 29 transitions. [2021-10-21 19:05:15,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:15,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:15,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:15,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 1] [2021-10-21 19:05:15,659 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:15,659 INFO L791 eck$LassoCheckResult]: Stem: 1387#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1383#L12-2 assume !!(main_~i~0 < main_~j~0); 1384#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1385#L12-2 assume !!(main_~i~0 < main_~j~0); 1386#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1390#L12-2 assume !!(main_~i~0 < main_~j~0); 1409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1408#L12-2 assume !!(main_~i~0 < main_~j~0); 1407#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1406#L12-2 assume !!(main_~i~0 < main_~j~0); 1405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1404#L12-2 assume !!(main_~i~0 < main_~j~0); 1403#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1402#L12-2 assume !!(main_~i~0 < main_~j~0); 1401#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1400#L12-2 assume !!(main_~i~0 < main_~j~0); 1399#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1398#L12-2 assume !!(main_~i~0 < main_~j~0); 1397#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1396#L12-2 assume !!(main_~i~0 < main_~j~0); 1394#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1393#L12-2 assume !!(main_~i~0 < main_~j~0); 1392#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1391#L12-2 assume !!(main_~i~0 < main_~j~0); 1388#L12 [2021-10-21 19:05:15,659 INFO L793 eck$LassoCheckResult]: Loop: 1388#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1389#L12-2 assume !!(main_~i~0 < main_~j~0); 1392#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1391#L12-2 assume !!(main_~i~0 < main_~j~0); 1388#L12 [2021-10-21 19:05:15,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,660 INFO L82 PathProgramCache]: Analyzing trace with hash 1018673001, now seen corresponding path program 11 times [2021-10-21 19:05:15,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,660 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495063798] [2021-10-21 19:05:15,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,660 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,667 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:15,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,687 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:15,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 9 times [2021-10-21 19:05:15,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,688 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27675706] [2021-10-21 19:05:15,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,688 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,692 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:15,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:15,694 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:15,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:15,694 INFO L82 PathProgramCache]: Analyzing trace with hash 567464865, now seen corresponding path program 11 times [2021-10-21 19:05:15,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:15,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329944118] [2021-10-21 19:05:15,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:15,695 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:15,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:15,808 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:15,808 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:15,808 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329944118] [2021-10-21 19:05:15,808 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329944118] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:15,809 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1141199301] [2021-10-21 19:05:15,809 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:15,809 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:15,809 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:15,815 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:15,833 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-10-21 19:05:15,927 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2021-10-21 19:05:15,928 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:15,928 INFO L263 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 13 conjunts are in the unsatisfiable core [2021-10-21 19:05:15,930 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:16,036 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:16,036 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1141199301] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:16,036 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:16,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2021-10-21 19:05:16,036 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484241845] [2021-10-21 19:05:16,086 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:16,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-10-21 19:05:16,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-10-21 19:05:16,088 INFO L87 Difference]: Start difference. First operand 27 states and 29 transitions. cyclomatic complexity: 3 Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 13 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:16,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:16,129 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2021-10-21 19:05:16,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-10-21 19:05:16,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2021-10-21 19:05:16,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:16,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 30 states and 32 transitions. [2021-10-21 19:05:16,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:16,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:16,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 32 transitions. [2021-10-21 19:05:16,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:16,130 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2021-10-21 19:05:16,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 32 transitions. [2021-10-21 19:05:16,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2021-10-21 19:05:16,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.0689655172413792) internal successors, (31), 28 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:16,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 31 transitions. [2021-10-21 19:05:16,133 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2021-10-21 19:05:16,133 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2021-10-21 19:05:16,133 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-21 19:05:16,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 31 transitions. [2021-10-21 19:05:16,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:16,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:16,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:16,134 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 1] [2021-10-21 19:05:16,134 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:16,134 INFO L791 eck$LassoCheckResult]: Stem: 1545#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1541#L12-2 assume !!(main_~i~0 < main_~j~0); 1542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1543#L12-2 assume !!(main_~i~0 < main_~j~0); 1544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1548#L12-2 assume !!(main_~i~0 < main_~j~0); 1569#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1568#L12-2 assume !!(main_~i~0 < main_~j~0); 1567#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1566#L12-2 assume !!(main_~i~0 < main_~j~0); 1565#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1564#L12-2 assume !!(main_~i~0 < main_~j~0); 1563#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1562#L12-2 assume !!(main_~i~0 < main_~j~0); 1561#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1560#L12-2 assume !!(main_~i~0 < main_~j~0); 1559#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1558#L12-2 assume !!(main_~i~0 < main_~j~0); 1557#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1556#L12-2 assume !!(main_~i~0 < main_~j~0); 1555#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1554#L12-2 assume !!(main_~i~0 < main_~j~0); 1552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1551#L12-2 assume !!(main_~i~0 < main_~j~0); 1550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1549#L12-2 assume !!(main_~i~0 < main_~j~0); 1546#L12 [2021-10-21 19:05:16,134 INFO L793 eck$LassoCheckResult]: Loop: 1546#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1547#L12-2 assume !!(main_~i~0 < main_~j~0); 1550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1549#L12-2 assume !!(main_~i~0 < main_~j~0); 1546#L12 [2021-10-21 19:05:16,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,135 INFO L82 PathProgramCache]: Analyzing trace with hash -307789114, now seen corresponding path program 12 times [2021-10-21 19:05:16,135 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,135 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865211898] [2021-10-21 19:05:16,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,135 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,141 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:16,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,158 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:16,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,159 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 10 times [2021-10-21 19:05:16,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,159 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949334] [2021-10-21 19:05:16,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,160 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,163 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:16,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,165 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:16,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,166 INFO L82 PathProgramCache]: Analyzing trace with hash -184309634, now seen corresponding path program 12 times [2021-10-21 19:05:16,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,167 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942180038] [2021-10-21 19:05:16,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,167 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:16,316 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:16,316 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:16,316 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942180038] [2021-10-21 19:05:16,316 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942180038] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:16,317 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [803227446] [2021-10-21 19:05:16,317 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:16,317 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:16,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:16,319 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:16,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-10-21 19:05:16,438 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2021-10-21 19:05:16,438 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:16,439 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-21 19:05:16,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:16,552 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:16,552 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [803227446] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:16,552 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:16,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2021-10-21 19:05:16,553 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230985348] [2021-10-21 19:05:16,597 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:16,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-10-21 19:05:16,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-10-21 19:05:16,598 INFO L87 Difference]: Start difference. First operand 29 states and 31 transitions. cyclomatic complexity: 3 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 14 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:16,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:16,642 INFO L93 Difference]: Finished difference Result 33 states and 35 transitions. [2021-10-21 19:05:16,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-10-21 19:05:16,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 35 transitions. [2021-10-21 19:05:16,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:16,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 32 states and 34 transitions. [2021-10-21 19:05:16,644 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:16,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:16,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 34 transitions. [2021-10-21 19:05:16,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:16,645 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 34 transitions. [2021-10-21 19:05:16,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 34 transitions. [2021-10-21 19:05:16,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 31. [2021-10-21 19:05:16,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.064516129032258) internal successors, (33), 30 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:16,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2021-10-21 19:05:16,657 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2021-10-21 19:05:16,657 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2021-10-21 19:05:16,657 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-21 19:05:16,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2021-10-21 19:05:16,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:16,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:16,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:16,662 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 13, 1] [2021-10-21 19:05:16,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:16,663 INFO L791 eck$LassoCheckResult]: Stem: 1714#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1710#L12-2 assume !!(main_~i~0 < main_~j~0); 1711#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1712#L12-2 assume !!(main_~i~0 < main_~j~0); 1713#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1717#L12-2 assume !!(main_~i~0 < main_~j~0); 1740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1739#L12-2 assume !!(main_~i~0 < main_~j~0); 1738#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1737#L12-2 assume !!(main_~i~0 < main_~j~0); 1736#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1735#L12-2 assume !!(main_~i~0 < main_~j~0); 1734#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1733#L12-2 assume !!(main_~i~0 < main_~j~0); 1732#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1731#L12-2 assume !!(main_~i~0 < main_~j~0); 1730#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1729#L12-2 assume !!(main_~i~0 < main_~j~0); 1728#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1727#L12-2 assume !!(main_~i~0 < main_~j~0); 1726#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1725#L12-2 assume !!(main_~i~0 < main_~j~0); 1724#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1723#L12-2 assume !!(main_~i~0 < main_~j~0); 1721#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1720#L12-2 assume !!(main_~i~0 < main_~j~0); 1719#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1718#L12-2 assume !!(main_~i~0 < main_~j~0); 1715#L12 [2021-10-21 19:05:16,663 INFO L793 eck$LassoCheckResult]: Loop: 1715#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1716#L12-2 assume !!(main_~i~0 < main_~j~0); 1719#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1718#L12-2 assume !!(main_~i~0 < main_~j~0); 1715#L12 [2021-10-21 19:05:16,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,664 INFO L82 PathProgramCache]: Analyzing trace with hash 567405283, now seen corresponding path program 13 times [2021-10-21 19:05:16,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916757700] [2021-10-21 19:05:16,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,664 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,674 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:16,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,684 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:16,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,684 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 11 times [2021-10-21 19:05:16,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,685 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99836915] [2021-10-21 19:05:16,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,685 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,689 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:16,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:16,692 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:16,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:16,692 INFO L82 PathProgramCache]: Analyzing trace with hash -1085097445, now seen corresponding path program 13 times [2021-10-21 19:05:16,693 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:16,693 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127392290] [2021-10-21 19:05:16,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:16,693 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:16,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:16,834 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:16,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:16,834 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127392290] [2021-10-21 19:05:16,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127392290] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:16,835 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1672809008] [2021-10-21 19:05:16,835 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:16,835 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:16,835 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:16,838 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:16,839 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-10-21 19:05:16,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:16,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-21 19:05:16,953 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:17,061 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:17,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1672809008] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:17,062 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:17,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2021-10-21 19:05:17,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522284809] [2021-10-21 19:05:17,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:17,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-10-21 19:05:17,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-10-21 19:05:17,110 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 3 Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 15 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:17,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:17,164 INFO L93 Difference]: Finished difference Result 35 states and 37 transitions. [2021-10-21 19:05:17,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-10-21 19:05:17,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 37 transitions. [2021-10-21 19:05:17,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:17,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 34 states and 36 transitions. [2021-10-21 19:05:17,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:17,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:17,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 36 transitions. [2021-10-21 19:05:17,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:17,166 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 36 transitions. [2021-10-21 19:05:17,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 36 transitions. [2021-10-21 19:05:17,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2021-10-21 19:05:17,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.0606060606060606) internal successors, (35), 32 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:17,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2021-10-21 19:05:17,168 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-21 19:05:17,168 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-21 19:05:17,168 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-21 19:05:17,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 35 transitions. [2021-10-21 19:05:17,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:17,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:17,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:17,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 14, 1] [2021-10-21 19:05:17,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:17,170 INFO L791 eck$LassoCheckResult]: Stem: 1894#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1890#L12-2 assume !!(main_~i~0 < main_~j~0); 1891#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1892#L12-2 assume !!(main_~i~0 < main_~j~0); 1893#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1897#L12-2 assume !!(main_~i~0 < main_~j~0); 1922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1921#L12-2 assume !!(main_~i~0 < main_~j~0); 1920#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1919#L12-2 assume !!(main_~i~0 < main_~j~0); 1918#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1917#L12-2 assume !!(main_~i~0 < main_~j~0); 1916#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1915#L12-2 assume !!(main_~i~0 < main_~j~0); 1914#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1913#L12-2 assume !!(main_~i~0 < main_~j~0); 1912#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1911#L12-2 assume !!(main_~i~0 < main_~j~0); 1910#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1909#L12-2 assume !!(main_~i~0 < main_~j~0); 1908#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1907#L12-2 assume !!(main_~i~0 < main_~j~0); 1906#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1905#L12-2 assume !!(main_~i~0 < main_~j~0); 1904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1903#L12-2 assume !!(main_~i~0 < main_~j~0); 1901#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1900#L12-2 assume !!(main_~i~0 < main_~j~0); 1899#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1898#L12-2 assume !!(main_~i~0 < main_~j~0); 1895#L12 [2021-10-21 19:05:17,170 INFO L793 eck$LassoCheckResult]: Loop: 1895#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1896#L12-2 assume !!(main_~i~0 < main_~j~0); 1899#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1898#L12-2 assume !!(main_~i~0 < main_~j~0); 1895#L12 [2021-10-21 19:05:17,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,170 INFO L82 PathProgramCache]: Analyzing trace with hash -184369216, now seen corresponding path program 14 times [2021-10-21 19:05:17,170 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,170 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622128538] [2021-10-21 19:05:17,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,171 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,179 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:17,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,188 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:17,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,188 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 12 times [2021-10-21 19:05:17,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,189 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918636417] [2021-10-21 19:05:17,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,189 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,192 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:17,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,194 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:17,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,195 INFO L82 PathProgramCache]: Analyzing trace with hash 841209976, now seen corresponding path program 14 times [2021-10-21 19:05:17,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,195 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400250477] [2021-10-21 19:05:17,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,196 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:17,361 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:17,362 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:17,362 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400250477] [2021-10-21 19:05:17,362 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400250477] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:17,362 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1955274059] [2021-10-21 19:05:17,363 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:17,363 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:17,363 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:17,374 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:17,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-10-21 19:05:17,516 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:17,516 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:17,517 INFO L263 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 16 conjunts are in the unsatisfiable core [2021-10-21 19:05:17,518 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:17,651 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:17,651 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1955274059] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:17,651 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:17,652 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2021-10-21 19:05:17,652 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611904794] [2021-10-21 19:05:17,703 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:17,703 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-10-21 19:05:17,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-10-21 19:05:17,704 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. cyclomatic complexity: 3 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 16 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:17,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:17,760 INFO L93 Difference]: Finished difference Result 37 states and 39 transitions. [2021-10-21 19:05:17,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-10-21 19:05:17,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 39 transitions. [2021-10-21 19:05:17,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:17,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 36 states and 38 transitions. [2021-10-21 19:05:17,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:17,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:17,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 38 transitions. [2021-10-21 19:05:17,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:17,763 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2021-10-21 19:05:17,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 38 transitions. [2021-10-21 19:05:17,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2021-10-21 19:05:17,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.0571428571428572) internal successors, (37), 34 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:17,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 37 transitions. [2021-10-21 19:05:17,765 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2021-10-21 19:05:17,765 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2021-10-21 19:05:17,765 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-21 19:05:17,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 37 transitions. [2021-10-21 19:05:17,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:17,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:17,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:17,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 15, 1] [2021-10-21 19:05:17,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:17,766 INFO L791 eck$LassoCheckResult]: Stem: 2085#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2081#L12-2 assume !!(main_~i~0 < main_~j~0); 2082#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2083#L12-2 assume !!(main_~i~0 < main_~j~0); 2084#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2088#L12-2 assume !!(main_~i~0 < main_~j~0); 2115#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2114#L12-2 assume !!(main_~i~0 < main_~j~0); 2113#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2112#L12-2 assume !!(main_~i~0 < main_~j~0); 2111#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2110#L12-2 assume !!(main_~i~0 < main_~j~0); 2109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2108#L12-2 assume !!(main_~i~0 < main_~j~0); 2107#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2106#L12-2 assume !!(main_~i~0 < main_~j~0); 2105#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2104#L12-2 assume !!(main_~i~0 < main_~j~0); 2103#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2102#L12-2 assume !!(main_~i~0 < main_~j~0); 2101#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2100#L12-2 assume !!(main_~i~0 < main_~j~0); 2099#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2098#L12-2 assume !!(main_~i~0 < main_~j~0); 2097#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2096#L12-2 assume !!(main_~i~0 < main_~j~0); 2095#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2094#L12-2 assume !!(main_~i~0 < main_~j~0); 2092#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2091#L12-2 assume !!(main_~i~0 < main_~j~0); 2090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2089#L12-2 assume !!(main_~i~0 < main_~j~0); 2086#L12 [2021-10-21 19:05:17,766 INFO L793 eck$LassoCheckResult]: Loop: 2086#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2087#L12-2 assume !!(main_~i~0 < main_~j~0); 2090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2089#L12-2 assume !!(main_~i~0 < main_~j~0); 2086#L12 [2021-10-21 19:05:17,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1085157027, now seen corresponding path program 15 times [2021-10-21 19:05:17,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406408814] [2021-10-21 19:05:17,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,768 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,778 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:17,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,787 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:17,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 13 times [2021-10-21 19:05:17,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,788 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016945161] [2021-10-21 19:05:17,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,788 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,791 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:17,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:17,793 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:17,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:17,794 INFO L82 PathProgramCache]: Analyzing trace with hash 891736981, now seen corresponding path program 15 times [2021-10-21 19:05:17,794 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:17,794 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453188356] [2021-10-21 19:05:17,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:17,794 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:17,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:17,973 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:17,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:17,974 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453188356] [2021-10-21 19:05:17,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453188356] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:17,987 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [529520610] [2021-10-21 19:05:17,987 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:17,987 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:17,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:17,989 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:17,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-10-21 19:05:18,166 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2021-10-21 19:05:18,167 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:18,168 INFO L263 TraceCheckSpWp]: Trace formula consists of 109 conjuncts, 17 conjunts are in the unsatisfiable core [2021-10-21 19:05:18,170 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:18,271 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:18,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [529520610] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:18,272 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:18,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2021-10-21 19:05:18,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599316563] [2021-10-21 19:05:18,314 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:18,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-10-21 19:05:18,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-10-21 19:05:18,315 INFO L87 Difference]: Start difference. First operand 35 states and 37 transitions. cyclomatic complexity: 3 Second operand has 18 states, 18 states have (on average 1.9444444444444444) internal successors, (35), 17 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:18,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:18,365 INFO L93 Difference]: Finished difference Result 39 states and 41 transitions. [2021-10-21 19:05:18,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-10-21 19:05:18,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 41 transitions. [2021-10-21 19:05:18,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:18,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 38 states and 40 transitions. [2021-10-21 19:05:18,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:18,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:18,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 40 transitions. [2021-10-21 19:05:18,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:18,368 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 40 transitions. [2021-10-21 19:05:18,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 40 transitions. [2021-10-21 19:05:18,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 37. [2021-10-21 19:05:18,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.054054054054054) internal successors, (39), 36 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:18,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 39 transitions. [2021-10-21 19:05:18,377 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2021-10-21 19:05:18,377 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2021-10-21 19:05:18,377 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-21 19:05:18,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 39 transitions. [2021-10-21 19:05:18,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:18,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:18,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:18,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 16, 1] [2021-10-21 19:05:18,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:18,379 INFO L791 eck$LassoCheckResult]: Stem: 2287#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2283#L12-2 assume !!(main_~i~0 < main_~j~0); 2284#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2285#L12-2 assume !!(main_~i~0 < main_~j~0); 2286#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2290#L12-2 assume !!(main_~i~0 < main_~j~0); 2319#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2318#L12-2 assume !!(main_~i~0 < main_~j~0); 2317#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2316#L12-2 assume !!(main_~i~0 < main_~j~0); 2315#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2314#L12-2 assume !!(main_~i~0 < main_~j~0); 2313#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2312#L12-2 assume !!(main_~i~0 < main_~j~0); 2311#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2310#L12-2 assume !!(main_~i~0 < main_~j~0); 2309#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2308#L12-2 assume !!(main_~i~0 < main_~j~0); 2307#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2306#L12-2 assume !!(main_~i~0 < main_~j~0); 2305#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2304#L12-2 assume !!(main_~i~0 < main_~j~0); 2303#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2302#L12-2 assume !!(main_~i~0 < main_~j~0); 2301#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2300#L12-2 assume !!(main_~i~0 < main_~j~0); 2299#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2298#L12-2 assume !!(main_~i~0 < main_~j~0); 2297#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2296#L12-2 assume !!(main_~i~0 < main_~j~0); 2294#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2293#L12-2 assume !!(main_~i~0 < main_~j~0); 2292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2291#L12-2 assume !!(main_~i~0 < main_~j~0); 2288#L12 [2021-10-21 19:05:18,379 INFO L793 eck$LassoCheckResult]: Loop: 2288#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2289#L12-2 assume !!(main_~i~0 < main_~j~0); 2292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2291#L12-2 assume !!(main_~i~0 < main_~j~0); 2288#L12 [2021-10-21 19:05:18,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:18,380 INFO L82 PathProgramCache]: Analyzing trace with hash 841150394, now seen corresponding path program 16 times [2021-10-21 19:05:18,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:18,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819393263] [2021-10-21 19:05:18,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:18,381 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:18,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:18,391 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:18,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:18,406 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:18,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:18,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 14 times [2021-10-21 19:05:18,407 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:18,407 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783444373] [2021-10-21 19:05:18,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:18,407 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:18,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:18,411 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:18,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:18,413 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:18,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:18,414 INFO L82 PathProgramCache]: Analyzing trace with hash -2091418766, now seen corresponding path program 16 times [2021-10-21 19:05:18,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:18,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822517127] [2021-10-21 19:05:18,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:18,414 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:18,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:18,607 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:18,607 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:18,607 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822517127] [2021-10-21 19:05:18,607 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822517127] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:18,607 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1758734486] [2021-10-21 19:05:18,608 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:18,608 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:18,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:18,613 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:18,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-10-21 19:05:18,786 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:18,786 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:18,787 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 18 conjunts are in the unsatisfiable core [2021-10-21 19:05:18,789 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:18,925 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:18,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1758734486] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:18,925 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:18,926 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2021-10-21 19:05:18,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413059991] [2021-10-21 19:05:18,969 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:18,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-10-21 19:05:18,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-10-21 19:05:18,970 INFO L87 Difference]: Start difference. First operand 37 states and 39 transitions. cyclomatic complexity: 3 Second operand has 19 states, 19 states have (on average 1.9473684210526316) internal successors, (37), 18 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:19,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:19,022 INFO L93 Difference]: Finished difference Result 41 states and 43 transitions. [2021-10-21 19:05:19,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-10-21 19:05:19,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 43 transitions. [2021-10-21 19:05:19,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:19,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 42 transitions. [2021-10-21 19:05:19,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:19,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:19,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 42 transitions. [2021-10-21 19:05:19,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:19,025 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 42 transitions. [2021-10-21 19:05:19,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 42 transitions. [2021-10-21 19:05:19,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2021-10-21 19:05:19,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.0512820512820513) internal successors, (41), 38 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:19,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 41 transitions. [2021-10-21 19:05:19,027 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-21 19:05:19,027 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-21 19:05:19,027 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-21 19:05:19,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 41 transitions. [2021-10-21 19:05:19,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:19,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:19,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:19,029 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 17, 1] [2021-10-21 19:05:19,029 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:19,029 INFO L791 eck$LassoCheckResult]: Stem: 2500#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2496#L12-2 assume !!(main_~i~0 < main_~j~0); 2497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2498#L12-2 assume !!(main_~i~0 < main_~j~0); 2499#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2503#L12-2 assume !!(main_~i~0 < main_~j~0); 2534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2533#L12-2 assume !!(main_~i~0 < main_~j~0); 2532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2531#L12-2 assume !!(main_~i~0 < main_~j~0); 2530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2529#L12-2 assume !!(main_~i~0 < main_~j~0); 2528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2527#L12-2 assume !!(main_~i~0 < main_~j~0); 2526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2525#L12-2 assume !!(main_~i~0 < main_~j~0); 2524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2523#L12-2 assume !!(main_~i~0 < main_~j~0); 2522#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2521#L12-2 assume !!(main_~i~0 < main_~j~0); 2520#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2519#L12-2 assume !!(main_~i~0 < main_~j~0); 2518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2517#L12-2 assume !!(main_~i~0 < main_~j~0); 2516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2515#L12-2 assume !!(main_~i~0 < main_~j~0); 2514#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2513#L12-2 assume !!(main_~i~0 < main_~j~0); 2512#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2511#L12-2 assume !!(main_~i~0 < main_~j~0); 2510#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2509#L12-2 assume !!(main_~i~0 < main_~j~0); 2507#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2506#L12-2 assume !!(main_~i~0 < main_~j~0); 2505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2504#L12-2 assume !!(main_~i~0 < main_~j~0); 2501#L12 [2021-10-21 19:05:19,029 INFO L793 eck$LassoCheckResult]: Loop: 2501#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2502#L12-2 assume !!(main_~i~0 < main_~j~0); 2505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2504#L12-2 assume !!(main_~i~0 < main_~j~0); 2501#L12 [2021-10-21 19:05:19,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,030 INFO L82 PathProgramCache]: Analyzing trace with hash 891677399, now seen corresponding path program 17 times [2021-10-21 19:05:19,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,030 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240567969] [2021-10-21 19:05:19,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,030 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,041 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:19,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,051 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:19,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,051 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 15 times [2021-10-21 19:05:19,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,052 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359649640] [2021-10-21 19:05:19,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,052 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,055 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:19,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,057 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:19,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,058 INFO L82 PathProgramCache]: Analyzing trace with hash 134062095, now seen corresponding path program 17 times [2021-10-21 19:05:19,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,058 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654405525] [2021-10-21 19:05:19,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,058 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:19,274 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:19,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:19,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1654405525] [2021-10-21 19:05:19,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1654405525] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:19,275 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1271435931] [2021-10-21 19:05:19,275 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:19,275 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:19,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:19,278 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:19,279 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-10-21 19:05:19,442 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2021-10-21 19:05:19,442 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:19,443 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-21 19:05:19,444 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:19,572 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:19,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1271435931] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:19,573 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:19,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2021-10-21 19:05:19,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558123981] [2021-10-21 19:05:19,633 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:19,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-10-21 19:05:19,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-10-21 19:05:19,636 INFO L87 Difference]: Start difference. First operand 39 states and 41 transitions. cyclomatic complexity: 3 Second operand has 20 states, 20 states have (on average 1.95) internal successors, (39), 19 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:19,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:19,687 INFO L93 Difference]: Finished difference Result 43 states and 45 transitions. [2021-10-21 19:05:19,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-10-21 19:05:19,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 45 transitions. [2021-10-21 19:05:19,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:19,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 44 transitions. [2021-10-21 19:05:19,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:19,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:19,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 44 transitions. [2021-10-21 19:05:19,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:19,690 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2021-10-21 19:05:19,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 44 transitions. [2021-10-21 19:05:19,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2021-10-21 19:05:19,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.048780487804878) internal successors, (43), 40 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:19,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 43 transitions. [2021-10-21 19:05:19,692 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2021-10-21 19:05:19,692 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2021-10-21 19:05:19,693 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-21 19:05:19,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 43 transitions. [2021-10-21 19:05:19,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:19,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:19,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:19,694 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 18, 1] [2021-10-21 19:05:19,694 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:19,695 INFO L791 eck$LassoCheckResult]: Stem: 2724#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2720#L12-2 assume !!(main_~i~0 < main_~j~0); 2721#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2722#L12-2 assume !!(main_~i~0 < main_~j~0); 2723#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2727#L12-2 assume !!(main_~i~0 < main_~j~0); 2760#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2759#L12-2 assume !!(main_~i~0 < main_~j~0); 2758#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2757#L12-2 assume !!(main_~i~0 < main_~j~0); 2756#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2755#L12-2 assume !!(main_~i~0 < main_~j~0); 2754#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2753#L12-2 assume !!(main_~i~0 < main_~j~0); 2752#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2751#L12-2 assume !!(main_~i~0 < main_~j~0); 2750#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2749#L12-2 assume !!(main_~i~0 < main_~j~0); 2748#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2747#L12-2 assume !!(main_~i~0 < main_~j~0); 2746#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2745#L12-2 assume !!(main_~i~0 < main_~j~0); 2744#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2743#L12-2 assume !!(main_~i~0 < main_~j~0); 2742#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2741#L12-2 assume !!(main_~i~0 < main_~j~0); 2740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2739#L12-2 assume !!(main_~i~0 < main_~j~0); 2738#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2737#L12-2 assume !!(main_~i~0 < main_~j~0); 2736#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2735#L12-2 assume !!(main_~i~0 < main_~j~0); 2734#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2733#L12-2 assume !!(main_~i~0 < main_~j~0); 2731#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2730#L12-2 assume !!(main_~i~0 < main_~j~0); 2729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2728#L12-2 assume !!(main_~i~0 < main_~j~0); 2725#L12 [2021-10-21 19:05:19,695 INFO L793 eck$LassoCheckResult]: Loop: 2725#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2726#L12-2 assume !!(main_~i~0 < main_~j~0); 2729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2728#L12-2 assume !!(main_~i~0 < main_~j~0); 2725#L12 [2021-10-21 19:05:19,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,695 INFO L82 PathProgramCache]: Analyzing trace with hash -2091478348, now seen corresponding path program 18 times [2021-10-21 19:05:19,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,696 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866338427] [2021-10-21 19:05:19,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,696 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,709 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:19,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,721 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:19,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,721 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 16 times [2021-10-21 19:05:19,721 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910439529] [2021-10-21 19:05:19,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,722 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,725 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:19,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:19,727 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:19,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:19,728 INFO L82 PathProgramCache]: Analyzing trace with hash -72543892, now seen corresponding path program 18 times [2021-10-21 19:05:19,728 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:19,728 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808743054] [2021-10-21 19:05:19,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:19,728 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:19,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:19,949 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:19,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:19,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808743054] [2021-10-21 19:05:19,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808743054] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:19,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1060563667] [2021-10-21 19:05:19,950 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:19,950 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:19,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:19,951 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:19,952 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-10-21 19:05:20,120 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2021-10-21 19:05:20,120 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:20,121 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-21 19:05:20,122 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:20,272 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:20,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1060563667] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:20,273 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:20,273 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2021-10-21 19:05:20,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705386578] [2021-10-21 19:05:20,321 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:20,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-21 19:05:20,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-10-21 19:05:20,322 INFO L87 Difference]: Start difference. First operand 41 states and 43 transitions. cyclomatic complexity: 3 Second operand has 21 states, 21 states have (on average 1.9523809523809523) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:20,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:20,378 INFO L93 Difference]: Finished difference Result 45 states and 47 transitions. [2021-10-21 19:05:20,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-10-21 19:05:20,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 47 transitions. [2021-10-21 19:05:20,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:20,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 46 transitions. [2021-10-21 19:05:20,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:20,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:20,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 46 transitions. [2021-10-21 19:05:20,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:20,382 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 46 transitions. [2021-10-21 19:05:20,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 46 transitions. [2021-10-21 19:05:20,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2021-10-21 19:05:20,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.0465116279069768) internal successors, (45), 42 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:20,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 45 transitions. [2021-10-21 19:05:20,384 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2021-10-21 19:05:20,384 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2021-10-21 19:05:20,384 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-21 19:05:20,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 45 transitions. [2021-10-21 19:05:20,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:20,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:20,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:20,385 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 19, 1] [2021-10-21 19:05:20,385 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:20,386 INFO L791 eck$LassoCheckResult]: Stem: 2959#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2955#L12-2 assume !!(main_~i~0 < main_~j~0); 2956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2957#L12-2 assume !!(main_~i~0 < main_~j~0); 2958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2962#L12-2 assume !!(main_~i~0 < main_~j~0); 2997#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2996#L12-2 assume !!(main_~i~0 < main_~j~0); 2995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2994#L12-2 assume !!(main_~i~0 < main_~j~0); 2993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2992#L12-2 assume !!(main_~i~0 < main_~j~0); 2991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2990#L12-2 assume !!(main_~i~0 < main_~j~0); 2989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2988#L12-2 assume !!(main_~i~0 < main_~j~0); 2987#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2986#L12-2 assume !!(main_~i~0 < main_~j~0); 2985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2984#L12-2 assume !!(main_~i~0 < main_~j~0); 2983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2982#L12-2 assume !!(main_~i~0 < main_~j~0); 2981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2980#L12-2 assume !!(main_~i~0 < main_~j~0); 2979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2978#L12-2 assume !!(main_~i~0 < main_~j~0); 2977#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2976#L12-2 assume !!(main_~i~0 < main_~j~0); 2975#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2974#L12-2 assume !!(main_~i~0 < main_~j~0); 2973#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2972#L12-2 assume !!(main_~i~0 < main_~j~0); 2971#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2970#L12-2 assume !!(main_~i~0 < main_~j~0); 2969#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2968#L12-2 assume !!(main_~i~0 < main_~j~0); 2966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2965#L12-2 assume !!(main_~i~0 < main_~j~0); 2964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2963#L12-2 assume !!(main_~i~0 < main_~j~0); 2960#L12 [2021-10-21 19:05:20,386 INFO L793 eck$LassoCheckResult]: Loop: 2960#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2961#L12-2 assume !!(main_~i~0 < main_~j~0); 2964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2963#L12-2 assume !!(main_~i~0 < main_~j~0); 2960#L12 [2021-10-21 19:05:20,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:20,386 INFO L82 PathProgramCache]: Analyzing trace with hash 134002513, now seen corresponding path program 19 times [2021-10-21 19:05:20,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:20,386 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955396835] [2021-10-21 19:05:20,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:20,387 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:20,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:20,416 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:20,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:20,431 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:20,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:20,433 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 17 times [2021-10-21 19:05:20,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:20,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462698925] [2021-10-21 19:05:20,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:20,434 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:20,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:20,439 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:20,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:20,441 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:20,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:20,442 INFO L82 PathProgramCache]: Analyzing trace with hash -1052401783, now seen corresponding path program 19 times [2021-10-21 19:05:20,442 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:20,442 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694021142] [2021-10-21 19:05:20,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:20,442 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:20,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:20,715 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:20,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:20,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694021142] [2021-10-21 19:05:20,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694021142] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:20,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1995115743] [2021-10-21 19:05:20,715 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:20,716 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:20,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:20,718 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:20,734 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-10-21 19:05:20,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:20,925 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 21 conjunts are in the unsatisfiable core [2021-10-21 19:05:20,926 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:21,084 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:21,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1995115743] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:21,084 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:21,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2021-10-21 19:05:21,085 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279713990] [2021-10-21 19:05:21,129 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:21,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-10-21 19:05:21,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-10-21 19:05:21,131 INFO L87 Difference]: Start difference. First operand 43 states and 45 transitions. cyclomatic complexity: 3 Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 21 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:21,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:21,182 INFO L93 Difference]: Finished difference Result 47 states and 49 transitions. [2021-10-21 19:05:21,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-10-21 19:05:21,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 49 transitions. [2021-10-21 19:05:21,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:21,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 46 states and 48 transitions. [2021-10-21 19:05:21,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:21,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:21,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 48 transitions. [2021-10-21 19:05:21,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:21,184 INFO L681 BuchiCegarLoop]: Abstraction has 46 states and 48 transitions. [2021-10-21 19:05:21,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 48 transitions. [2021-10-21 19:05:21,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2021-10-21 19:05:21,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0444444444444445) internal successors, (47), 44 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:21,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2021-10-21 19:05:21,186 INFO L704 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2021-10-21 19:05:21,186 INFO L587 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2021-10-21 19:05:21,186 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-21 19:05:21,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 47 transitions. [2021-10-21 19:05:21,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:21,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:21,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:21,187 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 20, 1] [2021-10-21 19:05:21,188 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:21,188 INFO L791 eck$LassoCheckResult]: Stem: 3205#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3201#L12-2 assume !!(main_~i~0 < main_~j~0); 3202#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3203#L12-2 assume !!(main_~i~0 < main_~j~0); 3204#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3208#L12-2 assume !!(main_~i~0 < main_~j~0); 3245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3244#L12-2 assume !!(main_~i~0 < main_~j~0); 3243#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3242#L12-2 assume !!(main_~i~0 < main_~j~0); 3241#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3240#L12-2 assume !!(main_~i~0 < main_~j~0); 3239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3238#L12-2 assume !!(main_~i~0 < main_~j~0); 3237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3236#L12-2 assume !!(main_~i~0 < main_~j~0); 3235#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3234#L12-2 assume !!(main_~i~0 < main_~j~0); 3233#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3232#L12-2 assume !!(main_~i~0 < main_~j~0); 3231#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3230#L12-2 assume !!(main_~i~0 < main_~j~0); 3229#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3228#L12-2 assume !!(main_~i~0 < main_~j~0); 3227#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3226#L12-2 assume !!(main_~i~0 < main_~j~0); 3225#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3224#L12-2 assume !!(main_~i~0 < main_~j~0); 3223#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3222#L12-2 assume !!(main_~i~0 < main_~j~0); 3221#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3220#L12-2 assume !!(main_~i~0 < main_~j~0); 3219#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3218#L12-2 assume !!(main_~i~0 < main_~j~0); 3217#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3216#L12-2 assume !!(main_~i~0 < main_~j~0); 3215#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3214#L12-2 assume !!(main_~i~0 < main_~j~0); 3212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3211#L12-2 assume !!(main_~i~0 < main_~j~0); 3210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3209#L12-2 assume !!(main_~i~0 < main_~j~0); 3206#L12 [2021-10-21 19:05:21,188 INFO L793 eck$LassoCheckResult]: Loop: 3206#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3207#L12-2 assume !!(main_~i~0 < main_~j~0); 3210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3209#L12-2 assume !!(main_~i~0 < main_~j~0); 3206#L12 [2021-10-21 19:05:21,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:21,188 INFO L82 PathProgramCache]: Analyzing trace with hash -72603474, now seen corresponding path program 20 times [2021-10-21 19:05:21,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:21,188 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195997097] [2021-10-21 19:05:21,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:21,189 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:21,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:21,207 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:21,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:21,219 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:21,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:21,219 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 18 times [2021-10-21 19:05:21,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:21,220 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819825036] [2021-10-21 19:05:21,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:21,220 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:21,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:21,224 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:21,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:21,226 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:21,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:21,226 INFO L82 PathProgramCache]: Analyzing trace with hash -2097997210, now seen corresponding path program 20 times [2021-10-21 19:05:21,227 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:21,227 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [208096669] [2021-10-21 19:05:21,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:21,227 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:21,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:21,540 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:21,540 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:21,540 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [208096669] [2021-10-21 19:05:21,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [208096669] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:21,540 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1423387469] [2021-10-21 19:05:21,541 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:21,541 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:21,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:21,547 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:21,562 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-10-21 19:05:21,765 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:21,765 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:21,767 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-21 19:05:21,768 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:21,956 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:21,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1423387469] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:21,957 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:21,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2021-10-21 19:05:21,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472968836] [2021-10-21 19:05:22,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:22,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-10-21 19:05:22,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-10-21 19:05:22,005 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. cyclomatic complexity: 3 Second operand has 23 states, 23 states have (on average 1.9565217391304348) internal successors, (45), 22 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:22,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:22,062 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2021-10-21 19:05:22,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-10-21 19:05:22,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 51 transitions. [2021-10-21 19:05:22,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:22,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 48 states and 50 transitions. [2021-10-21 19:05:22,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:22,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:22,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 50 transitions. [2021-10-21 19:05:22,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:22,064 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 50 transitions. [2021-10-21 19:05:22,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 50 transitions. [2021-10-21 19:05:22,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 47. [2021-10-21 19:05:22,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0425531914893618) internal successors, (49), 46 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:22,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2021-10-21 19:05:22,066 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2021-10-21 19:05:22,066 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2021-10-21 19:05:22,066 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-21 19:05:22,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2021-10-21 19:05:22,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:22,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:22,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:22,068 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 21, 1] [2021-10-21 19:05:22,068 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:22,068 INFO L791 eck$LassoCheckResult]: Stem: 3462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3458#L12-2 assume !!(main_~i~0 < main_~j~0); 3459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3460#L12-2 assume !!(main_~i~0 < main_~j~0); 3461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3465#L12-2 assume !!(main_~i~0 < main_~j~0); 3504#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3503#L12-2 assume !!(main_~i~0 < main_~j~0); 3502#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3501#L12-2 assume !!(main_~i~0 < main_~j~0); 3500#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3499#L12-2 assume !!(main_~i~0 < main_~j~0); 3498#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3497#L12-2 assume !!(main_~i~0 < main_~j~0); 3496#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3495#L12-2 assume !!(main_~i~0 < main_~j~0); 3494#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3493#L12-2 assume !!(main_~i~0 < main_~j~0); 3492#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3491#L12-2 assume !!(main_~i~0 < main_~j~0); 3490#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3489#L12-2 assume !!(main_~i~0 < main_~j~0); 3488#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3487#L12-2 assume !!(main_~i~0 < main_~j~0); 3486#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3485#L12-2 assume !!(main_~i~0 < main_~j~0); 3484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3483#L12-2 assume !!(main_~i~0 < main_~j~0); 3482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3481#L12-2 assume !!(main_~i~0 < main_~j~0); 3480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3479#L12-2 assume !!(main_~i~0 < main_~j~0); 3478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3477#L12-2 assume !!(main_~i~0 < main_~j~0); 3476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3475#L12-2 assume !!(main_~i~0 < main_~j~0); 3474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3473#L12-2 assume !!(main_~i~0 < main_~j~0); 3472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3471#L12-2 assume !!(main_~i~0 < main_~j~0); 3469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3468#L12-2 assume !!(main_~i~0 < main_~j~0); 3467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3466#L12-2 assume !!(main_~i~0 < main_~j~0); 3463#L12 [2021-10-21 19:05:22,068 INFO L793 eck$LassoCheckResult]: Loop: 3463#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3464#L12-2 assume !!(main_~i~0 < main_~j~0); 3467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3466#L12-2 assume !!(main_~i~0 < main_~j~0); 3463#L12 [2021-10-21 19:05:22,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:22,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1052461365, now seen corresponding path program 21 times [2021-10-21 19:05:22,069 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:22,069 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615000253] [2021-10-21 19:05:22,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:22,074 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:22,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:22,088 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:22,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:22,102 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:22,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:22,102 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 19 times [2021-10-21 19:05:22,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:22,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440659399] [2021-10-21 19:05:22,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:22,103 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:22,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:22,109 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:22,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:22,111 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:22,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:22,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1892855293, now seen corresponding path program 21 times [2021-10-21 19:05:22,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:22,112 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191482148] [2021-10-21 19:05:22,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:22,112 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:22,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:22,391 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:22,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:22,392 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191482148] [2021-10-21 19:05:22,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191482148] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:22,392 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1318517341] [2021-10-21 19:05:22,392 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:22,392 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:22,392 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:22,393 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:22,413 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-10-21 19:05:22,633 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2021-10-21 19:05:22,633 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:22,635 INFO L263 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 23 conjunts are in the unsatisfiable core [2021-10-21 19:05:22,636 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:22,894 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:22,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1318517341] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:22,895 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:22,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2021-10-21 19:05:22,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508542057] [2021-10-21 19:05:22,945 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:22,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-10-21 19:05:22,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-10-21 19:05:22,947 INFO L87 Difference]: Start difference. First operand 47 states and 49 transitions. cyclomatic complexity: 3 Second operand has 24 states, 24 states have (on average 1.9583333333333333) internal successors, (47), 23 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:23,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:23,005 INFO L93 Difference]: Finished difference Result 51 states and 53 transitions. [2021-10-21 19:05:23,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-10-21 19:05:23,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 53 transitions. [2021-10-21 19:05:23,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:23,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 52 transitions. [2021-10-21 19:05:23,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:23,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:23,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 52 transitions. [2021-10-21 19:05:23,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:23,007 INFO L681 BuchiCegarLoop]: Abstraction has 50 states and 52 transitions. [2021-10-21 19:05:23,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 52 transitions. [2021-10-21 19:05:23,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2021-10-21 19:05:23,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0408163265306123) internal successors, (51), 48 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:23,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2021-10-21 19:05:23,010 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2021-10-21 19:05:23,010 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2021-10-21 19:05:23,010 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-21 19:05:23,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 51 transitions. [2021-10-21 19:05:23,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:23,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:23,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:23,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 22, 1] [2021-10-21 19:05:23,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:23,011 INFO L791 eck$LassoCheckResult]: Stem: 3730#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3726#L12-2 assume !!(main_~i~0 < main_~j~0); 3727#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3728#L12-2 assume !!(main_~i~0 < main_~j~0); 3729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3733#L12-2 assume !!(main_~i~0 < main_~j~0); 3774#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3773#L12-2 assume !!(main_~i~0 < main_~j~0); 3772#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3771#L12-2 assume !!(main_~i~0 < main_~j~0); 3770#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3769#L12-2 assume !!(main_~i~0 < main_~j~0); 3768#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3767#L12-2 assume !!(main_~i~0 < main_~j~0); 3766#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3765#L12-2 assume !!(main_~i~0 < main_~j~0); 3764#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3763#L12-2 assume !!(main_~i~0 < main_~j~0); 3762#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3761#L12-2 assume !!(main_~i~0 < main_~j~0); 3760#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3759#L12-2 assume !!(main_~i~0 < main_~j~0); 3758#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3757#L12-2 assume !!(main_~i~0 < main_~j~0); 3756#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3755#L12-2 assume !!(main_~i~0 < main_~j~0); 3754#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3753#L12-2 assume !!(main_~i~0 < main_~j~0); 3752#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3751#L12-2 assume !!(main_~i~0 < main_~j~0); 3750#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3749#L12-2 assume !!(main_~i~0 < main_~j~0); 3748#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3747#L12-2 assume !!(main_~i~0 < main_~j~0); 3746#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3745#L12-2 assume !!(main_~i~0 < main_~j~0); 3744#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3743#L12-2 assume !!(main_~i~0 < main_~j~0); 3742#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3741#L12-2 assume !!(main_~i~0 < main_~j~0); 3740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3739#L12-2 assume !!(main_~i~0 < main_~j~0); 3737#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3736#L12-2 assume !!(main_~i~0 < main_~j~0); 3735#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3734#L12-2 assume !!(main_~i~0 < main_~j~0); 3731#L12 [2021-10-21 19:05:23,011 INFO L793 eck$LassoCheckResult]: Loop: 3731#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3732#L12-2 assume !!(main_~i~0 < main_~j~0); 3735#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3734#L12-2 assume !!(main_~i~0 < main_~j~0); 3731#L12 [2021-10-21 19:05:23,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:23,012 INFO L82 PathProgramCache]: Analyzing trace with hash -2098056792, now seen corresponding path program 22 times [2021-10-21 19:05:23,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:23,012 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795645871] [2021-10-21 19:05:23,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:23,012 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:23,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:23,038 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:23,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:23,060 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:23,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:23,061 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 20 times [2021-10-21 19:05:23,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:23,061 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22066281] [2021-10-21 19:05:23,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:23,062 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:23,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:23,066 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:23,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:23,068 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:23,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:23,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1974998624, now seen corresponding path program 22 times [2021-10-21 19:05:23,069 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:23,069 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722513071] [2021-10-21 19:05:23,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:23,069 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:23,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:23,387 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:23,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:23,387 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722513071] [2021-10-21 19:05:23,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722513071] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:23,387 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1610302642] [2021-10-21 19:05:23,387 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:23,388 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:23,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:23,394 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:23,412 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-10-21 19:05:23,663 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:23,663 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:23,664 INFO L263 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 24 conjunts are in the unsatisfiable core [2021-10-21 19:05:23,665 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:23,841 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:23,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1610302642] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:23,841 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:23,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2021-10-21 19:05:23,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894401885] [2021-10-21 19:05:23,880 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:23,881 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-10-21 19:05:23,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-10-21 19:05:23,881 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 24 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:23,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:23,947 INFO L93 Difference]: Finished difference Result 53 states and 55 transitions. [2021-10-21 19:05:23,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-10-21 19:05:23,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 55 transitions. [2021-10-21 19:05:23,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:23,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 54 transitions. [2021-10-21 19:05:23,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:23,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:23,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 54 transitions. [2021-10-21 19:05:23,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:23,949 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2021-10-21 19:05:23,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 54 transitions. [2021-10-21 19:05:23,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2021-10-21 19:05:23,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0392156862745099) internal successors, (53), 50 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:23,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 53 transitions. [2021-10-21 19:05:23,951 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2021-10-21 19:05:23,951 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2021-10-21 19:05:23,951 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-10-21 19:05:23,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 53 transitions. [2021-10-21 19:05:23,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:23,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:23,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:23,952 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 1] [2021-10-21 19:05:23,952 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:23,952 INFO L791 eck$LassoCheckResult]: Stem: 4009#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4005#L12-2 assume !!(main_~i~0 < main_~j~0); 4006#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4007#L12-2 assume !!(main_~i~0 < main_~j~0); 4008#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4012#L12-2 assume !!(main_~i~0 < main_~j~0); 4055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4054#L12-2 assume !!(main_~i~0 < main_~j~0); 4053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4052#L12-2 assume !!(main_~i~0 < main_~j~0); 4051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4050#L12-2 assume !!(main_~i~0 < main_~j~0); 4049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4048#L12-2 assume !!(main_~i~0 < main_~j~0); 4047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4046#L12-2 assume !!(main_~i~0 < main_~j~0); 4045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4044#L12-2 assume !!(main_~i~0 < main_~j~0); 4043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4042#L12-2 assume !!(main_~i~0 < main_~j~0); 4041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4040#L12-2 assume !!(main_~i~0 < main_~j~0); 4039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4038#L12-2 assume !!(main_~i~0 < main_~j~0); 4037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4036#L12-2 assume !!(main_~i~0 < main_~j~0); 4035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4034#L12-2 assume !!(main_~i~0 < main_~j~0); 4033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4032#L12-2 assume !!(main_~i~0 < main_~j~0); 4031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4030#L12-2 assume !!(main_~i~0 < main_~j~0); 4029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4028#L12-2 assume !!(main_~i~0 < main_~j~0); 4027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4026#L12-2 assume !!(main_~i~0 < main_~j~0); 4025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4024#L12-2 assume !!(main_~i~0 < main_~j~0); 4023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4022#L12-2 assume !!(main_~i~0 < main_~j~0); 4021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4020#L12-2 assume !!(main_~i~0 < main_~j~0); 4019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4018#L12-2 assume !!(main_~i~0 < main_~j~0); 4016#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4015#L12-2 assume !!(main_~i~0 < main_~j~0); 4014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4013#L12-2 assume !!(main_~i~0 < main_~j~0); 4010#L12 [2021-10-21 19:05:23,952 INFO L793 eck$LassoCheckResult]: Loop: 4010#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4011#L12-2 assume !!(main_~i~0 < main_~j~0); 4014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4013#L12-2 assume !!(main_~i~0 < main_~j~0); 4010#L12 [2021-10-21 19:05:23,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:23,953 INFO L82 PathProgramCache]: Analyzing trace with hash -1892914875, now seen corresponding path program 23 times [2021-10-21 19:05:23,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:23,953 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203117250] [2021-10-21 19:05:23,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:23,953 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:23,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:23,972 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:24,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:24,006 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:24,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:24,007 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 21 times [2021-10-21 19:05:24,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:24,007 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4481958] [2021-10-21 19:05:24,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:24,008 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:24,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:24,030 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:24,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:24,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:24,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:24,032 INFO L82 PathProgramCache]: Analyzing trace with hash -459065475, now seen corresponding path program 23 times [2021-10-21 19:05:24,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:24,033 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221679651] [2021-10-21 19:05:24,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:24,033 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:24,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:24,471 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:24,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:24,471 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221679651] [2021-10-21 19:05:24,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221679651] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:24,472 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1486728090] [2021-10-21 19:05:24,472 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:24,472 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:24,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:24,505 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:24,522 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-10-21 19:05:24,872 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2021-10-21 19:05:24,872 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:24,874 INFO L263 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 25 conjunts are in the unsatisfiable core [2021-10-21 19:05:24,875 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:25,008 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:25,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1486728090] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:25,008 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:25,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2021-10-21 19:05:25,009 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663010494] [2021-10-21 19:05:25,049 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:25,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-10-21 19:05:25,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-10-21 19:05:25,050 INFO L87 Difference]: Start difference. First operand 51 states and 53 transitions. cyclomatic complexity: 3 Second operand has 26 states, 26 states have (on average 1.9615384615384615) internal successors, (51), 25 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:25,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:25,114 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2021-10-21 19:05:25,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-10-21 19:05:25,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2021-10-21 19:05:25,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:25,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 54 states and 56 transitions. [2021-10-21 19:05:25,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:25,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:25,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 56 transitions. [2021-10-21 19:05:25,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:25,117 INFO L681 BuchiCegarLoop]: Abstraction has 54 states and 56 transitions. [2021-10-21 19:05:25,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 56 transitions. [2021-10-21 19:05:25,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 53. [2021-10-21 19:05:25,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.0377358490566038) internal successors, (55), 52 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:25,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 55 transitions. [2021-10-21 19:05:25,119 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2021-10-21 19:05:25,119 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2021-10-21 19:05:25,119 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-10-21 19:05:25,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 55 transitions. [2021-10-21 19:05:25,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:25,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:25,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:25,121 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 24, 1] [2021-10-21 19:05:25,121 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:25,121 INFO L791 eck$LassoCheckResult]: Stem: 4299#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4295#L12-2 assume !!(main_~i~0 < main_~j~0); 4296#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4297#L12-2 assume !!(main_~i~0 < main_~j~0); 4298#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4302#L12-2 assume !!(main_~i~0 < main_~j~0); 4347#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4346#L12-2 assume !!(main_~i~0 < main_~j~0); 4345#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4344#L12-2 assume !!(main_~i~0 < main_~j~0); 4343#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4342#L12-2 assume !!(main_~i~0 < main_~j~0); 4341#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4340#L12-2 assume !!(main_~i~0 < main_~j~0); 4339#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4338#L12-2 assume !!(main_~i~0 < main_~j~0); 4337#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4336#L12-2 assume !!(main_~i~0 < main_~j~0); 4335#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4334#L12-2 assume !!(main_~i~0 < main_~j~0); 4333#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4332#L12-2 assume !!(main_~i~0 < main_~j~0); 4331#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4330#L12-2 assume !!(main_~i~0 < main_~j~0); 4329#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4328#L12-2 assume !!(main_~i~0 < main_~j~0); 4327#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4326#L12-2 assume !!(main_~i~0 < main_~j~0); 4325#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4324#L12-2 assume !!(main_~i~0 < main_~j~0); 4323#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4322#L12-2 assume !!(main_~i~0 < main_~j~0); 4321#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4320#L12-2 assume !!(main_~i~0 < main_~j~0); 4319#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4318#L12-2 assume !!(main_~i~0 < main_~j~0); 4317#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4316#L12-2 assume !!(main_~i~0 < main_~j~0); 4315#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4314#L12-2 assume !!(main_~i~0 < main_~j~0); 4313#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4312#L12-2 assume !!(main_~i~0 < main_~j~0); 4311#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4310#L12-2 assume !!(main_~i~0 < main_~j~0); 4309#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4308#L12-2 assume !!(main_~i~0 < main_~j~0); 4306#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4305#L12-2 assume !!(main_~i~0 < main_~j~0); 4304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4303#L12-2 assume !!(main_~i~0 < main_~j~0); 4300#L12 [2021-10-21 19:05:25,121 INFO L793 eck$LassoCheckResult]: Loop: 4300#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4301#L12-2 assume !!(main_~i~0 < main_~j~0); 4304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4303#L12-2 assume !!(main_~i~0 < main_~j~0); 4300#L12 [2021-10-21 19:05:25,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:25,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1974939042, now seen corresponding path program 24 times [2021-10-21 19:05:25,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:25,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757342338] [2021-10-21 19:05:25,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:25,122 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:25,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:25,163 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:25,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:25,176 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:25,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:25,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 22 times [2021-10-21 19:05:25,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:25,176 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41634588] [2021-10-21 19:05:25,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:25,177 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:25,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:25,181 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:25,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:25,182 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:25,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:25,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1162511706, now seen corresponding path program 24 times [2021-10-21 19:05:25,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:25,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542136204] [2021-10-21 19:05:25,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:25,184 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:25,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:25,518 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:25,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:25,518 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542136204] [2021-10-21 19:05:25,518 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542136204] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:25,518 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1098652321] [2021-10-21 19:05:25,518 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:25,518 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:25,518 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:25,520 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:25,536 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-10-21 19:05:25,834 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 27 check-sat command(s) [2021-10-21 19:05:25,835 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:25,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 26 conjunts are in the unsatisfiable core [2021-10-21 19:05:25,836 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:26,058 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:26,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1098652321] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:26,059 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:26,059 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2021-10-21 19:05:26,059 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107048879] [2021-10-21 19:05:26,100 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:26,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-10-21 19:05:26,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-10-21 19:05:26,102 INFO L87 Difference]: Start difference. First operand 53 states and 55 transitions. cyclomatic complexity: 3 Second operand has 27 states, 27 states have (on average 1.962962962962963) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:26,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:26,204 INFO L93 Difference]: Finished difference Result 57 states and 59 transitions. [2021-10-21 19:05:26,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-10-21 19:05:26,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 59 transitions. [2021-10-21 19:05:26,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:26,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 56 states and 58 transitions. [2021-10-21 19:05:26,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:26,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:26,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 58 transitions. [2021-10-21 19:05:26,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:26,206 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 58 transitions. [2021-10-21 19:05:26,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 58 transitions. [2021-10-21 19:05:26,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 55. [2021-10-21 19:05:26,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.0363636363636364) internal successors, (57), 54 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:26,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2021-10-21 19:05:26,208 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2021-10-21 19:05:26,208 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2021-10-21 19:05:26,208 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-10-21 19:05:26,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2021-10-21 19:05:26,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:26,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:26,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:26,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 25, 1] [2021-10-21 19:05:26,209 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:26,210 INFO L791 eck$LassoCheckResult]: Stem: 4600#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4596#L12-2 assume !!(main_~i~0 < main_~j~0); 4597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4598#L12-2 assume !!(main_~i~0 < main_~j~0); 4599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4603#L12-2 assume !!(main_~i~0 < main_~j~0); 4650#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4649#L12-2 assume !!(main_~i~0 < main_~j~0); 4648#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4647#L12-2 assume !!(main_~i~0 < main_~j~0); 4646#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4645#L12-2 assume !!(main_~i~0 < main_~j~0); 4644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4643#L12-2 assume !!(main_~i~0 < main_~j~0); 4642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4641#L12-2 assume !!(main_~i~0 < main_~j~0); 4640#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4639#L12-2 assume !!(main_~i~0 < main_~j~0); 4638#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4637#L12-2 assume !!(main_~i~0 < main_~j~0); 4636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4635#L12-2 assume !!(main_~i~0 < main_~j~0); 4634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4633#L12-2 assume !!(main_~i~0 < main_~j~0); 4632#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4631#L12-2 assume !!(main_~i~0 < main_~j~0); 4630#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4629#L12-2 assume !!(main_~i~0 < main_~j~0); 4628#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4627#L12-2 assume !!(main_~i~0 < main_~j~0); 4626#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4625#L12-2 assume !!(main_~i~0 < main_~j~0); 4624#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4623#L12-2 assume !!(main_~i~0 < main_~j~0); 4622#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4621#L12-2 assume !!(main_~i~0 < main_~j~0); 4620#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4619#L12-2 assume !!(main_~i~0 < main_~j~0); 4618#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4617#L12-2 assume !!(main_~i~0 < main_~j~0); 4616#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4615#L12-2 assume !!(main_~i~0 < main_~j~0); 4614#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4613#L12-2 assume !!(main_~i~0 < main_~j~0); 4612#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4611#L12-2 assume !!(main_~i~0 < main_~j~0); 4610#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4609#L12-2 assume !!(main_~i~0 < main_~j~0); 4607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4606#L12-2 assume !!(main_~i~0 < main_~j~0); 4605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4604#L12-2 assume !!(main_~i~0 < main_~j~0); 4601#L12 [2021-10-21 19:05:26,210 INFO L793 eck$LassoCheckResult]: Loop: 4601#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4602#L12-2 assume !!(main_~i~0 < main_~j~0); 4605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4604#L12-2 assume !!(main_~i~0 < main_~j~0); 4601#L12 [2021-10-21 19:05:26,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:26,211 INFO L82 PathProgramCache]: Analyzing trace with hash -459125057, now seen corresponding path program 25 times [2021-10-21 19:05:26,211 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:26,211 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140698976] [2021-10-21 19:05:26,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:26,212 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:26,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:26,239 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:26,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:26,262 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:26,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:26,282 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 23 times [2021-10-21 19:05:26,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:26,283 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843251413] [2021-10-21 19:05:26,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:26,283 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:26,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:26,301 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:26,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:26,303 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:26,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:26,304 INFO L82 PathProgramCache]: Analyzing trace with hash 425054199, now seen corresponding path program 25 times [2021-10-21 19:05:26,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:26,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746539601] [2021-10-21 19:05:26,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:26,304 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:26,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:26,718 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:26,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:26,718 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746539601] [2021-10-21 19:05:26,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746539601] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:26,718 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1754835205] [2021-10-21 19:05:26,718 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:26,719 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:26,719 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:26,724 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:26,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-10-21 19:05:26,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:26,997 INFO L263 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 27 conjunts are in the unsatisfiable core [2021-10-21 19:05:26,998 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:27,195 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:27,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1754835205] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:27,195 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:27,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2021-10-21 19:05:27,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489573834] [2021-10-21 19:05:27,230 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:27,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-10-21 19:05:27,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-10-21 19:05:27,232 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 3 Second operand has 28 states, 28 states have (on average 1.9642857142857142) internal successors, (55), 27 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:27,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:27,314 INFO L93 Difference]: Finished difference Result 59 states and 61 transitions. [2021-10-21 19:05:27,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-10-21 19:05:27,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 61 transitions. [2021-10-21 19:05:27,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:27,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 58 states and 60 transitions. [2021-10-21 19:05:27,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:27,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:27,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 60 transitions. [2021-10-21 19:05:27,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:27,317 INFO L681 BuchiCegarLoop]: Abstraction has 58 states and 60 transitions. [2021-10-21 19:05:27,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 60 transitions. [2021-10-21 19:05:27,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2021-10-21 19:05:27,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.0350877192982457) internal successors, (59), 56 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:27,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 59 transitions. [2021-10-21 19:05:27,318 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2021-10-21 19:05:27,319 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2021-10-21 19:05:27,319 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-10-21 19:05:27,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 59 transitions. [2021-10-21 19:05:27,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:27,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:27,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:27,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 26, 1] [2021-10-21 19:05:27,320 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:27,320 INFO L791 eck$LassoCheckResult]: Stem: 4912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4908#L12-2 assume !!(main_~i~0 < main_~j~0); 4909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4910#L12-2 assume !!(main_~i~0 < main_~j~0); 4911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4915#L12-2 assume !!(main_~i~0 < main_~j~0); 4964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4963#L12-2 assume !!(main_~i~0 < main_~j~0); 4962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4961#L12-2 assume !!(main_~i~0 < main_~j~0); 4960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4959#L12-2 assume !!(main_~i~0 < main_~j~0); 4958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4957#L12-2 assume !!(main_~i~0 < main_~j~0); 4956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4955#L12-2 assume !!(main_~i~0 < main_~j~0); 4954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4953#L12-2 assume !!(main_~i~0 < main_~j~0); 4952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4951#L12-2 assume !!(main_~i~0 < main_~j~0); 4950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4949#L12-2 assume !!(main_~i~0 < main_~j~0); 4948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4947#L12-2 assume !!(main_~i~0 < main_~j~0); 4946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4945#L12-2 assume !!(main_~i~0 < main_~j~0); 4944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4943#L12-2 assume !!(main_~i~0 < main_~j~0); 4942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4941#L12-2 assume !!(main_~i~0 < main_~j~0); 4940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4939#L12-2 assume !!(main_~i~0 < main_~j~0); 4938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4937#L12-2 assume !!(main_~i~0 < main_~j~0); 4936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4935#L12-2 assume !!(main_~i~0 < main_~j~0); 4934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4933#L12-2 assume !!(main_~i~0 < main_~j~0); 4932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4931#L12-2 assume !!(main_~i~0 < main_~j~0); 4930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4929#L12-2 assume !!(main_~i~0 < main_~j~0); 4928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4927#L12-2 assume !!(main_~i~0 < main_~j~0); 4926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4925#L12-2 assume !!(main_~i~0 < main_~j~0); 4924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4923#L12-2 assume !!(main_~i~0 < main_~j~0); 4922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4921#L12-2 assume !!(main_~i~0 < main_~j~0); 4919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4918#L12-2 assume !!(main_~i~0 < main_~j~0); 4917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4916#L12-2 assume !!(main_~i~0 < main_~j~0); 4913#L12 [2021-10-21 19:05:27,321 INFO L793 eck$LassoCheckResult]: Loop: 4913#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4914#L12-2 assume !!(main_~i~0 < main_~j~0); 4917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4916#L12-2 assume !!(main_~i~0 < main_~j~0); 4913#L12 [2021-10-21 19:05:27,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:27,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1162452124, now seen corresponding path program 26 times [2021-10-21 19:05:27,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:27,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840313427] [2021-10-21 19:05:27,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:27,321 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:27,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:27,340 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:27,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:27,356 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:27,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:27,356 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 24 times [2021-10-21 19:05:27,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:27,357 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881931105] [2021-10-21 19:05:27,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:27,357 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:27,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:27,364 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:27,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:27,365 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:27,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:27,366 INFO L82 PathProgramCache]: Analyzing trace with hash 397993812, now seen corresponding path program 26 times [2021-10-21 19:05:27,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:27,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455879592] [2021-10-21 19:05:27,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:27,367 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:27,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:27,774 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:27,774 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:27,774 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455879592] [2021-10-21 19:05:27,774 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455879592] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:27,774 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1257715376] [2021-10-21 19:05:27,774 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:27,774 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:27,775 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:27,776 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:27,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-10-21 19:05:28,124 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:28,124 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:28,125 INFO L263 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 28 conjunts are in the unsatisfiable core [2021-10-21 19:05:28,127 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:28,290 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:28,290 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1257715376] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:28,290 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:28,290 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2021-10-21 19:05:28,291 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41885747] [2021-10-21 19:05:28,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:28,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-10-21 19:05:28,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-10-21 19:05:28,325 INFO L87 Difference]: Start difference. First operand 57 states and 59 transitions. cyclomatic complexity: 3 Second operand has 29 states, 29 states have (on average 1.9655172413793103) internal successors, (57), 28 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:28,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:28,426 INFO L93 Difference]: Finished difference Result 61 states and 63 transitions. [2021-10-21 19:05:28,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-10-21 19:05:28,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 63 transitions. [2021-10-21 19:05:28,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:28,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 60 states and 62 transitions. [2021-10-21 19:05:28,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:28,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:28,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 62 transitions. [2021-10-21 19:05:28,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:28,430 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 62 transitions. [2021-10-21 19:05:28,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 62 transitions. [2021-10-21 19:05:28,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 59. [2021-10-21 19:05:28,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.0338983050847457) internal successors, (61), 58 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:28,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 61 transitions. [2021-10-21 19:05:28,432 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2021-10-21 19:05:28,432 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2021-10-21 19:05:28,432 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-10-21 19:05:28,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 61 transitions. [2021-10-21 19:05:28,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:28,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:28,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:28,433 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 1] [2021-10-21 19:05:28,434 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:28,434 INFO L791 eck$LassoCheckResult]: Stem: 5235#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5231#L12-2 assume !!(main_~i~0 < main_~j~0); 5232#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5233#L12-2 assume !!(main_~i~0 < main_~j~0); 5234#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5238#L12-2 assume !!(main_~i~0 < main_~j~0); 5289#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5288#L12-2 assume !!(main_~i~0 < main_~j~0); 5287#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5286#L12-2 assume !!(main_~i~0 < main_~j~0); 5285#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5284#L12-2 assume !!(main_~i~0 < main_~j~0); 5283#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5282#L12-2 assume !!(main_~i~0 < main_~j~0); 5281#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5280#L12-2 assume !!(main_~i~0 < main_~j~0); 5279#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5278#L12-2 assume !!(main_~i~0 < main_~j~0); 5277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5276#L12-2 assume !!(main_~i~0 < main_~j~0); 5275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5274#L12-2 assume !!(main_~i~0 < main_~j~0); 5273#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5272#L12-2 assume !!(main_~i~0 < main_~j~0); 5271#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5270#L12-2 assume !!(main_~i~0 < main_~j~0); 5269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5268#L12-2 assume !!(main_~i~0 < main_~j~0); 5267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5266#L12-2 assume !!(main_~i~0 < main_~j~0); 5265#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5264#L12-2 assume !!(main_~i~0 < main_~j~0); 5263#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5262#L12-2 assume !!(main_~i~0 < main_~j~0); 5261#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5260#L12-2 assume !!(main_~i~0 < main_~j~0); 5259#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5258#L12-2 assume !!(main_~i~0 < main_~j~0); 5257#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5256#L12-2 assume !!(main_~i~0 < main_~j~0); 5255#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5254#L12-2 assume !!(main_~i~0 < main_~j~0); 5253#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5252#L12-2 assume !!(main_~i~0 < main_~j~0); 5251#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5250#L12-2 assume !!(main_~i~0 < main_~j~0); 5249#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5248#L12-2 assume !!(main_~i~0 < main_~j~0); 5247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5246#L12-2 assume !!(main_~i~0 < main_~j~0); 5245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5244#L12-2 assume !!(main_~i~0 < main_~j~0); 5242#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5241#L12-2 assume !!(main_~i~0 < main_~j~0); 5240#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5239#L12-2 assume !!(main_~i~0 < main_~j~0); 5236#L12 [2021-10-21 19:05:28,434 INFO L793 eck$LassoCheckResult]: Loop: 5236#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5237#L12-2 assume !!(main_~i~0 < main_~j~0); 5240#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5239#L12-2 assume !!(main_~i~0 < main_~j~0); 5236#L12 [2021-10-21 19:05:28,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:28,434 INFO L82 PathProgramCache]: Analyzing trace with hash 424994617, now seen corresponding path program 27 times [2021-10-21 19:05:28,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:28,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969082494] [2021-10-21 19:05:28,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:28,435 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:28,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:28,472 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:28,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:28,485 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:28,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:28,486 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 25 times [2021-10-21 19:05:28,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:28,486 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522302112] [2021-10-21 19:05:28,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:28,486 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:28,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:28,491 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:28,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:28,493 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:28,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:28,493 INFO L82 PathProgramCache]: Analyzing trace with hash 162765681, now seen corresponding path program 27 times [2021-10-21 19:05:28,493 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:28,493 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744246605] [2021-10-21 19:05:28,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:28,494 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:28,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:28,894 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:28,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:28,894 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744246605] [2021-10-21 19:05:28,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744246605] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:28,895 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1156564343] [2021-10-21 19:05:28,895 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:28,895 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:28,895 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:28,896 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:28,897 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-10-21 19:05:29,231 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2021-10-21 19:05:29,231 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:29,232 INFO L263 TraceCheckSpWp]: Trace formula consists of 181 conjuncts, 29 conjunts are in the unsatisfiable core [2021-10-21 19:05:29,233 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:29,421 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:29,421 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1156564343] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:29,421 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:29,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2021-10-21 19:05:29,422 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836070000] [2021-10-21 19:05:29,460 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:29,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-10-21 19:05:29,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-10-21 19:05:29,462 INFO L87 Difference]: Start difference. First operand 59 states and 61 transitions. cyclomatic complexity: 3 Second operand has 30 states, 30 states have (on average 1.9666666666666666) internal successors, (59), 29 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:29,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:29,545 INFO L93 Difference]: Finished difference Result 63 states and 65 transitions. [2021-10-21 19:05:29,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-10-21 19:05:29,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 65 transitions. [2021-10-21 19:05:29,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:29,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 62 states and 64 transitions. [2021-10-21 19:05:29,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:29,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:29,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 64 transitions. [2021-10-21 19:05:29,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:29,548 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 64 transitions. [2021-10-21 19:05:29,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 64 transitions. [2021-10-21 19:05:29,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2021-10-21 19:05:29,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.0327868852459017) internal successors, (63), 60 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:29,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 63 transitions. [2021-10-21 19:05:29,550 INFO L704 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2021-10-21 19:05:29,550 INFO L587 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2021-10-21 19:05:29,550 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-10-21 19:05:29,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 63 transitions. [2021-10-21 19:05:29,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:29,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:29,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:29,553 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 28, 1] [2021-10-21 19:05:29,553 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:29,553 INFO L791 eck$LassoCheckResult]: Stem: 5569#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5565#L12-2 assume !!(main_~i~0 < main_~j~0); 5566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5567#L12-2 assume !!(main_~i~0 < main_~j~0); 5568#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5572#L12-2 assume !!(main_~i~0 < main_~j~0); 5625#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5624#L12-2 assume !!(main_~i~0 < main_~j~0); 5623#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5622#L12-2 assume !!(main_~i~0 < main_~j~0); 5621#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5620#L12-2 assume !!(main_~i~0 < main_~j~0); 5619#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5618#L12-2 assume !!(main_~i~0 < main_~j~0); 5617#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5616#L12-2 assume !!(main_~i~0 < main_~j~0); 5615#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5614#L12-2 assume !!(main_~i~0 < main_~j~0); 5613#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5612#L12-2 assume !!(main_~i~0 < main_~j~0); 5611#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5610#L12-2 assume !!(main_~i~0 < main_~j~0); 5609#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5608#L12-2 assume !!(main_~i~0 < main_~j~0); 5607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5606#L12-2 assume !!(main_~i~0 < main_~j~0); 5605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5604#L12-2 assume !!(main_~i~0 < main_~j~0); 5603#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5602#L12-2 assume !!(main_~i~0 < main_~j~0); 5601#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5600#L12-2 assume !!(main_~i~0 < main_~j~0); 5599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5598#L12-2 assume !!(main_~i~0 < main_~j~0); 5597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5596#L12-2 assume !!(main_~i~0 < main_~j~0); 5595#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5594#L12-2 assume !!(main_~i~0 < main_~j~0); 5593#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5592#L12-2 assume !!(main_~i~0 < main_~j~0); 5591#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5590#L12-2 assume !!(main_~i~0 < main_~j~0); 5589#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5588#L12-2 assume !!(main_~i~0 < main_~j~0); 5587#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5586#L12-2 assume !!(main_~i~0 < main_~j~0); 5585#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5584#L12-2 assume !!(main_~i~0 < main_~j~0); 5583#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5582#L12-2 assume !!(main_~i~0 < main_~j~0); 5581#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5580#L12-2 assume !!(main_~i~0 < main_~j~0); 5579#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5578#L12-2 assume !!(main_~i~0 < main_~j~0); 5576#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5575#L12-2 assume !!(main_~i~0 < main_~j~0); 5574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5573#L12-2 assume !!(main_~i~0 < main_~j~0); 5570#L12 [2021-10-21 19:05:29,554 INFO L793 eck$LassoCheckResult]: Loop: 5570#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5571#L12-2 assume !!(main_~i~0 < main_~j~0); 5574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5573#L12-2 assume !!(main_~i~0 < main_~j~0); 5570#L12 [2021-10-21 19:05:29,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:29,554 INFO L82 PathProgramCache]: Analyzing trace with hash 397934230, now seen corresponding path program 28 times [2021-10-21 19:05:29,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:29,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635267878] [2021-10-21 19:05:29,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:29,555 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:29,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:29,573 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:29,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:29,593 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:29,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:29,593 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 26 times [2021-10-21 19:05:29,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:29,594 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288802972] [2021-10-21 19:05:29,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:29,594 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:29,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:29,602 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:29,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:29,603 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:29,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:29,604 INFO L82 PathProgramCache]: Analyzing trace with hash 1741798478, now seen corresponding path program 28 times [2021-10-21 19:05:29,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:29,604 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619123433] [2021-10-21 19:05:29,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:29,605 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:29,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:30,054 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:30,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:30,057 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619123433] [2021-10-21 19:05:30,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619123433] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:30,058 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [843620152] [2021-10-21 19:05:30,058 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:30,060 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:30,060 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:30,071 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:30,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-10-21 19:05:30,447 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:30,447 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:30,449 INFO L263 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 30 conjunts are in the unsatisfiable core [2021-10-21 19:05:30,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:30,601 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:30,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [843620152] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:30,602 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:30,602 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2021-10-21 19:05:30,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405315609] [2021-10-21 19:05:30,639 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:30,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-10-21 19:05:30,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-10-21 19:05:30,640 INFO L87 Difference]: Start difference. First operand 61 states and 63 transitions. cyclomatic complexity: 3 Second operand has 31 states, 31 states have (on average 1.967741935483871) internal successors, (61), 30 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:30,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:30,723 INFO L93 Difference]: Finished difference Result 65 states and 67 transitions. [2021-10-21 19:05:30,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-10-21 19:05:30,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 67 transitions. [2021-10-21 19:05:30,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:30,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 64 states and 66 transitions. [2021-10-21 19:05:30,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:30,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:30,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 66 transitions. [2021-10-21 19:05:30,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:30,725 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 66 transitions. [2021-10-21 19:05:30,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 66 transitions. [2021-10-21 19:05:30,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2021-10-21 19:05:30,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.0317460317460319) internal successors, (65), 62 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:30,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2021-10-21 19:05:30,727 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2021-10-21 19:05:30,728 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2021-10-21 19:05:30,728 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-10-21 19:05:30,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 65 transitions. [2021-10-21 19:05:30,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:30,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:30,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:30,729 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 29, 1] [2021-10-21 19:05:30,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:30,730 INFO L791 eck$LassoCheckResult]: Stem: 5914#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5910#L12-2 assume !!(main_~i~0 < main_~j~0); 5911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5912#L12-2 assume !!(main_~i~0 < main_~j~0); 5913#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5917#L12-2 assume !!(main_~i~0 < main_~j~0); 5972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5971#L12-2 assume !!(main_~i~0 < main_~j~0); 5970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5969#L12-2 assume !!(main_~i~0 < main_~j~0); 5968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5967#L12-2 assume !!(main_~i~0 < main_~j~0); 5966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5965#L12-2 assume !!(main_~i~0 < main_~j~0); 5964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5963#L12-2 assume !!(main_~i~0 < main_~j~0); 5962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5961#L12-2 assume !!(main_~i~0 < main_~j~0); 5960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5959#L12-2 assume !!(main_~i~0 < main_~j~0); 5958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5957#L12-2 assume !!(main_~i~0 < main_~j~0); 5956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5955#L12-2 assume !!(main_~i~0 < main_~j~0); 5954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5953#L12-2 assume !!(main_~i~0 < main_~j~0); 5952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5951#L12-2 assume !!(main_~i~0 < main_~j~0); 5950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5949#L12-2 assume !!(main_~i~0 < main_~j~0); 5948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5947#L12-2 assume !!(main_~i~0 < main_~j~0); 5946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5945#L12-2 assume !!(main_~i~0 < main_~j~0); 5944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5943#L12-2 assume !!(main_~i~0 < main_~j~0); 5942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5941#L12-2 assume !!(main_~i~0 < main_~j~0); 5940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5939#L12-2 assume !!(main_~i~0 < main_~j~0); 5938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5937#L12-2 assume !!(main_~i~0 < main_~j~0); 5936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5935#L12-2 assume !!(main_~i~0 < main_~j~0); 5934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5933#L12-2 assume !!(main_~i~0 < main_~j~0); 5932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5931#L12-2 assume !!(main_~i~0 < main_~j~0); 5930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5929#L12-2 assume !!(main_~i~0 < main_~j~0); 5928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5927#L12-2 assume !!(main_~i~0 < main_~j~0); 5926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5925#L12-2 assume !!(main_~i~0 < main_~j~0); 5924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5923#L12-2 assume !!(main_~i~0 < main_~j~0); 5921#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5920#L12-2 assume !!(main_~i~0 < main_~j~0); 5919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5918#L12-2 assume !!(main_~i~0 < main_~j~0); 5915#L12 [2021-10-21 19:05:30,730 INFO L793 eck$LassoCheckResult]: Loop: 5915#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5916#L12-2 assume !!(main_~i~0 < main_~j~0); 5919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5918#L12-2 assume !!(main_~i~0 < main_~j~0); 5915#L12 [2021-10-21 19:05:30,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:30,730 INFO L82 PathProgramCache]: Analyzing trace with hash 162706099, now seen corresponding path program 29 times [2021-10-21 19:05:30,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:30,731 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079711347] [2021-10-21 19:05:30,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:30,731 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:30,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:30,745 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:30,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:30,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:30,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:30,759 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 27 times [2021-10-21 19:05:30,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:30,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376509896] [2021-10-21 19:05:30,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:30,760 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:30,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:30,764 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:30,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:30,766 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:30,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:30,766 INFO L82 PathProgramCache]: Analyzing trace with hash -1226106389, now seen corresponding path program 29 times [2021-10-21 19:05:30,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:30,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113539826] [2021-10-21 19:05:30,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:30,767 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:30,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:31,231 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:31,232 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:31,232 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113539826] [2021-10-21 19:05:31,232 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113539826] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:31,232 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2078043135] [2021-10-21 19:05:31,232 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:31,232 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:31,233 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:31,235 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:31,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-10-21 19:05:31,660 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 32 check-sat command(s) [2021-10-21 19:05:31,660 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:31,661 INFO L263 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 31 conjunts are in the unsatisfiable core [2021-10-21 19:05:31,662 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:31,842 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:31,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2078043135] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:31,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:31,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2021-10-21 19:05:31,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884090543] [2021-10-21 19:05:31,888 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:31,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-10-21 19:05:31,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-10-21 19:05:31,889 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. cyclomatic complexity: 3 Second operand has 32 states, 32 states have (on average 1.96875) internal successors, (63), 31 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:31,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:31,949 INFO L93 Difference]: Finished difference Result 67 states and 69 transitions. [2021-10-21 19:05:31,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-10-21 19:05:31,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 69 transitions. [2021-10-21 19:05:31,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:31,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 66 states and 68 transitions. [2021-10-21 19:05:31,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:31,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:31,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 68 transitions. [2021-10-21 19:05:31,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:31,956 INFO L681 BuchiCegarLoop]: Abstraction has 66 states and 68 transitions. [2021-10-21 19:05:31,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 68 transitions. [2021-10-21 19:05:31,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 65. [2021-10-21 19:05:31,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.0307692307692307) internal successors, (67), 64 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:31,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 67 transitions. [2021-10-21 19:05:31,957 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2021-10-21 19:05:31,957 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2021-10-21 19:05:31,957 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-10-21 19:05:31,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 67 transitions. [2021-10-21 19:05:31,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:31,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:31,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:31,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 30, 1] [2021-10-21 19:05:31,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:31,958 INFO L791 eck$LassoCheckResult]: Stem: 6270#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 6266#L12-2 assume !!(main_~i~0 < main_~j~0); 6267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6268#L12-2 assume !!(main_~i~0 < main_~j~0); 6269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6273#L12-2 assume !!(main_~i~0 < main_~j~0); 6330#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6329#L12-2 assume !!(main_~i~0 < main_~j~0); 6328#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6327#L12-2 assume !!(main_~i~0 < main_~j~0); 6326#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6325#L12-2 assume !!(main_~i~0 < main_~j~0); 6324#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6323#L12-2 assume !!(main_~i~0 < main_~j~0); 6322#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6321#L12-2 assume !!(main_~i~0 < main_~j~0); 6320#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6319#L12-2 assume !!(main_~i~0 < main_~j~0); 6318#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6317#L12-2 assume !!(main_~i~0 < main_~j~0); 6316#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6315#L12-2 assume !!(main_~i~0 < main_~j~0); 6314#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6313#L12-2 assume !!(main_~i~0 < main_~j~0); 6312#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6311#L12-2 assume !!(main_~i~0 < main_~j~0); 6310#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6309#L12-2 assume !!(main_~i~0 < main_~j~0); 6308#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6307#L12-2 assume !!(main_~i~0 < main_~j~0); 6306#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6305#L12-2 assume !!(main_~i~0 < main_~j~0); 6304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6303#L12-2 assume !!(main_~i~0 < main_~j~0); 6302#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6301#L12-2 assume !!(main_~i~0 < main_~j~0); 6300#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6299#L12-2 assume !!(main_~i~0 < main_~j~0); 6298#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6297#L12-2 assume !!(main_~i~0 < main_~j~0); 6296#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6295#L12-2 assume !!(main_~i~0 < main_~j~0); 6294#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6293#L12-2 assume !!(main_~i~0 < main_~j~0); 6292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6291#L12-2 assume !!(main_~i~0 < main_~j~0); 6290#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6289#L12-2 assume !!(main_~i~0 < main_~j~0); 6288#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6287#L12-2 assume !!(main_~i~0 < main_~j~0); 6286#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6285#L12-2 assume !!(main_~i~0 < main_~j~0); 6284#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6283#L12-2 assume !!(main_~i~0 < main_~j~0); 6282#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6281#L12-2 assume !!(main_~i~0 < main_~j~0); 6280#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6279#L12-2 assume !!(main_~i~0 < main_~j~0); 6277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6276#L12-2 assume !!(main_~i~0 < main_~j~0); 6275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6274#L12-2 assume !!(main_~i~0 < main_~j~0); 6271#L12 [2021-10-21 19:05:31,958 INFO L793 eck$LassoCheckResult]: Loop: 6271#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 6272#L12-2 assume !!(main_~i~0 < main_~j~0); 6275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6274#L12-2 assume !!(main_~i~0 < main_~j~0); 6271#L12 [2021-10-21 19:05:31,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:31,959 INFO L82 PathProgramCache]: Analyzing trace with hash 1741738896, now seen corresponding path program 30 times [2021-10-21 19:05:31,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:31,959 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177310298] [2021-10-21 19:05:31,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:31,959 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:31,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:31,972 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:32,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:32,010 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:32,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:32,010 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 28 times [2021-10-21 19:05:32,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:32,011 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352274717] [2021-10-21 19:05:32,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:32,011 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:32,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:32,016 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:32,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:32,018 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:32,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:32,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1524399032, now seen corresponding path program 30 times [2021-10-21 19:05:32,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:32,019 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244958462] [2021-10-21 19:05:32,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:32,019 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:32,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:32,506 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:32,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:32,507 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244958462] [2021-10-21 19:05:32,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244958462] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:32,507 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1266375581] [2021-10-21 19:05:32,507 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:32,507 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:32,507 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:32,513 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:32,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-10-21 19:05:32,921 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 33 check-sat command(s) [2021-10-21 19:05:32,922 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:32,923 INFO L263 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 32 conjunts are in the unsatisfiable core [2021-10-21 19:05:32,923 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:33,156 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:33,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1266375581] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:33,157 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:33,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2021-10-21 19:05:33,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548046497] [2021-10-21 19:05:33,196 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:33,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-10-21 19:05:33,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-10-21 19:05:33,198 INFO L87 Difference]: Start difference. First operand 65 states and 67 transitions. cyclomatic complexity: 3 Second operand has 33 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 32 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:33,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:33,283 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2021-10-21 19:05:33,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-10-21 19:05:33,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 71 transitions. [2021-10-21 19:05:33,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:33,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 68 states and 70 transitions. [2021-10-21 19:05:33,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:33,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:33,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 70 transitions. [2021-10-21 19:05:33,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:33,285 INFO L681 BuchiCegarLoop]: Abstraction has 68 states and 70 transitions. [2021-10-21 19:05:33,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 70 transitions. [2021-10-21 19:05:33,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 67. [2021-10-21 19:05:33,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.0298507462686568) internal successors, (69), 66 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:33,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 69 transitions. [2021-10-21 19:05:33,287 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2021-10-21 19:05:33,287 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2021-10-21 19:05:33,287 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-10-21 19:05:33,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 69 transitions. [2021-10-21 19:05:33,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:33,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:33,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:33,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [32, 31, 1] [2021-10-21 19:05:33,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:33,289 INFO L791 eck$LassoCheckResult]: Stem: 6637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 6633#L12-2 assume !!(main_~i~0 < main_~j~0); 6634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6635#L12-2 assume !!(main_~i~0 < main_~j~0); 6636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6640#L12-2 assume !!(main_~i~0 < main_~j~0); 6699#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6698#L12-2 assume !!(main_~i~0 < main_~j~0); 6697#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6696#L12-2 assume !!(main_~i~0 < main_~j~0); 6695#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6694#L12-2 assume !!(main_~i~0 < main_~j~0); 6693#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6692#L12-2 assume !!(main_~i~0 < main_~j~0); 6691#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6690#L12-2 assume !!(main_~i~0 < main_~j~0); 6689#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6688#L12-2 assume !!(main_~i~0 < main_~j~0); 6687#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6686#L12-2 assume !!(main_~i~0 < main_~j~0); 6685#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6684#L12-2 assume !!(main_~i~0 < main_~j~0); 6683#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6682#L12-2 assume !!(main_~i~0 < main_~j~0); 6681#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6680#L12-2 assume !!(main_~i~0 < main_~j~0); 6679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6678#L12-2 assume !!(main_~i~0 < main_~j~0); 6677#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6676#L12-2 assume !!(main_~i~0 < main_~j~0); 6675#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6674#L12-2 assume !!(main_~i~0 < main_~j~0); 6673#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6672#L12-2 assume !!(main_~i~0 < main_~j~0); 6671#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6670#L12-2 assume !!(main_~i~0 < main_~j~0); 6669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6668#L12-2 assume !!(main_~i~0 < main_~j~0); 6667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6666#L12-2 assume !!(main_~i~0 < main_~j~0); 6665#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6664#L12-2 assume !!(main_~i~0 < main_~j~0); 6663#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6662#L12-2 assume !!(main_~i~0 < main_~j~0); 6661#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6660#L12-2 assume !!(main_~i~0 < main_~j~0); 6659#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6658#L12-2 assume !!(main_~i~0 < main_~j~0); 6657#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6656#L12-2 assume !!(main_~i~0 < main_~j~0); 6655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6654#L12-2 assume !!(main_~i~0 < main_~j~0); 6653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6652#L12-2 assume !!(main_~i~0 < main_~j~0); 6651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6650#L12-2 assume !!(main_~i~0 < main_~j~0); 6649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6648#L12-2 assume !!(main_~i~0 < main_~j~0); 6647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6646#L12-2 assume !!(main_~i~0 < main_~j~0); 6644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6643#L12-2 assume !!(main_~i~0 < main_~j~0); 6642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6641#L12-2 assume !!(main_~i~0 < main_~j~0); 6638#L12 [2021-10-21 19:05:33,289 INFO L793 eck$LassoCheckResult]: Loop: 6638#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 6639#L12-2 assume !!(main_~i~0 < main_~j~0); 6642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6641#L12-2 assume !!(main_~i~0 < main_~j~0); 6638#L12 [2021-10-21 19:05:33,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:33,290 INFO L82 PathProgramCache]: Analyzing trace with hash -1226165971, now seen corresponding path program 31 times [2021-10-21 19:05:33,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:33,290 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841787002] [2021-10-21 19:05:33,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:33,290 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:33,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:33,312 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:33,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:33,331 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:33,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:33,332 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 29 times [2021-10-21 19:05:33,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:33,332 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938426381] [2021-10-21 19:05:33,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:33,333 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:33,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:33,341 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:33,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:33,343 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:33,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:33,343 INFO L82 PathProgramCache]: Analyzing trace with hash -420820123, now seen corresponding path program 31 times [2021-10-21 19:05:33,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:33,343 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268694058] [2021-10-21 19:05:33,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:33,344 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:33,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:33,882 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:33,882 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:33,882 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268694058] [2021-10-21 19:05:33,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268694058] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:33,882 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1174248663] [2021-10-21 19:05:33,883 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:33,883 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:33,883 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:33,893 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:33,909 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-10-21 19:05:34,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:34,342 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 33 conjunts are in the unsatisfiable core [2021-10-21 19:05:34,343 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:34,572 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:34,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1174248663] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:34,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:34,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2021-10-21 19:05:34,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413148046] [2021-10-21 19:05:34,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:34,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-10-21 19:05:34,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-10-21 19:05:34,619 INFO L87 Difference]: Start difference. First operand 67 states and 69 transitions. cyclomatic complexity: 3 Second operand has 34 states, 34 states have (on average 1.9705882352941178) internal successors, (67), 33 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:34,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:34,732 INFO L93 Difference]: Finished difference Result 71 states and 73 transitions. [2021-10-21 19:05:34,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-10-21 19:05:34,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 73 transitions. [2021-10-21 19:05:34,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:34,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 72 transitions. [2021-10-21 19:05:34,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:34,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:34,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 72 transitions. [2021-10-21 19:05:34,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:34,735 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 72 transitions. [2021-10-21 19:05:34,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 72 transitions. [2021-10-21 19:05:34,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2021-10-21 19:05:34,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.0289855072463767) internal successors, (71), 68 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:34,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 71 transitions. [2021-10-21 19:05:34,738 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2021-10-21 19:05:34,738 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2021-10-21 19:05:34,738 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-10-21 19:05:34,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 71 transitions. [2021-10-21 19:05:34,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:34,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:34,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:34,740 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [33, 32, 1] [2021-10-21 19:05:34,740 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:34,740 INFO L791 eck$LassoCheckResult]: Stem: 7015#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7011#L12-2 assume !!(main_~i~0 < main_~j~0); 7012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7013#L12-2 assume !!(main_~i~0 < main_~j~0); 7014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7018#L12-2 assume !!(main_~i~0 < main_~j~0); 7079#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7078#L12-2 assume !!(main_~i~0 < main_~j~0); 7077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7076#L12-2 assume !!(main_~i~0 < main_~j~0); 7075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7074#L12-2 assume !!(main_~i~0 < main_~j~0); 7073#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7072#L12-2 assume !!(main_~i~0 < main_~j~0); 7071#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7070#L12-2 assume !!(main_~i~0 < main_~j~0); 7069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7068#L12-2 assume !!(main_~i~0 < main_~j~0); 7067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7066#L12-2 assume !!(main_~i~0 < main_~j~0); 7065#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7064#L12-2 assume !!(main_~i~0 < main_~j~0); 7063#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7062#L12-2 assume !!(main_~i~0 < main_~j~0); 7061#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7060#L12-2 assume !!(main_~i~0 < main_~j~0); 7059#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7058#L12-2 assume !!(main_~i~0 < main_~j~0); 7057#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7056#L12-2 assume !!(main_~i~0 < main_~j~0); 7055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7054#L12-2 assume !!(main_~i~0 < main_~j~0); 7053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7052#L12-2 assume !!(main_~i~0 < main_~j~0); 7051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7050#L12-2 assume !!(main_~i~0 < main_~j~0); 7049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7048#L12-2 assume !!(main_~i~0 < main_~j~0); 7047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7046#L12-2 assume !!(main_~i~0 < main_~j~0); 7045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7044#L12-2 assume !!(main_~i~0 < main_~j~0); 7043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7042#L12-2 assume !!(main_~i~0 < main_~j~0); 7041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7040#L12-2 assume !!(main_~i~0 < main_~j~0); 7039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7038#L12-2 assume !!(main_~i~0 < main_~j~0); 7037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7036#L12-2 assume !!(main_~i~0 < main_~j~0); 7035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7034#L12-2 assume !!(main_~i~0 < main_~j~0); 7033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7032#L12-2 assume !!(main_~i~0 < main_~j~0); 7031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7030#L12-2 assume !!(main_~i~0 < main_~j~0); 7029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7028#L12-2 assume !!(main_~i~0 < main_~j~0); 7027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7026#L12-2 assume !!(main_~i~0 < main_~j~0); 7025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7024#L12-2 assume !!(main_~i~0 < main_~j~0); 7022#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7021#L12-2 assume !!(main_~i~0 < main_~j~0); 7020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7019#L12-2 assume !!(main_~i~0 < main_~j~0); 7016#L12 [2021-10-21 19:05:34,740 INFO L793 eck$LassoCheckResult]: Loop: 7016#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7017#L12-2 assume !!(main_~i~0 < main_~j~0); 7020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7019#L12-2 assume !!(main_~i~0 < main_~j~0); 7016#L12 [2021-10-21 19:05:34,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:34,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1524458614, now seen corresponding path program 32 times [2021-10-21 19:05:34,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:34,741 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440586642] [2021-10-21 19:05:34,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:34,741 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:34,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:34,765 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:34,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:34,781 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:34,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:34,781 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 30 times [2021-10-21 19:05:34,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:34,782 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469062254] [2021-10-21 19:05:34,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:34,782 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:34,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:34,787 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:34,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:34,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:34,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:34,789 INFO L82 PathProgramCache]: Analyzing trace with hash -738410686, now seen corresponding path program 32 times [2021-10-21 19:05:34,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:34,789 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757410165] [2021-10-21 19:05:34,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:34,789 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:34,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:35,280 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:35,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:35,280 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757410165] [2021-10-21 19:05:35,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757410165] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:35,280 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [801957767] [2021-10-21 19:05:35,280 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:35,280 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:35,280 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:35,282 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:35,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-10-21 19:05:35,720 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:35,720 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:35,721 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 34 conjunts are in the unsatisfiable core [2021-10-21 19:05:35,723 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:35,910 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:35,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [801957767] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:35,911 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:35,911 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2021-10-21 19:05:35,911 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115932654] [2021-10-21 19:05:35,961 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:35,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-10-21 19:05:35,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-10-21 19:05:35,962 INFO L87 Difference]: Start difference. First operand 69 states and 71 transitions. cyclomatic complexity: 3 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 34 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:36,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:36,035 INFO L93 Difference]: Finished difference Result 73 states and 75 transitions. [2021-10-21 19:05:36,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-10-21 19:05:36,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 75 transitions. [2021-10-21 19:05:36,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:36,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 72 states and 74 transitions. [2021-10-21 19:05:36,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:36,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:36,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 74 transitions. [2021-10-21 19:05:36,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:36,037 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 74 transitions. [2021-10-21 19:05:36,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 74 transitions. [2021-10-21 19:05:36,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 71. [2021-10-21 19:05:36,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.028169014084507) internal successors, (73), 70 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:36,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 73 transitions. [2021-10-21 19:05:36,039 INFO L704 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2021-10-21 19:05:36,039 INFO L587 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2021-10-21 19:05:36,039 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-10-21 19:05:36,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 73 transitions. [2021-10-21 19:05:36,040 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:36,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:36,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:36,040 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [34, 33, 1] [2021-10-21 19:05:36,041 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:36,041 INFO L791 eck$LassoCheckResult]: Stem: 7404#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7400#L12-2 assume !!(main_~i~0 < main_~j~0); 7401#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7402#L12-2 assume !!(main_~i~0 < main_~j~0); 7403#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7407#L12-2 assume !!(main_~i~0 < main_~j~0); 7470#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7469#L12-2 assume !!(main_~i~0 < main_~j~0); 7468#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7467#L12-2 assume !!(main_~i~0 < main_~j~0); 7466#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7465#L12-2 assume !!(main_~i~0 < main_~j~0); 7464#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7463#L12-2 assume !!(main_~i~0 < main_~j~0); 7462#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7461#L12-2 assume !!(main_~i~0 < main_~j~0); 7460#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7459#L12-2 assume !!(main_~i~0 < main_~j~0); 7458#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7457#L12-2 assume !!(main_~i~0 < main_~j~0); 7456#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7455#L12-2 assume !!(main_~i~0 < main_~j~0); 7454#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7453#L12-2 assume !!(main_~i~0 < main_~j~0); 7452#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7451#L12-2 assume !!(main_~i~0 < main_~j~0); 7450#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7449#L12-2 assume !!(main_~i~0 < main_~j~0); 7448#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7447#L12-2 assume !!(main_~i~0 < main_~j~0); 7446#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7445#L12-2 assume !!(main_~i~0 < main_~j~0); 7444#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7443#L12-2 assume !!(main_~i~0 < main_~j~0); 7442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7441#L12-2 assume !!(main_~i~0 < main_~j~0); 7440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7439#L12-2 assume !!(main_~i~0 < main_~j~0); 7438#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7437#L12-2 assume !!(main_~i~0 < main_~j~0); 7436#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7435#L12-2 assume !!(main_~i~0 < main_~j~0); 7434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7433#L12-2 assume !!(main_~i~0 < main_~j~0); 7432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7431#L12-2 assume !!(main_~i~0 < main_~j~0); 7430#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7429#L12-2 assume !!(main_~i~0 < main_~j~0); 7428#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7427#L12-2 assume !!(main_~i~0 < main_~j~0); 7426#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7425#L12-2 assume !!(main_~i~0 < main_~j~0); 7424#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7423#L12-2 assume !!(main_~i~0 < main_~j~0); 7422#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7421#L12-2 assume !!(main_~i~0 < main_~j~0); 7420#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7419#L12-2 assume !!(main_~i~0 < main_~j~0); 7418#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7417#L12-2 assume !!(main_~i~0 < main_~j~0); 7416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7415#L12-2 assume !!(main_~i~0 < main_~j~0); 7414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7413#L12-2 assume !!(main_~i~0 < main_~j~0); 7411#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7410#L12-2 assume !!(main_~i~0 < main_~j~0); 7409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7408#L12-2 assume !!(main_~i~0 < main_~j~0); 7405#L12 [2021-10-21 19:05:36,041 INFO L793 eck$LassoCheckResult]: Loop: 7405#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7406#L12-2 assume !!(main_~i~0 < main_~j~0); 7409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7408#L12-2 assume !!(main_~i~0 < main_~j~0); 7405#L12 [2021-10-21 19:05:36,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:36,041 INFO L82 PathProgramCache]: Analyzing trace with hash -420879705, now seen corresponding path program 33 times [2021-10-21 19:05:36,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:36,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722276632] [2021-10-21 19:05:36,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:36,042 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:36,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:36,058 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:36,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:36,075 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:36,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:36,075 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 31 times [2021-10-21 19:05:36,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:36,075 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568555525] [2021-10-21 19:05:36,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:36,075 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:36,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:36,080 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:36,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:36,082 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:36,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:36,082 INFO L82 PathProgramCache]: Analyzing trace with hash -1000263713, now seen corresponding path program 33 times [2021-10-21 19:05:36,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:36,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575837671] [2021-10-21 19:05:36,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:36,083 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:36,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:36,676 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:36,676 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:36,676 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575837671] [2021-10-21 19:05:36,676 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575837671] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:36,676 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [147501433] [2021-10-21 19:05:36,676 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:36,677 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:36,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:36,683 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:36,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-10-21 19:05:37,295 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2021-10-21 19:05:37,295 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:37,297 INFO L263 TraceCheckSpWp]: Trace formula consists of 217 conjuncts, 35 conjunts are in the unsatisfiable core [2021-10-21 19:05:37,298 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:37,482 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:37,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [147501433] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:37,482 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:37,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2021-10-21 19:05:37,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923032078] [2021-10-21 19:05:37,515 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:37,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-10-21 19:05:37,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-10-21 19:05:37,516 INFO L87 Difference]: Start difference. First operand 71 states and 73 transitions. cyclomatic complexity: 3 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 35 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:37,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:37,583 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2021-10-21 19:05:37,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-10-21 19:05:37,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2021-10-21 19:05:37,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:37,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 74 states and 76 transitions. [2021-10-21 19:05:37,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:37,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:37,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 76 transitions. [2021-10-21 19:05:37,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:37,585 INFO L681 BuchiCegarLoop]: Abstraction has 74 states and 76 transitions. [2021-10-21 19:05:37,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 76 transitions. [2021-10-21 19:05:37,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 73. [2021-10-21 19:05:37,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.0273972602739727) internal successors, (75), 72 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:37,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 75 transitions. [2021-10-21 19:05:37,587 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2021-10-21 19:05:37,587 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2021-10-21 19:05:37,587 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-10-21 19:05:37,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 75 transitions. [2021-10-21 19:05:37,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:37,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:37,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:37,588 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [35, 34, 1] [2021-10-21 19:05:37,588 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:37,589 INFO L791 eck$LassoCheckResult]: Stem: 7804#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7800#L12-2 assume !!(main_~i~0 < main_~j~0); 7801#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7802#L12-2 assume !!(main_~i~0 < main_~j~0); 7803#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7807#L12-2 assume !!(main_~i~0 < main_~j~0); 7872#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7871#L12-2 assume !!(main_~i~0 < main_~j~0); 7870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7869#L12-2 assume !!(main_~i~0 < main_~j~0); 7868#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7867#L12-2 assume !!(main_~i~0 < main_~j~0); 7866#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7865#L12-2 assume !!(main_~i~0 < main_~j~0); 7864#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7863#L12-2 assume !!(main_~i~0 < main_~j~0); 7862#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7861#L12-2 assume !!(main_~i~0 < main_~j~0); 7860#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7859#L12-2 assume !!(main_~i~0 < main_~j~0); 7858#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7857#L12-2 assume !!(main_~i~0 < main_~j~0); 7856#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7855#L12-2 assume !!(main_~i~0 < main_~j~0); 7854#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7853#L12-2 assume !!(main_~i~0 < main_~j~0); 7852#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7851#L12-2 assume !!(main_~i~0 < main_~j~0); 7850#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7849#L12-2 assume !!(main_~i~0 < main_~j~0); 7848#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7847#L12-2 assume !!(main_~i~0 < main_~j~0); 7846#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7845#L12-2 assume !!(main_~i~0 < main_~j~0); 7844#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7843#L12-2 assume !!(main_~i~0 < main_~j~0); 7842#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7841#L12-2 assume !!(main_~i~0 < main_~j~0); 7840#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7839#L12-2 assume !!(main_~i~0 < main_~j~0); 7838#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7837#L12-2 assume !!(main_~i~0 < main_~j~0); 7836#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7835#L12-2 assume !!(main_~i~0 < main_~j~0); 7834#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7833#L12-2 assume !!(main_~i~0 < main_~j~0); 7832#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7831#L12-2 assume !!(main_~i~0 < main_~j~0); 7830#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7829#L12-2 assume !!(main_~i~0 < main_~j~0); 7828#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7827#L12-2 assume !!(main_~i~0 < main_~j~0); 7826#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7825#L12-2 assume !!(main_~i~0 < main_~j~0); 7824#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7823#L12-2 assume !!(main_~i~0 < main_~j~0); 7822#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7821#L12-2 assume !!(main_~i~0 < main_~j~0); 7820#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7819#L12-2 assume !!(main_~i~0 < main_~j~0); 7818#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7817#L12-2 assume !!(main_~i~0 < main_~j~0); 7816#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7815#L12-2 assume !!(main_~i~0 < main_~j~0); 7814#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7813#L12-2 assume !!(main_~i~0 < main_~j~0); 7811#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7810#L12-2 assume !!(main_~i~0 < main_~j~0); 7809#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7808#L12-2 assume !!(main_~i~0 < main_~j~0); 7805#L12 [2021-10-21 19:05:37,589 INFO L793 eck$LassoCheckResult]: Loop: 7805#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7806#L12-2 assume !!(main_~i~0 < main_~j~0); 7809#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7808#L12-2 assume !!(main_~i~0 < main_~j~0); 7805#L12 [2021-10-21 19:05:37,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:37,589 INFO L82 PathProgramCache]: Analyzing trace with hash -738470268, now seen corresponding path program 34 times [2021-10-21 19:05:37,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:37,590 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251065550] [2021-10-21 19:05:37,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:37,590 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:37,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:37,608 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:37,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:37,625 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:37,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:37,625 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 32 times [2021-10-21 19:05:37,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:37,626 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720332050] [2021-10-21 19:05:37,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:37,626 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:37,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:37,631 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:37,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:37,633 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:37,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:37,633 INFO L82 PathProgramCache]: Analyzing trace with hash 762047804, now seen corresponding path program 34 times [2021-10-21 19:05:37,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:37,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786625021] [2021-10-21 19:05:37,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:37,634 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:37,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:38,294 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:38,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:38,294 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786625021] [2021-10-21 19:05:38,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786625021] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:38,294 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [922963832] [2021-10-21 19:05:38,295 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:38,295 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:38,295 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:38,297 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:38,313 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-10-21 19:05:38,835 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:38,835 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:38,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 36 conjunts are in the unsatisfiable core [2021-10-21 19:05:38,838 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:39,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:39,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [922963832] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:39,068 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:39,069 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2021-10-21 19:05:39,069 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379907087] [2021-10-21 19:05:39,103 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:39,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-10-21 19:05:39,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-10-21 19:05:39,104 INFO L87 Difference]: Start difference. First operand 73 states and 75 transitions. cyclomatic complexity: 3 Second operand has 37 states, 37 states have (on average 1.972972972972973) internal successors, (73), 36 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:39,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:39,189 INFO L93 Difference]: Finished difference Result 77 states and 79 transitions. [2021-10-21 19:05:39,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-10-21 19:05:39,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 79 transitions. [2021-10-21 19:05:39,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:39,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 76 states and 78 transitions. [2021-10-21 19:05:39,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:39,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:39,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 78 transitions. [2021-10-21 19:05:39,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:39,196 INFO L681 BuchiCegarLoop]: Abstraction has 76 states and 78 transitions. [2021-10-21 19:05:39,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 78 transitions. [2021-10-21 19:05:39,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2021-10-21 19:05:39,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0266666666666666) internal successors, (77), 74 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:39,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2021-10-21 19:05:39,206 INFO L704 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2021-10-21 19:05:39,206 INFO L587 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2021-10-21 19:05:39,206 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-10-21 19:05:39,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2021-10-21 19:05:39,207 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:39,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:39,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:39,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [36, 35, 1] [2021-10-21 19:05:39,209 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:39,209 INFO L791 eck$LassoCheckResult]: Stem: 8215#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 8211#L12-2 assume !!(main_~i~0 < main_~j~0); 8212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8213#L12-2 assume !!(main_~i~0 < main_~j~0); 8214#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8218#L12-2 assume !!(main_~i~0 < main_~j~0); 8285#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8284#L12-2 assume !!(main_~i~0 < main_~j~0); 8283#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8282#L12-2 assume !!(main_~i~0 < main_~j~0); 8281#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8280#L12-2 assume !!(main_~i~0 < main_~j~0); 8279#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8278#L12-2 assume !!(main_~i~0 < main_~j~0); 8277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8276#L12-2 assume !!(main_~i~0 < main_~j~0); 8275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8274#L12-2 assume !!(main_~i~0 < main_~j~0); 8273#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8272#L12-2 assume !!(main_~i~0 < main_~j~0); 8271#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8270#L12-2 assume !!(main_~i~0 < main_~j~0); 8269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8268#L12-2 assume !!(main_~i~0 < main_~j~0); 8267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8266#L12-2 assume !!(main_~i~0 < main_~j~0); 8265#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8264#L12-2 assume !!(main_~i~0 < main_~j~0); 8263#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8262#L12-2 assume !!(main_~i~0 < main_~j~0); 8261#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8260#L12-2 assume !!(main_~i~0 < main_~j~0); 8259#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8258#L12-2 assume !!(main_~i~0 < main_~j~0); 8257#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8256#L12-2 assume !!(main_~i~0 < main_~j~0); 8255#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8254#L12-2 assume !!(main_~i~0 < main_~j~0); 8253#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8252#L12-2 assume !!(main_~i~0 < main_~j~0); 8251#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8250#L12-2 assume !!(main_~i~0 < main_~j~0); 8249#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8248#L12-2 assume !!(main_~i~0 < main_~j~0); 8247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8246#L12-2 assume !!(main_~i~0 < main_~j~0); 8245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8244#L12-2 assume !!(main_~i~0 < main_~j~0); 8243#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8242#L12-2 assume !!(main_~i~0 < main_~j~0); 8241#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8240#L12-2 assume !!(main_~i~0 < main_~j~0); 8239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8238#L12-2 assume !!(main_~i~0 < main_~j~0); 8237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8236#L12-2 assume !!(main_~i~0 < main_~j~0); 8235#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8234#L12-2 assume !!(main_~i~0 < main_~j~0); 8233#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8232#L12-2 assume !!(main_~i~0 < main_~j~0); 8231#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8230#L12-2 assume !!(main_~i~0 < main_~j~0); 8229#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8228#L12-2 assume !!(main_~i~0 < main_~j~0); 8227#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8226#L12-2 assume !!(main_~i~0 < main_~j~0); 8225#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8224#L12-2 assume !!(main_~i~0 < main_~j~0); 8222#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8221#L12-2 assume !!(main_~i~0 < main_~j~0); 8220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8219#L12-2 assume !!(main_~i~0 < main_~j~0); 8216#L12 [2021-10-21 19:05:39,209 INFO L793 eck$LassoCheckResult]: Loop: 8216#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 8217#L12-2 assume !!(main_~i~0 < main_~j~0); 8220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8219#L12-2 assume !!(main_~i~0 < main_~j~0); 8216#L12 [2021-10-21 19:05:39,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:39,210 INFO L82 PathProgramCache]: Analyzing trace with hash -1000323295, now seen corresponding path program 35 times [2021-10-21 19:05:39,210 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:39,210 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981465607] [2021-10-21 19:05:39,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:39,210 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:39,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:39,235 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:39,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:39,255 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:39,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:39,256 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 33 times [2021-10-21 19:05:39,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:39,256 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186862756] [2021-10-21 19:05:39,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:39,256 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:39,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:39,266 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:39,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:39,268 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:39,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:39,269 INFO L82 PathProgramCache]: Analyzing trace with hash 2126301017, now seen corresponding path program 35 times [2021-10-21 19:05:39,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:39,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662996127] [2021-10-21 19:05:39,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:39,269 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:39,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:39,873 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:39,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:39,873 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662996127] [2021-10-21 19:05:39,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662996127] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:39,874 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [419607693] [2021-10-21 19:05:39,874 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:39,874 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:39,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:39,875 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:39,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-10-21 19:05:40,365 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 38 check-sat command(s) [2021-10-21 19:05:40,365 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:40,367 INFO L263 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 37 conjunts are in the unsatisfiable core [2021-10-21 19:05:40,368 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:40,613 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:40,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [419607693] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:40,613 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:40,613 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2021-10-21 19:05:40,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896518677] [2021-10-21 19:05:40,654 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:40,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-10-21 19:05:40,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-10-21 19:05:40,656 INFO L87 Difference]: Start difference. First operand 75 states and 77 transitions. cyclomatic complexity: 3 Second operand has 38 states, 38 states have (on average 1.9736842105263157) internal successors, (75), 37 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:40,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:40,750 INFO L93 Difference]: Finished difference Result 79 states and 81 transitions. [2021-10-21 19:05:40,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-10-21 19:05:40,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 81 transitions. [2021-10-21 19:05:40,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:40,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 78 states and 80 transitions. [2021-10-21 19:05:40,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:40,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:40,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 80 transitions. [2021-10-21 19:05:40,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:40,752 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 80 transitions. [2021-10-21 19:05:40,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 80 transitions. [2021-10-21 19:05:40,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 77. [2021-10-21 19:05:40,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.025974025974026) internal successors, (79), 76 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:40,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 79 transitions. [2021-10-21 19:05:40,754 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2021-10-21 19:05:40,754 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2021-10-21 19:05:40,754 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-10-21 19:05:40,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 79 transitions. [2021-10-21 19:05:40,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:40,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:40,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:40,755 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [37, 36, 1] [2021-10-21 19:05:40,755 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:40,755 INFO L791 eck$LassoCheckResult]: Stem: 8637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 8633#L12-2 assume !!(main_~i~0 < main_~j~0); 8634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8635#L12-2 assume !!(main_~i~0 < main_~j~0); 8636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8640#L12-2 assume !!(main_~i~0 < main_~j~0); 8709#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8708#L12-2 assume !!(main_~i~0 < main_~j~0); 8707#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8706#L12-2 assume !!(main_~i~0 < main_~j~0); 8705#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8704#L12-2 assume !!(main_~i~0 < main_~j~0); 8703#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8702#L12-2 assume !!(main_~i~0 < main_~j~0); 8701#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8700#L12-2 assume !!(main_~i~0 < main_~j~0); 8699#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8698#L12-2 assume !!(main_~i~0 < main_~j~0); 8697#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8696#L12-2 assume !!(main_~i~0 < main_~j~0); 8695#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8694#L12-2 assume !!(main_~i~0 < main_~j~0); 8693#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8692#L12-2 assume !!(main_~i~0 < main_~j~0); 8691#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8690#L12-2 assume !!(main_~i~0 < main_~j~0); 8689#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8688#L12-2 assume !!(main_~i~0 < main_~j~0); 8687#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8686#L12-2 assume !!(main_~i~0 < main_~j~0); 8685#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8684#L12-2 assume !!(main_~i~0 < main_~j~0); 8683#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8682#L12-2 assume !!(main_~i~0 < main_~j~0); 8681#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8680#L12-2 assume !!(main_~i~0 < main_~j~0); 8679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8678#L12-2 assume !!(main_~i~0 < main_~j~0); 8677#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8676#L12-2 assume !!(main_~i~0 < main_~j~0); 8675#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8674#L12-2 assume !!(main_~i~0 < main_~j~0); 8673#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8672#L12-2 assume !!(main_~i~0 < main_~j~0); 8671#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8670#L12-2 assume !!(main_~i~0 < main_~j~0); 8669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8668#L12-2 assume !!(main_~i~0 < main_~j~0); 8667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8666#L12-2 assume !!(main_~i~0 < main_~j~0); 8665#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8664#L12-2 assume !!(main_~i~0 < main_~j~0); 8663#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8662#L12-2 assume !!(main_~i~0 < main_~j~0); 8661#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8660#L12-2 assume !!(main_~i~0 < main_~j~0); 8659#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8658#L12-2 assume !!(main_~i~0 < main_~j~0); 8657#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8656#L12-2 assume !!(main_~i~0 < main_~j~0); 8655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8654#L12-2 assume !!(main_~i~0 < main_~j~0); 8653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8652#L12-2 assume !!(main_~i~0 < main_~j~0); 8651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8650#L12-2 assume !!(main_~i~0 < main_~j~0); 8649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8648#L12-2 assume !!(main_~i~0 < main_~j~0); 8647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8646#L12-2 assume !!(main_~i~0 < main_~j~0); 8644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8643#L12-2 assume !!(main_~i~0 < main_~j~0); 8642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8641#L12-2 assume !!(main_~i~0 < main_~j~0); 8638#L12 [2021-10-21 19:05:40,756 INFO L793 eck$LassoCheckResult]: Loop: 8638#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 8639#L12-2 assume !!(main_~i~0 < main_~j~0); 8642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8641#L12-2 assume !!(main_~i~0 < main_~j~0); 8638#L12 [2021-10-21 19:05:40,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:40,756 INFO L82 PathProgramCache]: Analyzing trace with hash 761988222, now seen corresponding path program 36 times [2021-10-21 19:05:40,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:40,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373282698] [2021-10-21 19:05:40,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:40,756 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:40,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:40,777 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:40,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:40,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:40,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:40,795 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 34 times [2021-10-21 19:05:40,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:40,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409190925] [2021-10-21 19:05:40,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:40,796 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:40,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:40,844 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:40,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:40,846 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:40,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:40,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1086353866, now seen corresponding path program 36 times [2021-10-21 19:05:40,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:40,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400939975] [2021-10-21 19:05:40,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:40,846 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:40,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:41,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:41,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:41,446 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400939975] [2021-10-21 19:05:41,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400939975] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:41,446 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [153597656] [2021-10-21 19:05:41,447 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:41,447 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:41,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:41,448 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:41,449 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-10-21 19:05:41,961 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2021-10-21 19:05:41,961 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:41,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 38 conjunts are in the unsatisfiable core [2021-10-21 19:05:41,964 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:42,194 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:42,194 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [153597656] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:42,194 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:42,194 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2021-10-21 19:05:42,195 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436147333] [2021-10-21 19:05:42,235 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:42,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-10-21 19:05:42,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2021-10-21 19:05:42,237 INFO L87 Difference]: Start difference. First operand 77 states and 79 transitions. cyclomatic complexity: 3 Second operand has 39 states, 39 states have (on average 1.9743589743589745) internal successors, (77), 38 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:42,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:42,336 INFO L93 Difference]: Finished difference Result 81 states and 83 transitions. [2021-10-21 19:05:42,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-10-21 19:05:42,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 83 transitions. [2021-10-21 19:05:42,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:42,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 82 transitions. [2021-10-21 19:05:42,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:42,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:42,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 82 transitions. [2021-10-21 19:05:42,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:42,339 INFO L681 BuchiCegarLoop]: Abstraction has 80 states and 82 transitions. [2021-10-21 19:05:42,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 82 transitions. [2021-10-21 19:05:42,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 79. [2021-10-21 19:05:42,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.0253164556962024) internal successors, (81), 78 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:42,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 81 transitions. [2021-10-21 19:05:42,341 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2021-10-21 19:05:42,341 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2021-10-21 19:05:42,341 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-10-21 19:05:42,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 81 transitions. [2021-10-21 19:05:42,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:42,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:42,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:42,342 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [38, 37, 1] [2021-10-21 19:05:42,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:42,343 INFO L791 eck$LassoCheckResult]: Stem: 9070#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9066#L12-2 assume !!(main_~i~0 < main_~j~0); 9067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9068#L12-2 assume !!(main_~i~0 < main_~j~0); 9069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9073#L12-2 assume !!(main_~i~0 < main_~j~0); 9144#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9143#L12-2 assume !!(main_~i~0 < main_~j~0); 9142#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9141#L12-2 assume !!(main_~i~0 < main_~j~0); 9140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9139#L12-2 assume !!(main_~i~0 < main_~j~0); 9138#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9137#L12-2 assume !!(main_~i~0 < main_~j~0); 9136#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9135#L12-2 assume !!(main_~i~0 < main_~j~0); 9134#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9133#L12-2 assume !!(main_~i~0 < main_~j~0); 9132#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9131#L12-2 assume !!(main_~i~0 < main_~j~0); 9130#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9129#L12-2 assume !!(main_~i~0 < main_~j~0); 9128#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9127#L12-2 assume !!(main_~i~0 < main_~j~0); 9126#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9125#L12-2 assume !!(main_~i~0 < main_~j~0); 9124#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9123#L12-2 assume !!(main_~i~0 < main_~j~0); 9122#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9121#L12-2 assume !!(main_~i~0 < main_~j~0); 9120#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9119#L12-2 assume !!(main_~i~0 < main_~j~0); 9118#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9117#L12-2 assume !!(main_~i~0 < main_~j~0); 9116#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9115#L12-2 assume !!(main_~i~0 < main_~j~0); 9114#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9113#L12-2 assume !!(main_~i~0 < main_~j~0); 9112#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9111#L12-2 assume !!(main_~i~0 < main_~j~0); 9110#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9109#L12-2 assume !!(main_~i~0 < main_~j~0); 9108#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9107#L12-2 assume !!(main_~i~0 < main_~j~0); 9106#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9105#L12-2 assume !!(main_~i~0 < main_~j~0); 9104#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9103#L12-2 assume !!(main_~i~0 < main_~j~0); 9102#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9101#L12-2 assume !!(main_~i~0 < main_~j~0); 9100#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9099#L12-2 assume !!(main_~i~0 < main_~j~0); 9098#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9097#L12-2 assume !!(main_~i~0 < main_~j~0); 9096#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9095#L12-2 assume !!(main_~i~0 < main_~j~0); 9094#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9093#L12-2 assume !!(main_~i~0 < main_~j~0); 9092#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9091#L12-2 assume !!(main_~i~0 < main_~j~0); 9090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9089#L12-2 assume !!(main_~i~0 < main_~j~0); 9088#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9087#L12-2 assume !!(main_~i~0 < main_~j~0); 9086#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9085#L12-2 assume !!(main_~i~0 < main_~j~0); 9084#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9083#L12-2 assume !!(main_~i~0 < main_~j~0); 9082#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9081#L12-2 assume !!(main_~i~0 < main_~j~0); 9080#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9079#L12-2 assume !!(main_~i~0 < main_~j~0); 9077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9076#L12-2 assume !!(main_~i~0 < main_~j~0); 9075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9074#L12-2 assume !!(main_~i~0 < main_~j~0); 9071#L12 [2021-10-21 19:05:42,343 INFO L793 eck$LassoCheckResult]: Loop: 9071#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9072#L12-2 assume !!(main_~i~0 < main_~j~0); 9075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9074#L12-2 assume !!(main_~i~0 < main_~j~0); 9071#L12 [2021-10-21 19:05:42,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:42,343 INFO L82 PathProgramCache]: Analyzing trace with hash 2126241435, now seen corresponding path program 37 times [2021-10-21 19:05:42,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:42,343 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004139915] [2021-10-21 19:05:42,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:42,343 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:42,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:42,395 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:42,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:42,418 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:42,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:42,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 35 times [2021-10-21 19:05:42,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:42,419 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136562263] [2021-10-21 19:05:42,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:42,419 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:42,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:42,425 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:42,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:42,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:42,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:42,427 INFO L82 PathProgramCache]: Analyzing trace with hash -366210605, now seen corresponding path program 37 times [2021-10-21 19:05:42,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:42,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154744578] [2021-10-21 19:05:42,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:42,428 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:42,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:43,127 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:43,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:43,127 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154744578] [2021-10-21 19:05:43,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154744578] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:43,128 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [367383934] [2021-10-21 19:05:43,128 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:43,128 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:43,128 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:43,134 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:43,141 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-10-21 19:05:43,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:43,660 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 39 conjunts are in the unsatisfiable core [2021-10-21 19:05:43,661 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:43,938 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:43,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [367383934] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:43,938 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:43,938 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2021-10-21 19:05:43,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434683662] [2021-10-21 19:05:43,973 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:43,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-10-21 19:05:43,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2021-10-21 19:05:43,974 INFO L87 Difference]: Start difference. First operand 79 states and 81 transitions. cyclomatic complexity: 3 Second operand has 40 states, 40 states have (on average 1.975) internal successors, (79), 39 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:44,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:44,061 INFO L93 Difference]: Finished difference Result 83 states and 85 transitions. [2021-10-21 19:05:44,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-10-21 19:05:44,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 85 transitions. [2021-10-21 19:05:44,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:44,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 82 states and 84 transitions. [2021-10-21 19:05:44,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:44,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:44,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 84 transitions. [2021-10-21 19:05:44,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:44,063 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 84 transitions. [2021-10-21 19:05:44,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 84 transitions. [2021-10-21 19:05:44,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2021-10-21 19:05:44,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.0246913580246915) internal successors, (83), 80 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:44,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 83 transitions. [2021-10-21 19:05:44,067 INFO L704 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2021-10-21 19:05:44,067 INFO L587 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2021-10-21 19:05:44,067 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-10-21 19:05:44,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 83 transitions. [2021-10-21 19:05:44,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:44,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:44,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:44,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [39, 38, 1] [2021-10-21 19:05:44,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:44,069 INFO L791 eck$LassoCheckResult]: Stem: 9514#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9510#L12-2 assume !!(main_~i~0 < main_~j~0); 9511#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9512#L12-2 assume !!(main_~i~0 < main_~j~0); 9513#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9517#L12-2 assume !!(main_~i~0 < main_~j~0); 9590#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9589#L12-2 assume !!(main_~i~0 < main_~j~0); 9588#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9587#L12-2 assume !!(main_~i~0 < main_~j~0); 9586#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9585#L12-2 assume !!(main_~i~0 < main_~j~0); 9584#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9583#L12-2 assume !!(main_~i~0 < main_~j~0); 9582#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9581#L12-2 assume !!(main_~i~0 < main_~j~0); 9580#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9579#L12-2 assume !!(main_~i~0 < main_~j~0); 9578#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9577#L12-2 assume !!(main_~i~0 < main_~j~0); 9576#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9575#L12-2 assume !!(main_~i~0 < main_~j~0); 9574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9573#L12-2 assume !!(main_~i~0 < main_~j~0); 9572#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9571#L12-2 assume !!(main_~i~0 < main_~j~0); 9570#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9569#L12-2 assume !!(main_~i~0 < main_~j~0); 9568#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9567#L12-2 assume !!(main_~i~0 < main_~j~0); 9566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9565#L12-2 assume !!(main_~i~0 < main_~j~0); 9564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9563#L12-2 assume !!(main_~i~0 < main_~j~0); 9562#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9561#L12-2 assume !!(main_~i~0 < main_~j~0); 9560#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9559#L12-2 assume !!(main_~i~0 < main_~j~0); 9558#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9557#L12-2 assume !!(main_~i~0 < main_~j~0); 9556#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9555#L12-2 assume !!(main_~i~0 < main_~j~0); 9554#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9553#L12-2 assume !!(main_~i~0 < main_~j~0); 9552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9551#L12-2 assume !!(main_~i~0 < main_~j~0); 9550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9549#L12-2 assume !!(main_~i~0 < main_~j~0); 9548#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9547#L12-2 assume !!(main_~i~0 < main_~j~0); 9546#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9545#L12-2 assume !!(main_~i~0 < main_~j~0); 9544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9543#L12-2 assume !!(main_~i~0 < main_~j~0); 9542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9541#L12-2 assume !!(main_~i~0 < main_~j~0); 9540#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9539#L12-2 assume !!(main_~i~0 < main_~j~0); 9538#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9537#L12-2 assume !!(main_~i~0 < main_~j~0); 9536#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9535#L12-2 assume !!(main_~i~0 < main_~j~0); 9534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9533#L12-2 assume !!(main_~i~0 < main_~j~0); 9532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9531#L12-2 assume !!(main_~i~0 < main_~j~0); 9530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9529#L12-2 assume !!(main_~i~0 < main_~j~0); 9528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9527#L12-2 assume !!(main_~i~0 < main_~j~0); 9526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9525#L12-2 assume !!(main_~i~0 < main_~j~0); 9524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9523#L12-2 assume !!(main_~i~0 < main_~j~0); 9521#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9520#L12-2 assume !!(main_~i~0 < main_~j~0); 9519#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9518#L12-2 assume !!(main_~i~0 < main_~j~0); 9515#L12 [2021-10-21 19:05:44,070 INFO L793 eck$LassoCheckResult]: Loop: 9515#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9516#L12-2 assume !!(main_~i~0 < main_~j~0); 9519#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9518#L12-2 assume !!(main_~i~0 < main_~j~0); 9515#L12 [2021-10-21 19:05:44,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:44,070 INFO L82 PathProgramCache]: Analyzing trace with hash -1086413448, now seen corresponding path program 38 times [2021-10-21 19:05:44,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:44,070 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427452673] [2021-10-21 19:05:44,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:44,071 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:44,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:44,118 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:44,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:44,173 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:44,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:44,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 36 times [2021-10-21 19:05:44,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:44,174 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898689051] [2021-10-21 19:05:44,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:44,175 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:44,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:44,185 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:44,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:44,186 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:44,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:44,187 INFO L82 PathProgramCache]: Analyzing trace with hash 201728560, now seen corresponding path program 38 times [2021-10-21 19:05:44,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:44,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606470012] [2021-10-21 19:05:44,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:44,187 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:44,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:44,836 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:44,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:44,836 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606470012] [2021-10-21 19:05:44,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606470012] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:44,836 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1973767024] [2021-10-21 19:05:44,836 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:44,836 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:44,836 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:44,838 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:44,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-10-21 19:05:45,393 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:45,393 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:45,394 INFO L263 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 40 conjunts are in the unsatisfiable core [2021-10-21 19:05:45,396 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:45,640 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:45,640 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1973767024] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:45,640 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:45,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2021-10-21 19:05:45,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615040745] [2021-10-21 19:05:45,679 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:45,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-10-21 19:05:45,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2021-10-21 19:05:45,680 INFO L87 Difference]: Start difference. First operand 81 states and 83 transitions. cyclomatic complexity: 3 Second operand has 41 states, 41 states have (on average 1.975609756097561) internal successors, (81), 40 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:45,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:45,783 INFO L93 Difference]: Finished difference Result 85 states and 87 transitions. [2021-10-21 19:05:45,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-10-21 19:05:45,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 87 transitions. [2021-10-21 19:05:45,784 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:45,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 86 transitions. [2021-10-21 19:05:45,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:45,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:45,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 86 transitions. [2021-10-21 19:05:45,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:45,785 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 86 transitions. [2021-10-21 19:05:45,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 86 transitions. [2021-10-21 19:05:45,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 83. [2021-10-21 19:05:45,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.0240963855421688) internal successors, (85), 82 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:45,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 85 transitions. [2021-10-21 19:05:45,832 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2021-10-21 19:05:45,832 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2021-10-21 19:05:45,832 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-10-21 19:05:45,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 85 transitions. [2021-10-21 19:05:45,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:45,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:45,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:45,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [40, 39, 1] [2021-10-21 19:05:45,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:45,834 INFO L791 eck$LassoCheckResult]: Stem: 9969#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9965#L12-2 assume !!(main_~i~0 < main_~j~0); 9966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9967#L12-2 assume !!(main_~i~0 < main_~j~0); 9968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9972#L12-2 assume !!(main_~i~0 < main_~j~0); 10047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10046#L12-2 assume !!(main_~i~0 < main_~j~0); 10045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10044#L12-2 assume !!(main_~i~0 < main_~j~0); 10043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10042#L12-2 assume !!(main_~i~0 < main_~j~0); 10041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10040#L12-2 assume !!(main_~i~0 < main_~j~0); 10039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10038#L12-2 assume !!(main_~i~0 < main_~j~0); 10037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10036#L12-2 assume !!(main_~i~0 < main_~j~0); 10035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10034#L12-2 assume !!(main_~i~0 < main_~j~0); 10033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10032#L12-2 assume !!(main_~i~0 < main_~j~0); 10031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10030#L12-2 assume !!(main_~i~0 < main_~j~0); 10029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10028#L12-2 assume !!(main_~i~0 < main_~j~0); 10027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10026#L12-2 assume !!(main_~i~0 < main_~j~0); 10025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10024#L12-2 assume !!(main_~i~0 < main_~j~0); 10023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10022#L12-2 assume !!(main_~i~0 < main_~j~0); 10021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10020#L12-2 assume !!(main_~i~0 < main_~j~0); 10019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10018#L12-2 assume !!(main_~i~0 < main_~j~0); 10017#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10016#L12-2 assume !!(main_~i~0 < main_~j~0); 10015#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10014#L12-2 assume !!(main_~i~0 < main_~j~0); 10013#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10012#L12-2 assume !!(main_~i~0 < main_~j~0); 10011#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10010#L12-2 assume !!(main_~i~0 < main_~j~0); 10009#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10008#L12-2 assume !!(main_~i~0 < main_~j~0); 10007#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10006#L12-2 assume !!(main_~i~0 < main_~j~0); 10005#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10004#L12-2 assume !!(main_~i~0 < main_~j~0); 10003#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10002#L12-2 assume !!(main_~i~0 < main_~j~0); 10001#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10000#L12-2 assume !!(main_~i~0 < main_~j~0); 9999#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9998#L12-2 assume !!(main_~i~0 < main_~j~0); 9997#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9996#L12-2 assume !!(main_~i~0 < main_~j~0); 9995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9994#L12-2 assume !!(main_~i~0 < main_~j~0); 9993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9992#L12-2 assume !!(main_~i~0 < main_~j~0); 9991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9990#L12-2 assume !!(main_~i~0 < main_~j~0); 9989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9988#L12-2 assume !!(main_~i~0 < main_~j~0); 9987#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9986#L12-2 assume !!(main_~i~0 < main_~j~0); 9985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9984#L12-2 assume !!(main_~i~0 < main_~j~0); 9983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9982#L12-2 assume !!(main_~i~0 < main_~j~0); 9981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9980#L12-2 assume !!(main_~i~0 < main_~j~0); 9979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9978#L12-2 assume !!(main_~i~0 < main_~j~0); 9976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9975#L12-2 assume !!(main_~i~0 < main_~j~0); 9974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9973#L12-2 assume !!(main_~i~0 < main_~j~0); 9970#L12 [2021-10-21 19:05:45,834 INFO L793 eck$LassoCheckResult]: Loop: 9970#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9971#L12-2 assume !!(main_~i~0 < main_~j~0); 9974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9973#L12-2 assume !!(main_~i~0 < main_~j~0); 9970#L12 [2021-10-21 19:05:45,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:45,834 INFO L82 PathProgramCache]: Analyzing trace with hash -366270187, now seen corresponding path program 39 times [2021-10-21 19:05:45,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:45,834 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936030298] [2021-10-21 19:05:45,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:45,834 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:45,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:45,857 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:45,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:45,877 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:45,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:45,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 37 times [2021-10-21 19:05:45,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:45,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257550637] [2021-10-21 19:05:45,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:45,878 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:45,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:45,885 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:45,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:45,886 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:45,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:45,887 INFO L82 PathProgramCache]: Analyzing trace with hash 530419533, now seen corresponding path program 39 times [2021-10-21 19:05:45,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:45,887 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590763251] [2021-10-21 19:05:45,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:45,887 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:45,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:46,553 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:46,553 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:46,553 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590763251] [2021-10-21 19:05:46,553 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590763251] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:46,554 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [268509223] [2021-10-21 19:05:46,554 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:46,554 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:46,554 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:46,555 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:46,556 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-10-21 19:05:47,150 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2021-10-21 19:05:47,150 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:47,152 INFO L263 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 41 conjunts are in the unsatisfiable core [2021-10-21 19:05:47,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:47,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:47,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [268509223] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:47,373 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:47,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2021-10-21 19:05:47,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7966132] [2021-10-21 19:05:47,424 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:47,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-10-21 19:05:47,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2021-10-21 19:05:47,425 INFO L87 Difference]: Start difference. First operand 83 states and 85 transitions. cyclomatic complexity: 3 Second operand has 42 states, 42 states have (on average 1.9761904761904763) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:47,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:47,512 INFO L93 Difference]: Finished difference Result 87 states and 89 transitions. [2021-10-21 19:05:47,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-10-21 19:05:47,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 89 transitions. [2021-10-21 19:05:47,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:47,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 86 states and 88 transitions. [2021-10-21 19:05:47,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:47,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:47,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 88 transitions. [2021-10-21 19:05:47,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:47,516 INFO L681 BuchiCegarLoop]: Abstraction has 86 states and 88 transitions. [2021-10-21 19:05:47,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 88 transitions. [2021-10-21 19:05:47,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 85. [2021-10-21 19:05:47,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.0235294117647058) internal successors, (87), 84 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:47,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 87 transitions. [2021-10-21 19:05:47,518 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2021-10-21 19:05:47,518 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2021-10-21 19:05:47,519 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-10-21 19:05:47,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 87 transitions. [2021-10-21 19:05:47,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:47,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:47,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:47,520 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [41, 40, 1] [2021-10-21 19:05:47,520 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:47,521 INFO L791 eck$LassoCheckResult]: Stem: 10435#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 10431#L12-2 assume !!(main_~i~0 < main_~j~0); 10432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10433#L12-2 assume !!(main_~i~0 < main_~j~0); 10434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10438#L12-2 assume !!(main_~i~0 < main_~j~0); 10515#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10514#L12-2 assume !!(main_~i~0 < main_~j~0); 10513#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10512#L12-2 assume !!(main_~i~0 < main_~j~0); 10511#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10510#L12-2 assume !!(main_~i~0 < main_~j~0); 10509#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10508#L12-2 assume !!(main_~i~0 < main_~j~0); 10507#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10506#L12-2 assume !!(main_~i~0 < main_~j~0); 10505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10504#L12-2 assume !!(main_~i~0 < main_~j~0); 10503#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10502#L12-2 assume !!(main_~i~0 < main_~j~0); 10501#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10500#L12-2 assume !!(main_~i~0 < main_~j~0); 10499#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10498#L12-2 assume !!(main_~i~0 < main_~j~0); 10497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10496#L12-2 assume !!(main_~i~0 < main_~j~0); 10495#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10494#L12-2 assume !!(main_~i~0 < main_~j~0); 10493#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10492#L12-2 assume !!(main_~i~0 < main_~j~0); 10491#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10490#L12-2 assume !!(main_~i~0 < main_~j~0); 10489#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10488#L12-2 assume !!(main_~i~0 < main_~j~0); 10487#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10486#L12-2 assume !!(main_~i~0 < main_~j~0); 10485#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10484#L12-2 assume !!(main_~i~0 < main_~j~0); 10483#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10482#L12-2 assume !!(main_~i~0 < main_~j~0); 10481#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10480#L12-2 assume !!(main_~i~0 < main_~j~0); 10479#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10478#L12-2 assume !!(main_~i~0 < main_~j~0); 10477#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10476#L12-2 assume !!(main_~i~0 < main_~j~0); 10475#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10474#L12-2 assume !!(main_~i~0 < main_~j~0); 10473#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10472#L12-2 assume !!(main_~i~0 < main_~j~0); 10471#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10470#L12-2 assume !!(main_~i~0 < main_~j~0); 10469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10468#L12-2 assume !!(main_~i~0 < main_~j~0); 10467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10466#L12-2 assume !!(main_~i~0 < main_~j~0); 10465#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10464#L12-2 assume !!(main_~i~0 < main_~j~0); 10463#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10462#L12-2 assume !!(main_~i~0 < main_~j~0); 10461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10460#L12-2 assume !!(main_~i~0 < main_~j~0); 10459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10458#L12-2 assume !!(main_~i~0 < main_~j~0); 10457#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10456#L12-2 assume !!(main_~i~0 < main_~j~0); 10455#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10454#L12-2 assume !!(main_~i~0 < main_~j~0); 10453#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10452#L12-2 assume !!(main_~i~0 < main_~j~0); 10451#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10450#L12-2 assume !!(main_~i~0 < main_~j~0); 10449#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10448#L12-2 assume !!(main_~i~0 < main_~j~0); 10447#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10446#L12-2 assume !!(main_~i~0 < main_~j~0); 10445#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10444#L12-2 assume !!(main_~i~0 < main_~j~0); 10442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10441#L12-2 assume !!(main_~i~0 < main_~j~0); 10440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10439#L12-2 assume !!(main_~i~0 < main_~j~0); 10436#L12 [2021-10-21 19:05:47,521 INFO L793 eck$LassoCheckResult]: Loop: 10436#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 10437#L12-2 assume !!(main_~i~0 < main_~j~0); 10440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10439#L12-2 assume !!(main_~i~0 < main_~j~0); 10436#L12 [2021-10-21 19:05:47,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:47,521 INFO L82 PathProgramCache]: Analyzing trace with hash 201668978, now seen corresponding path program 40 times [2021-10-21 19:05:47,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:47,522 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583575403] [2021-10-21 19:05:47,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:47,522 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:47,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:47,592 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:47,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:47,618 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:47,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:47,619 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 38 times [2021-10-21 19:05:47,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:47,619 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425373531] [2021-10-21 19:05:47,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:47,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:47,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:47,626 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:47,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:47,633 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:47,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:47,633 INFO L82 PathProgramCache]: Analyzing trace with hash -1425135318, now seen corresponding path program 40 times [2021-10-21 19:05:47,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:47,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326838399] [2021-10-21 19:05:47,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:47,634 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:47,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:48,411 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:48,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:48,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326838399] [2021-10-21 19:05:48,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326838399] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:48,412 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [688398461] [2021-10-21 19:05:48,412 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:05:48,412 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:48,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:48,413 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:48,414 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-10-21 19:05:49,006 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:05:49,007 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:49,008 INFO L263 TraceCheckSpWp]: Trace formula consists of 259 conjuncts, 42 conjunts are in the unsatisfiable core [2021-10-21 19:05:49,009 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:49,277 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:49,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [688398461] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:49,278 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:49,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2021-10-21 19:05:49,278 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265140382] [2021-10-21 19:05:49,319 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:49,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-10-21 19:05:49,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2021-10-21 19:05:49,321 INFO L87 Difference]: Start difference. First operand 85 states and 87 transitions. cyclomatic complexity: 3 Second operand has 43 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 42 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:49,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:49,427 INFO L93 Difference]: Finished difference Result 89 states and 91 transitions. [2021-10-21 19:05:49,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-10-21 19:05:49,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 91 transitions. [2021-10-21 19:05:49,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:49,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 88 states and 90 transitions. [2021-10-21 19:05:49,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:49,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:49,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 90 transitions. [2021-10-21 19:05:49,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:49,430 INFO L681 BuchiCegarLoop]: Abstraction has 88 states and 90 transitions. [2021-10-21 19:05:49,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 90 transitions. [2021-10-21 19:05:49,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2021-10-21 19:05:49,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.0229885057471264) internal successors, (89), 86 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:49,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 89 transitions. [2021-10-21 19:05:49,432 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2021-10-21 19:05:49,432 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2021-10-21 19:05:49,432 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-10-21 19:05:49,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 89 transitions. [2021-10-21 19:05:49,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:49,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:49,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:49,433 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [42, 41, 1] [2021-10-21 19:05:49,433 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:49,434 INFO L791 eck$LassoCheckResult]: Stem: 10912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 10908#L12-2 assume !!(main_~i~0 < main_~j~0); 10909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10910#L12-2 assume !!(main_~i~0 < main_~j~0); 10911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10915#L12-2 assume !!(main_~i~0 < main_~j~0); 10994#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10993#L12-2 assume !!(main_~i~0 < main_~j~0); 10992#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10991#L12-2 assume !!(main_~i~0 < main_~j~0); 10990#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10989#L12-2 assume !!(main_~i~0 < main_~j~0); 10988#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10987#L12-2 assume !!(main_~i~0 < main_~j~0); 10986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10985#L12-2 assume !!(main_~i~0 < main_~j~0); 10984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10983#L12-2 assume !!(main_~i~0 < main_~j~0); 10982#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10981#L12-2 assume !!(main_~i~0 < main_~j~0); 10980#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10979#L12-2 assume !!(main_~i~0 < main_~j~0); 10978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10977#L12-2 assume !!(main_~i~0 < main_~j~0); 10976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10975#L12-2 assume !!(main_~i~0 < main_~j~0); 10974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10973#L12-2 assume !!(main_~i~0 < main_~j~0); 10972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10971#L12-2 assume !!(main_~i~0 < main_~j~0); 10970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10969#L12-2 assume !!(main_~i~0 < main_~j~0); 10968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10967#L12-2 assume !!(main_~i~0 < main_~j~0); 10966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10965#L12-2 assume !!(main_~i~0 < main_~j~0); 10964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10963#L12-2 assume !!(main_~i~0 < main_~j~0); 10962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10961#L12-2 assume !!(main_~i~0 < main_~j~0); 10960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10959#L12-2 assume !!(main_~i~0 < main_~j~0); 10958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10957#L12-2 assume !!(main_~i~0 < main_~j~0); 10956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10955#L12-2 assume !!(main_~i~0 < main_~j~0); 10954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10953#L12-2 assume !!(main_~i~0 < main_~j~0); 10952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10951#L12-2 assume !!(main_~i~0 < main_~j~0); 10950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10949#L12-2 assume !!(main_~i~0 < main_~j~0); 10948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10947#L12-2 assume !!(main_~i~0 < main_~j~0); 10946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10945#L12-2 assume !!(main_~i~0 < main_~j~0); 10944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10943#L12-2 assume !!(main_~i~0 < main_~j~0); 10942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10941#L12-2 assume !!(main_~i~0 < main_~j~0); 10940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10939#L12-2 assume !!(main_~i~0 < main_~j~0); 10938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10937#L12-2 assume !!(main_~i~0 < main_~j~0); 10936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10935#L12-2 assume !!(main_~i~0 < main_~j~0); 10934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10933#L12-2 assume !!(main_~i~0 < main_~j~0); 10932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10931#L12-2 assume !!(main_~i~0 < main_~j~0); 10930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10929#L12-2 assume !!(main_~i~0 < main_~j~0); 10928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10927#L12-2 assume !!(main_~i~0 < main_~j~0); 10926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10925#L12-2 assume !!(main_~i~0 < main_~j~0); 10924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10923#L12-2 assume !!(main_~i~0 < main_~j~0); 10922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10921#L12-2 assume !!(main_~i~0 < main_~j~0); 10919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10918#L12-2 assume !!(main_~i~0 < main_~j~0); 10917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10916#L12-2 assume !!(main_~i~0 < main_~j~0); 10913#L12 [2021-10-21 19:05:49,434 INFO L793 eck$LassoCheckResult]: Loop: 10913#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 10914#L12-2 assume !!(main_~i~0 < main_~j~0); 10917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10916#L12-2 assume !!(main_~i~0 < main_~j~0); 10913#L12 [2021-10-21 19:05:49,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:49,434 INFO L82 PathProgramCache]: Analyzing trace with hash 530359951, now seen corresponding path program 41 times [2021-10-21 19:05:49,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:49,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507171668] [2021-10-21 19:05:49,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:49,434 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:49,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:49,517 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:49,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:49,539 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:49,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:49,539 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 39 times [2021-10-21 19:05:49,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:49,539 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524501433] [2021-10-21 19:05:49,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:49,540 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:49,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:49,549 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:49,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:49,552 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:49,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:49,552 INFO L82 PathProgramCache]: Analyzing trace with hash 482328519, now seen corresponding path program 41 times [2021-10-21 19:05:49,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:49,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736299369] [2021-10-21 19:05:49,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:49,553 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:49,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:50,284 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:50,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:50,284 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736299369] [2021-10-21 19:05:50,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736299369] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:50,284 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1264765155] [2021-10-21 19:05:50,284 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:05:50,284 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:50,285 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:50,286 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:50,286 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-10-21 19:05:50,939 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 44 check-sat command(s) [2021-10-21 19:05:50,939 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:50,942 INFO L263 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 43 conjunts are in the unsatisfiable core [2021-10-21 19:05:50,943 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:51,189 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:51,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1264765155] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:51,189 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:51,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2021-10-21 19:05:51,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484732872] [2021-10-21 19:05:51,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:51,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-10-21 19:05:51,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2021-10-21 19:05:51,269 INFO L87 Difference]: Start difference. First operand 87 states and 89 transitions. cyclomatic complexity: 3 Second operand has 44 states, 44 states have (on average 1.9772727272727273) internal successors, (87), 43 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:51,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:51,377 INFO L93 Difference]: Finished difference Result 91 states and 93 transitions. [2021-10-21 19:05:51,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-10-21 19:05:51,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 93 transitions. [2021-10-21 19:05:51,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:51,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 90 states and 92 transitions. [2021-10-21 19:05:51,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:51,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:51,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 92 transitions. [2021-10-21 19:05:51,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:51,379 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 92 transitions. [2021-10-21 19:05:51,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 92 transitions. [2021-10-21 19:05:51,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 89. [2021-10-21 19:05:51,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.0224719101123596) internal successors, (91), 88 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:51,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 91 transitions. [2021-10-21 19:05:51,381 INFO L704 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2021-10-21 19:05:51,382 INFO L587 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2021-10-21 19:05:51,382 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-10-21 19:05:51,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 91 transitions. [2021-10-21 19:05:51,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:51,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:51,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:51,383 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [43, 42, 1] [2021-10-21 19:05:51,383 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:51,384 INFO L791 eck$LassoCheckResult]: Stem: 11400#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 11396#L12-2 assume !!(main_~i~0 < main_~j~0); 11397#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11398#L12-2 assume !!(main_~i~0 < main_~j~0); 11399#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11403#L12-2 assume !!(main_~i~0 < main_~j~0); 11484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11483#L12-2 assume !!(main_~i~0 < main_~j~0); 11482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11481#L12-2 assume !!(main_~i~0 < main_~j~0); 11480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11479#L12-2 assume !!(main_~i~0 < main_~j~0); 11478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11477#L12-2 assume !!(main_~i~0 < main_~j~0); 11476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11475#L12-2 assume !!(main_~i~0 < main_~j~0); 11474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11473#L12-2 assume !!(main_~i~0 < main_~j~0); 11472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11471#L12-2 assume !!(main_~i~0 < main_~j~0); 11470#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11469#L12-2 assume !!(main_~i~0 < main_~j~0); 11468#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11467#L12-2 assume !!(main_~i~0 < main_~j~0); 11466#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11465#L12-2 assume !!(main_~i~0 < main_~j~0); 11464#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11463#L12-2 assume !!(main_~i~0 < main_~j~0); 11462#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11461#L12-2 assume !!(main_~i~0 < main_~j~0); 11460#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11459#L12-2 assume !!(main_~i~0 < main_~j~0); 11458#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11457#L12-2 assume !!(main_~i~0 < main_~j~0); 11456#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11455#L12-2 assume !!(main_~i~0 < main_~j~0); 11454#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11453#L12-2 assume !!(main_~i~0 < main_~j~0); 11452#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11451#L12-2 assume !!(main_~i~0 < main_~j~0); 11450#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11449#L12-2 assume !!(main_~i~0 < main_~j~0); 11448#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11447#L12-2 assume !!(main_~i~0 < main_~j~0); 11446#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11445#L12-2 assume !!(main_~i~0 < main_~j~0); 11444#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11443#L12-2 assume !!(main_~i~0 < main_~j~0); 11442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11441#L12-2 assume !!(main_~i~0 < main_~j~0); 11440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11439#L12-2 assume !!(main_~i~0 < main_~j~0); 11438#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11437#L12-2 assume !!(main_~i~0 < main_~j~0); 11436#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11435#L12-2 assume !!(main_~i~0 < main_~j~0); 11434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11433#L12-2 assume !!(main_~i~0 < main_~j~0); 11432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11431#L12-2 assume !!(main_~i~0 < main_~j~0); 11430#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11429#L12-2 assume !!(main_~i~0 < main_~j~0); 11428#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11427#L12-2 assume !!(main_~i~0 < main_~j~0); 11426#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11425#L12-2 assume !!(main_~i~0 < main_~j~0); 11424#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11423#L12-2 assume !!(main_~i~0 < main_~j~0); 11422#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11421#L12-2 assume !!(main_~i~0 < main_~j~0); 11420#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11419#L12-2 assume !!(main_~i~0 < main_~j~0); 11418#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11417#L12-2 assume !!(main_~i~0 < main_~j~0); 11416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11415#L12-2 assume !!(main_~i~0 < main_~j~0); 11414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11413#L12-2 assume !!(main_~i~0 < main_~j~0); 11412#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11411#L12-2 assume !!(main_~i~0 < main_~j~0); 11410#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11409#L12-2 assume !!(main_~i~0 < main_~j~0); 11407#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11406#L12-2 assume !!(main_~i~0 < main_~j~0); 11405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11404#L12-2 assume !!(main_~i~0 < main_~j~0); 11401#L12 [2021-10-21 19:05:51,384 INFO L793 eck$LassoCheckResult]: Loop: 11401#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 11402#L12-2 assume !!(main_~i~0 < main_~j~0); 11405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11404#L12-2 assume !!(main_~i~0 < main_~j~0); 11401#L12 [2021-10-21 19:05:51,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:51,384 INFO L82 PathProgramCache]: Analyzing trace with hash -1425194900, now seen corresponding path program 42 times [2021-10-21 19:05:51,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:51,385 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356814220] [2021-10-21 19:05:51,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:51,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:51,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:51,413 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:51,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:51,439 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:51,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:51,439 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 40 times [2021-10-21 19:05:51,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:51,440 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055464086] [2021-10-21 19:05:51,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:51,440 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:51,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:51,452 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:51,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:51,454 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:51,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:51,455 INFO L82 PathProgramCache]: Analyzing trace with hash -395959516, now seen corresponding path program 42 times [2021-10-21 19:05:51,455 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:51,455 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080224391] [2021-10-21 19:05:51,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:51,456 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:51,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:52,271 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:52,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:52,273 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080224391] [2021-10-21 19:05:52,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080224391] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:52,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1057899996] [2021-10-21 19:05:52,274 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:05:52,274 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:52,274 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:52,276 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:52,289 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-10-21 19:05:52,961 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2021-10-21 19:05:52,961 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:52,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 44 conjunts are in the unsatisfiable core [2021-10-21 19:05:52,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:53,221 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:53,221 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1057899996] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:53,222 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:53,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2021-10-21 19:05:53,222 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957741111] [2021-10-21 19:05:53,266 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:53,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-10-21 19:05:53,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2021-10-21 19:05:53,267 INFO L87 Difference]: Start difference. First operand 89 states and 91 transitions. cyclomatic complexity: 3 Second operand has 45 states, 45 states have (on average 1.9777777777777779) internal successors, (89), 44 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:53,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:53,353 INFO L93 Difference]: Finished difference Result 93 states and 95 transitions. [2021-10-21 19:05:53,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-10-21 19:05:53,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 95 transitions. [2021-10-21 19:05:53,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:53,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 92 states and 94 transitions. [2021-10-21 19:05:53,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:53,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:53,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 94 transitions. [2021-10-21 19:05:53,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:53,355 INFO L681 BuchiCegarLoop]: Abstraction has 92 states and 94 transitions. [2021-10-21 19:05:53,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 94 transitions. [2021-10-21 19:05:53,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 91. [2021-10-21 19:05:53,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.021978021978022) internal successors, (93), 90 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:53,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 93 transitions. [2021-10-21 19:05:53,357 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2021-10-21 19:05:53,357 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2021-10-21 19:05:53,357 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-10-21 19:05:53,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 93 transitions. [2021-10-21 19:05:53,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:53,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:53,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:53,359 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [44, 43, 1] [2021-10-21 19:05:53,359 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:53,359 INFO L791 eck$LassoCheckResult]: Stem: 11899#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 11895#L12-2 assume !!(main_~i~0 < main_~j~0); 11896#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11897#L12-2 assume !!(main_~i~0 < main_~j~0); 11898#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11902#L12-2 assume !!(main_~i~0 < main_~j~0); 11985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11984#L12-2 assume !!(main_~i~0 < main_~j~0); 11983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11982#L12-2 assume !!(main_~i~0 < main_~j~0); 11981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11980#L12-2 assume !!(main_~i~0 < main_~j~0); 11979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11978#L12-2 assume !!(main_~i~0 < main_~j~0); 11977#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11976#L12-2 assume !!(main_~i~0 < main_~j~0); 11975#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11974#L12-2 assume !!(main_~i~0 < main_~j~0); 11973#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11972#L12-2 assume !!(main_~i~0 < main_~j~0); 11971#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11970#L12-2 assume !!(main_~i~0 < main_~j~0); 11969#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11968#L12-2 assume !!(main_~i~0 < main_~j~0); 11967#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11966#L12-2 assume !!(main_~i~0 < main_~j~0); 11965#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11964#L12-2 assume !!(main_~i~0 < main_~j~0); 11963#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11962#L12-2 assume !!(main_~i~0 < main_~j~0); 11961#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11960#L12-2 assume !!(main_~i~0 < main_~j~0); 11959#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11958#L12-2 assume !!(main_~i~0 < main_~j~0); 11957#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11956#L12-2 assume !!(main_~i~0 < main_~j~0); 11955#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11954#L12-2 assume !!(main_~i~0 < main_~j~0); 11953#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11952#L12-2 assume !!(main_~i~0 < main_~j~0); 11951#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11950#L12-2 assume !!(main_~i~0 < main_~j~0); 11949#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11948#L12-2 assume !!(main_~i~0 < main_~j~0); 11947#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11946#L12-2 assume !!(main_~i~0 < main_~j~0); 11945#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11944#L12-2 assume !!(main_~i~0 < main_~j~0); 11943#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11942#L12-2 assume !!(main_~i~0 < main_~j~0); 11941#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11940#L12-2 assume !!(main_~i~0 < main_~j~0); 11939#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11938#L12-2 assume !!(main_~i~0 < main_~j~0); 11937#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11936#L12-2 assume !!(main_~i~0 < main_~j~0); 11935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11934#L12-2 assume !!(main_~i~0 < main_~j~0); 11933#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11932#L12-2 assume !!(main_~i~0 < main_~j~0); 11931#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11930#L12-2 assume !!(main_~i~0 < main_~j~0); 11929#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11928#L12-2 assume !!(main_~i~0 < main_~j~0); 11927#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11926#L12-2 assume !!(main_~i~0 < main_~j~0); 11925#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11924#L12-2 assume !!(main_~i~0 < main_~j~0); 11923#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11922#L12-2 assume !!(main_~i~0 < main_~j~0); 11921#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11920#L12-2 assume !!(main_~i~0 < main_~j~0); 11919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11918#L12-2 assume !!(main_~i~0 < main_~j~0); 11917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11916#L12-2 assume !!(main_~i~0 < main_~j~0); 11915#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11914#L12-2 assume !!(main_~i~0 < main_~j~0); 11913#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11912#L12-2 assume !!(main_~i~0 < main_~j~0); 11911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11910#L12-2 assume !!(main_~i~0 < main_~j~0); 11909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11908#L12-2 assume !!(main_~i~0 < main_~j~0); 11906#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11905#L12-2 assume !!(main_~i~0 < main_~j~0); 11904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11903#L12-2 assume !!(main_~i~0 < main_~j~0); 11900#L12 [2021-10-21 19:05:53,359 INFO L793 eck$LassoCheckResult]: Loop: 11900#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 11901#L12-2 assume !!(main_~i~0 < main_~j~0); 11904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11903#L12-2 assume !!(main_~i~0 < main_~j~0); 11900#L12 [2021-10-21 19:05:53,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:53,360 INFO L82 PathProgramCache]: Analyzing trace with hash 482268937, now seen corresponding path program 43 times [2021-10-21 19:05:53,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:53,360 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792751533] [2021-10-21 19:05:53,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:53,361 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:53,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:53,386 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:53,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:53,413 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:53,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:53,414 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 41 times [2021-10-21 19:05:53,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:53,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24728217] [2021-10-21 19:05:53,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:53,415 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:53,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:53,495 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:53,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:53,497 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:53,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:53,498 INFO L82 PathProgramCache]: Analyzing trace with hash 1677796161, now seen corresponding path program 43 times [2021-10-21 19:05:53,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:53,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673644620] [2021-10-21 19:05:53,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:53,498 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:53,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:54,342 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:54,342 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:54,342 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673644620] [2021-10-21 19:05:54,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673644620] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:54,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [604378652] [2021-10-21 19:05:54,343 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-21 19:05:54,343 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:54,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:54,344 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:54,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-10-21 19:05:55,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:55,034 INFO L263 TraceCheckSpWp]: Trace formula consists of 277 conjuncts, 45 conjunts are in the unsatisfiable core [2021-10-21 19:05:55,036 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:55,266 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:55,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [604378652] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:55,267 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:55,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2021-10-21 19:05:55,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038208060] [2021-10-21 19:05:55,309 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:55,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-10-21 19:05:55,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2021-10-21 19:05:55,310 INFO L87 Difference]: Start difference. First operand 91 states and 93 transitions. cyclomatic complexity: 3 Second operand has 46 states, 46 states have (on average 1.9782608695652173) internal successors, (91), 45 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:55,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:55,395 INFO L93 Difference]: Finished difference Result 95 states and 97 transitions. [2021-10-21 19:05:55,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-10-21 19:05:55,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 97 transitions. [2021-10-21 19:05:55,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:55,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 94 states and 96 transitions. [2021-10-21 19:05:55,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:55,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:55,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 96 transitions. [2021-10-21 19:05:55,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:55,397 INFO L681 BuchiCegarLoop]: Abstraction has 94 states and 96 transitions. [2021-10-21 19:05:55,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 96 transitions. [2021-10-21 19:05:55,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2021-10-21 19:05:55,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.021505376344086) internal successors, (95), 92 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:55,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 95 transitions. [2021-10-21 19:05:55,399 INFO L704 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2021-10-21 19:05:55,399 INFO L587 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2021-10-21 19:05:55,399 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-10-21 19:05:55,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 95 transitions. [2021-10-21 19:05:55,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:55,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:55,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:55,401 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [45, 44, 1] [2021-10-21 19:05:55,401 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:55,401 INFO L791 eck$LassoCheckResult]: Stem: 12409#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 12405#L12-2 assume !!(main_~i~0 < main_~j~0); 12406#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12407#L12-2 assume !!(main_~i~0 < main_~j~0); 12408#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12412#L12-2 assume !!(main_~i~0 < main_~j~0); 12497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12496#L12-2 assume !!(main_~i~0 < main_~j~0); 12495#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12494#L12-2 assume !!(main_~i~0 < main_~j~0); 12493#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12492#L12-2 assume !!(main_~i~0 < main_~j~0); 12491#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12490#L12-2 assume !!(main_~i~0 < main_~j~0); 12489#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12488#L12-2 assume !!(main_~i~0 < main_~j~0); 12487#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12486#L12-2 assume !!(main_~i~0 < main_~j~0); 12485#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12484#L12-2 assume !!(main_~i~0 < main_~j~0); 12483#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12482#L12-2 assume !!(main_~i~0 < main_~j~0); 12481#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12480#L12-2 assume !!(main_~i~0 < main_~j~0); 12479#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12478#L12-2 assume !!(main_~i~0 < main_~j~0); 12477#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12476#L12-2 assume !!(main_~i~0 < main_~j~0); 12475#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12474#L12-2 assume !!(main_~i~0 < main_~j~0); 12473#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12472#L12-2 assume !!(main_~i~0 < main_~j~0); 12471#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12470#L12-2 assume !!(main_~i~0 < main_~j~0); 12469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12468#L12-2 assume !!(main_~i~0 < main_~j~0); 12467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12466#L12-2 assume !!(main_~i~0 < main_~j~0); 12465#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12464#L12-2 assume !!(main_~i~0 < main_~j~0); 12463#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12462#L12-2 assume !!(main_~i~0 < main_~j~0); 12461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12460#L12-2 assume !!(main_~i~0 < main_~j~0); 12459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12458#L12-2 assume !!(main_~i~0 < main_~j~0); 12457#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12456#L12-2 assume !!(main_~i~0 < main_~j~0); 12455#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12454#L12-2 assume !!(main_~i~0 < main_~j~0); 12453#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12452#L12-2 assume !!(main_~i~0 < main_~j~0); 12451#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12450#L12-2 assume !!(main_~i~0 < main_~j~0); 12449#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12448#L12-2 assume !!(main_~i~0 < main_~j~0); 12447#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12446#L12-2 assume !!(main_~i~0 < main_~j~0); 12445#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12444#L12-2 assume !!(main_~i~0 < main_~j~0); 12443#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12442#L12-2 assume !!(main_~i~0 < main_~j~0); 12441#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12440#L12-2 assume !!(main_~i~0 < main_~j~0); 12439#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12438#L12-2 assume !!(main_~i~0 < main_~j~0); 12437#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12436#L12-2 assume !!(main_~i~0 < main_~j~0); 12435#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12434#L12-2 assume !!(main_~i~0 < main_~j~0); 12433#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12432#L12-2 assume !!(main_~i~0 < main_~j~0); 12431#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12430#L12-2 assume !!(main_~i~0 < main_~j~0); 12429#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12428#L12-2 assume !!(main_~i~0 < main_~j~0); 12427#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12426#L12-2 assume !!(main_~i~0 < main_~j~0); 12425#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12424#L12-2 assume !!(main_~i~0 < main_~j~0); 12423#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12422#L12-2 assume !!(main_~i~0 < main_~j~0); 12421#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12420#L12-2 assume !!(main_~i~0 < main_~j~0); 12419#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12418#L12-2 assume !!(main_~i~0 < main_~j~0); 12416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12415#L12-2 assume !!(main_~i~0 < main_~j~0); 12414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12413#L12-2 assume !!(main_~i~0 < main_~j~0); 12410#L12 [2021-10-21 19:05:55,401 INFO L793 eck$LassoCheckResult]: Loop: 12410#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 12411#L12-2 assume !!(main_~i~0 < main_~j~0); 12414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12413#L12-2 assume !!(main_~i~0 < main_~j~0); 12410#L12 [2021-10-21 19:05:55,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:55,401 INFO L82 PathProgramCache]: Analyzing trace with hash -396019098, now seen corresponding path program 44 times [2021-10-21 19:05:55,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:55,402 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847048452] [2021-10-21 19:05:55,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:55,402 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:55,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:55,426 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:55,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:55,449 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:55,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:55,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 42 times [2021-10-21 19:05:55,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:55,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340993160] [2021-10-21 19:05:55,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:55,450 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:55,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:55,458 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:55,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:55,459 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:55,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:55,460 INFO L82 PathProgramCache]: Analyzing trace with hash 1692176414, now seen corresponding path program 44 times [2021-10-21 19:05:55,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:55,460 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872519443] [2021-10-21 19:05:55,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:55,460 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:55,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:56,374 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:56,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:56,375 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872519443] [2021-10-21 19:05:56,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872519443] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:56,375 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [946319241] [2021-10-21 19:05:56,375 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-21 19:05:56,375 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:56,376 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:56,381 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:56,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-10-21 19:05:57,093 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-21 19:05:57,093 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:57,094 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 46 conjunts are in the unsatisfiable core [2021-10-21 19:05:57,096 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:57,374 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:57,374 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [946319241] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:57,374 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:57,374 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2021-10-21 19:05:57,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81660588] [2021-10-21 19:05:57,406 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:57,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-10-21 19:05:57,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2021-10-21 19:05:57,408 INFO L87 Difference]: Start difference. First operand 93 states and 95 transitions. cyclomatic complexity: 3 Second operand has 47 states, 47 states have (on average 1.9787234042553192) internal successors, (93), 46 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:57,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:57,493 INFO L93 Difference]: Finished difference Result 97 states and 99 transitions. [2021-10-21 19:05:57,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-10-21 19:05:57,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 99 transitions. [2021-10-21 19:05:57,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:57,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 96 states and 98 transitions. [2021-10-21 19:05:57,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:57,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:57,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 98 transitions. [2021-10-21 19:05:57,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:57,494 INFO L681 BuchiCegarLoop]: Abstraction has 96 states and 98 transitions. [2021-10-21 19:05:57,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 98 transitions. [2021-10-21 19:05:57,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 95. [2021-10-21 19:05:57,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.0210526315789474) internal successors, (97), 94 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:57,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 97 transitions. [2021-10-21 19:05:57,496 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2021-10-21 19:05:57,496 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2021-10-21 19:05:57,496 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-10-21 19:05:57,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 97 transitions. [2021-10-21 19:05:57,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:57,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:57,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:57,497 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 45, 1] [2021-10-21 19:05:57,497 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:57,498 INFO L791 eck$LassoCheckResult]: Stem: 12930#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 12926#L12-2 assume !!(main_~i~0 < main_~j~0); 12927#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12928#L12-2 assume !!(main_~i~0 < main_~j~0); 12929#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12933#L12-2 assume !!(main_~i~0 < main_~j~0); 13020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13019#L12-2 assume !!(main_~i~0 < main_~j~0); 13018#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13017#L12-2 assume !!(main_~i~0 < main_~j~0); 13016#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13015#L12-2 assume !!(main_~i~0 < main_~j~0); 13014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13013#L12-2 assume !!(main_~i~0 < main_~j~0); 13012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13011#L12-2 assume !!(main_~i~0 < main_~j~0); 13010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13009#L12-2 assume !!(main_~i~0 < main_~j~0); 13008#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13007#L12-2 assume !!(main_~i~0 < main_~j~0); 13006#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13005#L12-2 assume !!(main_~i~0 < main_~j~0); 13004#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13003#L12-2 assume !!(main_~i~0 < main_~j~0); 13002#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13001#L12-2 assume !!(main_~i~0 < main_~j~0); 13000#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12999#L12-2 assume !!(main_~i~0 < main_~j~0); 12998#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12997#L12-2 assume !!(main_~i~0 < main_~j~0); 12996#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12995#L12-2 assume !!(main_~i~0 < main_~j~0); 12994#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12993#L12-2 assume !!(main_~i~0 < main_~j~0); 12992#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12991#L12-2 assume !!(main_~i~0 < main_~j~0); 12990#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12989#L12-2 assume !!(main_~i~0 < main_~j~0); 12988#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12987#L12-2 assume !!(main_~i~0 < main_~j~0); 12986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12985#L12-2 assume !!(main_~i~0 < main_~j~0); 12984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12983#L12-2 assume !!(main_~i~0 < main_~j~0); 12982#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12981#L12-2 assume !!(main_~i~0 < main_~j~0); 12980#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12979#L12-2 assume !!(main_~i~0 < main_~j~0); 12978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12977#L12-2 assume !!(main_~i~0 < main_~j~0); 12976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12975#L12-2 assume !!(main_~i~0 < main_~j~0); 12974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12973#L12-2 assume !!(main_~i~0 < main_~j~0); 12972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12971#L12-2 assume !!(main_~i~0 < main_~j~0); 12970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12969#L12-2 assume !!(main_~i~0 < main_~j~0); 12968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12967#L12-2 assume !!(main_~i~0 < main_~j~0); 12966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12965#L12-2 assume !!(main_~i~0 < main_~j~0); 12964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12963#L12-2 assume !!(main_~i~0 < main_~j~0); 12962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12961#L12-2 assume !!(main_~i~0 < main_~j~0); 12960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12959#L12-2 assume !!(main_~i~0 < main_~j~0); 12958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12957#L12-2 assume !!(main_~i~0 < main_~j~0); 12956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12955#L12-2 assume !!(main_~i~0 < main_~j~0); 12954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12953#L12-2 assume !!(main_~i~0 < main_~j~0); 12952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12951#L12-2 assume !!(main_~i~0 < main_~j~0); 12950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12949#L12-2 assume !!(main_~i~0 < main_~j~0); 12948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12947#L12-2 assume !!(main_~i~0 < main_~j~0); 12946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12945#L12-2 assume !!(main_~i~0 < main_~j~0); 12944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12943#L12-2 assume !!(main_~i~0 < main_~j~0); 12942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12941#L12-2 assume !!(main_~i~0 < main_~j~0); 12940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12939#L12-2 assume !!(main_~i~0 < main_~j~0); 12937#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12936#L12-2 assume !!(main_~i~0 < main_~j~0); 12935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12934#L12-2 assume !!(main_~i~0 < main_~j~0); 12931#L12 [2021-10-21 19:05:57,498 INFO L793 eck$LassoCheckResult]: Loop: 12931#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 12932#L12-2 assume !!(main_~i~0 < main_~j~0); 12935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12934#L12-2 assume !!(main_~i~0 < main_~j~0); 12931#L12 [2021-10-21 19:05:57,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:57,498 INFO L82 PathProgramCache]: Analyzing trace with hash 1677736579, now seen corresponding path program 45 times [2021-10-21 19:05:57,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:57,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23990917] [2021-10-21 19:05:57,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:57,498 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:57,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:57,524 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:57,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:57,547 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:57,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:57,548 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 43 times [2021-10-21 19:05:57,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:57,548 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061450143] [2021-10-21 19:05:57,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:57,549 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:57,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:57,556 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:57,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:57,558 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:57,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:57,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1668269637, now seen corresponding path program 45 times [2021-10-21 19:05:57,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:57,558 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889815296] [2021-10-21 19:05:57,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:57,559 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:57,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:05:58,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:58,484 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:05:58,484 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889815296] [2021-10-21 19:05:58,484 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889815296] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:58,484 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1862225488] [2021-10-21 19:05:58,484 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-21 19:05:58,485 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:05:58,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:05:58,498 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:05:58,499 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-10-21 19:05:59,250 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2021-10-21 19:05:59,250 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:05:59,252 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 47 conjunts are in the unsatisfiable core [2021-10-21 19:05:59,253 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:05:59,548 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:05:59,548 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1862225488] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:05:59,549 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:05:59,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2021-10-21 19:05:59,549 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40416313] [2021-10-21 19:05:59,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:05:59,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-10-21 19:05:59,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2021-10-21 19:05:59,592 INFO L87 Difference]: Start difference. First operand 95 states and 97 transitions. cyclomatic complexity: 3 Second operand has 48 states, 48 states have (on average 1.9791666666666667) internal successors, (95), 47 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:59,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:05:59,706 INFO L93 Difference]: Finished difference Result 99 states and 101 transitions. [2021-10-21 19:05:59,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-10-21 19:05:59,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 101 transitions. [2021-10-21 19:05:59,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:59,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 98 states and 100 transitions. [2021-10-21 19:05:59,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:05:59,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:05:59,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 100 transitions. [2021-10-21 19:05:59,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:05:59,708 INFO L681 BuchiCegarLoop]: Abstraction has 98 states and 100 transitions. [2021-10-21 19:05:59,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 100 transitions. [2021-10-21 19:05:59,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 97. [2021-10-21 19:05:59,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0206185567010309) internal successors, (99), 96 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:05:59,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 99 transitions. [2021-10-21 19:05:59,710 INFO L704 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2021-10-21 19:05:59,710 INFO L587 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2021-10-21 19:05:59,710 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-10-21 19:05:59,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 99 transitions. [2021-10-21 19:05:59,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:05:59,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:05:59,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:05:59,712 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [47, 46, 1] [2021-10-21 19:05:59,712 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:05:59,712 INFO L791 eck$LassoCheckResult]: Stem: 13462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 13458#L12-2 assume !!(main_~i~0 < main_~j~0); 13459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13460#L12-2 assume !!(main_~i~0 < main_~j~0); 13461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13465#L12-2 assume !!(main_~i~0 < main_~j~0); 13554#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13553#L12-2 assume !!(main_~i~0 < main_~j~0); 13552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13551#L12-2 assume !!(main_~i~0 < main_~j~0); 13550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13549#L12-2 assume !!(main_~i~0 < main_~j~0); 13548#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13547#L12-2 assume !!(main_~i~0 < main_~j~0); 13546#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13545#L12-2 assume !!(main_~i~0 < main_~j~0); 13544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13543#L12-2 assume !!(main_~i~0 < main_~j~0); 13542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13541#L12-2 assume !!(main_~i~0 < main_~j~0); 13540#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13539#L12-2 assume !!(main_~i~0 < main_~j~0); 13538#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13537#L12-2 assume !!(main_~i~0 < main_~j~0); 13536#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13535#L12-2 assume !!(main_~i~0 < main_~j~0); 13534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13533#L12-2 assume !!(main_~i~0 < main_~j~0); 13532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13531#L12-2 assume !!(main_~i~0 < main_~j~0); 13530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13529#L12-2 assume !!(main_~i~0 < main_~j~0); 13528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13527#L12-2 assume !!(main_~i~0 < main_~j~0); 13526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13525#L12-2 assume !!(main_~i~0 < main_~j~0); 13524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13523#L12-2 assume !!(main_~i~0 < main_~j~0); 13522#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13521#L12-2 assume !!(main_~i~0 < main_~j~0); 13520#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13519#L12-2 assume !!(main_~i~0 < main_~j~0); 13518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13517#L12-2 assume !!(main_~i~0 < main_~j~0); 13516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13515#L12-2 assume !!(main_~i~0 < main_~j~0); 13514#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13513#L12-2 assume !!(main_~i~0 < main_~j~0); 13512#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13511#L12-2 assume !!(main_~i~0 < main_~j~0); 13510#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13509#L12-2 assume !!(main_~i~0 < main_~j~0); 13508#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13507#L12-2 assume !!(main_~i~0 < main_~j~0); 13506#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13505#L12-2 assume !!(main_~i~0 < main_~j~0); 13504#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13503#L12-2 assume !!(main_~i~0 < main_~j~0); 13502#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13501#L12-2 assume !!(main_~i~0 < main_~j~0); 13500#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13499#L12-2 assume !!(main_~i~0 < main_~j~0); 13498#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13497#L12-2 assume !!(main_~i~0 < main_~j~0); 13496#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13495#L12-2 assume !!(main_~i~0 < main_~j~0); 13494#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13493#L12-2 assume !!(main_~i~0 < main_~j~0); 13492#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13491#L12-2 assume !!(main_~i~0 < main_~j~0); 13490#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13489#L12-2 assume !!(main_~i~0 < main_~j~0); 13488#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13487#L12-2 assume !!(main_~i~0 < main_~j~0); 13486#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13485#L12-2 assume !!(main_~i~0 < main_~j~0); 13484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13483#L12-2 assume !!(main_~i~0 < main_~j~0); 13482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13481#L12-2 assume !!(main_~i~0 < main_~j~0); 13480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13479#L12-2 assume !!(main_~i~0 < main_~j~0); 13478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13477#L12-2 assume !!(main_~i~0 < main_~j~0); 13476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13475#L12-2 assume !!(main_~i~0 < main_~j~0); 13474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13473#L12-2 assume !!(main_~i~0 < main_~j~0); 13472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13471#L12-2 assume !!(main_~i~0 < main_~j~0); 13469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13468#L12-2 assume !!(main_~i~0 < main_~j~0); 13467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13466#L12-2 assume !!(main_~i~0 < main_~j~0); 13463#L12 [2021-10-21 19:05:59,712 INFO L793 eck$LassoCheckResult]: Loop: 13463#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 13464#L12-2 assume !!(main_~i~0 < main_~j~0); 13467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13466#L12-2 assume !!(main_~i~0 < main_~j~0); 13463#L12 [2021-10-21 19:05:59,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:59,712 INFO L82 PathProgramCache]: Analyzing trace with hash 1692116832, now seen corresponding path program 46 times [2021-10-21 19:05:59,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:59,713 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094097307] [2021-10-21 19:05:59,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:59,713 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:59,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:59,743 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:59,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:59,768 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:59,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:59,768 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 44 times [2021-10-21 19:05:59,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:59,769 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373063777] [2021-10-21 19:05:59,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:59,769 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:59,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:59,777 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:05:59,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:05:59,779 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:05:59,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:05:59,779 INFO L82 PathProgramCache]: Analyzing trace with hash -1241518056, now seen corresponding path program 46 times [2021-10-21 19:05:59,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:05:59,779 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196279804] [2021-10-21 19:05:59,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:05:59,780 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:05:59,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:06:00,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:00,845 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:06:00,845 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196279804] [2021-10-21 19:06:00,845 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196279804] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:00,846 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1631286358] [2021-10-21 19:06:00,846 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-21 19:06:00,846 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:06:00,846 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:06:00,848 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:06:00,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-10-21 19:06:01,628 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-21 19:06:01,628 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:06:01,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 295 conjuncts, 48 conjunts are in the unsatisfiable core [2021-10-21 19:06:01,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:06:01,894 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:01,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1631286358] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:01,895 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:06:01,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2021-10-21 19:06:01,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315623851] [2021-10-21 19:06:01,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:06:01,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-10-21 19:06:01,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-10-21 19:06:01,940 INFO L87 Difference]: Start difference. First operand 97 states and 99 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 48 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:02,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:06:02,035 INFO L93 Difference]: Finished difference Result 101 states and 103 transitions. [2021-10-21 19:06:02,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-10-21 19:06:02,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 103 transitions. [2021-10-21 19:06:02,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:02,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 100 states and 102 transitions. [2021-10-21 19:06:02,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:06:02,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:06:02,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 102 transitions. [2021-10-21 19:06:02,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:06:02,037 INFO L681 BuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2021-10-21 19:06:02,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 102 transitions. [2021-10-21 19:06:02,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2021-10-21 19:06:02,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.02020202020202) internal successors, (101), 98 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:02,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 101 transitions. [2021-10-21 19:06:02,039 INFO L704 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2021-10-21 19:06:02,039 INFO L587 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2021-10-21 19:06:02,039 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-10-21 19:06:02,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 101 transitions. [2021-10-21 19:06:02,040 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:02,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:06:02,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:06:02,041 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [48, 47, 1] [2021-10-21 19:06:02,041 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:06:02,041 INFO L791 eck$LassoCheckResult]: Stem: 14005#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 14001#L12-2 assume !!(main_~i~0 < main_~j~0); 14002#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14003#L12-2 assume !!(main_~i~0 < main_~j~0); 14004#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14008#L12-2 assume !!(main_~i~0 < main_~j~0); 14099#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14098#L12-2 assume !!(main_~i~0 < main_~j~0); 14097#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14096#L12-2 assume !!(main_~i~0 < main_~j~0); 14095#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14094#L12-2 assume !!(main_~i~0 < main_~j~0); 14093#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14092#L12-2 assume !!(main_~i~0 < main_~j~0); 14091#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14090#L12-2 assume !!(main_~i~0 < main_~j~0); 14089#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14088#L12-2 assume !!(main_~i~0 < main_~j~0); 14087#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14086#L12-2 assume !!(main_~i~0 < main_~j~0); 14085#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14084#L12-2 assume !!(main_~i~0 < main_~j~0); 14083#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14082#L12-2 assume !!(main_~i~0 < main_~j~0); 14081#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14080#L12-2 assume !!(main_~i~0 < main_~j~0); 14079#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14078#L12-2 assume !!(main_~i~0 < main_~j~0); 14077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14076#L12-2 assume !!(main_~i~0 < main_~j~0); 14075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14074#L12-2 assume !!(main_~i~0 < main_~j~0); 14073#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14072#L12-2 assume !!(main_~i~0 < main_~j~0); 14071#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14070#L12-2 assume !!(main_~i~0 < main_~j~0); 14069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14068#L12-2 assume !!(main_~i~0 < main_~j~0); 14067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14066#L12-2 assume !!(main_~i~0 < main_~j~0); 14065#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14064#L12-2 assume !!(main_~i~0 < main_~j~0); 14063#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14062#L12-2 assume !!(main_~i~0 < main_~j~0); 14061#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14060#L12-2 assume !!(main_~i~0 < main_~j~0); 14059#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14058#L12-2 assume !!(main_~i~0 < main_~j~0); 14057#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14056#L12-2 assume !!(main_~i~0 < main_~j~0); 14055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14054#L12-2 assume !!(main_~i~0 < main_~j~0); 14053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14052#L12-2 assume !!(main_~i~0 < main_~j~0); 14051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14050#L12-2 assume !!(main_~i~0 < main_~j~0); 14049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14048#L12-2 assume !!(main_~i~0 < main_~j~0); 14047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14046#L12-2 assume !!(main_~i~0 < main_~j~0); 14045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14044#L12-2 assume !!(main_~i~0 < main_~j~0); 14043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14042#L12-2 assume !!(main_~i~0 < main_~j~0); 14041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14040#L12-2 assume !!(main_~i~0 < main_~j~0); 14039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14038#L12-2 assume !!(main_~i~0 < main_~j~0); 14037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14036#L12-2 assume !!(main_~i~0 < main_~j~0); 14035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14034#L12-2 assume !!(main_~i~0 < main_~j~0); 14033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14032#L12-2 assume !!(main_~i~0 < main_~j~0); 14031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14030#L12-2 assume !!(main_~i~0 < main_~j~0); 14029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14028#L12-2 assume !!(main_~i~0 < main_~j~0); 14027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14026#L12-2 assume !!(main_~i~0 < main_~j~0); 14025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14024#L12-2 assume !!(main_~i~0 < main_~j~0); 14023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14022#L12-2 assume !!(main_~i~0 < main_~j~0); 14021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14020#L12-2 assume !!(main_~i~0 < main_~j~0); 14019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14018#L12-2 assume !!(main_~i~0 < main_~j~0); 14017#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14016#L12-2 assume !!(main_~i~0 < main_~j~0); 14015#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14014#L12-2 assume !!(main_~i~0 < main_~j~0); 14012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14011#L12-2 assume !!(main_~i~0 < main_~j~0); 14010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14009#L12-2 assume !!(main_~i~0 < main_~j~0); 14006#L12 [2021-10-21 19:06:02,041 INFO L793 eck$LassoCheckResult]: Loop: 14006#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 14007#L12-2 assume !!(main_~i~0 < main_~j~0); 14010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14009#L12-2 assume !!(main_~i~0 < main_~j~0); 14006#L12 [2021-10-21 19:06:02,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:02,042 INFO L82 PathProgramCache]: Analyzing trace with hash -1668329219, now seen corresponding path program 47 times [2021-10-21 19:06:02,042 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:02,042 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054978710] [2021-10-21 19:06:02,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:02,042 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:02,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:02,069 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:02,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:02,099 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:02,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:02,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 45 times [2021-10-21 19:06:02,099 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:02,100 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737339907] [2021-10-21 19:06:02,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:02,100 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:02,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:02,114 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:02,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:02,115 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:02,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:02,116 INFO L82 PathProgramCache]: Analyzing trace with hash 844858165, now seen corresponding path program 47 times [2021-10-21 19:06:02,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:02,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016104098] [2021-10-21 19:06:02,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:02,116 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:02,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:06:03,165 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:03,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:06:03,165 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016104098] [2021-10-21 19:06:03,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016104098] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:03,165 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1997470411] [2021-10-21 19:06:03,165 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-21 19:06:03,166 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:06:03,166 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:06:03,168 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:06:03,170 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2021-10-21 19:06:04,000 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 50 check-sat command(s) [2021-10-21 19:06:04,000 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:06:04,002 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 49 conjunts are in the unsatisfiable core [2021-10-21 19:06:04,004 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:06:04,383 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:04,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1997470411] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:04,384 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:06:04,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2021-10-21 19:06:04,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756370129] [2021-10-21 19:06:04,428 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:06:04,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-10-21 19:06:04,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2021-10-21 19:06:04,430 INFO L87 Difference]: Start difference. First operand 99 states and 101 transitions. cyclomatic complexity: 3 Second operand has 50 states, 50 states have (on average 1.98) internal successors, (99), 49 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:04,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:06:04,549 INFO L93 Difference]: Finished difference Result 103 states and 105 transitions. [2021-10-21 19:06:04,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-10-21 19:06:04,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 105 transitions. [2021-10-21 19:06:04,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:04,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 102 states and 104 transitions. [2021-10-21 19:06:04,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:06:04,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:06:04,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 104 transitions. [2021-10-21 19:06:04,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:06:04,551 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 104 transitions. [2021-10-21 19:06:04,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 104 transitions. [2021-10-21 19:06:04,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 101. [2021-10-21 19:06:04,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.0198019801980198) internal successors, (103), 100 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:04,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 103 transitions. [2021-10-21 19:06:04,553 INFO L704 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2021-10-21 19:06:04,553 INFO L587 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2021-10-21 19:06:04,553 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-10-21 19:06:04,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 103 transitions. [2021-10-21 19:06:04,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:04,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:06:04,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:06:04,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [49, 48, 1] [2021-10-21 19:06:04,555 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:06:04,555 INFO L791 eck$LassoCheckResult]: Stem: 14559#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 14555#L12-2 assume !!(main_~i~0 < main_~j~0); 14556#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14557#L12-2 assume !!(main_~i~0 < main_~j~0); 14558#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14562#L12-2 assume !!(main_~i~0 < main_~j~0); 14655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14654#L12-2 assume !!(main_~i~0 < main_~j~0); 14653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14652#L12-2 assume !!(main_~i~0 < main_~j~0); 14651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14650#L12-2 assume !!(main_~i~0 < main_~j~0); 14649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14648#L12-2 assume !!(main_~i~0 < main_~j~0); 14647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14646#L12-2 assume !!(main_~i~0 < main_~j~0); 14645#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14644#L12-2 assume !!(main_~i~0 < main_~j~0); 14643#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14642#L12-2 assume !!(main_~i~0 < main_~j~0); 14641#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14640#L12-2 assume !!(main_~i~0 < main_~j~0); 14639#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14638#L12-2 assume !!(main_~i~0 < main_~j~0); 14637#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14636#L12-2 assume !!(main_~i~0 < main_~j~0); 14635#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14634#L12-2 assume !!(main_~i~0 < main_~j~0); 14633#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14632#L12-2 assume !!(main_~i~0 < main_~j~0); 14631#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14630#L12-2 assume !!(main_~i~0 < main_~j~0); 14629#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14628#L12-2 assume !!(main_~i~0 < main_~j~0); 14627#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14626#L12-2 assume !!(main_~i~0 < main_~j~0); 14625#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14624#L12-2 assume !!(main_~i~0 < main_~j~0); 14623#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14622#L12-2 assume !!(main_~i~0 < main_~j~0); 14621#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14620#L12-2 assume !!(main_~i~0 < main_~j~0); 14619#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14618#L12-2 assume !!(main_~i~0 < main_~j~0); 14617#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14616#L12-2 assume !!(main_~i~0 < main_~j~0); 14615#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14614#L12-2 assume !!(main_~i~0 < main_~j~0); 14613#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14612#L12-2 assume !!(main_~i~0 < main_~j~0); 14611#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14610#L12-2 assume !!(main_~i~0 < main_~j~0); 14609#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14608#L12-2 assume !!(main_~i~0 < main_~j~0); 14607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14606#L12-2 assume !!(main_~i~0 < main_~j~0); 14605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14604#L12-2 assume !!(main_~i~0 < main_~j~0); 14603#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14602#L12-2 assume !!(main_~i~0 < main_~j~0); 14601#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14600#L12-2 assume !!(main_~i~0 < main_~j~0); 14599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14598#L12-2 assume !!(main_~i~0 < main_~j~0); 14597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14596#L12-2 assume !!(main_~i~0 < main_~j~0); 14595#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14594#L12-2 assume !!(main_~i~0 < main_~j~0); 14593#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14592#L12-2 assume !!(main_~i~0 < main_~j~0); 14591#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14590#L12-2 assume !!(main_~i~0 < main_~j~0); 14589#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14588#L12-2 assume !!(main_~i~0 < main_~j~0); 14587#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14586#L12-2 assume !!(main_~i~0 < main_~j~0); 14585#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14584#L12-2 assume !!(main_~i~0 < main_~j~0); 14583#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14582#L12-2 assume !!(main_~i~0 < main_~j~0); 14581#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14580#L12-2 assume !!(main_~i~0 < main_~j~0); 14579#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14578#L12-2 assume !!(main_~i~0 < main_~j~0); 14577#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14576#L12-2 assume !!(main_~i~0 < main_~j~0); 14575#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14574#L12-2 assume !!(main_~i~0 < main_~j~0); 14573#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14572#L12-2 assume !!(main_~i~0 < main_~j~0); 14571#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14570#L12-2 assume !!(main_~i~0 < main_~j~0); 14569#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14568#L12-2 assume !!(main_~i~0 < main_~j~0); 14566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14565#L12-2 assume !!(main_~i~0 < main_~j~0); 14564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14563#L12-2 assume !!(main_~i~0 < main_~j~0); 14560#L12 [2021-10-21 19:06:04,555 INFO L793 eck$LassoCheckResult]: Loop: 14560#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 14561#L12-2 assume !!(main_~i~0 < main_~j~0); 14564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14563#L12-2 assume !!(main_~i~0 < main_~j~0); 14560#L12 [2021-10-21 19:06:04,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:04,555 INFO L82 PathProgramCache]: Analyzing trace with hash -1241577638, now seen corresponding path program 48 times [2021-10-21 19:06:04,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:04,555 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541578699] [2021-10-21 19:06:04,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:04,556 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:04,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:04,597 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:04,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:04,623 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:04,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:04,624 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 46 times [2021-10-21 19:06:04,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:04,624 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706082837] [2021-10-21 19:06:04,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:04,625 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:04,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:04,633 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:04,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:04,634 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:04,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:04,635 INFO L82 PathProgramCache]: Analyzing trace with hash 102679314, now seen corresponding path program 48 times [2021-10-21 19:06:04,635 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:04,635 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332785833] [2021-10-21 19:06:04,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:04,635 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:04,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-21 19:06:05,577 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:05,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-21 19:06:05,577 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332785833] [2021-10-21 19:06:05,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332785833] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:05,577 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1173199155] [2021-10-21 19:06:05,577 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-21 19:06:05,578 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-21 19:06:05,578 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 [2021-10-21 19:06:05,579 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-21 19:06:05,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2021-10-21 19:06:06,464 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2021-10-21 19:06:06,464 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-21 19:06:06,466 INFO L263 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 50 conjunts are in the unsatisfiable core [2021-10-21 19:06:06,468 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-21 19:06:06,728 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-21 19:06:06,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1173199155] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-21 19:06:06,729 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-21 19:06:06,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2021-10-21 19:06:06,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1819188436] [2021-10-21 19:06:06,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-21 19:06:06,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-10-21 19:06:06,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2021-10-21 19:06:06,765 INFO L87 Difference]: Start difference. First operand 101 states and 103 transitions. cyclomatic complexity: 3 Second operand has 51 states, 51 states have (on average 1.9803921568627452) internal successors, (101), 50 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:06,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-21 19:06:06,862 INFO L93 Difference]: Finished difference Result 105 states and 107 transitions. [2021-10-21 19:06:06,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2021-10-21 19:06:06,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 107 transitions. [2021-10-21 19:06:06,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:06,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 106 transitions. [2021-10-21 19:06:06,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-21 19:06:06,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-21 19:06:06,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 106 transitions. [2021-10-21 19:06:06,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-21 19:06:06,864 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 106 transitions. [2021-10-21 19:06:06,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 106 transitions. [2021-10-21 19:06:06,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 103. [2021-10-21 19:06:06,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.0194174757281553) internal successors, (105), 102 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-21 19:06:06,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 105 transitions. [2021-10-21 19:06:06,867 INFO L704 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2021-10-21 19:06:06,867 INFO L587 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2021-10-21 19:06:06,867 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-10-21 19:06:06,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 105 transitions. [2021-10-21 19:06:06,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-21 19:06:06,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-21 19:06:06,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-21 19:06:06,868 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [50, 49, 1] [2021-10-21 19:06:06,868 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-21 19:06:06,868 INFO L791 eck$LassoCheckResult]: Stem: 15124#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 15120#L12-2 assume !!(main_~i~0 < main_~j~0); 15121#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15122#L12-2 assume !!(main_~i~0 < main_~j~0); 15123#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15127#L12-2 assume !!(main_~i~0 < main_~j~0); 15222#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15221#L12-2 assume !!(main_~i~0 < main_~j~0); 15220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15219#L12-2 assume !!(main_~i~0 < main_~j~0); 15218#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15217#L12-2 assume !!(main_~i~0 < main_~j~0); 15216#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15215#L12-2 assume !!(main_~i~0 < main_~j~0); 15214#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15213#L12-2 assume !!(main_~i~0 < main_~j~0); 15212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15211#L12-2 assume !!(main_~i~0 < main_~j~0); 15210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15209#L12-2 assume !!(main_~i~0 < main_~j~0); 15208#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15207#L12-2 assume !!(main_~i~0 < main_~j~0); 15206#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15205#L12-2 assume !!(main_~i~0 < main_~j~0); 15204#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15203#L12-2 assume !!(main_~i~0 < main_~j~0); 15202#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15201#L12-2 assume !!(main_~i~0 < main_~j~0); 15200#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15199#L12-2 assume !!(main_~i~0 < main_~j~0); 15198#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15197#L12-2 assume !!(main_~i~0 < main_~j~0); 15196#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15195#L12-2 assume !!(main_~i~0 < main_~j~0); 15194#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15193#L12-2 assume !!(main_~i~0 < main_~j~0); 15192#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15191#L12-2 assume !!(main_~i~0 < main_~j~0); 15190#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15189#L12-2 assume !!(main_~i~0 < main_~j~0); 15188#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15187#L12-2 assume !!(main_~i~0 < main_~j~0); 15186#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15185#L12-2 assume !!(main_~i~0 < main_~j~0); 15184#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15183#L12-2 assume !!(main_~i~0 < main_~j~0); 15182#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15181#L12-2 assume !!(main_~i~0 < main_~j~0); 15180#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15179#L12-2 assume !!(main_~i~0 < main_~j~0); 15178#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15177#L12-2 assume !!(main_~i~0 < main_~j~0); 15176#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15175#L12-2 assume !!(main_~i~0 < main_~j~0); 15174#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15173#L12-2 assume !!(main_~i~0 < main_~j~0); 15172#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15171#L12-2 assume !!(main_~i~0 < main_~j~0); 15170#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15169#L12-2 assume !!(main_~i~0 < main_~j~0); 15168#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15167#L12-2 assume !!(main_~i~0 < main_~j~0); 15166#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15165#L12-2 assume !!(main_~i~0 < main_~j~0); 15164#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15163#L12-2 assume !!(main_~i~0 < main_~j~0); 15162#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15161#L12-2 assume !!(main_~i~0 < main_~j~0); 15160#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15159#L12-2 assume !!(main_~i~0 < main_~j~0); 15158#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15157#L12-2 assume !!(main_~i~0 < main_~j~0); 15156#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15155#L12-2 assume !!(main_~i~0 < main_~j~0); 15154#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15153#L12-2 assume !!(main_~i~0 < main_~j~0); 15152#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15151#L12-2 assume !!(main_~i~0 < main_~j~0); 15150#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15149#L12-2 assume !!(main_~i~0 < main_~j~0); 15148#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15147#L12-2 assume !!(main_~i~0 < main_~j~0); 15146#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15145#L12-2 assume !!(main_~i~0 < main_~j~0); 15144#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15143#L12-2 assume !!(main_~i~0 < main_~j~0); 15142#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15141#L12-2 assume !!(main_~i~0 < main_~j~0); 15140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15139#L12-2 assume !!(main_~i~0 < main_~j~0); 15138#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15137#L12-2 assume !!(main_~i~0 < main_~j~0); 15136#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15135#L12-2 assume !!(main_~i~0 < main_~j~0); 15134#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15133#L12-2 assume !!(main_~i~0 < main_~j~0); 15131#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15130#L12-2 assume !!(main_~i~0 < main_~j~0); 15129#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15128#L12-2 assume !!(main_~i~0 < main_~j~0); 15125#L12 [2021-10-21 19:06:06,868 INFO L793 eck$LassoCheckResult]: Loop: 15125#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 15126#L12-2 assume !!(main_~i~0 < main_~j~0); 15129#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15128#L12-2 assume !!(main_~i~0 < main_~j~0); 15125#L12 [2021-10-21 19:06:06,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:06,869 INFO L82 PathProgramCache]: Analyzing trace with hash 844798583, now seen corresponding path program 49 times [2021-10-21 19:06:06,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:06,869 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242564565] [2021-10-21 19:06:06,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:06,869 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:06,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:06,900 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:06,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:06,926 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:06,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:06,927 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 47 times [2021-10-21 19:06:06,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:06,927 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972090999] [2021-10-21 19:06:06,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:06,927 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:06,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:06,938 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:06,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:06,939 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:06,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-21 19:06:06,940 INFO L82 PathProgramCache]: Analyzing trace with hash -166625361, now seen corresponding path program 49 times [2021-10-21 19:06:06,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-21 19:06:06,940 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602840649] [2021-10-21 19:06:06,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-21 19:06:06,940 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-21 19:06:07,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:07,109 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-21 19:06:07,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-21 19:06:07,137 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-21 19:06:09,454 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.10 07:06:09 BoogieIcfgContainer [2021-10-21 19:06:09,454 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-21 19:06:09,455 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-21 19:06:09,455 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-21 19:06:09,455 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-21 19:06:09,455 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.10 07:05:08" (3/4) ... [2021-10-21 19:06:09,457 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-21 19:06:09,510 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/witness.graphml [2021-10-21 19:06:09,510 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-21 19:06:09,511 INFO L168 Benchmark]: Toolchain (without parser) took 61115.41 ms. Allocated memory was 109.1 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 75.2 MB in the beginning and 390.4 MB in the end (delta: -315.2 MB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. [2021-10-21 19:06:09,512 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 79.7 MB. Free memory was 50.1 MB in the beginning and 50.1 MB in the end (delta: 26.8 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-21 19:06:09,512 INFO L168 Benchmark]: CACSL2BoogieTranslator took 212.65 ms. Allocated memory is still 109.1 MB. Free memory was 75.2 MB in the beginning and 87.4 MB in the end (delta: -12.2 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-21 19:06:09,513 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.12 ms. Allocated memory is still 109.1 MB. Free memory was 87.4 MB in the beginning and 85.9 MB in the end (delta: 1.6 MB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-21 19:06:09,513 INFO L168 Benchmark]: Boogie Preprocessor took 27.56 ms. Allocated memory is still 109.1 MB. Free memory was 85.9 MB in the beginning and 85.4 MB in the end (delta: 498.4 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-21 19:06:09,513 INFO L168 Benchmark]: RCFGBuilder took 248.78 ms. Allocated memory is still 109.1 MB. Free memory was 85.4 MB in the beginning and 77.5 MB in the end (delta: 7.9 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-21 19:06:09,514 INFO L168 Benchmark]: BuchiAutomizer took 60512.91 ms. Allocated memory was 109.1 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 77.5 MB in the beginning and 393.5 MB in the end (delta: -316.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. [2021-10-21 19:06:09,514 INFO L168 Benchmark]: Witness Printer took 55.47 ms. Allocated memory is still 1.5 GB. Free memory was 393.5 MB in the beginning and 390.4 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-21 19:06:09,516 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 79.7 MB. Free memory was 50.1 MB in the beginning and 50.1 MB in the end (delta: 26.8 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 212.65 ms. Allocated memory is still 109.1 MB. Free memory was 75.2 MB in the beginning and 87.4 MB in the end (delta: -12.2 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 37.12 ms. Allocated memory is still 109.1 MB. Free memory was 87.4 MB in the beginning and 85.9 MB in the end (delta: 1.6 MB). There was no memory consumed. Max. memory is 16.1 GB. * Boogie Preprocessor took 27.56 ms. Allocated memory is still 109.1 MB. Free memory was 85.9 MB in the beginning and 85.4 MB in the end (delta: 498.4 kB). There was no memory consumed. Max. memory is 16.1 GB. * RCFGBuilder took 248.78 ms. Allocated memory is still 109.1 MB. Free memory was 85.4 MB in the beginning and 77.5 MB in the end (delta: 7.9 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 60512.91 ms. Allocated memory was 109.1 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 77.5 MB in the beginning and 393.5 MB in the end (delta: -316.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. * Witness Printer took 55.47 ms. Allocated memory is still 1.5 GB. Free memory was 393.5 MB in the beginning and 390.4 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 53 terminating modules (49 trivial, 2 deterministic, 2 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function j and consists of 4 locations. One deterministic module has affine ranking function j and consists of 3 locations. One nondeterministic module has affine ranking function j and consists of 3 locations. One nondeterministic module has affine ranking function 103 + -2 * j and consists of 3 locations. 49 modules have a trivial ranking function, the largest among these consists of 51 locations. The remainder module has 103 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 60.4s and 51 iterations. TraceHistogramMax:50. Analysis of lassos took 55.7s. Construction of modules took 2.2s. Büchi inclusion checks took 1.8s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 53. Automata minimization 156.3ms AutomataMinimizationTime, 53 MinimizatonAttempts, 57 StatesRemovedByMinimization, 51 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 103 states and ocurred in iteration 50. Nontrivial modules had stage [2, 0, 2, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 126 SDtfs, 29 SDslu, 3 SDs, 0 SdLazy, 2770 SolverSat, 171 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2261.1ms Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc46 concLT1 SILN0 SILU0 SILI0 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital18 mio100 ax166 hnf100 lsp59 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq166 hnf93 smp100 dnf100 smp100 tf107 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 60ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 5 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.6s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 12]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, i=49, j=51} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 12]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int j; [L8] j = 100 [L9] i = 0 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j Loop: [L12] COND FALSE !(51 < j) [L13] i = i-1 [L13] j = j+1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-21 19:06:09,582 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:09,792 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Ended with exit code 0 [2021-10-21 19:06:09,991 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Ended with exit code 0 [2021-10-21 19:06:10,192 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Ended with exit code 0 [2021-10-21 19:06:10,391 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Ended with exit code 0 [2021-10-21 19:06:10,591 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2021-10-21 19:06:10,792 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Ended with exit code 0 [2021-10-21 19:06:10,993 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2021-10-21 19:06:11,192 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2021-10-21 19:06:11,393 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2021-10-21 19:06:11,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:11,792 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Ended with exit code 0 [2021-10-21 19:06:11,994 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:12,193 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Ended with exit code 0 [2021-10-21 19:06:12,393 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2021-10-21 19:06:12,593 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2021-10-21 19:06:12,793 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:12,993 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2021-10-21 19:06:13,194 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:13,393 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2021-10-21 19:06:13,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:13,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2021-10-21 19:06:13,994 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:14,198 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Ended with exit code 0 [2021-10-21 19:06:14,394 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2021-10-21 19:06:14,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:14,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2021-10-21 19:06:14,994 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2021-10-21 19:06:15,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2021-10-21 19:06:15,395 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:15,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2021-10-21 19:06:15,802 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:15,995 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2021-10-21 19:06:16,196 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:16,396 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Ended with exit code 0 [2021-10-21 19:06:16,596 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2021-10-21 19:06:16,796 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2021-10-21 19:06:16,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2021-10-21 19:06:17,197 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:17,397 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2021-10-21 19:06:17,597 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2021-10-21 19:06:17,796 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2021-10-21 19:06:17,997 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2021-10-21 19:06:18,199 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2021-10-21 19:06:18,398 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:18,598 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2021-10-21 19:06:18,798 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2021-10-21 19:06:18,998 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2021-10-21 19:06:19,203 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0622703-f05d-4d1a-ae0e-3c33887bcafa/bin/uautomizer-j4sWxH34Be/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...