./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NO_22.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NO_22.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2aebec197cf7bd355d2eb5f718c983de149eae8f5ff2da107813d58a220d4744 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 08:59:37,690 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 08:59:37,694 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 08:59:37,749 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 08:59:37,750 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 08:59:37,756 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 08:59:37,760 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 08:59:37,766 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 08:59:37,770 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 08:59:37,777 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 08:59:37,779 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 08:59:37,781 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 08:59:37,782 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 08:59:37,786 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 08:59:37,789 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 08:59:37,792 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 08:59:37,795 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 08:59:37,797 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 08:59:37,803 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 08:59:37,814 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 08:59:37,817 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 08:59:37,819 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 08:59:37,824 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 08:59:37,825 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 08:59:37,838 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 08:59:37,838 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 08:59:37,839 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 08:59:37,842 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 08:59:37,843 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 08:59:37,846 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 08:59:37,846 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 08:59:37,848 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 08:59:37,851 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 08:59:37,853 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 08:59:37,855 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 08:59:37,856 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 08:59:37,857 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 08:59:37,858 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 08:59:37,858 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 08:59:37,860 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 08:59:37,861 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 08:59:37,862 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-10-28 08:59:37,928 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 08:59:37,928 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 08:59:37,929 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 08:59:37,929 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 08:59:37,931 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 08:59:37,932 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 08:59:37,932 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 08:59:37,932 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 08:59:37,933 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 08:59:37,933 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 08:59:37,933 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 08:59:37,933 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 08:59:37,934 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 08:59:37,934 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 08:59:37,934 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 08:59:37,934 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 08:59:37,935 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 08:59:37,935 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 08:59:37,935 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 08:59:37,936 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 08:59:37,936 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 08:59:37,936 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 08:59:37,936 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 08:59:37,937 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 08:59:37,937 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 08:59:37,937 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 08:59:37,937 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 08:59:37,938 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 08:59:37,938 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 08:59:37,939 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 08:59:37,940 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2aebec197cf7bd355d2eb5f718c983de149eae8f5ff2da107813d58a220d4744 [2021-10-28 08:59:38,340 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 08:59:38,394 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 08:59:38,398 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 08:59:38,401 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 08:59:38,402 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 08:59:38,403 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/termination-restricted-15/NO_22.c [2021-10-28 08:59:38,529 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/data/01d8cff78/493168aedfc34754831f17967b3a4ad7/FLAGf0e00a593 [2021-10-28 08:59:39,074 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 08:59:39,075 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/sv-benchmarks/c/termination-restricted-15/NO_22.c [2021-10-28 08:59:39,082 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/data/01d8cff78/493168aedfc34754831f17967b3a4ad7/FLAGf0e00a593 [2021-10-28 08:59:39,420 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/data/01d8cff78/493168aedfc34754831f17967b3a4ad7 [2021-10-28 08:59:39,423 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 08:59:39,426 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 08:59:39,436 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 08:59:39,437 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 08:59:39,446 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 08:59:39,447 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,449 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a343dd2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39, skipping insertion in model container [2021-10-28 08:59:39,449 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,462 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 08:59:39,481 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 08:59:39,665 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 08:59:39,674 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 08:59:39,707 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 08:59:39,721 INFO L208 MainTranslator]: Completed translation [2021-10-28 08:59:39,721 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39 WrapperNode [2021-10-28 08:59:39,722 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 08:59:39,723 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 08:59:39,723 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 08:59:39,723 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 08:59:39,733 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,740 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,761 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 08:59:39,762 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 08:59:39,763 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 08:59:39,763 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 08:59:39,775 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,775 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,776 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,776 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,778 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,784 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,785 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,786 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 08:59:39,787 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 08:59:39,788 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 08:59:39,788 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 08:59:39,791 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (1/1) ... [2021-10-28 08:59:39,803 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:39,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:39,836 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:39,862 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 08:59:39,901 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 08:59:39,902 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 08:59:40,056 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 08:59:40,057 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2021-10-28 08:59:40,059 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:59:40 BoogieIcfgContainer [2021-10-28 08:59:40,060 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 08:59:40,061 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 08:59:40,061 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 08:59:40,064 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 08:59:40,064 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:59:40,065 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 08:59:39" (1/3) ... [2021-10-28 08:59:40,066 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8d84e3e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 08:59:40, skipping insertion in model container [2021-10-28 08:59:40,066 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:59:40,066 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:59:39" (2/3) ... [2021-10-28 08:59:40,067 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8d84e3e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 08:59:40, skipping insertion in model container [2021-10-28 08:59:40,067 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:59:40,067 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:59:40" (3/3) ... [2021-10-28 08:59:40,069 INFO L389 chiAutomizerObserver]: Analyzing ICFG NO_22.c [2021-10-28 08:59:40,126 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 08:59:40,126 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 08:59:40,126 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 08:59:40,126 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 08:59:40,127 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 08:59:40,127 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 08:59:40,127 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 08:59:40,127 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 08:59:40,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:40,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:40,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:40,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:40,175 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-28 08:59:40,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 08:59:40,175 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 08:59:40,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:40,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:40,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:40,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:40,178 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-28 08:59:40,178 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 08:59:40,186 INFO L791 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 4#L10-2true [2021-10-28 08:59:40,187 INFO L793 eck$LassoCheckResult]: Loop: 4#L10-2true assume !!(main_~i~0 < 100); 6#L10true assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4#L10-2true [2021-10-28 08:59:40,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:40,195 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2021-10-28 08:59:40,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:40,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270119039] [2021-10-28 08:59:40,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:40,209 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:40,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,306 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:40,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,329 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:40,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:40,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 1 times [2021-10-28 08:59:40,333 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:40,334 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366256086] [2021-10-28 08:59:40,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:40,335 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:40,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,348 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:40,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,355 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:40,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:40,357 INFO L85 PathProgramCache]: Analyzing trace with hash 31075, now seen corresponding path program 1 times [2021-10-28 08:59:40,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:40,358 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358966984] [2021-10-28 08:59:40,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:40,359 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:40,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,369 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:40,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:40,376 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:40,457 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:40,458 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:40,459 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:40,459 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:40,459 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 08:59:40,459 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:40,459 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:40,460 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:40,460 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration1_Loop [2021-10-28 08:59:40,460 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:40,460 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:40,484 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:40,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:40,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:40,603 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:40,604 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 08:59:40,607 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:40,607 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:40,610 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:40,668 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-10-28 08:59:40,670 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:40,670 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:40,703 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 08:59:40,704 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 08:59:40,737 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:40,738 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:40,738 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:40,740 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:40,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-10-28 08:59:40,752 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:40,752 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:40,786 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 08:59:40,786 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 08:59:40,834 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:40,835 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:40,835 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:40,847 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:40,856 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:40,856 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:40,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-10-28 08:59:40,917 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2021-10-28 08:59:40,918 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:40,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:40,919 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:40,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-10-28 08:59:40,936 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 08:59:40,937 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:40,996 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 08:59:41,012 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:41,012 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:41,013 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:41,013 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:41,013 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:41,013 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 08:59:41,014 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,014 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:41,014 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:41,014 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration1_Loop [2021-10-28 08:59:41,014 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:41,014 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:41,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,023 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,042 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,112 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:41,118 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 08:59:41,119 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,120 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,121 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,128 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 08:59:41,140 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 08:59:41,140 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 08:59:41,140 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 08:59:41,141 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 08:59:41,148 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 08:59:41,149 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 08:59:41,152 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-10-28 08:59:41,173 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 08:59:41,198 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:41,199 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,199 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,200 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,203 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-10-28 08:59:41,204 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 08:59:41,215 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 08:59:41,215 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 08:59:41,215 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 08:59:41,216 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 08:59:41,216 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 08:59:41,221 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 08:59:41,221 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 08:59:41,243 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 08:59:41,247 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 08:59:41,247 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 08:59:41,249 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,250 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,259 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-10-28 08:59:41,266 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 08:59:41,267 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 08:59:41,267 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 08:59:41,268 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0) = -2*ULTIMATE.start_main_~i~0 + 99 Supporting invariants [] [2021-10-28 08:59:41,311 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:41,314 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 08:59:41,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:41,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:41,354 WARN L261 TraceCheckSpWp]: Trace formula consists of 4 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:41,355 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:41,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:41,367 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:41,367 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:41,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:41,431 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-28 08:59:41,433 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:41,510 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 23 states and 30 transitions. Complement of second has 6 states. [2021-10-28 08:59:41,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:41,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:41,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2021-10-28 08:59:41,519 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 2 letters. [2021-10-28 08:59:41,520 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:41,520 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 3 letters. Loop has 2 letters. [2021-10-28 08:59:41,521 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:41,521 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 4 letters. [2021-10-28 08:59:41,521 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:41,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 30 transitions. [2021-10-28 08:59:41,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:41,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 7 states and 10 transitions. [2021-10-28 08:59:41,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2021-10-28 08:59:41,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 08:59:41,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 10 transitions. [2021-10-28 08:59:41,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:41,547 INFO L681 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 08:59:41,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 10 transitions. [2021-10-28 08:59:41,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2021-10-28 08:59:41,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 6 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:41,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 10 transitions. [2021-10-28 08:59:41,583 INFO L704 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 08:59:41,583 INFO L587 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 08:59:41,583 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 08:59:41,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 10 transitions. [2021-10-28 08:59:41,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:41,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:41,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:41,585 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] [2021-10-28 08:59:41,585 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 08:59:41,585 INFO L791 eck$LassoCheckResult]: Stem: 68#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 69#L10-2 assume !!(main_~i~0 < 100); 67#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 63#L10-2 [2021-10-28 08:59:41,586 INFO L793 eck$LassoCheckResult]: Loop: 63#L10-2 assume !!(main_~i~0 < 100); 64#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 63#L10-2 [2021-10-28 08:59:41,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:41,586 INFO L85 PathProgramCache]: Analyzing trace with hash 31077, now seen corresponding path program 1 times [2021-10-28 08:59:41,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:41,587 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096196043] [2021-10-28 08:59:41,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:41,588 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:41,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:41,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:41,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:41,632 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096196043] [2021-10-28 08:59:41,633 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096196043] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:59:41,633 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:59:41,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2021-10-28 08:59:41,634 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396332008] [2021-10-28 08:59:41,637 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:59:41,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:41,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 2 times [2021-10-28 08:59:41,638 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:41,638 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456915066] [2021-10-28 08:59:41,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:41,639 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:41,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:41,645 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:41,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:41,650 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:41,675 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:41,675 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:41,676 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:41,676 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:41,676 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 08:59:41,676 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,676 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:41,677 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:41,677 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration2_Loop [2021-10-28 08:59:41,677 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:41,677 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:41,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,696 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,771 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:41,771 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 08:59:41,771 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,772 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,775 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:41,775 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:41,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-10-28 08:59:41,796 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 08:59:41,796 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 08:59:41,820 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-10-28 08:59:41,821 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,821 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,822 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,823 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-10-28 08:59:41,827 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:41,827 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:41,867 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-10-28 08:59:41,867 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:41,899 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:41,900 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-10-28 08:59:41,904 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 08:59:41,904 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:41,954 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 08:59:41,961 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:41,962 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:41,962 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:41,962 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:41,962 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:41,962 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 08:59:41,962 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:41,962 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:41,962 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:41,962 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration2_Loop [2021-10-28 08:59:41,962 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:41,963 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:41,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:41,984 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,028 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:42,029 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 08:59:42,029 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,029 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,031 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,039 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 08:59:42,051 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 08:59:42,051 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 08:59:42,051 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 08:59:42,052 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 08:59:42,052 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 08:59:42,053 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 08:59:42,054 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 08:59:42,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-10-28 08:59:42,070 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 08:59:42,075 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 08:59:42,075 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 08:59:42,075 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,078 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-10-28 08:59:42,083 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 08:59:42,084 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 08:59:42,084 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 08:59:42,084 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0) = -2*ULTIMATE.start_main_~i~0 + 99 Supporting invariants [] [2021-10-28 08:59:42,127 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:42,127 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 08:59:42,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:42,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:42,163 INFO L263 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:42,165 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:42,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:42,192 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:42,193 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:42,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:42,210 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-28 08:59:42,210 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:42,226 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 16 transitions. Complement of second has 5 states. [2021-10-28 08:59:42,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:42,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:42,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-28 08:59:42,227 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 2 letters. [2021-10-28 08:59:42,228 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:42,228 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 5 letters. Loop has 2 letters. [2021-10-28 08:59:42,228 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:42,228 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 4 letters. [2021-10-28 08:59:42,229 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:42,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 16 transitions. [2021-10-28 08:59:42,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:42,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 16 transitions. [2021-10-28 08:59:42,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-10-28 08:59:42,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 08:59:42,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 16 transitions. [2021-10-28 08:59:42,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:42,232 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2021-10-28 08:59:42,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 16 transitions. [2021-10-28 08:59:42,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2021-10-28 08:59:42,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 10 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:42,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 16 transitions. [2021-10-28 08:59:42,240 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2021-10-28 08:59:42,241 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:42,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:59:42,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:59:42,249 INFO L87 Difference]: Start difference. First operand 11 states and 16 transitions. Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:42,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:42,265 INFO L93 Difference]: Finished difference Result 13 states and 17 transitions. [2021-10-28 08:59:42,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:59:42,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 17 transitions. [2021-10-28 08:59:42,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:42,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 16 transitions. [2021-10-28 08:59:42,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-10-28 08:59:42,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 08:59:42,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 16 transitions. [2021-10-28 08:59:42,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:42,272 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-10-28 08:59:42,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 16 transitions. [2021-10-28 08:59:42,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2021-10-28 08:59:42,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:42,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2021-10-28 08:59:42,280 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2021-10-28 08:59:42,280 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2021-10-28 08:59:42,280 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 08:59:42,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2021-10-28 08:59:42,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 08:59:42,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:42,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:42,282 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1, 1] [2021-10-28 08:59:42,282 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 08:59:42,282 INFO L791 eck$LassoCheckResult]: Stem: 144#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 139#L10-2 assume !!(main_~i~0 < 100); 140#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 149#L10-2 assume !!(main_~i~0 < 100); 148#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 146#L10-2 assume !!(main_~i~0 < 100); 142#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 145#L10-2 [2021-10-28 08:59:42,282 INFO L793 eck$LassoCheckResult]: Loop: 145#L10-2 assume !!(main_~i~0 < 100); 147#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 145#L10-2 [2021-10-28 08:59:42,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:42,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1366043347, now seen corresponding path program 1 times [2021-10-28 08:59:42,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:42,283 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059738366] [2021-10-28 08:59:42,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:42,284 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:42,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:42,347 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:42,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:42,348 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059738366] [2021-10-28 08:59:42,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059738366] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:42,349 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1530046725] [2021-10-28 08:59:42,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:42,349 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:42,349 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,363 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,396 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2021-10-28 08:59:42,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-10-28 08:59:42,440 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:42,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:42,465 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 3 conjunts are in the unsatisfiable core [2021-10-28 08:59:42,466 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:42,526 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:42,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1530046725] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:42,527 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:42,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2021-10-28 08:59:42,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642347170] [2021-10-28 08:59:42,528 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:59:42,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:42,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 3 times [2021-10-28 08:59:42,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:42,529 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816130072] [2021-10-28 08:59:42,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:42,529 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:42,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:42,535 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:42,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:42,539 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:42,560 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:42,561 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:42,561 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:42,561 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:42,561 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 08:59:42,561 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,561 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:42,562 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:42,562 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration3_Loop [2021-10-28 08:59:42,562 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:42,562 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:42,564 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,567 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,574 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,611 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:42,611 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 08:59:42,612 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,612 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,613 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,627 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:42,628 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:42,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-10-28 08:59:42,654 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 08:59:42,655 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 08:59:42,701 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:42,701 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,701 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,702 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,707 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:42,707 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:42,720 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-10-28 08:59:42,761 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:42,761 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,762 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2021-10-28 08:59:42,764 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 08:59:42,764 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:42,838 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 08:59:42,849 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:42,849 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:42,849 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:42,849 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:42,849 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:42,849 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 08:59:42,849 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,850 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:42,850 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:42,850 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration3_Loop [2021-10-28 08:59:42,850 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:42,850 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:42,851 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,867 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,871 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:42,927 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:42,927 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 08:59:42,927 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,929 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,933 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 08:59:42,946 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 08:59:42,946 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 08:59:42,946 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 08:59:42,946 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 08:59:42,946 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 08:59:42,949 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 08:59:42,949 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 08:59:42,953 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-10-28 08:59:42,962 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 08:59:42,965 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 08:59:42,965 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 08:59:42,965 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:42,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:42,971 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:42,978 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 08:59:42,978 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 08:59:42,978 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 08:59:42,978 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0) = -2*ULTIMATE.start_main_~i~0 + 99 Supporting invariants [] [2021-10-28 08:59:42,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2021-10-28 08:59:43,020 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:43,021 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 08:59:43,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,120 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,121 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:43,131 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-28 08:59:43,132 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,143 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 13 states and 19 transitions. Complement of second has 5 states. [2021-10-28 08:59:43,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:43,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-28 08:59:43,145 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-28 08:59:43,145 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:43,145 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 08:59:43,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,169 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,170 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,206 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,207 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:43,219 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-28 08:59:43,220 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,234 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 13 states and 19 transitions. Complement of second has 5 states. [2021-10-28 08:59:43,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:43,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2021-10-28 08:59:43,235 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-28 08:59:43,236 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:43,236 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 08:59:43,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,262 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,263 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,292 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,293 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:43,310 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2021-10-28 08:59:43,310 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,329 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 15 states and 22 transitions. Complement of second has 4 states. [2021-10-28 08:59:43,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:43,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 7 transitions. [2021-10-28 08:59:43,331 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 2 letters. [2021-10-28 08:59:43,331 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:43,331 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 9 letters. Loop has 2 letters. [2021-10-28 08:59:43,332 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:43,332 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 4 letters. [2021-10-28 08:59:43,333 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:43,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 22 transitions. [2021-10-28 08:59:43,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 08:59:43,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 13 states and 18 transitions. [2021-10-28 08:59:43,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 08:59:43,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 08:59:43,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 18 transitions. [2021-10-28 08:59:43,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:43,340 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 18 transitions. [2021-10-28 08:59:43,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 18 transitions. [2021-10-28 08:59:43,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 6. [2021-10-28 08:59:43,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.3333333333333333) internal successors, (8), 5 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 8 transitions. [2021-10-28 08:59:43,347 INFO L704 BuchiCegarLoop]: Abstraction has 6 states and 8 transitions. [2021-10-28 08:59:43,347 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:43,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 08:59:43,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 08:59:43,349 INFO L87 Difference]: Start difference. First operand 6 states and 8 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:43,372 INFO L93 Difference]: Finished difference Result 10 states and 12 transitions. [2021-10-28 08:59:43,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 08:59:43,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 12 transitions. [2021-10-28 08:59:43,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 08:59:43,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 9 states and 11 transitions. [2021-10-28 08:59:43,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2021-10-28 08:59:43,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4 [2021-10-28 08:59:43,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2021-10-28 08:59:43,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:43,376 INFO L681 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-10-28 08:59:43,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2021-10-28 08:59:43,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2021-10-28 08:59:43,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.25) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:43,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 10 transitions. [2021-10-28 08:59:43,381 INFO L704 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-10-28 08:59:43,381 INFO L587 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-10-28 08:59:43,382 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 08:59:43,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 10 transitions. [2021-10-28 08:59:43,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 08:59:43,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:43,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:43,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1] [2021-10-28 08:59:43,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 08:59:43,385 INFO L791 eck$LassoCheckResult]: Stem: 339#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 335#L10-2 assume !!(main_~i~0 < 100); 336#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 337#L10-2 assume !!(main_~i~0 < 100); 338#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 342#L10-2 assume !!(main_~i~0 < 100); 340#L10 [2021-10-28 08:59:43,385 INFO L793 eck$LassoCheckResult]: Loop: 340#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 341#L10-2 assume !!(main_~i~0 < 100); 340#L10 [2021-10-28 08:59:43,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,385 INFO L85 PathProgramCache]: Analyzing trace with hash 925765348, now seen corresponding path program 2 times [2021-10-28 08:59:43,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:43,386 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718216852] [2021-10-28 08:59:43,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:43,387 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:43,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:43,413 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:43,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:43,423 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:43,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1436, now seen corresponding path program 1 times [2021-10-28 08:59:43,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:43,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861182261] [2021-10-28 08:59:43,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:43,425 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:43,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:43,432 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:43,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:43,446 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:43,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:43,447 INFO L85 PathProgramCache]: Analyzing trace with hash 602269631, now seen corresponding path program 2 times [2021-10-28 08:59:43,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:43,448 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643663642] [2021-10-28 08:59:43,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:43,448 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:43,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:43,498 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:43,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:43,499 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643663642] [2021-10-28 08:59:43,500 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643663642] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:43,506 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [273494971] [2021-10-28 08:59:43,506 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 08:59:43,507 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:43,507 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:43,508 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:43,534 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-10-28 08:59:43,565 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 08:59:43,565 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:43,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:43,566 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:43,620 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:43,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [273494971] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:43,625 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:43,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2021-10-28 08:59:43,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071078901] [2021-10-28 08:59:43,655 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:43,655 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:43,655 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:43,656 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:43,656 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 08:59:43,656 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:43,656 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:43,656 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:43,656 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration4_Loop [2021-10-28 08:59:43,657 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:43,657 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:43,660 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,667 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,672 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,716 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:43,717 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 08:59:43,717 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:43,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:43,722 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:43,728 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 08:59:43,728 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:43,741 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2021-10-28 08:59:43,795 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:43,796 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:43,796 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:43,797 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:43,808 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 08:59:43,809 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 08:59:43,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2021-10-28 08:59:43,871 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 08:59:43,873 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:43,874 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 08:59:43,874 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 08:59:43,874 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 08:59:43,874 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 08:59:43,874 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 08:59:43,874 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:43,874 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 08:59:43,874 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 08:59:43,874 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_22.c_Iteration4_Loop [2021-10-28 08:59:43,874 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 08:59:43,875 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 08:59:43,876 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,889 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,893 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 08:59:43,963 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 08:59:43,964 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 08:59:43,964 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:43,965 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:43,966 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:43,974 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 08:59:43,985 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 08:59:43,986 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 08:59:43,986 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 08:59:43,986 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 08:59:43,986 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 08:59:43,988 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 08:59:43,988 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 08:59:43,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-10-28 08:59:43,999 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 08:59:44,015 INFO L443 ModelExtractionUtils]: Simplification made 2 calls to the SMT solver. [2021-10-28 08:59:44,015 INFO L444 ModelExtractionUtils]: 1 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 08:59:44,015 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:59:44,015 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:44,016 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:59:44,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-10-28 08:59:44,018 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 08:59:44,018 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 08:59:44,018 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 08:59:44,018 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0) = 1*ULTIMATE.start_main_~i~0 Supporting invariants [] [2021-10-28 08:59:44,042 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:44,043 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 08:59:44,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,074 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,075 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,106 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,107 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:44,148 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 08:59:44,148 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,155 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 8 states and 10 transitions. Complement of second has 3 states. [2021-10-28 08:59:44,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:44,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2021-10-28 08:59:44,158 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-28 08:59:44,158 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:44,158 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 08:59:44,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,180 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,180 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,202 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,202 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:44,239 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 08:59:44,240 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,249 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 8 states and 10 transitions. Complement of second has 3 states. [2021-10-28 08:59:44,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:44,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2021-10-28 08:59:44,255 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-28 08:59:44,255 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:44,255 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 08:59:44,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,275 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,276 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,300 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,300 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:59:44,329 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 08:59:44,330 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,345 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 12 states and 14 transitions. Complement of second has 4 states. [2021-10-28 08:59:44,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 08:59:44,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2021-10-28 08:59:44,370 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 2 letters. [2021-10-28 08:59:44,370 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:44,370 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 8 letters. Loop has 2 letters. [2021-10-28 08:59:44,370 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:44,371 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 4 letters. [2021-10-28 08:59:44,371 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 08:59:44,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 14 transitions. [2021-10-28 08:59:44,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2021-10-28 08:59:44,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 10 states and 12 transitions. [2021-10-28 08:59:44,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:44,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:44,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 12 transitions. [2021-10-28 08:59:44,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:44,390 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2021-10-28 08:59:44,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 12 transitions. [2021-10-28 08:59:44,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 9. [2021-10-28 08:59:44,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2021-10-28 08:59:44,394 INFO L704 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-10-28 08:59:44,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:44,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 08:59:44,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-10-28 08:59:44,397 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. Second operand has 5 states, 5 states have (on average 1.6) internal successors, (8), 4 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:44,412 INFO L93 Difference]: Finished difference Result 13 states and 15 transitions. [2021-10-28 08:59:44,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 08:59:44,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 15 transitions. [2021-10-28 08:59:44,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:44,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 14 transitions. [2021-10-28 08:59:44,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:44,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:44,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 14 transitions. [2021-10-28 08:59:44,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:44,417 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 14 transitions. [2021-10-28 08:59:44,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 14 transitions. [2021-10-28 08:59:44,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2021-10-28 08:59:44,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.1818181818181819) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 13 transitions. [2021-10-28 08:59:44,429 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2021-10-28 08:59:44,430 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2021-10-28 08:59:44,430 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 08:59:44,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 13 transitions. [2021-10-28 08:59:44,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:44,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:44,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:44,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 1] [2021-10-28 08:59:44,432 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:44,433 INFO L791 eck$LassoCheckResult]: Stem: 519#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 515#L10-2 assume !!(main_~i~0 < 100); 516#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 517#L10-2 assume !!(main_~i~0 < 100); 518#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 525#L10-2 assume !!(main_~i~0 < 100); 524#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 523#L10-2 assume !!(main_~i~0 < 100); 520#L10 [2021-10-28 08:59:44,433 INFO L793 eck$LassoCheckResult]: Loop: 520#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 521#L10-2 assume !!(main_~i~0 < 100); 524#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 523#L10-2 assume !!(main_~i~0 < 100); 520#L10 [2021-10-28 08:59:44,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,433 INFO L85 PathProgramCache]: Analyzing trace with hash 602269569, now seen corresponding path program 3 times [2021-10-28 08:59:44,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047277479] [2021-10-28 08:59:44,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,434 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,456 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:44,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,463 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:44,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,463 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 1 times [2021-10-28 08:59:44,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,464 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958563003] [2021-10-28 08:59:44,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,464 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,469 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:44,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,489 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:44,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,496 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:44,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1740322745, now seen corresponding path program 3 times [2021-10-28 08:59:44,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,500 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166197859] [2021-10-28 08:59:44,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,500 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,539 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2021-10-28 08:59:44,563 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:44,564 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:44,564 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166197859] [2021-10-28 08:59:44,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166197859] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:44,564 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [696131182] [2021-10-28 08:59:44,565 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 08:59:44,565 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:44,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:44,566 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:44,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-10-28 08:59:44,629 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2021-10-28 08:59:44,629 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:44,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 25 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,631 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:44,677 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:44,677 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [696131182] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:44,678 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:44,678 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2021-10-28 08:59:44,678 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456026870] [2021-10-28 08:59:44,717 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:44,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 08:59:44,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-10-28 08:59:44,718 INFO L87 Difference]: Start difference. First operand 11 states and 13 transitions. cyclomatic complexity: 3 Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:44,744 INFO L93 Difference]: Finished difference Result 15 states and 17 transitions. [2021-10-28 08:59:44,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 08:59:44,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 17 transitions. [2021-10-28 08:59:44,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:44,748 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 14 states and 16 transitions. [2021-10-28 08:59:44,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:44,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:44,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2021-10-28 08:59:44,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:44,749 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 16 transitions. [2021-10-28 08:59:44,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2021-10-28 08:59:44,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2021-10-28 08:59:44,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.1538461538461537) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:44,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2021-10-28 08:59:44,752 INFO L704 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2021-10-28 08:59:44,753 INFO L587 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2021-10-28 08:59:44,753 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 08:59:44,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2021-10-28 08:59:44,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:44,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:44,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:44,756 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 1] [2021-10-28 08:59:44,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:44,757 INFO L791 eck$LassoCheckResult]: Stem: 589#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 585#L10-2 assume !!(main_~i~0 < 100); 586#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 587#L10-2 assume !!(main_~i~0 < 100); 588#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 597#L10-2 assume !!(main_~i~0 < 100); 596#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 595#L10-2 assume !!(main_~i~0 < 100); 594#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 593#L10-2 assume !!(main_~i~0 < 100); 590#L10 [2021-10-28 08:59:44,757 INFO L793 eck$LassoCheckResult]: Loop: 590#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 591#L10-2 assume !!(main_~i~0 < 100); 594#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 593#L10-2 assume !!(main_~i~0 < 100); 590#L10 [2021-10-28 08:59:44,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1039528738, now seen corresponding path program 4 times [2021-10-28 08:59:44,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620166013] [2021-10-28 08:59:44,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,759 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,777 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:44,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,798 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:44,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 2 times [2021-10-28 08:59:44,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,804 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067185000] [2021-10-28 08:59:44,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,804 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,809 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:44,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:44,816 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:44,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:44,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1650681494, now seen corresponding path program 4 times [2021-10-28 08:59:44,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:44,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865343784] [2021-10-28 08:59:44,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:44,818 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:44,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:44,893 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:44,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:44,894 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865343784] [2021-10-28 08:59:44,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865343784] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:44,894 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1415074523] [2021-10-28 08:59:44,895 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 08:59:44,895 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:44,895 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:44,898 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:44,920 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-10-28 08:59:44,965 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 08:59:44,966 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:44,966 INFO L263 TraceCheckSpWp]: Trace formula consists of 29 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-28 08:59:44,967 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:45,035 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,035 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1415074523] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,036 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:45,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2021-10-28 08:59:45,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974061918] [2021-10-28 08:59:45,070 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:45,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-28 08:59:45,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-10-28 08:59:45,071 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:45,097 INFO L93 Difference]: Finished difference Result 17 states and 19 transitions. [2021-10-28 08:59:45,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 08:59:45,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 19 transitions. [2021-10-28 08:59:45,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 16 states and 18 transitions. [2021-10-28 08:59:45,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:45,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:45,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 18 transitions. [2021-10-28 08:59:45,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:45,100 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2021-10-28 08:59:45,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 18 transitions. [2021-10-28 08:59:45,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2021-10-28 08:59:45,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.1333333333333333) internal successors, (17), 14 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 17 transitions. [2021-10-28 08:59:45,103 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2021-10-28 08:59:45,103 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2021-10-28 08:59:45,103 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 08:59:45,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 17 transitions. [2021-10-28 08:59:45,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:45,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:45,105 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 1] [2021-10-28 08:59:45,105 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:45,105 INFO L791 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 666#L10-2 assume !!(main_~i~0 < 100); 667#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 668#L10-2 assume !!(main_~i~0 < 100); 669#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 680#L10-2 assume !!(main_~i~0 < 100); 679#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 678#L10-2 assume !!(main_~i~0 < 100); 676#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 675#L10-2 assume !!(main_~i~0 < 100); 674#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 673#L10-2 assume !!(main_~i~0 < 100); 671#L10 [2021-10-28 08:59:45,105 INFO L793 eck$LassoCheckResult]: Loop: 671#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 672#L10-2 assume !!(main_~i~0 < 100); 674#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 673#L10-2 assume !!(main_~i~0 < 100); 671#L10 [2021-10-28 08:59:45,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1740263163, now seen corresponding path program 5 times [2021-10-28 08:59:45,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626355183] [2021-10-28 08:59:45,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,107 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,114 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,120 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,121 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 3 times [2021-10-28 08:59:45,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665137027] [2021-10-28 08:59:45,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,122 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,126 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,129 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1404785203, now seen corresponding path program 5 times [2021-10-28 08:59:45,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349997423] [2021-10-28 08:59:45,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,131 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:45,189 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:45,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349997423] [2021-10-28 08:59:45,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349997423] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1313923222] [2021-10-28 08:59:45,190 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 08:59:45,191 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:45,191 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:45,194 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:45,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-10-28 08:59:45,271 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-10-28 08:59:45,272 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:45,272 INFO L263 TraceCheckSpWp]: Trace formula consists of 33 conjuncts, 7 conjunts are in the unsatisfiable core [2021-10-28 08:59:45,273 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:45,338 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,339 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1313923222] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,339 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:45,339 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2021-10-28 08:59:45,340 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758992490] [2021-10-28 08:59:45,370 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:45,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-10-28 08:59:45,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-10-28 08:59:45,371 INFO L87 Difference]: Start difference. First operand 15 states and 17 transitions. cyclomatic complexity: 3 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:45,397 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2021-10-28 08:59:45,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-10-28 08:59:45,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2021-10-28 08:59:45,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 18 states and 20 transitions. [2021-10-28 08:59:45,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:45,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:45,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 20 transitions. [2021-10-28 08:59:45,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:45,402 INFO L681 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2021-10-28 08:59:45,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 20 transitions. [2021-10-28 08:59:45,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 17. [2021-10-28 08:59:45,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.1176470588235294) internal successors, (19), 16 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 19 transitions. [2021-10-28 08:59:45,410 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2021-10-28 08:59:45,411 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2021-10-28 08:59:45,411 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 08:59:45,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 19 transitions. [2021-10-28 08:59:45,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:45,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:45,418 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 1] [2021-10-28 08:59:45,418 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:45,418 INFO L791 eck$LassoCheckResult]: Stem: 762#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 758#L10-2 assume !!(main_~i~0 < 100); 759#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 760#L10-2 assume !!(main_~i~0 < 100); 761#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 765#L10-2 assume !!(main_~i~0 < 100); 774#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 773#L10-2 assume !!(main_~i~0 < 100); 772#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 771#L10-2 assume !!(main_~i~0 < 100); 769#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 768#L10-2 assume !!(main_~i~0 < 100); 767#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 766#L10-2 assume !!(main_~i~0 < 100); 763#L10 [2021-10-28 08:59:45,419 INFO L793 eck$LassoCheckResult]: Loop: 763#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 764#L10-2 assume !!(main_~i~0 < 100); 767#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 766#L10-2 assume !!(main_~i~0 < 100); 763#L10 [2021-10-28 08:59:45,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1650621912, now seen corresponding path program 6 times [2021-10-28 08:59:45,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,420 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004411697] [2021-10-28 08:59:45,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,420 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,439 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,453 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 4 times [2021-10-28 08:59:45,455 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,455 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261640158] [2021-10-28 08:59:45,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,456 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,461 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,469 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1321650832, now seen corresponding path program 6 times [2021-10-28 08:59:45,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,470 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494212239] [2021-10-28 08:59:45,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,470 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:45,561 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:45,562 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494212239] [2021-10-28 08:59:45,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494212239] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,562 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1110185742] [2021-10-28 08:59:45,562 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 08:59:45,563 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:45,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:45,565 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:45,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-10-28 08:59:45,661 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2021-10-28 08:59:45,661 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:45,662 INFO L263 TraceCheckSpWp]: Trace formula consists of 37 conjuncts, 8 conjunts are in the unsatisfiable core [2021-10-28 08:59:45,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:45,729 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1110185742] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,730 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:45,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2021-10-28 08:59:45,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358299585] [2021-10-28 08:59:45,777 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:45,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-10-28 08:59:45,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-10-28 08:59:45,783 INFO L87 Difference]: Start difference. First operand 17 states and 19 transitions. cyclomatic complexity: 3 Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:45,812 INFO L93 Difference]: Finished difference Result 21 states and 23 transitions. [2021-10-28 08:59:45,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-10-28 08:59:45,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 23 transitions. [2021-10-28 08:59:45,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 20 states and 22 transitions. [2021-10-28 08:59:45,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:45,823 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:45,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 22 transitions. [2021-10-28 08:59:45,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:45,824 INFO L681 BuchiCegarLoop]: Abstraction has 20 states and 22 transitions. [2021-10-28 08:59:45,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 22 transitions. [2021-10-28 08:59:45,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 19. [2021-10-28 08:59:45,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:45,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2021-10-28 08:59:45,831 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2021-10-28 08:59:45,831 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2021-10-28 08:59:45,831 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 08:59:45,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2021-10-28 08:59:45,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:45,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:45,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:45,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 1] [2021-10-28 08:59:45,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:45,833 INFO L791 eck$LassoCheckResult]: Stem: 865#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 861#L10-2 assume !!(main_~i~0 < 100); 862#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 863#L10-2 assume !!(main_~i~0 < 100); 864#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 868#L10-2 assume !!(main_~i~0 < 100); 879#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 878#L10-2 assume !!(main_~i~0 < 100); 877#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 876#L10-2 assume !!(main_~i~0 < 100); 875#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 874#L10-2 assume !!(main_~i~0 < 100); 872#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 871#L10-2 assume !!(main_~i~0 < 100); 870#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 869#L10-2 assume !!(main_~i~0 < 100); 866#L10 [2021-10-28 08:59:45,834 INFO L793 eck$LassoCheckResult]: Loop: 866#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 867#L10-2 assume !!(main_~i~0 < 100); 870#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 869#L10-2 assume !!(main_~i~0 < 100); 866#L10 [2021-10-28 08:59:45,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,834 INFO L85 PathProgramCache]: Analyzing trace with hash 1404725621, now seen corresponding path program 7 times [2021-10-28 08:59:45,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895108071] [2021-10-28 08:59:45,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,841 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,857 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,865 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,869 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 5 times [2021-10-28 08:59:45,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,869 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105493884] [2021-10-28 08:59:45,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,870 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,884 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:45,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:45,888 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:45,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:45,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1261068371, now seen corresponding path program 7 times [2021-10-28 08:59:45,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:45,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542486078] [2021-10-28 08:59:45,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:45,890 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:45,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:45,981 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:45,982 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:45,982 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542486078] [2021-10-28 08:59:45,982 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542486078] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:45,982 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [791452689] [2021-10-28 08:59:45,983 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 08:59:45,983 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:45,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:45,991 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:46,013 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-10-28 08:59:46,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:46,077 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 9 conjunts are in the unsatisfiable core [2021-10-28 08:59:46,078 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:46,163 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:46,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [791452689] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:46,163 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:46,163 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2021-10-28 08:59:46,164 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999304032] [2021-10-28 08:59:46,197 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:46,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-10-28 08:59:46,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-10-28 08:59:46,198 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 3 Second operand has 10 states, 10 states have (on average 1.9) internal successors, (19), 9 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:46,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:46,228 INFO L93 Difference]: Finished difference Result 23 states and 25 transitions. [2021-10-28 08:59:46,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 08:59:46,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 25 transitions. [2021-10-28 08:59:46,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:46,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 22 states and 24 transitions. [2021-10-28 08:59:46,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:46,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:46,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 24 transitions. [2021-10-28 08:59:46,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:46,231 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 24 transitions. [2021-10-28 08:59:46,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 24 transitions. [2021-10-28 08:59:46,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2021-10-28 08:59:46,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.0952380952380953) internal successors, (23), 20 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:46,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 23 transitions. [2021-10-28 08:59:46,235 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-28 08:59:46,235 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-28 08:59:46,235 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 08:59:46,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 23 transitions. [2021-10-28 08:59:46,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:46,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:46,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:46,237 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 1] [2021-10-28 08:59:46,237 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:46,237 INFO L791 eck$LassoCheckResult]: Stem: 979#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 975#L10-2 assume !!(main_~i~0 < 100); 976#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 977#L10-2 assume !!(main_~i~0 < 100); 978#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 982#L10-2 assume !!(main_~i~0 < 100); 995#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 994#L10-2 assume !!(main_~i~0 < 100); 993#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 992#L10-2 assume !!(main_~i~0 < 100); 991#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 990#L10-2 assume !!(main_~i~0 < 100); 989#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 988#L10-2 assume !!(main_~i~0 < 100); 986#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 985#L10-2 assume !!(main_~i~0 < 100); 984#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 983#L10-2 assume !!(main_~i~0 < 100); 980#L10 [2021-10-28 08:59:46,237 INFO L793 eck$LassoCheckResult]: Loop: 980#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 981#L10-2 assume !!(main_~i~0 < 100); 984#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 983#L10-2 assume !!(main_~i~0 < 100); 980#L10 [2021-10-28 08:59:46,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1321591250, now seen corresponding path program 8 times [2021-10-28 08:59:46,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,238 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125865163] [2021-10-28 08:59:46,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,239 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,246 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:46,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,253 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:46,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 6 times [2021-10-28 08:59:46,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,254 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171618739] [2021-10-28 08:59:46,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,255 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,258 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:46,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,261 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:46,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,261 INFO L85 PathProgramCache]: Analyzing trace with hash -763125366, now seen corresponding path program 8 times [2021-10-28 08:59:46,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376249120] [2021-10-28 08:59:46,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,262 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:46,343 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:46,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:46,350 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376249120] [2021-10-28 08:59:46,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376249120] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:46,350 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1044545019] [2021-10-28 08:59:46,351 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 08:59:46,351 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:46,351 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:46,353 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:46,372 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-10-28 08:59:46,439 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 08:59:46,440 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:46,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 45 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 08:59:46,442 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:46,526 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:46,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1044545019] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:46,527 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:46,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2021-10-28 08:59:46,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130165114] [2021-10-28 08:59:46,556 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:46,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-10-28 08:59:46,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-10-28 08:59:46,558 INFO L87 Difference]: Start difference. First operand 21 states and 23 transitions. cyclomatic complexity: 3 Second operand has 11 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:46,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:46,595 INFO L93 Difference]: Finished difference Result 25 states and 27 transitions. [2021-10-28 08:59:46,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 08:59:46,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 27 transitions. [2021-10-28 08:59:46,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:46,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 24 states and 26 transitions. [2021-10-28 08:59:46,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:46,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:46,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 26 transitions. [2021-10-28 08:59:46,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:46,600 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2021-10-28 08:59:46,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 26 transitions. [2021-10-28 08:59:46,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 23. [2021-10-28 08:59:46,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.0869565217391304) internal successors, (25), 22 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:46,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2021-10-28 08:59:46,606 INFO L704 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2021-10-28 08:59:46,607 INFO L587 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2021-10-28 08:59:46,607 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 08:59:46,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 25 transitions. [2021-10-28 08:59:46,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:46,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:46,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:46,609 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 1] [2021-10-28 08:59:46,609 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:46,610 INFO L791 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1100#L10-2 assume !!(main_~i~0 < 100); 1101#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1102#L10-2 assume !!(main_~i~0 < 100); 1103#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1107#L10-2 assume !!(main_~i~0 < 100); 1122#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1121#L10-2 assume !!(main_~i~0 < 100); 1120#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1119#L10-2 assume !!(main_~i~0 < 100); 1118#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1117#L10-2 assume !!(main_~i~0 < 100); 1116#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1115#L10-2 assume !!(main_~i~0 < 100); 1114#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1113#L10-2 assume !!(main_~i~0 < 100); 1111#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1110#L10-2 assume !!(main_~i~0 < 100); 1109#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1108#L10-2 assume !!(main_~i~0 < 100); 1105#L10 [2021-10-28 08:59:46,610 INFO L793 eck$LassoCheckResult]: Loop: 1105#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1106#L10-2 assume !!(main_~i~0 < 100); 1109#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1108#L10-2 assume !!(main_~i~0 < 100); 1105#L10 [2021-10-28 08:59:46,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,610 INFO L85 PathProgramCache]: Analyzing trace with hash -1261127953, now seen corresponding path program 9 times [2021-10-28 08:59:46,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,611 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046664112] [2021-10-28 08:59:46,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,611 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,623 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:46,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,639 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:46,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 7 times [2021-10-28 08:59:46,640 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,640 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027090761] [2021-10-28 08:59:46,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,641 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,644 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:46,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:46,647 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:46,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:46,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1018732583, now seen corresponding path program 9 times [2021-10-28 08:59:46,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:46,671 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345459917] [2021-10-28 08:59:46,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:46,672 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:46,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:46,778 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:46,778 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:46,778 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345459917] [2021-10-28 08:59:46,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345459917] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:46,779 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1643427363] [2021-10-28 08:59:46,779 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 08:59:46,779 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:46,780 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:46,782 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:46,806 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-10-28 08:59:46,890 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2021-10-28 08:59:46,891 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:46,892 INFO L263 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 11 conjunts are in the unsatisfiable core [2021-10-28 08:59:46,893 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:46,988 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:46,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1643427363] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:46,989 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:46,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2021-10-28 08:59:46,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427816876] [2021-10-28 08:59:47,031 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:47,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-10-28 08:59:47,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-10-28 08:59:47,032 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. cyclomatic complexity: 3 Second operand has 12 states, 12 states have (on average 1.9166666666666667) internal successors, (23), 11 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:47,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:47,068 INFO L93 Difference]: Finished difference Result 27 states and 29 transitions. [2021-10-28 08:59:47,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-10-28 08:59:47,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 29 transitions. [2021-10-28 08:59:47,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:47,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 26 states and 28 transitions. [2021-10-28 08:59:47,071 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:47,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:47,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 28 transitions. [2021-10-28 08:59:47,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:47,072 INFO L681 BuchiCegarLoop]: Abstraction has 26 states and 28 transitions. [2021-10-28 08:59:47,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 28 transitions. [2021-10-28 08:59:47,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2021-10-28 08:59:47,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.08) internal successors, (27), 24 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:47,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 27 transitions. [2021-10-28 08:59:47,075 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2021-10-28 08:59:47,075 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2021-10-28 08:59:47,075 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 08:59:47,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 27 transitions. [2021-10-28 08:59:47,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:47,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:47,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:47,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 10, 1] [2021-10-28 08:59:47,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:47,078 INFO L791 eck$LassoCheckResult]: Stem: 1240#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1236#L10-2 assume !!(main_~i~0 < 100); 1237#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1238#L10-2 assume !!(main_~i~0 < 100); 1239#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1243#L10-2 assume !!(main_~i~0 < 100); 1260#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1259#L10-2 assume !!(main_~i~0 < 100); 1258#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1257#L10-2 assume !!(main_~i~0 < 100); 1256#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1255#L10-2 assume !!(main_~i~0 < 100); 1254#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1253#L10-2 assume !!(main_~i~0 < 100); 1252#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1251#L10-2 assume !!(main_~i~0 < 100); 1250#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1249#L10-2 assume !!(main_~i~0 < 100); 1247#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1246#L10-2 assume !!(main_~i~0 < 100); 1245#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1244#L10-2 assume !!(main_~i~0 < 100); 1241#L10 [2021-10-28 08:59:47,078 INFO L793 eck$LassoCheckResult]: Loop: 1241#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1242#L10-2 assume !!(main_~i~0 < 100); 1245#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1244#L10-2 assume !!(main_~i~0 < 100); 1241#L10 [2021-10-28 08:59:47,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,079 INFO L85 PathProgramCache]: Analyzing trace with hash -763184948, now seen corresponding path program 10 times [2021-10-28 08:59:47,079 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,079 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404940278] [2021-10-28 08:59:47,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,080 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,088 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:47,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,096 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:47,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,096 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 8 times [2021-10-28 08:59:47,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,097 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260679657] [2021-10-28 08:59:47,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,097 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,102 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:47,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,105 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:47,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,106 INFO L85 PathProgramCache]: Analyzing trace with hash -307729532, now seen corresponding path program 10 times [2021-10-28 08:59:47,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,106 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368263385] [2021-10-28 08:59:47,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,107 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:47,227 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:47,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:47,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368263385] [2021-10-28 08:59:47,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368263385] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:47,228 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [320759656] [2021-10-28 08:59:47,228 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 08:59:47,228 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:47,228 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:47,234 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:47,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-10-28 08:59:47,352 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 08:59:47,352 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:47,353 INFO L263 TraceCheckSpWp]: Trace formula consists of 53 conjuncts, 12 conjunts are in the unsatisfiable core [2021-10-28 08:59:47,354 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:47,455 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:47,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [320759656] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:47,456 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:47,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2021-10-28 08:59:47,457 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473106140] [2021-10-28 08:59:47,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:47,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-10-28 08:59:47,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-10-28 08:59:47,489 INFO L87 Difference]: Start difference. First operand 25 states and 27 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 12 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:47,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:47,527 INFO L93 Difference]: Finished difference Result 29 states and 31 transitions. [2021-10-28 08:59:47,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-10-28 08:59:47,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 31 transitions. [2021-10-28 08:59:47,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:47,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 28 states and 30 transitions. [2021-10-28 08:59:47,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:47,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:47,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 30 transitions. [2021-10-28 08:59:47,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:47,532 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2021-10-28 08:59:47,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 30 transitions. [2021-10-28 08:59:47,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2021-10-28 08:59:47,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.0740740740740742) internal successors, (29), 26 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:47,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 29 transitions. [2021-10-28 08:59:47,541 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-28 08:59:47,541 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-28 08:59:47,541 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 08:59:47,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 29 transitions. [2021-10-28 08:59:47,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:47,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:47,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:47,543 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 1] [2021-10-28 08:59:47,543 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:47,545 INFO L791 eck$LassoCheckResult]: Stem: 1387#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1383#L10-2 assume !!(main_~i~0 < 100); 1384#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1385#L10-2 assume !!(main_~i~0 < 100); 1386#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1390#L10-2 assume !!(main_~i~0 < 100); 1409#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1408#L10-2 assume !!(main_~i~0 < 100); 1407#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1406#L10-2 assume !!(main_~i~0 < 100); 1405#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1404#L10-2 assume !!(main_~i~0 < 100); 1403#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1402#L10-2 assume !!(main_~i~0 < 100); 1401#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1400#L10-2 assume !!(main_~i~0 < 100); 1399#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1398#L10-2 assume !!(main_~i~0 < 100); 1397#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1396#L10-2 assume !!(main_~i~0 < 100); 1394#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1393#L10-2 assume !!(main_~i~0 < 100); 1392#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1391#L10-2 assume !!(main_~i~0 < 100); 1388#L10 [2021-10-28 08:59:47,545 INFO L793 eck$LassoCheckResult]: Loop: 1388#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1389#L10-2 assume !!(main_~i~0 < 100); 1392#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1391#L10-2 assume !!(main_~i~0 < 100); 1388#L10 [2021-10-28 08:59:47,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1018673001, now seen corresponding path program 11 times [2021-10-28 08:59:47,546 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,546 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714738532] [2021-10-28 08:59:47,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,546 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,553 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:47,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,564 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:47,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,564 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 9 times [2021-10-28 08:59:47,565 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,565 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431960777] [2021-10-28 08:59:47,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,565 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,573 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:47,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:47,575 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:47,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:47,576 INFO L85 PathProgramCache]: Analyzing trace with hash 567464865, now seen corresponding path program 11 times [2021-10-28 08:59:47,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:47,576 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527451286] [2021-10-28 08:59:47,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:47,577 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:47,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:47,719 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:47,719 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:47,720 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527451286] [2021-10-28 08:59:47,720 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527451286] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:47,720 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [172591902] [2021-10-28 08:59:47,720 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 08:59:47,720 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:47,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:47,724 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:47,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-10-28 08:59:47,867 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2021-10-28 08:59:47,867 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:47,868 INFO L263 TraceCheckSpWp]: Trace formula consists of 57 conjuncts, 13 conjunts are in the unsatisfiable core [2021-10-28 08:59:47,869 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:47,985 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:47,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [172591902] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:47,985 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:47,985 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2021-10-28 08:59:47,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303538365] [2021-10-28 08:59:48,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:48,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-10-28 08:59:48,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-10-28 08:59:48,020 INFO L87 Difference]: Start difference. First operand 27 states and 29 transitions. cyclomatic complexity: 3 Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 13 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:48,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:48,071 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2021-10-28 08:59:48,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-10-28 08:59:48,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2021-10-28 08:59:48,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:48,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 30 states and 32 transitions. [2021-10-28 08:59:48,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:48,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:48,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 32 transitions. [2021-10-28 08:59:48,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:48,074 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2021-10-28 08:59:48,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 32 transitions. [2021-10-28 08:59:48,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2021-10-28 08:59:48,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.0689655172413792) internal successors, (31), 28 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:48,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 31 transitions. [2021-10-28 08:59:48,080 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2021-10-28 08:59:48,081 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2021-10-28 08:59:48,081 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 08:59:48,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 31 transitions. [2021-10-28 08:59:48,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:48,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:48,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:48,082 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 1] [2021-10-28 08:59:48,082 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:48,083 INFO L791 eck$LassoCheckResult]: Stem: 1545#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1541#L10-2 assume !!(main_~i~0 < 100); 1542#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1543#L10-2 assume !!(main_~i~0 < 100); 1544#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1548#L10-2 assume !!(main_~i~0 < 100); 1569#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1568#L10-2 assume !!(main_~i~0 < 100); 1567#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1566#L10-2 assume !!(main_~i~0 < 100); 1565#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1564#L10-2 assume !!(main_~i~0 < 100); 1563#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1562#L10-2 assume !!(main_~i~0 < 100); 1561#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1560#L10-2 assume !!(main_~i~0 < 100); 1559#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1558#L10-2 assume !!(main_~i~0 < 100); 1557#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1556#L10-2 assume !!(main_~i~0 < 100); 1555#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1554#L10-2 assume !!(main_~i~0 < 100); 1552#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1551#L10-2 assume !!(main_~i~0 < 100); 1550#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1549#L10-2 assume !!(main_~i~0 < 100); 1546#L10 [2021-10-28 08:59:48,083 INFO L793 eck$LassoCheckResult]: Loop: 1546#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1547#L10-2 assume !!(main_~i~0 < 100); 1550#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1549#L10-2 assume !!(main_~i~0 < 100); 1546#L10 [2021-10-28 08:59:48,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,083 INFO L85 PathProgramCache]: Analyzing trace with hash -307789114, now seen corresponding path program 12 times [2021-10-28 08:59:48,084 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,084 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940786838] [2021-10-28 08:59:48,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,084 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,092 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:48,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,098 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:48,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,099 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 10 times [2021-10-28 08:59:48,099 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,099 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328784787] [2021-10-28 08:59:48,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,099 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,104 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:48,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,106 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:48,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,106 INFO L85 PathProgramCache]: Analyzing trace with hash -184309634, now seen corresponding path program 12 times [2021-10-28 08:59:48,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684097630] [2021-10-28 08:59:48,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,107 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:48,266 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:48,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:48,267 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684097630] [2021-10-28 08:59:48,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1684097630] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:48,267 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2121339093] [2021-10-28 08:59:48,268 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 08:59:48,268 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:48,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:48,274 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:48,290 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-10-28 08:59:48,406 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2021-10-28 08:59:48,407 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:48,408 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 08:59:48,409 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:48,523 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:48,524 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2121339093] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:48,524 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:48,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2021-10-28 08:59:48,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046802277] [2021-10-28 08:59:48,553 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:48,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-10-28 08:59:48,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-10-28 08:59:48,554 INFO L87 Difference]: Start difference. First operand 29 states and 31 transitions. cyclomatic complexity: 3 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 14 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:48,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:48,598 INFO L93 Difference]: Finished difference Result 33 states and 35 transitions. [2021-10-28 08:59:48,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-10-28 08:59:48,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 35 transitions. [2021-10-28 08:59:48,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:48,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 32 states and 34 transitions. [2021-10-28 08:59:48,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:48,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:48,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 34 transitions. [2021-10-28 08:59:48,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:48,601 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 34 transitions. [2021-10-28 08:59:48,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 34 transitions. [2021-10-28 08:59:48,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 31. [2021-10-28 08:59:48,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.064516129032258) internal successors, (33), 30 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:48,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2021-10-28 08:59:48,615 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2021-10-28 08:59:48,615 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2021-10-28 08:59:48,615 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 08:59:48,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2021-10-28 08:59:48,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:48,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:48,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:48,619 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 13, 1] [2021-10-28 08:59:48,621 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:48,622 INFO L791 eck$LassoCheckResult]: Stem: 1714#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1710#L10-2 assume !!(main_~i~0 < 100); 1711#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1712#L10-2 assume !!(main_~i~0 < 100); 1713#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1717#L10-2 assume !!(main_~i~0 < 100); 1740#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1739#L10-2 assume !!(main_~i~0 < 100); 1738#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1737#L10-2 assume !!(main_~i~0 < 100); 1736#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1735#L10-2 assume !!(main_~i~0 < 100); 1734#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1733#L10-2 assume !!(main_~i~0 < 100); 1732#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1731#L10-2 assume !!(main_~i~0 < 100); 1730#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1729#L10-2 assume !!(main_~i~0 < 100); 1728#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1727#L10-2 assume !!(main_~i~0 < 100); 1726#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1725#L10-2 assume !!(main_~i~0 < 100); 1724#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1723#L10-2 assume !!(main_~i~0 < 100); 1721#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1720#L10-2 assume !!(main_~i~0 < 100); 1719#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1718#L10-2 assume !!(main_~i~0 < 100); 1715#L10 [2021-10-28 08:59:48,623 INFO L793 eck$LassoCheckResult]: Loop: 1715#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1716#L10-2 assume !!(main_~i~0 < 100); 1719#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1718#L10-2 assume !!(main_~i~0 < 100); 1715#L10 [2021-10-28 08:59:48,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,624 INFO L85 PathProgramCache]: Analyzing trace with hash 567405283, now seen corresponding path program 13 times [2021-10-28 08:59:48,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,624 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612665141] [2021-10-28 08:59:48,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,625 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,633 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:48,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,647 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:48,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 11 times [2021-10-28 08:59:48,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,649 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860885675] [2021-10-28 08:59:48,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,649 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,654 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:48,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:48,659 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:48,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:48,660 INFO L85 PathProgramCache]: Analyzing trace with hash -1085097445, now seen corresponding path program 13 times [2021-10-28 08:59:48,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:48,660 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147185278] [2021-10-28 08:59:48,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:48,660 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:48,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:48,865 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:48,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:48,865 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147185278] [2021-10-28 08:59:48,866 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147185278] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:48,866 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1036047742] [2021-10-28 08:59:48,866 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 08:59:48,866 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:48,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:48,871 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:48,878 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-10-28 08:59:49,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:49,005 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 08:59:49,007 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:49,127 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:49,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1036047742] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:49,128 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:49,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2021-10-28 08:59:49,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486249306] [2021-10-28 08:59:49,159 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:49,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-10-28 08:59:49,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-10-28 08:59:49,161 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 3 Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 15 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:49,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:49,222 INFO L93 Difference]: Finished difference Result 35 states and 37 transitions. [2021-10-28 08:59:49,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-10-28 08:59:49,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 37 transitions. [2021-10-28 08:59:49,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:49,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 34 states and 36 transitions. [2021-10-28 08:59:49,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:49,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:49,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 36 transitions. [2021-10-28 08:59:49,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:49,225 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 36 transitions. [2021-10-28 08:59:49,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 36 transitions. [2021-10-28 08:59:49,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2021-10-28 08:59:49,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.0606060606060606) internal successors, (35), 32 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:49,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2021-10-28 08:59:49,230 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-28 08:59:49,230 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-28 08:59:49,230 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 08:59:49,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 35 transitions. [2021-10-28 08:59:49,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:49,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:49,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:49,234 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 14, 1] [2021-10-28 08:59:49,234 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:49,234 INFO L791 eck$LassoCheckResult]: Stem: 1894#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 1890#L10-2 assume !!(main_~i~0 < 100); 1891#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1892#L10-2 assume !!(main_~i~0 < 100); 1893#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1897#L10-2 assume !!(main_~i~0 < 100); 1922#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1921#L10-2 assume !!(main_~i~0 < 100); 1920#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1919#L10-2 assume !!(main_~i~0 < 100); 1918#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1917#L10-2 assume !!(main_~i~0 < 100); 1916#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1915#L10-2 assume !!(main_~i~0 < 100); 1914#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1913#L10-2 assume !!(main_~i~0 < 100); 1912#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1911#L10-2 assume !!(main_~i~0 < 100); 1910#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1909#L10-2 assume !!(main_~i~0 < 100); 1908#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1907#L10-2 assume !!(main_~i~0 < 100); 1906#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1905#L10-2 assume !!(main_~i~0 < 100); 1904#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1903#L10-2 assume !!(main_~i~0 < 100); 1901#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1900#L10-2 assume !!(main_~i~0 < 100); 1899#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1898#L10-2 assume !!(main_~i~0 < 100); 1895#L10 [2021-10-28 08:59:49,234 INFO L793 eck$LassoCheckResult]: Loop: 1895#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 1896#L10-2 assume !!(main_~i~0 < 100); 1899#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 1898#L10-2 assume !!(main_~i~0 < 100); 1895#L10 [2021-10-28 08:59:49,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,235 INFO L85 PathProgramCache]: Analyzing trace with hash -184369216, now seen corresponding path program 14 times [2021-10-28 08:59:49,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,235 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81003636] [2021-10-28 08:59:49,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,236 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,252 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:49,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,259 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:49,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 12 times [2021-10-28 08:59:49,261 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577997443] [2021-10-28 08:59:49,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,262 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,266 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:49,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,268 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:49,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,269 INFO L85 PathProgramCache]: Analyzing trace with hash 841209976, now seen corresponding path program 14 times [2021-10-28 08:59:49,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937106841] [2021-10-28 08:59:49,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,269 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:49,450 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:49,451 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:49,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937106841] [2021-10-28 08:59:49,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937106841] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:49,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [36448838] [2021-10-28 08:59:49,451 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 08:59:49,452 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:49,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:49,469 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:49,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-10-28 08:59:49,613 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 08:59:49,613 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:49,614 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 16 conjunts are in the unsatisfiable core [2021-10-28 08:59:49,615 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:49,749 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:49,750 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [36448838] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:49,750 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:49,750 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2021-10-28 08:59:49,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907166523] [2021-10-28 08:59:49,799 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:49,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-10-28 08:59:49,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-10-28 08:59:49,800 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. cyclomatic complexity: 3 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 16 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:49,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:49,858 INFO L93 Difference]: Finished difference Result 37 states and 39 transitions. [2021-10-28 08:59:49,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-10-28 08:59:49,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 39 transitions. [2021-10-28 08:59:49,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:49,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 36 states and 38 transitions. [2021-10-28 08:59:49,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:49,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:49,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 38 transitions. [2021-10-28 08:59:49,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:49,861 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2021-10-28 08:59:49,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 38 transitions. [2021-10-28 08:59:49,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2021-10-28 08:59:49,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.0571428571428572) internal successors, (37), 34 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:49,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 37 transitions. [2021-10-28 08:59:49,863 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2021-10-28 08:59:49,863 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2021-10-28 08:59:49,863 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 08:59:49,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 37 transitions. [2021-10-28 08:59:49,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:49,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:49,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:49,865 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 15, 1] [2021-10-28 08:59:49,865 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:49,865 INFO L791 eck$LassoCheckResult]: Stem: 2085#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 2081#L10-2 assume !!(main_~i~0 < 100); 2082#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2083#L10-2 assume !!(main_~i~0 < 100); 2084#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2088#L10-2 assume !!(main_~i~0 < 100); 2115#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2114#L10-2 assume !!(main_~i~0 < 100); 2113#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2112#L10-2 assume !!(main_~i~0 < 100); 2111#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2110#L10-2 assume !!(main_~i~0 < 100); 2109#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2108#L10-2 assume !!(main_~i~0 < 100); 2107#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2106#L10-2 assume !!(main_~i~0 < 100); 2105#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2104#L10-2 assume !!(main_~i~0 < 100); 2103#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2102#L10-2 assume !!(main_~i~0 < 100); 2101#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2100#L10-2 assume !!(main_~i~0 < 100); 2099#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2098#L10-2 assume !!(main_~i~0 < 100); 2097#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2096#L10-2 assume !!(main_~i~0 < 100); 2095#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2094#L10-2 assume !!(main_~i~0 < 100); 2092#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2091#L10-2 assume !!(main_~i~0 < 100); 2090#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2089#L10-2 assume !!(main_~i~0 < 100); 2086#L10 [2021-10-28 08:59:49,866 INFO L793 eck$LassoCheckResult]: Loop: 2086#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 2087#L10-2 assume !!(main_~i~0 < 100); 2090#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2089#L10-2 assume !!(main_~i~0 < 100); 2086#L10 [2021-10-28 08:59:49,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,866 INFO L85 PathProgramCache]: Analyzing trace with hash -1085157027, now seen corresponding path program 15 times [2021-10-28 08:59:49,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,867 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155811891] [2021-10-28 08:59:49,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,867 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,875 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:49,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,881 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:49,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 13 times [2021-10-28 08:59:49,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,882 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3332339] [2021-10-28 08:59:49,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,883 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,887 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:49,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:49,888 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:49,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:49,889 INFO L85 PathProgramCache]: Analyzing trace with hash 891736981, now seen corresponding path program 15 times [2021-10-28 08:59:49,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:49,889 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361410299] [2021-10-28 08:59:49,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:49,890 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:49,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:50,079 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:50,079 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:50,079 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361410299] [2021-10-28 08:59:50,079 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361410299] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:50,079 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [770316064] [2021-10-28 08:59:50,079 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 08:59:50,079 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:50,080 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:50,082 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:50,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-10-28 08:59:50,273 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2021-10-28 08:59:50,274 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:50,275 INFO L263 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 17 conjunts are in the unsatisfiable core [2021-10-28 08:59:50,277 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:50,429 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:50,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [770316064] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:50,430 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:50,430 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2021-10-28 08:59:50,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857020304] [2021-10-28 08:59:50,464 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:50,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-10-28 08:59:50,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-10-28 08:59:50,465 INFO L87 Difference]: Start difference. First operand 35 states and 37 transitions. cyclomatic complexity: 3 Second operand has 18 states, 18 states have (on average 1.9444444444444444) internal successors, (35), 17 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:50,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:50,526 INFO L93 Difference]: Finished difference Result 39 states and 41 transitions. [2021-10-28 08:59:50,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-10-28 08:59:50,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 41 transitions. [2021-10-28 08:59:50,527 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:50,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 38 states and 40 transitions. [2021-10-28 08:59:50,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:50,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:50,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 40 transitions. [2021-10-28 08:59:50,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:50,531 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 40 transitions. [2021-10-28 08:59:50,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 40 transitions. [2021-10-28 08:59:50,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 37. [2021-10-28 08:59:50,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.054054054054054) internal successors, (39), 36 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:50,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 39 transitions. [2021-10-28 08:59:50,533 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2021-10-28 08:59:50,533 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2021-10-28 08:59:50,533 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-28 08:59:50,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 39 transitions. [2021-10-28 08:59:50,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:50,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:50,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:50,534 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 16, 1] [2021-10-28 08:59:50,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:50,535 INFO L791 eck$LassoCheckResult]: Stem: 2287#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 2283#L10-2 assume !!(main_~i~0 < 100); 2284#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2285#L10-2 assume !!(main_~i~0 < 100); 2286#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2290#L10-2 assume !!(main_~i~0 < 100); 2319#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2318#L10-2 assume !!(main_~i~0 < 100); 2317#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2316#L10-2 assume !!(main_~i~0 < 100); 2315#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2314#L10-2 assume !!(main_~i~0 < 100); 2313#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2312#L10-2 assume !!(main_~i~0 < 100); 2311#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2310#L10-2 assume !!(main_~i~0 < 100); 2309#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2308#L10-2 assume !!(main_~i~0 < 100); 2307#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2306#L10-2 assume !!(main_~i~0 < 100); 2305#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2304#L10-2 assume !!(main_~i~0 < 100); 2303#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2302#L10-2 assume !!(main_~i~0 < 100); 2301#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2300#L10-2 assume !!(main_~i~0 < 100); 2299#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2298#L10-2 assume !!(main_~i~0 < 100); 2297#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2296#L10-2 assume !!(main_~i~0 < 100); 2294#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2293#L10-2 assume !!(main_~i~0 < 100); 2292#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2291#L10-2 assume !!(main_~i~0 < 100); 2288#L10 [2021-10-28 08:59:50,535 INFO L793 eck$LassoCheckResult]: Loop: 2288#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 2289#L10-2 assume !!(main_~i~0 < 100); 2292#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2291#L10-2 assume !!(main_~i~0 < 100); 2288#L10 [2021-10-28 08:59:50,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:50,535 INFO L85 PathProgramCache]: Analyzing trace with hash 841150394, now seen corresponding path program 16 times [2021-10-28 08:59:50,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:50,536 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353774604] [2021-10-28 08:59:50,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:50,536 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:50,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:50,566 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:50,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:50,575 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:50,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:50,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 14 times [2021-10-28 08:59:50,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:50,576 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122978986] [2021-10-28 08:59:50,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:50,576 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:50,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:50,581 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:50,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:50,583 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:50,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:50,584 INFO L85 PathProgramCache]: Analyzing trace with hash -2091418766, now seen corresponding path program 16 times [2021-10-28 08:59:50,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:50,584 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274639461] [2021-10-28 08:59:50,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:50,585 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:50,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:50,828 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:50,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:50,828 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274639461] [2021-10-28 08:59:50,829 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274639461] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:50,829 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1470909930] [2021-10-28 08:59:50,829 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 08:59:50,829 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:50,829 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:50,838 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:50,854 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-10-28 08:59:51,014 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 08:59:51,014 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:51,015 INFO L263 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 18 conjunts are in the unsatisfiable core [2021-10-28 08:59:51,017 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:51,169 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:51,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1470909930] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:51,170 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:51,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2021-10-28 08:59:51,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435559518] [2021-10-28 08:59:51,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:51,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-10-28 08:59:51,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-10-28 08:59:51,201 INFO L87 Difference]: Start difference. First operand 37 states and 39 transitions. cyclomatic complexity: 3 Second operand has 19 states, 19 states have (on average 1.9473684210526316) internal successors, (37), 18 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:51,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:51,255 INFO L93 Difference]: Finished difference Result 41 states and 43 transitions. [2021-10-28 08:59:51,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-10-28 08:59:51,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 43 transitions. [2021-10-28 08:59:51,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:51,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 42 transitions. [2021-10-28 08:59:51,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:51,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:51,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 42 transitions. [2021-10-28 08:59:51,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:51,265 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 42 transitions. [2021-10-28 08:59:51,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 42 transitions. [2021-10-28 08:59:51,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2021-10-28 08:59:51,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.0512820512820513) internal successors, (41), 38 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:51,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 41 transitions. [2021-10-28 08:59:51,270 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-28 08:59:51,270 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-28 08:59:51,270 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-28 08:59:51,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 41 transitions. [2021-10-28 08:59:51,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:51,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:51,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:51,273 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 17, 1] [2021-10-28 08:59:51,273 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:51,273 INFO L791 eck$LassoCheckResult]: Stem: 2500#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 2496#L10-2 assume !!(main_~i~0 < 100); 2497#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2498#L10-2 assume !!(main_~i~0 < 100); 2499#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2503#L10-2 assume !!(main_~i~0 < 100); 2534#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2533#L10-2 assume !!(main_~i~0 < 100); 2532#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2531#L10-2 assume !!(main_~i~0 < 100); 2530#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2529#L10-2 assume !!(main_~i~0 < 100); 2528#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2527#L10-2 assume !!(main_~i~0 < 100); 2526#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2525#L10-2 assume !!(main_~i~0 < 100); 2524#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2523#L10-2 assume !!(main_~i~0 < 100); 2522#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2521#L10-2 assume !!(main_~i~0 < 100); 2520#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2519#L10-2 assume !!(main_~i~0 < 100); 2518#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2517#L10-2 assume !!(main_~i~0 < 100); 2516#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2515#L10-2 assume !!(main_~i~0 < 100); 2514#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2513#L10-2 assume !!(main_~i~0 < 100); 2512#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2511#L10-2 assume !!(main_~i~0 < 100); 2510#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2509#L10-2 assume !!(main_~i~0 < 100); 2507#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2506#L10-2 assume !!(main_~i~0 < 100); 2505#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2504#L10-2 assume !!(main_~i~0 < 100); 2501#L10 [2021-10-28 08:59:51,274 INFO L793 eck$LassoCheckResult]: Loop: 2501#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 2502#L10-2 assume !!(main_~i~0 < 100); 2505#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2504#L10-2 assume !!(main_~i~0 < 100); 2501#L10 [2021-10-28 08:59:51,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:51,274 INFO L85 PathProgramCache]: Analyzing trace with hash 891677399, now seen corresponding path program 17 times [2021-10-28 08:59:51,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:51,276 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109360305] [2021-10-28 08:59:51,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:51,276 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:51,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:51,291 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:51,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:51,303 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:51,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:51,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 15 times [2021-10-28 08:59:51,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:51,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082453386] [2021-10-28 08:59:51,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:51,305 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:51,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:51,309 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:51,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:51,312 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:51,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:51,313 INFO L85 PathProgramCache]: Analyzing trace with hash 134062095, now seen corresponding path program 17 times [2021-10-28 08:59:51,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:51,313 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830627071] [2021-10-28 08:59:51,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:51,313 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:51,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:51,611 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:51,612 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:51,612 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830627071] [2021-10-28 08:59:51,612 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830627071] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:51,612 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [405526527] [2021-10-28 08:59:51,613 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 08:59:51,613 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:51,613 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:51,621 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:51,652 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-10-28 08:59:51,810 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2021-10-28 08:59:51,810 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:51,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 08:59:51,812 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:51,942 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:51,943 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [405526527] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:51,943 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:51,943 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2021-10-28 08:59:51,943 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060513086] [2021-10-28 08:59:51,974 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:51,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-10-28 08:59:51,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-10-28 08:59:51,976 INFO L87 Difference]: Start difference. First operand 39 states and 41 transitions. cyclomatic complexity: 3 Second operand has 20 states, 20 states have (on average 1.95) internal successors, (39), 19 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:52,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:52,040 INFO L93 Difference]: Finished difference Result 43 states and 45 transitions. [2021-10-28 08:59:52,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-10-28 08:59:52,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 45 transitions. [2021-10-28 08:59:52,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:52,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 44 transitions. [2021-10-28 08:59:52,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:52,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:52,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 44 transitions. [2021-10-28 08:59:52,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:52,054 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2021-10-28 08:59:52,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 44 transitions. [2021-10-28 08:59:52,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2021-10-28 08:59:52,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.048780487804878) internal successors, (43), 40 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:52,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 43 transitions. [2021-10-28 08:59:52,058 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2021-10-28 08:59:52,058 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2021-10-28 08:59:52,058 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-28 08:59:52,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 43 transitions. [2021-10-28 08:59:52,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:52,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:52,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:52,062 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 18, 1] [2021-10-28 08:59:52,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:52,063 INFO L791 eck$LassoCheckResult]: Stem: 2724#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 2720#L10-2 assume !!(main_~i~0 < 100); 2721#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2722#L10-2 assume !!(main_~i~0 < 100); 2723#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2727#L10-2 assume !!(main_~i~0 < 100); 2760#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2759#L10-2 assume !!(main_~i~0 < 100); 2758#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2757#L10-2 assume !!(main_~i~0 < 100); 2756#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2755#L10-2 assume !!(main_~i~0 < 100); 2754#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2753#L10-2 assume !!(main_~i~0 < 100); 2752#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2751#L10-2 assume !!(main_~i~0 < 100); 2750#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2749#L10-2 assume !!(main_~i~0 < 100); 2748#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2747#L10-2 assume !!(main_~i~0 < 100); 2746#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2745#L10-2 assume !!(main_~i~0 < 100); 2744#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2743#L10-2 assume !!(main_~i~0 < 100); 2742#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2741#L10-2 assume !!(main_~i~0 < 100); 2740#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2739#L10-2 assume !!(main_~i~0 < 100); 2738#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2737#L10-2 assume !!(main_~i~0 < 100); 2736#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2735#L10-2 assume !!(main_~i~0 < 100); 2734#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2733#L10-2 assume !!(main_~i~0 < 100); 2731#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2730#L10-2 assume !!(main_~i~0 < 100); 2729#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2728#L10-2 assume !!(main_~i~0 < 100); 2725#L10 [2021-10-28 08:59:52,063 INFO L793 eck$LassoCheckResult]: Loop: 2725#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 2726#L10-2 assume !!(main_~i~0 < 100); 2729#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2728#L10-2 assume !!(main_~i~0 < 100); 2725#L10 [2021-10-28 08:59:52,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,065 INFO L85 PathProgramCache]: Analyzing trace with hash -2091478348, now seen corresponding path program 18 times [2021-10-28 08:59:52,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,065 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43252334] [2021-10-28 08:59:52,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,065 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,074 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:52,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,091 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:52,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,093 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 16 times [2021-10-28 08:59:52,093 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,093 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446147315] [2021-10-28 08:59:52,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,093 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,101 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:52,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,103 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:52,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,103 INFO L85 PathProgramCache]: Analyzing trace with hash -72543892, now seen corresponding path program 18 times [2021-10-28 08:59:52,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,104 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094554944] [2021-10-28 08:59:52,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,104 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:52,383 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:52,384 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:52,384 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094554944] [2021-10-28 08:59:52,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094554944] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:52,384 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1668811207] [2021-10-28 08:59:52,385 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 08:59:52,385 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:52,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:52,387 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:52,393 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-10-28 08:59:52,611 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2021-10-28 08:59:52,611 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:52,612 INFO L263 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 08:59:52,613 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:52,799 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:52,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1668811207] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:52,800 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:52,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2021-10-28 08:59:52,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341714031] [2021-10-28 08:59:52,835 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:52,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-28 08:59:52,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-10-28 08:59:52,836 INFO L87 Difference]: Start difference. First operand 41 states and 43 transitions. cyclomatic complexity: 3 Second operand has 21 states, 21 states have (on average 1.9523809523809523) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:52,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:52,896 INFO L93 Difference]: Finished difference Result 45 states and 47 transitions. [2021-10-28 08:59:52,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-10-28 08:59:52,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 47 transitions. [2021-10-28 08:59:52,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:52,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 46 transitions. [2021-10-28 08:59:52,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:52,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:52,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 46 transitions. [2021-10-28 08:59:52,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:52,900 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 46 transitions. [2021-10-28 08:59:52,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 46 transitions. [2021-10-28 08:59:52,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2021-10-28 08:59:52,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.0465116279069768) internal successors, (45), 42 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:52,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 45 transitions. [2021-10-28 08:59:52,911 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2021-10-28 08:59:52,911 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2021-10-28 08:59:52,911 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-28 08:59:52,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 45 transitions. [2021-10-28 08:59:52,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:52,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:52,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:52,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 19, 1] [2021-10-28 08:59:52,913 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:52,914 INFO L791 eck$LassoCheckResult]: Stem: 2959#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 2955#L10-2 assume !!(main_~i~0 < 100); 2956#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2957#L10-2 assume !!(main_~i~0 < 100); 2958#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2962#L10-2 assume !!(main_~i~0 < 100); 2997#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2996#L10-2 assume !!(main_~i~0 < 100); 2995#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2994#L10-2 assume !!(main_~i~0 < 100); 2993#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2992#L10-2 assume !!(main_~i~0 < 100); 2991#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2990#L10-2 assume !!(main_~i~0 < 100); 2989#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2988#L10-2 assume !!(main_~i~0 < 100); 2987#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2986#L10-2 assume !!(main_~i~0 < 100); 2985#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2984#L10-2 assume !!(main_~i~0 < 100); 2983#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2982#L10-2 assume !!(main_~i~0 < 100); 2981#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2980#L10-2 assume !!(main_~i~0 < 100); 2979#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2978#L10-2 assume !!(main_~i~0 < 100); 2977#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2976#L10-2 assume !!(main_~i~0 < 100); 2975#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2974#L10-2 assume !!(main_~i~0 < 100); 2973#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2972#L10-2 assume !!(main_~i~0 < 100); 2971#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2970#L10-2 assume !!(main_~i~0 < 100); 2969#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2968#L10-2 assume !!(main_~i~0 < 100); 2966#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2965#L10-2 assume !!(main_~i~0 < 100); 2964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2963#L10-2 assume !!(main_~i~0 < 100); 2960#L10 [2021-10-28 08:59:52,916 INFO L793 eck$LassoCheckResult]: Loop: 2960#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 2961#L10-2 assume !!(main_~i~0 < 100); 2964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 2963#L10-2 assume !!(main_~i~0 < 100); 2960#L10 [2021-10-28 08:59:52,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,917 INFO L85 PathProgramCache]: Analyzing trace with hash 134002513, now seen corresponding path program 19 times [2021-10-28 08:59:52,917 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,917 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109246680] [2021-10-28 08:59:52,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,918 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,928 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:52,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,943 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:52,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 17 times [2021-10-28 08:59:52,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,946 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935471275] [2021-10-28 08:59:52,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,946 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,951 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:52,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:52,953 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:52,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:52,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1052401783, now seen corresponding path program 19 times [2021-10-28 08:59:52,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:52,954 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494027906] [2021-10-28 08:59:52,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:52,955 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:52,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:53,285 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:53,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:53,285 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494027906] [2021-10-28 08:59:53,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494027906] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:53,285 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1190004418] [2021-10-28 08:59:53,285 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 08:59:53,285 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:53,286 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:53,291 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:53,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-10-28 08:59:53,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:53,492 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 21 conjunts are in the unsatisfiable core [2021-10-28 08:59:53,493 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:53,654 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:53,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1190004418] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:53,655 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:53,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2021-10-28 08:59:53,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392998915] [2021-10-28 08:59:53,685 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:53,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-10-28 08:59:53,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-10-28 08:59:53,686 INFO L87 Difference]: Start difference. First operand 43 states and 45 transitions. cyclomatic complexity: 3 Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 21 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:53,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:53,754 INFO L93 Difference]: Finished difference Result 47 states and 49 transitions. [2021-10-28 08:59:53,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-10-28 08:59:53,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 49 transitions. [2021-10-28 08:59:53,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:53,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 46 states and 48 transitions. [2021-10-28 08:59:53,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:53,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:53,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 48 transitions. [2021-10-28 08:59:53,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:53,756 INFO L681 BuchiCegarLoop]: Abstraction has 46 states and 48 transitions. [2021-10-28 08:59:53,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 48 transitions. [2021-10-28 08:59:53,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2021-10-28 08:59:53,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0444444444444445) internal successors, (47), 44 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:53,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2021-10-28 08:59:53,760 INFO L704 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2021-10-28 08:59:53,760 INFO L587 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2021-10-28 08:59:53,760 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-28 08:59:53,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 47 transitions. [2021-10-28 08:59:53,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:53,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:53,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:53,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 20, 1] [2021-10-28 08:59:53,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:53,762 INFO L791 eck$LassoCheckResult]: Stem: 3205#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 3201#L10-2 assume !!(main_~i~0 < 100); 3202#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3203#L10-2 assume !!(main_~i~0 < 100); 3204#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3208#L10-2 assume !!(main_~i~0 < 100); 3245#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3244#L10-2 assume !!(main_~i~0 < 100); 3243#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3242#L10-2 assume !!(main_~i~0 < 100); 3241#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3240#L10-2 assume !!(main_~i~0 < 100); 3239#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3238#L10-2 assume !!(main_~i~0 < 100); 3237#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3236#L10-2 assume !!(main_~i~0 < 100); 3235#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3234#L10-2 assume !!(main_~i~0 < 100); 3233#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3232#L10-2 assume !!(main_~i~0 < 100); 3231#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3230#L10-2 assume !!(main_~i~0 < 100); 3229#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3228#L10-2 assume !!(main_~i~0 < 100); 3227#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3226#L10-2 assume !!(main_~i~0 < 100); 3225#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3224#L10-2 assume !!(main_~i~0 < 100); 3223#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3222#L10-2 assume !!(main_~i~0 < 100); 3221#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3220#L10-2 assume !!(main_~i~0 < 100); 3219#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3218#L10-2 assume !!(main_~i~0 < 100); 3217#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3216#L10-2 assume !!(main_~i~0 < 100); 3215#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3214#L10-2 assume !!(main_~i~0 < 100); 3212#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3211#L10-2 assume !!(main_~i~0 < 100); 3210#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3209#L10-2 assume !!(main_~i~0 < 100); 3206#L10 [2021-10-28 08:59:53,762 INFO L793 eck$LassoCheckResult]: Loop: 3206#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 3207#L10-2 assume !!(main_~i~0 < 100); 3210#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3209#L10-2 assume !!(main_~i~0 < 100); 3206#L10 [2021-10-28 08:59:53,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:53,763 INFO L85 PathProgramCache]: Analyzing trace with hash -72603474, now seen corresponding path program 20 times [2021-10-28 08:59:53,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:53,763 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831734802] [2021-10-28 08:59:53,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:53,763 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:53,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:53,772 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:53,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:53,796 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:53,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:53,797 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 18 times [2021-10-28 08:59:53,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:53,798 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350602467] [2021-10-28 08:59:53,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:53,798 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:53,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:53,804 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:53,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:53,806 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:53,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:53,807 INFO L85 PathProgramCache]: Analyzing trace with hash -2097997210, now seen corresponding path program 20 times [2021-10-28 08:59:53,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:53,807 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858317837] [2021-10-28 08:59:53,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:53,808 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:53,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:54,128 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:54,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:54,128 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858317837] [2021-10-28 08:59:54,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858317837] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:54,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [777441721] [2021-10-28 08:59:54,129 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 08:59:54,129 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:54,129 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:54,131 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:54,132 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-10-28 08:59:54,356 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 08:59:54,356 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:54,357 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 08:59:54,358 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:54,552 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:54,553 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [777441721] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:54,553 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:54,553 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2021-10-28 08:59:54,553 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300321958] [2021-10-28 08:59:54,589 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:54,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-10-28 08:59:54,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-10-28 08:59:54,591 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. cyclomatic complexity: 3 Second operand has 23 states, 23 states have (on average 1.9565217391304348) internal successors, (45), 22 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:54,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:54,656 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2021-10-28 08:59:54,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-10-28 08:59:54,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 51 transitions. [2021-10-28 08:59:54,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:54,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 48 states and 50 transitions. [2021-10-28 08:59:54,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:54,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:54,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 50 transitions. [2021-10-28 08:59:54,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:54,659 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 50 transitions. [2021-10-28 08:59:54,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 50 transitions. [2021-10-28 08:59:54,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 47. [2021-10-28 08:59:54,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0425531914893618) internal successors, (49), 46 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:54,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2021-10-28 08:59:54,661 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2021-10-28 08:59:54,661 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2021-10-28 08:59:54,661 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-28 08:59:54,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2021-10-28 08:59:54,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:54,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:54,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:54,662 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 21, 1] [2021-10-28 08:59:54,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:54,663 INFO L791 eck$LassoCheckResult]: Stem: 3462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 3458#L10-2 assume !!(main_~i~0 < 100); 3459#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3460#L10-2 assume !!(main_~i~0 < 100); 3461#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3465#L10-2 assume !!(main_~i~0 < 100); 3504#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3503#L10-2 assume !!(main_~i~0 < 100); 3502#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3501#L10-2 assume !!(main_~i~0 < 100); 3500#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3499#L10-2 assume !!(main_~i~0 < 100); 3498#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3497#L10-2 assume !!(main_~i~0 < 100); 3496#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3495#L10-2 assume !!(main_~i~0 < 100); 3494#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3493#L10-2 assume !!(main_~i~0 < 100); 3492#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3491#L10-2 assume !!(main_~i~0 < 100); 3490#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3489#L10-2 assume !!(main_~i~0 < 100); 3488#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3487#L10-2 assume !!(main_~i~0 < 100); 3486#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3485#L10-2 assume !!(main_~i~0 < 100); 3484#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3483#L10-2 assume !!(main_~i~0 < 100); 3482#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3481#L10-2 assume !!(main_~i~0 < 100); 3480#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3479#L10-2 assume !!(main_~i~0 < 100); 3478#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3477#L10-2 assume !!(main_~i~0 < 100); 3476#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3475#L10-2 assume !!(main_~i~0 < 100); 3474#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3473#L10-2 assume !!(main_~i~0 < 100); 3472#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3471#L10-2 assume !!(main_~i~0 < 100); 3469#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3468#L10-2 assume !!(main_~i~0 < 100); 3467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3466#L10-2 assume !!(main_~i~0 < 100); 3463#L10 [2021-10-28 08:59:54,663 INFO L793 eck$LassoCheckResult]: Loop: 3463#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 3464#L10-2 assume !!(main_~i~0 < 100); 3467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3466#L10-2 assume !!(main_~i~0 < 100); 3463#L10 [2021-10-28 08:59:54,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:54,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1052461365, now seen corresponding path program 21 times [2021-10-28 08:59:54,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:54,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484297097] [2021-10-28 08:59:54,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:54,664 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:54,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:54,704 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:54,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:54,723 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:54,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:54,724 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 19 times [2021-10-28 08:59:54,724 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:54,724 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381581520] [2021-10-28 08:59:54,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:54,725 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:54,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:54,742 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:54,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:54,744 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:54,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:54,744 INFO L85 PathProgramCache]: Analyzing trace with hash -1892855293, now seen corresponding path program 21 times [2021-10-28 08:59:54,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:54,745 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857356187] [2021-10-28 08:59:54,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:54,745 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:54,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:55,207 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:55,207 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:55,208 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857356187] [2021-10-28 08:59:55,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857356187] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:55,208 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [83294629] [2021-10-28 08:59:55,208 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 08:59:55,208 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:55,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:55,211 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:55,237 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-10-28 08:59:55,470 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2021-10-28 08:59:55,470 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:55,472 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 23 conjunts are in the unsatisfiable core [2021-10-28 08:59:55,473 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:55,634 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:55,634 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [83294629] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:55,634 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:55,635 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2021-10-28 08:59:55,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161346799] [2021-10-28 08:59:55,685 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:55,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-10-28 08:59:55,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-10-28 08:59:55,686 INFO L87 Difference]: Start difference. First operand 47 states and 49 transitions. cyclomatic complexity: 3 Second operand has 24 states, 24 states have (on average 1.9583333333333333) internal successors, (47), 23 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:55,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:55,766 INFO L93 Difference]: Finished difference Result 51 states and 53 transitions. [2021-10-28 08:59:55,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-10-28 08:59:55,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 53 transitions. [2021-10-28 08:59:55,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:55,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 52 transitions. [2021-10-28 08:59:55,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:55,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:55,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 52 transitions. [2021-10-28 08:59:55,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:55,769 INFO L681 BuchiCegarLoop]: Abstraction has 50 states and 52 transitions. [2021-10-28 08:59:55,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 52 transitions. [2021-10-28 08:59:55,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2021-10-28 08:59:55,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0408163265306123) internal successors, (51), 48 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:55,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2021-10-28 08:59:55,772 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2021-10-28 08:59:55,772 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2021-10-28 08:59:55,772 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-28 08:59:55,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 51 transitions. [2021-10-28 08:59:55,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:55,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:55,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:55,774 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 22, 1] [2021-10-28 08:59:55,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:55,775 INFO L791 eck$LassoCheckResult]: Stem: 3730#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 3726#L10-2 assume !!(main_~i~0 < 100); 3727#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3728#L10-2 assume !!(main_~i~0 < 100); 3729#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3733#L10-2 assume !!(main_~i~0 < 100); 3774#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3773#L10-2 assume !!(main_~i~0 < 100); 3772#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3771#L10-2 assume !!(main_~i~0 < 100); 3770#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3769#L10-2 assume !!(main_~i~0 < 100); 3768#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3767#L10-2 assume !!(main_~i~0 < 100); 3766#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3765#L10-2 assume !!(main_~i~0 < 100); 3764#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3763#L10-2 assume !!(main_~i~0 < 100); 3762#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3761#L10-2 assume !!(main_~i~0 < 100); 3760#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3759#L10-2 assume !!(main_~i~0 < 100); 3758#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3757#L10-2 assume !!(main_~i~0 < 100); 3756#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3755#L10-2 assume !!(main_~i~0 < 100); 3754#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3753#L10-2 assume !!(main_~i~0 < 100); 3752#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3751#L10-2 assume !!(main_~i~0 < 100); 3750#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3749#L10-2 assume !!(main_~i~0 < 100); 3748#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3747#L10-2 assume !!(main_~i~0 < 100); 3746#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3745#L10-2 assume !!(main_~i~0 < 100); 3744#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3743#L10-2 assume !!(main_~i~0 < 100); 3742#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3741#L10-2 assume !!(main_~i~0 < 100); 3740#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3739#L10-2 assume !!(main_~i~0 < 100); 3737#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3736#L10-2 assume !!(main_~i~0 < 100); 3735#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3734#L10-2 assume !!(main_~i~0 < 100); 3731#L10 [2021-10-28 08:59:55,775 INFO L793 eck$LassoCheckResult]: Loop: 3731#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 3732#L10-2 assume !!(main_~i~0 < 100); 3735#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 3734#L10-2 assume !!(main_~i~0 < 100); 3731#L10 [2021-10-28 08:59:55,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:55,775 INFO L85 PathProgramCache]: Analyzing trace with hash -2098056792, now seen corresponding path program 22 times [2021-10-28 08:59:55,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:55,776 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079943983] [2021-10-28 08:59:55,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:55,776 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:55,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:55,786 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:55,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:55,794 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:55,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:55,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 20 times [2021-10-28 08:59:55,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:55,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953351232] [2021-10-28 08:59:55,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:55,795 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:55,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:55,799 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:55,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:55,801 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:55,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:55,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1974998624, now seen corresponding path program 22 times [2021-10-28 08:59:55,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:55,802 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765495204] [2021-10-28 08:59:55,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:55,802 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:55,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:56,146 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:56,146 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:56,147 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765495204] [2021-10-28 08:59:56,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765495204] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:56,147 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87412908] [2021-10-28 08:59:56,147 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 08:59:56,147 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:56,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:56,148 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:56,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-10-28 08:59:56,432 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 08:59:56,432 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:56,433 INFO L263 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 24 conjunts are in the unsatisfiable core [2021-10-28 08:59:56,434 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:56,643 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:56,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87412908] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:56,644 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:56,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2021-10-28 08:59:56,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253401268] [2021-10-28 08:59:56,681 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:56,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-10-28 08:59:56,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-10-28 08:59:56,682 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 24 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:56,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:56,746 INFO L93 Difference]: Finished difference Result 53 states and 55 transitions. [2021-10-28 08:59:56,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-10-28 08:59:56,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 55 transitions. [2021-10-28 08:59:56,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:56,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 54 transitions. [2021-10-28 08:59:56,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:56,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:56,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 54 transitions. [2021-10-28 08:59:56,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:56,750 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2021-10-28 08:59:56,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 54 transitions. [2021-10-28 08:59:56,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2021-10-28 08:59:56,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0392156862745099) internal successors, (53), 50 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:56,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 53 transitions. [2021-10-28 08:59:56,752 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2021-10-28 08:59:56,752 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2021-10-28 08:59:56,753 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-10-28 08:59:56,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 53 transitions. [2021-10-28 08:59:56,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:56,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:56,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:56,755 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 1] [2021-10-28 08:59:56,755 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:56,755 INFO L791 eck$LassoCheckResult]: Stem: 4009#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 4005#L10-2 assume !!(main_~i~0 < 100); 4006#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4007#L10-2 assume !!(main_~i~0 < 100); 4008#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4012#L10-2 assume !!(main_~i~0 < 100); 4055#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4054#L10-2 assume !!(main_~i~0 < 100); 4053#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4052#L10-2 assume !!(main_~i~0 < 100); 4051#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4050#L10-2 assume !!(main_~i~0 < 100); 4049#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4048#L10-2 assume !!(main_~i~0 < 100); 4047#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4046#L10-2 assume !!(main_~i~0 < 100); 4045#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4044#L10-2 assume !!(main_~i~0 < 100); 4043#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4042#L10-2 assume !!(main_~i~0 < 100); 4041#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4040#L10-2 assume !!(main_~i~0 < 100); 4039#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4038#L10-2 assume !!(main_~i~0 < 100); 4037#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4036#L10-2 assume !!(main_~i~0 < 100); 4035#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4034#L10-2 assume !!(main_~i~0 < 100); 4033#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4032#L10-2 assume !!(main_~i~0 < 100); 4031#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4030#L10-2 assume !!(main_~i~0 < 100); 4029#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4028#L10-2 assume !!(main_~i~0 < 100); 4027#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4026#L10-2 assume !!(main_~i~0 < 100); 4025#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4024#L10-2 assume !!(main_~i~0 < 100); 4023#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4022#L10-2 assume !!(main_~i~0 < 100); 4021#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4020#L10-2 assume !!(main_~i~0 < 100); 4019#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4018#L10-2 assume !!(main_~i~0 < 100); 4016#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4015#L10-2 assume !!(main_~i~0 < 100); 4014#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4013#L10-2 assume !!(main_~i~0 < 100); 4010#L10 [2021-10-28 08:59:56,755 INFO L793 eck$LassoCheckResult]: Loop: 4010#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 4011#L10-2 assume !!(main_~i~0 < 100); 4014#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4013#L10-2 assume !!(main_~i~0 < 100); 4010#L10 [2021-10-28 08:59:56,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:56,756 INFO L85 PathProgramCache]: Analyzing trace with hash -1892914875, now seen corresponding path program 23 times [2021-10-28 08:59:56,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:56,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629160700] [2021-10-28 08:59:56,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:56,757 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:56,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:56,770 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:56,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:56,781 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:56,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:56,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 21 times [2021-10-28 08:59:56,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:56,782 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445181103] [2021-10-28 08:59:56,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:56,782 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:56,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:56,789 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:56,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:56,791 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:56,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:56,792 INFO L85 PathProgramCache]: Analyzing trace with hash -459065475, now seen corresponding path program 23 times [2021-10-28 08:59:56,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:56,792 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500337477] [2021-10-28 08:59:56,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:56,793 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:56,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:57,180 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:57,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:57,180 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500337477] [2021-10-28 08:59:57,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500337477] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:57,180 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [5739320] [2021-10-28 08:59:57,180 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 08:59:57,181 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:57,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:57,187 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:57,206 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-10-28 08:59:57,512 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2021-10-28 08:59:57,512 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:57,513 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 25 conjunts are in the unsatisfiable core [2021-10-28 08:59:57,513 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:57,704 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:57,705 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [5739320] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:57,705 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:57,705 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2021-10-28 08:59:57,705 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3328826] [2021-10-28 08:59:57,739 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:57,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-10-28 08:59:57,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-10-28 08:59:57,741 INFO L87 Difference]: Start difference. First operand 51 states and 53 transitions. cyclomatic complexity: 3 Second operand has 26 states, 26 states have (on average 1.9615384615384615) internal successors, (51), 25 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:57,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:57,814 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2021-10-28 08:59:57,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-10-28 08:59:57,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2021-10-28 08:59:57,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:57,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 54 states and 56 transitions. [2021-10-28 08:59:57,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:57,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:57,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 56 transitions. [2021-10-28 08:59:57,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:57,816 INFO L681 BuchiCegarLoop]: Abstraction has 54 states and 56 transitions. [2021-10-28 08:59:57,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 56 transitions. [2021-10-28 08:59:57,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 53. [2021-10-28 08:59:57,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.0377358490566038) internal successors, (55), 52 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:57,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 55 transitions. [2021-10-28 08:59:57,818 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2021-10-28 08:59:57,818 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2021-10-28 08:59:57,819 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-10-28 08:59:57,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 55 transitions. [2021-10-28 08:59:57,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:57,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:57,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:57,820 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 24, 1] [2021-10-28 08:59:57,820 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:57,820 INFO L791 eck$LassoCheckResult]: Stem: 4299#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 4295#L10-2 assume !!(main_~i~0 < 100); 4296#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4297#L10-2 assume !!(main_~i~0 < 100); 4298#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4302#L10-2 assume !!(main_~i~0 < 100); 4347#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4346#L10-2 assume !!(main_~i~0 < 100); 4345#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4344#L10-2 assume !!(main_~i~0 < 100); 4343#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4342#L10-2 assume !!(main_~i~0 < 100); 4341#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4340#L10-2 assume !!(main_~i~0 < 100); 4339#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4338#L10-2 assume !!(main_~i~0 < 100); 4337#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4336#L10-2 assume !!(main_~i~0 < 100); 4335#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4334#L10-2 assume !!(main_~i~0 < 100); 4333#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4332#L10-2 assume !!(main_~i~0 < 100); 4331#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4330#L10-2 assume !!(main_~i~0 < 100); 4329#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4328#L10-2 assume !!(main_~i~0 < 100); 4327#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4326#L10-2 assume !!(main_~i~0 < 100); 4325#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4324#L10-2 assume !!(main_~i~0 < 100); 4323#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4322#L10-2 assume !!(main_~i~0 < 100); 4321#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4320#L10-2 assume !!(main_~i~0 < 100); 4319#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4318#L10-2 assume !!(main_~i~0 < 100); 4317#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4316#L10-2 assume !!(main_~i~0 < 100); 4315#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4314#L10-2 assume !!(main_~i~0 < 100); 4313#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4312#L10-2 assume !!(main_~i~0 < 100); 4311#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4310#L10-2 assume !!(main_~i~0 < 100); 4309#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4308#L10-2 assume !!(main_~i~0 < 100); 4306#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4305#L10-2 assume !!(main_~i~0 < 100); 4304#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4303#L10-2 assume !!(main_~i~0 < 100); 4300#L10 [2021-10-28 08:59:57,820 INFO L793 eck$LassoCheckResult]: Loop: 4300#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 4301#L10-2 assume !!(main_~i~0 < 100); 4304#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4303#L10-2 assume !!(main_~i~0 < 100); 4300#L10 [2021-10-28 08:59:57,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:57,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1974939042, now seen corresponding path program 24 times [2021-10-28 08:59:57,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:57,821 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251240788] [2021-10-28 08:59:57,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:57,821 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:57,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:57,835 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:57,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:57,845 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:57,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:57,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 22 times [2021-10-28 08:59:57,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:57,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117980277] [2021-10-28 08:59:57,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:57,847 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:57,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:57,884 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:57,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:57,885 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:57,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:57,886 INFO L85 PathProgramCache]: Analyzing trace with hash 1162511706, now seen corresponding path program 24 times [2021-10-28 08:59:57,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:57,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604267638] [2021-10-28 08:59:57,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:57,886 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:57,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:58,274 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:58,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:58,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604267638] [2021-10-28 08:59:58,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604267638] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:58,275 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1829084894] [2021-10-28 08:59:58,275 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 08:59:58,275 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:58,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:58,282 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:58,287 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-10-28 08:59:58,648 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 27 check-sat command(s) [2021-10-28 08:59:58,648 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 08:59:58,650 INFO L263 TraceCheckSpWp]: Trace formula consists of 109 conjuncts, 26 conjunts are in the unsatisfiable core [2021-10-28 08:59:58,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:58,863 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:58,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1829084894] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:58,863 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:58,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2021-10-28 08:59:58,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063958629] [2021-10-28 08:59:58,896 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:58,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-10-28 08:59:58,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-10-28 08:59:58,897 INFO L87 Difference]: Start difference. First operand 53 states and 55 transitions. cyclomatic complexity: 3 Second operand has 27 states, 27 states have (on average 1.962962962962963) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:58,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:59:58,982 INFO L93 Difference]: Finished difference Result 57 states and 59 transitions. [2021-10-28 08:59:58,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-10-28 08:59:58,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 59 transitions. [2021-10-28 08:59:58,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:58,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 56 states and 58 transitions. [2021-10-28 08:59:58,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 08:59:58,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 08:59:58,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 58 transitions. [2021-10-28 08:59:58,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 08:59:58,985 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 58 transitions. [2021-10-28 08:59:58,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 58 transitions. [2021-10-28 08:59:58,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 55. [2021-10-28 08:59:58,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.0363636363636364) internal successors, (57), 54 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:59:58,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2021-10-28 08:59:58,988 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2021-10-28 08:59:58,988 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2021-10-28 08:59:58,988 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-10-28 08:59:58,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2021-10-28 08:59:58,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 08:59:58,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:59:58,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:59:58,989 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 25, 1] [2021-10-28 08:59:58,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 08:59:58,990 INFO L791 eck$LassoCheckResult]: Stem: 4600#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 4596#L10-2 assume !!(main_~i~0 < 100); 4597#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4598#L10-2 assume !!(main_~i~0 < 100); 4599#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4603#L10-2 assume !!(main_~i~0 < 100); 4650#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4649#L10-2 assume !!(main_~i~0 < 100); 4648#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4647#L10-2 assume !!(main_~i~0 < 100); 4646#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4645#L10-2 assume !!(main_~i~0 < 100); 4644#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4643#L10-2 assume !!(main_~i~0 < 100); 4642#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4641#L10-2 assume !!(main_~i~0 < 100); 4640#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4639#L10-2 assume !!(main_~i~0 < 100); 4638#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4637#L10-2 assume !!(main_~i~0 < 100); 4636#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4635#L10-2 assume !!(main_~i~0 < 100); 4634#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4633#L10-2 assume !!(main_~i~0 < 100); 4632#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4631#L10-2 assume !!(main_~i~0 < 100); 4630#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4629#L10-2 assume !!(main_~i~0 < 100); 4628#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4627#L10-2 assume !!(main_~i~0 < 100); 4626#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4625#L10-2 assume !!(main_~i~0 < 100); 4624#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4623#L10-2 assume !!(main_~i~0 < 100); 4622#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4621#L10-2 assume !!(main_~i~0 < 100); 4620#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4619#L10-2 assume !!(main_~i~0 < 100); 4618#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4617#L10-2 assume !!(main_~i~0 < 100); 4616#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4615#L10-2 assume !!(main_~i~0 < 100); 4614#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4613#L10-2 assume !!(main_~i~0 < 100); 4612#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4611#L10-2 assume !!(main_~i~0 < 100); 4610#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4609#L10-2 assume !!(main_~i~0 < 100); 4607#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4606#L10-2 assume !!(main_~i~0 < 100); 4605#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4604#L10-2 assume !!(main_~i~0 < 100); 4601#L10 [2021-10-28 08:59:58,990 INFO L793 eck$LassoCheckResult]: Loop: 4601#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 4602#L10-2 assume !!(main_~i~0 < 100); 4605#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4604#L10-2 assume !!(main_~i~0 < 100); 4601#L10 [2021-10-28 08:59:58,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:58,990 INFO L85 PathProgramCache]: Analyzing trace with hash -459125057, now seen corresponding path program 25 times [2021-10-28 08:59:58,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:58,990 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334871973] [2021-10-28 08:59:58,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:58,991 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:59,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:59,001 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:59,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:59,011 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:59,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:59,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 23 times [2021-10-28 08:59:59,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:59,012 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705584725] [2021-10-28 08:59:59,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:59,013 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:59,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:59,017 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:59:59,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:59:59,019 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:59:59,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:59:59,020 INFO L85 PathProgramCache]: Analyzing trace with hash 425054199, now seen corresponding path program 25 times [2021-10-28 08:59:59,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:59:59,020 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204014843] [2021-10-28 08:59:59,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:59:59,021 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:59:59,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:59,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:59:59,417 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204014843] [2021-10-28 08:59:59,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204014843] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:59,417 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [595707677] [2021-10-28 08:59:59,417 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 08:59:59,417 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 08:59:59,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:59:59,418 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 08:59:59,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-10-28 08:59:59,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:59:59,735 INFO L263 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 27 conjunts are in the unsatisfiable core [2021-10-28 08:59:59,739 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 08:59:59,943 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 08:59:59,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [595707677] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 08:59:59,944 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 08:59:59,944 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2021-10-28 08:59:59,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876137118] [2021-10-28 08:59:59,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:59:59,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-10-28 08:59:59,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-10-28 08:59:59,976 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 3 Second operand has 28 states, 28 states have (on average 1.9642857142857142) internal successors, (55), 27 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:00,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:00,054 INFO L93 Difference]: Finished difference Result 59 states and 61 transitions. [2021-10-28 09:00:00,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-10-28 09:00:00,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 61 transitions. [2021-10-28 09:00:00,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:00,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 58 states and 60 transitions. [2021-10-28 09:00:00,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:00,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:00,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 60 transitions. [2021-10-28 09:00:00,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:00,057 INFO L681 BuchiCegarLoop]: Abstraction has 58 states and 60 transitions. [2021-10-28 09:00:00,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 60 transitions. [2021-10-28 09:00:00,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2021-10-28 09:00:00,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.0350877192982457) internal successors, (59), 56 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:00,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 59 transitions. [2021-10-28 09:00:00,059 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2021-10-28 09:00:00,060 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2021-10-28 09:00:00,060 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-10-28 09:00:00,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 59 transitions. [2021-10-28 09:00:00,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:00,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:00,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:00,062 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 26, 1] [2021-10-28 09:00:00,062 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:00,062 INFO L791 eck$LassoCheckResult]: Stem: 4912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 4908#L10-2 assume !!(main_~i~0 < 100); 4909#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4910#L10-2 assume !!(main_~i~0 < 100); 4911#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4915#L10-2 assume !!(main_~i~0 < 100); 4964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4963#L10-2 assume !!(main_~i~0 < 100); 4962#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4961#L10-2 assume !!(main_~i~0 < 100); 4960#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4959#L10-2 assume !!(main_~i~0 < 100); 4958#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4957#L10-2 assume !!(main_~i~0 < 100); 4956#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4955#L10-2 assume !!(main_~i~0 < 100); 4954#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4953#L10-2 assume !!(main_~i~0 < 100); 4952#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4951#L10-2 assume !!(main_~i~0 < 100); 4950#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4949#L10-2 assume !!(main_~i~0 < 100); 4948#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4947#L10-2 assume !!(main_~i~0 < 100); 4946#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4945#L10-2 assume !!(main_~i~0 < 100); 4944#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4943#L10-2 assume !!(main_~i~0 < 100); 4942#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4941#L10-2 assume !!(main_~i~0 < 100); 4940#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4939#L10-2 assume !!(main_~i~0 < 100); 4938#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4937#L10-2 assume !!(main_~i~0 < 100); 4936#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4935#L10-2 assume !!(main_~i~0 < 100); 4934#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4933#L10-2 assume !!(main_~i~0 < 100); 4932#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4931#L10-2 assume !!(main_~i~0 < 100); 4930#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4929#L10-2 assume !!(main_~i~0 < 100); 4928#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4927#L10-2 assume !!(main_~i~0 < 100); 4926#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4925#L10-2 assume !!(main_~i~0 < 100); 4924#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4923#L10-2 assume !!(main_~i~0 < 100); 4922#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4921#L10-2 assume !!(main_~i~0 < 100); 4919#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4918#L10-2 assume !!(main_~i~0 < 100); 4917#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4916#L10-2 assume !!(main_~i~0 < 100); 4913#L10 [2021-10-28 09:00:00,062 INFO L793 eck$LassoCheckResult]: Loop: 4913#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 4914#L10-2 assume !!(main_~i~0 < 100); 4917#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 4916#L10-2 assume !!(main_~i~0 < 100); 4913#L10 [2021-10-28 09:00:00,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:00,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1162452124, now seen corresponding path program 26 times [2021-10-28 09:00:00,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:00,063 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550177318] [2021-10-28 09:00:00,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:00,063 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:00,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:00,078 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:00,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:00,090 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:00,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:00,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 24 times [2021-10-28 09:00:00,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:00,091 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787857443] [2021-10-28 09:00:00,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:00,091 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:00,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:00,121 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:00,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:00,122 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:00,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:00,123 INFO L85 PathProgramCache]: Analyzing trace with hash 397993812, now seen corresponding path program 26 times [2021-10-28 09:00:00,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:00,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643171262] [2021-10-28 09:00:00,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:00,124 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:00,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:00,561 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:00,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:00,561 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643171262] [2021-10-28 09:00:00,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643171262] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:00,561 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [917299602] [2021-10-28 09:00:00,562 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:00:00,562 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:00,562 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:00,567 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:00,568 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-10-28 09:00:00,891 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:00:00,892 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:00,893 INFO L263 TraceCheckSpWp]: Trace formula consists of 117 conjuncts, 28 conjunts are in the unsatisfiable core [2021-10-28 09:00:00,893 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:01,123 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:01,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [917299602] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:01,124 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:01,124 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2021-10-28 09:00:01,124 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264368170] [2021-10-28 09:00:01,163 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:01,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-10-28 09:00:01,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-10-28 09:00:01,165 INFO L87 Difference]: Start difference. First operand 57 states and 59 transitions. cyclomatic complexity: 3 Second operand has 29 states, 29 states have (on average 1.9655172413793103) internal successors, (57), 28 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:01,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:01,278 INFO L93 Difference]: Finished difference Result 61 states and 63 transitions. [2021-10-28 09:00:01,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-10-28 09:00:01,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 63 transitions. [2021-10-28 09:00:01,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:01,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 60 states and 62 transitions. [2021-10-28 09:00:01,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:01,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:01,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 62 transitions. [2021-10-28 09:00:01,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:01,281 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 62 transitions. [2021-10-28 09:00:01,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 62 transitions. [2021-10-28 09:00:01,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 59. [2021-10-28 09:00:01,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.0338983050847457) internal successors, (61), 58 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:01,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 61 transitions. [2021-10-28 09:00:01,284 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2021-10-28 09:00:01,284 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2021-10-28 09:00:01,284 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-10-28 09:00:01,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 61 transitions. [2021-10-28 09:00:01,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:01,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:01,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:01,286 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 1] [2021-10-28 09:00:01,286 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:01,286 INFO L791 eck$LassoCheckResult]: Stem: 5235#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 5231#L10-2 assume !!(main_~i~0 < 100); 5232#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5233#L10-2 assume !!(main_~i~0 < 100); 5234#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5238#L10-2 assume !!(main_~i~0 < 100); 5289#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5288#L10-2 assume !!(main_~i~0 < 100); 5287#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5286#L10-2 assume !!(main_~i~0 < 100); 5285#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5284#L10-2 assume !!(main_~i~0 < 100); 5283#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5282#L10-2 assume !!(main_~i~0 < 100); 5281#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5280#L10-2 assume !!(main_~i~0 < 100); 5279#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5278#L10-2 assume !!(main_~i~0 < 100); 5277#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5276#L10-2 assume !!(main_~i~0 < 100); 5275#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5274#L10-2 assume !!(main_~i~0 < 100); 5273#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5272#L10-2 assume !!(main_~i~0 < 100); 5271#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5270#L10-2 assume !!(main_~i~0 < 100); 5269#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5268#L10-2 assume !!(main_~i~0 < 100); 5267#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5266#L10-2 assume !!(main_~i~0 < 100); 5265#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5264#L10-2 assume !!(main_~i~0 < 100); 5263#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5262#L10-2 assume !!(main_~i~0 < 100); 5261#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5260#L10-2 assume !!(main_~i~0 < 100); 5259#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5258#L10-2 assume !!(main_~i~0 < 100); 5257#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5256#L10-2 assume !!(main_~i~0 < 100); 5255#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5254#L10-2 assume !!(main_~i~0 < 100); 5253#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5252#L10-2 assume !!(main_~i~0 < 100); 5251#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5250#L10-2 assume !!(main_~i~0 < 100); 5249#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5248#L10-2 assume !!(main_~i~0 < 100); 5247#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5246#L10-2 assume !!(main_~i~0 < 100); 5245#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5244#L10-2 assume !!(main_~i~0 < 100); 5242#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5241#L10-2 assume !!(main_~i~0 < 100); 5240#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5239#L10-2 assume !!(main_~i~0 < 100); 5236#L10 [2021-10-28 09:00:01,286 INFO L793 eck$LassoCheckResult]: Loop: 5236#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 5237#L10-2 assume !!(main_~i~0 < 100); 5240#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5239#L10-2 assume !!(main_~i~0 < 100); 5236#L10 [2021-10-28 09:00:01,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:01,287 INFO L85 PathProgramCache]: Analyzing trace with hash 424994617, now seen corresponding path program 27 times [2021-10-28 09:00:01,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:01,287 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511888714] [2021-10-28 09:00:01,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:01,288 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:01,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:01,299 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:01,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:01,309 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:01,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:01,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 25 times [2021-10-28 09:00:01,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:01,310 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806811328] [2021-10-28 09:00:01,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:01,310 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:01,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:01,315 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:01,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:01,316 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:01,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:01,317 INFO L85 PathProgramCache]: Analyzing trace with hash 162765681, now seen corresponding path program 27 times [2021-10-28 09:00:01,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:01,317 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718160135] [2021-10-28 09:00:01,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:01,318 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:01,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:01,826 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:01,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:01,826 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718160135] [2021-10-28 09:00:01,826 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718160135] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:01,826 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [470464] [2021-10-28 09:00:01,826 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:00:01,827 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:01,827 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:01,829 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:01,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-10-28 09:00:02,213 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2021-10-28 09:00:02,213 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:02,214 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 29 conjunts are in the unsatisfiable core [2021-10-28 09:00:02,215 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:02,455 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:02,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [470464] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:02,456 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:02,456 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2021-10-28 09:00:02,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040658516] [2021-10-28 09:00:02,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:02,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-10-28 09:00:02,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-10-28 09:00:02,488 INFO L87 Difference]: Start difference. First operand 59 states and 61 transitions. cyclomatic complexity: 3 Second operand has 30 states, 30 states have (on average 1.9666666666666666) internal successors, (59), 29 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:02,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:02,564 INFO L93 Difference]: Finished difference Result 63 states and 65 transitions. [2021-10-28 09:00:02,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-10-28 09:00:02,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 65 transitions. [2021-10-28 09:00:02,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:02,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 62 states and 64 transitions. [2021-10-28 09:00:02,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:02,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:02,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 64 transitions. [2021-10-28 09:00:02,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:02,567 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 64 transitions. [2021-10-28 09:00:02,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 64 transitions. [2021-10-28 09:00:02,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2021-10-28 09:00:02,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.0327868852459017) internal successors, (63), 60 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:02,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 63 transitions. [2021-10-28 09:00:02,570 INFO L704 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2021-10-28 09:00:02,570 INFO L587 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2021-10-28 09:00:02,570 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-10-28 09:00:02,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 63 transitions. [2021-10-28 09:00:02,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:02,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:02,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:02,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 28, 1] [2021-10-28 09:00:02,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:02,577 INFO L791 eck$LassoCheckResult]: Stem: 5569#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 5565#L10-2 assume !!(main_~i~0 < 100); 5566#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5567#L10-2 assume !!(main_~i~0 < 100); 5568#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5572#L10-2 assume !!(main_~i~0 < 100); 5625#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5624#L10-2 assume !!(main_~i~0 < 100); 5623#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5622#L10-2 assume !!(main_~i~0 < 100); 5621#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5620#L10-2 assume !!(main_~i~0 < 100); 5619#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5618#L10-2 assume !!(main_~i~0 < 100); 5617#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5616#L10-2 assume !!(main_~i~0 < 100); 5615#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5614#L10-2 assume !!(main_~i~0 < 100); 5613#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5612#L10-2 assume !!(main_~i~0 < 100); 5611#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5610#L10-2 assume !!(main_~i~0 < 100); 5609#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5608#L10-2 assume !!(main_~i~0 < 100); 5607#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5606#L10-2 assume !!(main_~i~0 < 100); 5605#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5604#L10-2 assume !!(main_~i~0 < 100); 5603#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5602#L10-2 assume !!(main_~i~0 < 100); 5601#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5600#L10-2 assume !!(main_~i~0 < 100); 5599#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5598#L10-2 assume !!(main_~i~0 < 100); 5597#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5596#L10-2 assume !!(main_~i~0 < 100); 5595#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5594#L10-2 assume !!(main_~i~0 < 100); 5593#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5592#L10-2 assume !!(main_~i~0 < 100); 5591#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5590#L10-2 assume !!(main_~i~0 < 100); 5589#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5588#L10-2 assume !!(main_~i~0 < 100); 5587#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5586#L10-2 assume !!(main_~i~0 < 100); 5585#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5584#L10-2 assume !!(main_~i~0 < 100); 5583#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5582#L10-2 assume !!(main_~i~0 < 100); 5581#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5580#L10-2 assume !!(main_~i~0 < 100); 5579#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5578#L10-2 assume !!(main_~i~0 < 100); 5576#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5575#L10-2 assume !!(main_~i~0 < 100); 5574#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5573#L10-2 assume !!(main_~i~0 < 100); 5570#L10 [2021-10-28 09:00:02,577 INFO L793 eck$LassoCheckResult]: Loop: 5570#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 5571#L10-2 assume !!(main_~i~0 < 100); 5574#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5573#L10-2 assume !!(main_~i~0 < 100); 5570#L10 [2021-10-28 09:00:02,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:02,577 INFO L85 PathProgramCache]: Analyzing trace with hash 397934230, now seen corresponding path program 28 times [2021-10-28 09:00:02,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:02,578 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41786643] [2021-10-28 09:00:02,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:02,578 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:02,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:02,593 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:02,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:02,609 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:02,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:02,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 26 times [2021-10-28 09:00:02,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:02,610 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473182809] [2021-10-28 09:00:02,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:02,610 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:02,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:02,617 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:02,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:02,618 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:02,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:02,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1741798478, now seen corresponding path program 28 times [2021-10-28 09:00:02,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:02,619 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383125106] [2021-10-28 09:00:02,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:02,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:02,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:03,139 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:03,140 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:03,140 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1383125106] [2021-10-28 09:00:03,140 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1383125106] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:03,140 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [271550271] [2021-10-28 09:00:03,140 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 09:00:03,140 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:03,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:03,142 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:03,143 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-10-28 09:00:03,521 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 09:00:03,521 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:03,522 INFO L263 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 30 conjunts are in the unsatisfiable core [2021-10-28 09:00:03,523 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:03,743 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:03,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [271550271] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:03,743 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:03,743 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2021-10-28 09:00:03,743 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650764755] [2021-10-28 09:00:03,779 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:03,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-10-28 09:00:03,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-10-28 09:00:03,781 INFO L87 Difference]: Start difference. First operand 61 states and 63 transitions. cyclomatic complexity: 3 Second operand has 31 states, 31 states have (on average 1.967741935483871) internal successors, (61), 30 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:03,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:03,868 INFO L93 Difference]: Finished difference Result 65 states and 67 transitions. [2021-10-28 09:00:03,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-10-28 09:00:03,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 67 transitions. [2021-10-28 09:00:03,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:03,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 64 states and 66 transitions. [2021-10-28 09:00:03,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:03,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:03,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 66 transitions. [2021-10-28 09:00:03,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:03,872 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 66 transitions. [2021-10-28 09:00:03,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 66 transitions. [2021-10-28 09:00:03,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2021-10-28 09:00:03,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.0317460317460319) internal successors, (65), 62 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:03,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2021-10-28 09:00:03,875 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2021-10-28 09:00:03,875 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2021-10-28 09:00:03,875 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-10-28 09:00:03,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 65 transitions. [2021-10-28 09:00:03,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:03,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:03,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:03,877 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 29, 1] [2021-10-28 09:00:03,877 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:03,878 INFO L791 eck$LassoCheckResult]: Stem: 5914#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 5910#L10-2 assume !!(main_~i~0 < 100); 5911#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5912#L10-2 assume !!(main_~i~0 < 100); 5913#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5917#L10-2 assume !!(main_~i~0 < 100); 5972#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5971#L10-2 assume !!(main_~i~0 < 100); 5970#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5969#L10-2 assume !!(main_~i~0 < 100); 5968#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5967#L10-2 assume !!(main_~i~0 < 100); 5966#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5965#L10-2 assume !!(main_~i~0 < 100); 5964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5963#L10-2 assume !!(main_~i~0 < 100); 5962#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5961#L10-2 assume !!(main_~i~0 < 100); 5960#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5959#L10-2 assume !!(main_~i~0 < 100); 5958#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5957#L10-2 assume !!(main_~i~0 < 100); 5956#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5955#L10-2 assume !!(main_~i~0 < 100); 5954#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5953#L10-2 assume !!(main_~i~0 < 100); 5952#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5951#L10-2 assume !!(main_~i~0 < 100); 5950#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5949#L10-2 assume !!(main_~i~0 < 100); 5948#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5947#L10-2 assume !!(main_~i~0 < 100); 5946#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5945#L10-2 assume !!(main_~i~0 < 100); 5944#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5943#L10-2 assume !!(main_~i~0 < 100); 5942#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5941#L10-2 assume !!(main_~i~0 < 100); 5940#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5939#L10-2 assume !!(main_~i~0 < 100); 5938#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5937#L10-2 assume !!(main_~i~0 < 100); 5936#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5935#L10-2 assume !!(main_~i~0 < 100); 5934#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5933#L10-2 assume !!(main_~i~0 < 100); 5932#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5931#L10-2 assume !!(main_~i~0 < 100); 5930#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5929#L10-2 assume !!(main_~i~0 < 100); 5928#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5927#L10-2 assume !!(main_~i~0 < 100); 5926#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5925#L10-2 assume !!(main_~i~0 < 100); 5924#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5923#L10-2 assume !!(main_~i~0 < 100); 5921#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5920#L10-2 assume !!(main_~i~0 < 100); 5919#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5918#L10-2 assume !!(main_~i~0 < 100); 5915#L10 [2021-10-28 09:00:03,878 INFO L793 eck$LassoCheckResult]: Loop: 5915#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 5916#L10-2 assume !!(main_~i~0 < 100); 5919#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 5918#L10-2 assume !!(main_~i~0 < 100); 5915#L10 [2021-10-28 09:00:03,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:03,878 INFO L85 PathProgramCache]: Analyzing trace with hash 162706099, now seen corresponding path program 29 times [2021-10-28 09:00:03,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:03,879 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129703300] [2021-10-28 09:00:03,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:03,879 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:03,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:03,896 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:03,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:03,956 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:03,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:03,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 27 times [2021-10-28 09:00:03,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:03,957 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493467349] [2021-10-28 09:00:03,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:03,958 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:03,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:03,963 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:03,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:03,964 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:03,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:03,965 INFO L85 PathProgramCache]: Analyzing trace with hash -1226106389, now seen corresponding path program 29 times [2021-10-28 09:00:03,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:03,965 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340975978] [2021-10-28 09:00:03,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:03,965 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:03,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:04,521 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:04,521 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:04,521 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340975978] [2021-10-28 09:00:04,521 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340975978] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:04,521 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1173382217] [2021-10-28 09:00:04,522 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 09:00:04,522 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:04,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:04,524 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:04,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-10-28 09:00:05,048 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 32 check-sat command(s) [2021-10-28 09:00:05,049 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:05,050 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 31 conjunts are in the unsatisfiable core [2021-10-28 09:00:05,052 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:05,243 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:05,243 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1173382217] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:05,243 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:05,243 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2021-10-28 09:00:05,243 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058546873] [2021-10-28 09:00:05,267 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:05,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-10-28 09:00:05,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-10-28 09:00:05,269 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. cyclomatic complexity: 3 Second operand has 32 states, 32 states have (on average 1.96875) internal successors, (63), 31 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:05,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:05,428 INFO L93 Difference]: Finished difference Result 67 states and 69 transitions. [2021-10-28 09:00:05,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-10-28 09:00:05,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 69 transitions. [2021-10-28 09:00:05,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:05,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 66 states and 68 transitions. [2021-10-28 09:00:05,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:05,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:05,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 68 transitions. [2021-10-28 09:00:05,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:05,431 INFO L681 BuchiCegarLoop]: Abstraction has 66 states and 68 transitions. [2021-10-28 09:00:05,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 68 transitions. [2021-10-28 09:00:05,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 65. [2021-10-28 09:00:05,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.0307692307692307) internal successors, (67), 64 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:05,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 67 transitions. [2021-10-28 09:00:05,434 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2021-10-28 09:00:05,434 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2021-10-28 09:00:05,434 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-10-28 09:00:05,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 67 transitions. [2021-10-28 09:00:05,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:05,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:05,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:05,436 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 30, 1] [2021-10-28 09:00:05,436 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:05,436 INFO L791 eck$LassoCheckResult]: Stem: 6270#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 6266#L10-2 assume !!(main_~i~0 < 100); 6267#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6268#L10-2 assume !!(main_~i~0 < 100); 6269#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6273#L10-2 assume !!(main_~i~0 < 100); 6330#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6329#L10-2 assume !!(main_~i~0 < 100); 6328#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6327#L10-2 assume !!(main_~i~0 < 100); 6326#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6325#L10-2 assume !!(main_~i~0 < 100); 6324#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6323#L10-2 assume !!(main_~i~0 < 100); 6322#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6321#L10-2 assume !!(main_~i~0 < 100); 6320#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6319#L10-2 assume !!(main_~i~0 < 100); 6318#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6317#L10-2 assume !!(main_~i~0 < 100); 6316#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6315#L10-2 assume !!(main_~i~0 < 100); 6314#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6313#L10-2 assume !!(main_~i~0 < 100); 6312#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6311#L10-2 assume !!(main_~i~0 < 100); 6310#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6309#L10-2 assume !!(main_~i~0 < 100); 6308#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6307#L10-2 assume !!(main_~i~0 < 100); 6306#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6305#L10-2 assume !!(main_~i~0 < 100); 6304#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6303#L10-2 assume !!(main_~i~0 < 100); 6302#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6301#L10-2 assume !!(main_~i~0 < 100); 6300#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6299#L10-2 assume !!(main_~i~0 < 100); 6298#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6297#L10-2 assume !!(main_~i~0 < 100); 6296#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6295#L10-2 assume !!(main_~i~0 < 100); 6294#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6293#L10-2 assume !!(main_~i~0 < 100); 6292#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6291#L10-2 assume !!(main_~i~0 < 100); 6290#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6289#L10-2 assume !!(main_~i~0 < 100); 6288#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6287#L10-2 assume !!(main_~i~0 < 100); 6286#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6285#L10-2 assume !!(main_~i~0 < 100); 6284#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6283#L10-2 assume !!(main_~i~0 < 100); 6282#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6281#L10-2 assume !!(main_~i~0 < 100); 6280#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6279#L10-2 assume !!(main_~i~0 < 100); 6277#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6276#L10-2 assume !!(main_~i~0 < 100); 6275#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6274#L10-2 assume !!(main_~i~0 < 100); 6271#L10 [2021-10-28 09:00:05,436 INFO L793 eck$LassoCheckResult]: Loop: 6271#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 6272#L10-2 assume !!(main_~i~0 < 100); 6275#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6274#L10-2 assume !!(main_~i~0 < 100); 6271#L10 [2021-10-28 09:00:05,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:05,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1741738896, now seen corresponding path program 30 times [2021-10-28 09:00:05,437 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:05,437 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619194402] [2021-10-28 09:00:05,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:05,438 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:05,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:05,451 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:05,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:05,468 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:05,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:05,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 28 times [2021-10-28 09:00:05,469 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:05,469 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835537516] [2021-10-28 09:00:05,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:05,470 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:05,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:05,476 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:05,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:05,477 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:05,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:05,478 INFO L85 PathProgramCache]: Analyzing trace with hash -1524399032, now seen corresponding path program 30 times [2021-10-28 09:00:05,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:05,478 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985574009] [2021-10-28 09:00:05,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:05,479 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:05,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:06,052 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:06,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:06,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985574009] [2021-10-28 09:00:06,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985574009] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:06,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522236828] [2021-10-28 09:00:06,053 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 09:00:06,053 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:06,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:06,057 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:06,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-10-28 09:00:06,532 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 33 check-sat command(s) [2021-10-28 09:00:06,532 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:06,534 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 32 conjunts are in the unsatisfiable core [2021-10-28 09:00:06,535 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:06,785 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:06,786 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [522236828] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:06,786 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:06,786 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2021-10-28 09:00:06,786 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045103116] [2021-10-28 09:00:06,810 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:06,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-10-28 09:00:06,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-10-28 09:00:06,811 INFO L87 Difference]: Start difference. First operand 65 states and 67 transitions. cyclomatic complexity: 3 Second operand has 33 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 32 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:06,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:06,916 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2021-10-28 09:00:06,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-10-28 09:00:06,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 71 transitions. [2021-10-28 09:00:06,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:06,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 68 states and 70 transitions. [2021-10-28 09:00:06,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:06,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:06,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 70 transitions. [2021-10-28 09:00:06,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:06,920 INFO L681 BuchiCegarLoop]: Abstraction has 68 states and 70 transitions. [2021-10-28 09:00:06,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 70 transitions. [2021-10-28 09:00:06,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 67. [2021-10-28 09:00:06,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.0298507462686568) internal successors, (69), 66 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:06,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 69 transitions. [2021-10-28 09:00:06,923 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2021-10-28 09:00:06,923 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2021-10-28 09:00:06,923 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-10-28 09:00:06,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 69 transitions. [2021-10-28 09:00:06,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:06,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:06,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:06,925 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [32, 31, 1] [2021-10-28 09:00:06,925 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:06,925 INFO L791 eck$LassoCheckResult]: Stem: 6637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 6633#L10-2 assume !!(main_~i~0 < 100); 6634#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6635#L10-2 assume !!(main_~i~0 < 100); 6636#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6640#L10-2 assume !!(main_~i~0 < 100); 6699#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6698#L10-2 assume !!(main_~i~0 < 100); 6697#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6696#L10-2 assume !!(main_~i~0 < 100); 6695#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6694#L10-2 assume !!(main_~i~0 < 100); 6693#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6692#L10-2 assume !!(main_~i~0 < 100); 6691#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6690#L10-2 assume !!(main_~i~0 < 100); 6689#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6688#L10-2 assume !!(main_~i~0 < 100); 6687#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6686#L10-2 assume !!(main_~i~0 < 100); 6685#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6684#L10-2 assume !!(main_~i~0 < 100); 6683#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6682#L10-2 assume !!(main_~i~0 < 100); 6681#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6680#L10-2 assume !!(main_~i~0 < 100); 6679#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6678#L10-2 assume !!(main_~i~0 < 100); 6677#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6676#L10-2 assume !!(main_~i~0 < 100); 6675#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6674#L10-2 assume !!(main_~i~0 < 100); 6673#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6672#L10-2 assume !!(main_~i~0 < 100); 6671#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6670#L10-2 assume !!(main_~i~0 < 100); 6669#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6668#L10-2 assume !!(main_~i~0 < 100); 6667#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6666#L10-2 assume !!(main_~i~0 < 100); 6665#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6664#L10-2 assume !!(main_~i~0 < 100); 6663#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6662#L10-2 assume !!(main_~i~0 < 100); 6661#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6660#L10-2 assume !!(main_~i~0 < 100); 6659#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6658#L10-2 assume !!(main_~i~0 < 100); 6657#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6656#L10-2 assume !!(main_~i~0 < 100); 6655#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6654#L10-2 assume !!(main_~i~0 < 100); 6653#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6652#L10-2 assume !!(main_~i~0 < 100); 6651#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6650#L10-2 assume !!(main_~i~0 < 100); 6649#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6648#L10-2 assume !!(main_~i~0 < 100); 6647#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6646#L10-2 assume !!(main_~i~0 < 100); 6644#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6643#L10-2 assume !!(main_~i~0 < 100); 6642#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6641#L10-2 assume !!(main_~i~0 < 100); 6638#L10 [2021-10-28 09:00:06,926 INFO L793 eck$LassoCheckResult]: Loop: 6638#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 6639#L10-2 assume !!(main_~i~0 < 100); 6642#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 6641#L10-2 assume !!(main_~i~0 < 100); 6638#L10 [2021-10-28 09:00:06,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:06,926 INFO L85 PathProgramCache]: Analyzing trace with hash -1226165971, now seen corresponding path program 31 times [2021-10-28 09:00:06,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:06,927 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505908754] [2021-10-28 09:00:06,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:06,927 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:06,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:06,959 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:06,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:06,972 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:06,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:06,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 29 times [2021-10-28 09:00:06,973 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:06,973 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324520554] [2021-10-28 09:00:06,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:06,973 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:06,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:06,980 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:06,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:06,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:06,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:06,985 INFO L85 PathProgramCache]: Analyzing trace with hash -420820123, now seen corresponding path program 31 times [2021-10-28 09:00:06,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:06,985 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602153715] [2021-10-28 09:00:06,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:06,986 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:07,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:07,557 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:07,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:07,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602153715] [2021-10-28 09:00:07,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602153715] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:07,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [358813090] [2021-10-28 09:00:07,558 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:00:07,562 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:07,562 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:07,566 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:07,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-10-28 09:00:08,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:08,007 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 33 conjunts are in the unsatisfiable core [2021-10-28 09:00:08,009 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:08,252 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:08,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [358813090] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:08,252 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:08,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2021-10-28 09:00:08,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607355277] [2021-10-28 09:00:08,282 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:08,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-10-28 09:00:08,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-10-28 09:00:08,284 INFO L87 Difference]: Start difference. First operand 67 states and 69 transitions. cyclomatic complexity: 3 Second operand has 34 states, 34 states have (on average 1.9705882352941178) internal successors, (67), 33 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:08,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:08,372 INFO L93 Difference]: Finished difference Result 71 states and 73 transitions. [2021-10-28 09:00:08,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-10-28 09:00:08,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 73 transitions. [2021-10-28 09:00:08,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:08,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 72 transitions. [2021-10-28 09:00:08,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:08,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:08,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 72 transitions. [2021-10-28 09:00:08,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:08,377 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 72 transitions. [2021-10-28 09:00:08,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 72 transitions. [2021-10-28 09:00:08,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2021-10-28 09:00:08,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.0289855072463767) internal successors, (71), 68 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:08,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 71 transitions. [2021-10-28 09:00:08,380 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2021-10-28 09:00:08,380 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2021-10-28 09:00:08,381 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-10-28 09:00:08,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 71 transitions. [2021-10-28 09:00:08,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:08,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:08,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:08,383 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [33, 32, 1] [2021-10-28 09:00:08,383 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:08,384 INFO L791 eck$LassoCheckResult]: Stem: 7015#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 7011#L10-2 assume !!(main_~i~0 < 100); 7012#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7013#L10-2 assume !!(main_~i~0 < 100); 7014#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7018#L10-2 assume !!(main_~i~0 < 100); 7079#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7078#L10-2 assume !!(main_~i~0 < 100); 7077#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7076#L10-2 assume !!(main_~i~0 < 100); 7075#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7074#L10-2 assume !!(main_~i~0 < 100); 7073#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7072#L10-2 assume !!(main_~i~0 < 100); 7071#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7070#L10-2 assume !!(main_~i~0 < 100); 7069#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7068#L10-2 assume !!(main_~i~0 < 100); 7067#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7066#L10-2 assume !!(main_~i~0 < 100); 7065#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7064#L10-2 assume !!(main_~i~0 < 100); 7063#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7062#L10-2 assume !!(main_~i~0 < 100); 7061#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7060#L10-2 assume !!(main_~i~0 < 100); 7059#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7058#L10-2 assume !!(main_~i~0 < 100); 7057#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7056#L10-2 assume !!(main_~i~0 < 100); 7055#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7054#L10-2 assume !!(main_~i~0 < 100); 7053#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7052#L10-2 assume !!(main_~i~0 < 100); 7051#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7050#L10-2 assume !!(main_~i~0 < 100); 7049#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7048#L10-2 assume !!(main_~i~0 < 100); 7047#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7046#L10-2 assume !!(main_~i~0 < 100); 7045#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7044#L10-2 assume !!(main_~i~0 < 100); 7043#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7042#L10-2 assume !!(main_~i~0 < 100); 7041#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7040#L10-2 assume !!(main_~i~0 < 100); 7039#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7038#L10-2 assume !!(main_~i~0 < 100); 7037#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7036#L10-2 assume !!(main_~i~0 < 100); 7035#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7034#L10-2 assume !!(main_~i~0 < 100); 7033#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7032#L10-2 assume !!(main_~i~0 < 100); 7031#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7030#L10-2 assume !!(main_~i~0 < 100); 7029#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7028#L10-2 assume !!(main_~i~0 < 100); 7027#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7026#L10-2 assume !!(main_~i~0 < 100); 7025#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7024#L10-2 assume !!(main_~i~0 < 100); 7022#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7021#L10-2 assume !!(main_~i~0 < 100); 7020#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7019#L10-2 assume !!(main_~i~0 < 100); 7016#L10 [2021-10-28 09:00:08,384 INFO L793 eck$LassoCheckResult]: Loop: 7016#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 7017#L10-2 assume !!(main_~i~0 < 100); 7020#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7019#L10-2 assume !!(main_~i~0 < 100); 7016#L10 [2021-10-28 09:00:08,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:08,384 INFO L85 PathProgramCache]: Analyzing trace with hash -1524458614, now seen corresponding path program 32 times [2021-10-28 09:00:08,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:08,385 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335663446] [2021-10-28 09:00:08,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:08,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:08,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:08,404 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:08,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:08,426 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:08,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:08,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 30 times [2021-10-28 09:00:08,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:08,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856732054] [2021-10-28 09:00:08,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:08,427 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:08,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:08,437 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:08,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:08,439 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:08,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:08,439 INFO L85 PathProgramCache]: Analyzing trace with hash -738410686, now seen corresponding path program 32 times [2021-10-28 09:00:08,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:08,440 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038466365] [2021-10-28 09:00:08,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:08,440 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:08,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:08,986 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:08,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:08,986 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038466365] [2021-10-28 09:00:08,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038466365] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:08,986 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2053935098] [2021-10-28 09:00:08,987 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:00:08,987 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:08,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:08,988 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:09,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-10-28 09:00:09,474 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:00:09,474 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:09,475 INFO L263 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 34 conjunts are in the unsatisfiable core [2021-10-28 09:00:09,481 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:09,687 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:09,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2053935098] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:09,688 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:09,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2021-10-28 09:00:09,688 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881438553] [2021-10-28 09:00:09,730 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:09,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-10-28 09:00:09,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-10-28 09:00:09,731 INFO L87 Difference]: Start difference. First operand 69 states and 71 transitions. cyclomatic complexity: 3 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 34 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:09,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:09,806 INFO L93 Difference]: Finished difference Result 73 states and 75 transitions. [2021-10-28 09:00:09,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-10-28 09:00:09,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 75 transitions. [2021-10-28 09:00:09,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:09,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 72 states and 74 transitions. [2021-10-28 09:00:09,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:09,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:09,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 74 transitions. [2021-10-28 09:00:09,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:09,813 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 74 transitions. [2021-10-28 09:00:09,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 74 transitions. [2021-10-28 09:00:09,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 71. [2021-10-28 09:00:09,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.028169014084507) internal successors, (73), 70 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:09,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 73 transitions. [2021-10-28 09:00:09,815 INFO L704 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2021-10-28 09:00:09,815 INFO L587 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2021-10-28 09:00:09,815 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-10-28 09:00:09,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 73 transitions. [2021-10-28 09:00:09,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:09,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:09,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:09,817 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [34, 33, 1] [2021-10-28 09:00:09,818 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:09,818 INFO L791 eck$LassoCheckResult]: Stem: 7404#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 7400#L10-2 assume !!(main_~i~0 < 100); 7401#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7402#L10-2 assume !!(main_~i~0 < 100); 7403#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7407#L10-2 assume !!(main_~i~0 < 100); 7470#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7469#L10-2 assume !!(main_~i~0 < 100); 7468#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7467#L10-2 assume !!(main_~i~0 < 100); 7466#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7465#L10-2 assume !!(main_~i~0 < 100); 7464#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7463#L10-2 assume !!(main_~i~0 < 100); 7462#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7461#L10-2 assume !!(main_~i~0 < 100); 7460#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7459#L10-2 assume !!(main_~i~0 < 100); 7458#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7457#L10-2 assume !!(main_~i~0 < 100); 7456#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7455#L10-2 assume !!(main_~i~0 < 100); 7454#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7453#L10-2 assume !!(main_~i~0 < 100); 7452#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7451#L10-2 assume !!(main_~i~0 < 100); 7450#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7449#L10-2 assume !!(main_~i~0 < 100); 7448#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7447#L10-2 assume !!(main_~i~0 < 100); 7446#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7445#L10-2 assume !!(main_~i~0 < 100); 7444#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7443#L10-2 assume !!(main_~i~0 < 100); 7442#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7441#L10-2 assume !!(main_~i~0 < 100); 7440#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7439#L10-2 assume !!(main_~i~0 < 100); 7438#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7437#L10-2 assume !!(main_~i~0 < 100); 7436#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7435#L10-2 assume !!(main_~i~0 < 100); 7434#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7433#L10-2 assume !!(main_~i~0 < 100); 7432#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7431#L10-2 assume !!(main_~i~0 < 100); 7430#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7429#L10-2 assume !!(main_~i~0 < 100); 7428#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7427#L10-2 assume !!(main_~i~0 < 100); 7426#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7425#L10-2 assume !!(main_~i~0 < 100); 7424#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7423#L10-2 assume !!(main_~i~0 < 100); 7422#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7421#L10-2 assume !!(main_~i~0 < 100); 7420#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7419#L10-2 assume !!(main_~i~0 < 100); 7418#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7417#L10-2 assume !!(main_~i~0 < 100); 7416#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7415#L10-2 assume !!(main_~i~0 < 100); 7414#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7413#L10-2 assume !!(main_~i~0 < 100); 7411#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7410#L10-2 assume !!(main_~i~0 < 100); 7409#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7408#L10-2 assume !!(main_~i~0 < 100); 7405#L10 [2021-10-28 09:00:09,818 INFO L793 eck$LassoCheckResult]: Loop: 7405#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 7406#L10-2 assume !!(main_~i~0 < 100); 7409#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7408#L10-2 assume !!(main_~i~0 < 100); 7405#L10 [2021-10-28 09:00:09,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:09,819 INFO L85 PathProgramCache]: Analyzing trace with hash -420879705, now seen corresponding path program 33 times [2021-10-28 09:00:09,819 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:09,819 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406710684] [2021-10-28 09:00:09,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:09,819 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:09,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:09,833 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:09,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:09,847 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:09,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:09,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 31 times [2021-10-28 09:00:09,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:09,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094979559] [2021-10-28 09:00:09,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:09,848 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:09,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:09,854 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:09,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:09,856 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:09,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:09,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1000263713, now seen corresponding path program 33 times [2021-10-28 09:00:09,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:09,857 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127264601] [2021-10-28 09:00:09,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:09,857 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:09,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:10,516 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:10,517 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:10,517 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127264601] [2021-10-28 09:00:10,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127264601] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:10,517 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [683185197] [2021-10-28 09:00:10,517 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:00:10,517 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:10,517 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:10,522 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:10,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-10-28 09:00:11,014 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2021-10-28 09:00:11,015 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:11,016 INFO L263 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 35 conjunts are in the unsatisfiable core [2021-10-28 09:00:11,017 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:11,355 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:11,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [683185197] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:11,356 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:11,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2021-10-28 09:00:11,356 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014969367] [2021-10-28 09:00:11,382 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:11,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-10-28 09:00:11,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-10-28 09:00:11,383 INFO L87 Difference]: Start difference. First operand 71 states and 73 transitions. cyclomatic complexity: 3 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 35 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:11,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:11,482 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2021-10-28 09:00:11,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-10-28 09:00:11,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2021-10-28 09:00:11,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:11,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 74 states and 76 transitions. [2021-10-28 09:00:11,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:11,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:11,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 76 transitions. [2021-10-28 09:00:11,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:11,484 INFO L681 BuchiCegarLoop]: Abstraction has 74 states and 76 transitions. [2021-10-28 09:00:11,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 76 transitions. [2021-10-28 09:00:11,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 73. [2021-10-28 09:00:11,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.0273972602739727) internal successors, (75), 72 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:11,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 75 transitions. [2021-10-28 09:00:11,487 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2021-10-28 09:00:11,487 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2021-10-28 09:00:11,487 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-10-28 09:00:11,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 75 transitions. [2021-10-28 09:00:11,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:11,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:11,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:11,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [35, 34, 1] [2021-10-28 09:00:11,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:11,489 INFO L791 eck$LassoCheckResult]: Stem: 7804#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 7800#L10-2 assume !!(main_~i~0 < 100); 7801#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7802#L10-2 assume !!(main_~i~0 < 100); 7803#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7807#L10-2 assume !!(main_~i~0 < 100); 7872#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7871#L10-2 assume !!(main_~i~0 < 100); 7870#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7869#L10-2 assume !!(main_~i~0 < 100); 7868#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7867#L10-2 assume !!(main_~i~0 < 100); 7866#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7865#L10-2 assume !!(main_~i~0 < 100); 7864#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7863#L10-2 assume !!(main_~i~0 < 100); 7862#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7861#L10-2 assume !!(main_~i~0 < 100); 7860#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7859#L10-2 assume !!(main_~i~0 < 100); 7858#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7857#L10-2 assume !!(main_~i~0 < 100); 7856#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7855#L10-2 assume !!(main_~i~0 < 100); 7854#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7853#L10-2 assume !!(main_~i~0 < 100); 7852#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7851#L10-2 assume !!(main_~i~0 < 100); 7850#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7849#L10-2 assume !!(main_~i~0 < 100); 7848#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7847#L10-2 assume !!(main_~i~0 < 100); 7846#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7845#L10-2 assume !!(main_~i~0 < 100); 7844#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7843#L10-2 assume !!(main_~i~0 < 100); 7842#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7841#L10-2 assume !!(main_~i~0 < 100); 7840#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7839#L10-2 assume !!(main_~i~0 < 100); 7838#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7837#L10-2 assume !!(main_~i~0 < 100); 7836#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7835#L10-2 assume !!(main_~i~0 < 100); 7834#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7833#L10-2 assume !!(main_~i~0 < 100); 7832#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7831#L10-2 assume !!(main_~i~0 < 100); 7830#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7829#L10-2 assume !!(main_~i~0 < 100); 7828#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7827#L10-2 assume !!(main_~i~0 < 100); 7826#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7825#L10-2 assume !!(main_~i~0 < 100); 7824#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7823#L10-2 assume !!(main_~i~0 < 100); 7822#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7821#L10-2 assume !!(main_~i~0 < 100); 7820#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7819#L10-2 assume !!(main_~i~0 < 100); 7818#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7817#L10-2 assume !!(main_~i~0 < 100); 7816#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7815#L10-2 assume !!(main_~i~0 < 100); 7814#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7813#L10-2 assume !!(main_~i~0 < 100); 7811#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7810#L10-2 assume !!(main_~i~0 < 100); 7809#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7808#L10-2 assume !!(main_~i~0 < 100); 7805#L10 [2021-10-28 09:00:11,489 INFO L793 eck$LassoCheckResult]: Loop: 7805#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 7806#L10-2 assume !!(main_~i~0 < 100); 7809#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 7808#L10-2 assume !!(main_~i~0 < 100); 7805#L10 [2021-10-28 09:00:11,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:11,490 INFO L85 PathProgramCache]: Analyzing trace with hash -738470268, now seen corresponding path program 34 times [2021-10-28 09:00:11,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:11,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087092236] [2021-10-28 09:00:11,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:11,491 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:11,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:11,507 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:11,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:11,519 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:11,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:11,520 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 32 times [2021-10-28 09:00:11,520 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:11,521 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550251352] [2021-10-28 09:00:11,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:11,521 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:11,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:11,528 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:11,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:11,529 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:11,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:11,530 INFO L85 PathProgramCache]: Analyzing trace with hash 762047804, now seen corresponding path program 34 times [2021-10-28 09:00:11,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:11,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814543206] [2021-10-28 09:00:11,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:11,531 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:11,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:12,255 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:12,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:12,255 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814543206] [2021-10-28 09:00:12,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814543206] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:12,256 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [691136117] [2021-10-28 09:00:12,256 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 09:00:12,256 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:12,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:12,262 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:12,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-10-28 09:00:12,966 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 09:00:12,966 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:12,968 INFO L263 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 36 conjunts are in the unsatisfiable core [2021-10-28 09:00:12,969 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:13,240 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:13,241 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [691136117] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:13,241 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:13,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2021-10-28 09:00:13,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753187474] [2021-10-28 09:00:13,269 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:13,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-10-28 09:00:13,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-10-28 09:00:13,272 INFO L87 Difference]: Start difference. First operand 73 states and 75 transitions. cyclomatic complexity: 3 Second operand has 37 states, 37 states have (on average 1.972972972972973) internal successors, (73), 36 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:13,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:13,375 INFO L93 Difference]: Finished difference Result 77 states and 79 transitions. [2021-10-28 09:00:13,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-10-28 09:00:13,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 79 transitions. [2021-10-28 09:00:13,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:13,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 76 states and 78 transitions. [2021-10-28 09:00:13,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:13,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:13,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 78 transitions. [2021-10-28 09:00:13,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:13,378 INFO L681 BuchiCegarLoop]: Abstraction has 76 states and 78 transitions. [2021-10-28 09:00:13,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 78 transitions. [2021-10-28 09:00:13,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2021-10-28 09:00:13,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0266666666666666) internal successors, (77), 74 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:13,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2021-10-28 09:00:13,380 INFO L704 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2021-10-28 09:00:13,380 INFO L587 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2021-10-28 09:00:13,380 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-10-28 09:00:13,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2021-10-28 09:00:13,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:13,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:13,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:13,393 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [36, 35, 1] [2021-10-28 09:00:13,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:13,393 INFO L791 eck$LassoCheckResult]: Stem: 8215#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 8211#L10-2 assume !!(main_~i~0 < 100); 8212#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8213#L10-2 assume !!(main_~i~0 < 100); 8214#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8218#L10-2 assume !!(main_~i~0 < 100); 8285#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8284#L10-2 assume !!(main_~i~0 < 100); 8283#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8282#L10-2 assume !!(main_~i~0 < 100); 8281#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8280#L10-2 assume !!(main_~i~0 < 100); 8279#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8278#L10-2 assume !!(main_~i~0 < 100); 8277#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8276#L10-2 assume !!(main_~i~0 < 100); 8275#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8274#L10-2 assume !!(main_~i~0 < 100); 8273#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8272#L10-2 assume !!(main_~i~0 < 100); 8271#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8270#L10-2 assume !!(main_~i~0 < 100); 8269#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8268#L10-2 assume !!(main_~i~0 < 100); 8267#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8266#L10-2 assume !!(main_~i~0 < 100); 8265#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8264#L10-2 assume !!(main_~i~0 < 100); 8263#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8262#L10-2 assume !!(main_~i~0 < 100); 8261#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8260#L10-2 assume !!(main_~i~0 < 100); 8259#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8258#L10-2 assume !!(main_~i~0 < 100); 8257#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8256#L10-2 assume !!(main_~i~0 < 100); 8255#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8254#L10-2 assume !!(main_~i~0 < 100); 8253#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8252#L10-2 assume !!(main_~i~0 < 100); 8251#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8250#L10-2 assume !!(main_~i~0 < 100); 8249#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8248#L10-2 assume !!(main_~i~0 < 100); 8247#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8246#L10-2 assume !!(main_~i~0 < 100); 8245#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8244#L10-2 assume !!(main_~i~0 < 100); 8243#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8242#L10-2 assume !!(main_~i~0 < 100); 8241#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8240#L10-2 assume !!(main_~i~0 < 100); 8239#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8238#L10-2 assume !!(main_~i~0 < 100); 8237#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8236#L10-2 assume !!(main_~i~0 < 100); 8235#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8234#L10-2 assume !!(main_~i~0 < 100); 8233#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8232#L10-2 assume !!(main_~i~0 < 100); 8231#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8230#L10-2 assume !!(main_~i~0 < 100); 8229#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8228#L10-2 assume !!(main_~i~0 < 100); 8227#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8226#L10-2 assume !!(main_~i~0 < 100); 8225#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8224#L10-2 assume !!(main_~i~0 < 100); 8222#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8221#L10-2 assume !!(main_~i~0 < 100); 8220#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8219#L10-2 assume !!(main_~i~0 < 100); 8216#L10 [2021-10-28 09:00:13,394 INFO L793 eck$LassoCheckResult]: Loop: 8216#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 8217#L10-2 assume !!(main_~i~0 < 100); 8220#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8219#L10-2 assume !!(main_~i~0 < 100); 8216#L10 [2021-10-28 09:00:13,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:13,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1000323295, now seen corresponding path program 35 times [2021-10-28 09:00:13,394 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:13,394 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360427809] [2021-10-28 09:00:13,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:13,395 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:13,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:13,461 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:13,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:13,476 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:13,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:13,476 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 33 times [2021-10-28 09:00:13,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:13,477 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762555634] [2021-10-28 09:00:13,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:13,477 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:13,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:13,484 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:13,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:13,485 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:13,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:13,486 INFO L85 PathProgramCache]: Analyzing trace with hash 2126301017, now seen corresponding path program 35 times [2021-10-28 09:00:13,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:13,486 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315614081] [2021-10-28 09:00:13,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:13,487 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:13,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:14,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:14,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:14,235 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315614081] [2021-10-28 09:00:14,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315614081] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:14,235 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [585945526] [2021-10-28 09:00:14,236 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 09:00:14,236 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:14,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:14,242 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:14,262 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-10-28 09:00:15,038 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 38 check-sat command(s) [2021-10-28 09:00:15,038 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:15,040 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 37 conjunts are in the unsatisfiable core [2021-10-28 09:00:15,041 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:15,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:15,358 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [585945526] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:15,358 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:15,359 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2021-10-28 09:00:15,359 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006127451] [2021-10-28 09:00:15,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:15,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-10-28 09:00:15,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-10-28 09:00:15,396 INFO L87 Difference]: Start difference. First operand 75 states and 77 transitions. cyclomatic complexity: 3 Second operand has 38 states, 38 states have (on average 1.9736842105263157) internal successors, (75), 37 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:15,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:15,555 INFO L93 Difference]: Finished difference Result 79 states and 81 transitions. [2021-10-28 09:00:15,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-10-28 09:00:15,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 81 transitions. [2021-10-28 09:00:15,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:15,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 78 states and 80 transitions. [2021-10-28 09:00:15,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:15,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:15,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 80 transitions. [2021-10-28 09:00:15,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:15,558 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 80 transitions. [2021-10-28 09:00:15,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 80 transitions. [2021-10-28 09:00:15,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 77. [2021-10-28 09:00:15,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.025974025974026) internal successors, (79), 76 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:15,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 79 transitions. [2021-10-28 09:00:15,561 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2021-10-28 09:00:15,561 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2021-10-28 09:00:15,561 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-10-28 09:00:15,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 79 transitions. [2021-10-28 09:00:15,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:15,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:15,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:15,565 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [37, 36, 1] [2021-10-28 09:00:15,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:15,565 INFO L791 eck$LassoCheckResult]: Stem: 8637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 8633#L10-2 assume !!(main_~i~0 < 100); 8634#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8635#L10-2 assume !!(main_~i~0 < 100); 8636#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8640#L10-2 assume !!(main_~i~0 < 100); 8709#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8708#L10-2 assume !!(main_~i~0 < 100); 8707#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8706#L10-2 assume !!(main_~i~0 < 100); 8705#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8704#L10-2 assume !!(main_~i~0 < 100); 8703#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8702#L10-2 assume !!(main_~i~0 < 100); 8701#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8700#L10-2 assume !!(main_~i~0 < 100); 8699#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8698#L10-2 assume !!(main_~i~0 < 100); 8697#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8696#L10-2 assume !!(main_~i~0 < 100); 8695#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8694#L10-2 assume !!(main_~i~0 < 100); 8693#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8692#L10-2 assume !!(main_~i~0 < 100); 8691#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8690#L10-2 assume !!(main_~i~0 < 100); 8689#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8688#L10-2 assume !!(main_~i~0 < 100); 8687#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8686#L10-2 assume !!(main_~i~0 < 100); 8685#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8684#L10-2 assume !!(main_~i~0 < 100); 8683#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8682#L10-2 assume !!(main_~i~0 < 100); 8681#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8680#L10-2 assume !!(main_~i~0 < 100); 8679#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8678#L10-2 assume !!(main_~i~0 < 100); 8677#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8676#L10-2 assume !!(main_~i~0 < 100); 8675#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8674#L10-2 assume !!(main_~i~0 < 100); 8673#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8672#L10-2 assume !!(main_~i~0 < 100); 8671#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8670#L10-2 assume !!(main_~i~0 < 100); 8669#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8668#L10-2 assume !!(main_~i~0 < 100); 8667#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8666#L10-2 assume !!(main_~i~0 < 100); 8665#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8664#L10-2 assume !!(main_~i~0 < 100); 8663#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8662#L10-2 assume !!(main_~i~0 < 100); 8661#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8660#L10-2 assume !!(main_~i~0 < 100); 8659#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8658#L10-2 assume !!(main_~i~0 < 100); 8657#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8656#L10-2 assume !!(main_~i~0 < 100); 8655#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8654#L10-2 assume !!(main_~i~0 < 100); 8653#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8652#L10-2 assume !!(main_~i~0 < 100); 8651#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8650#L10-2 assume !!(main_~i~0 < 100); 8649#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8648#L10-2 assume !!(main_~i~0 < 100); 8647#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8646#L10-2 assume !!(main_~i~0 < 100); 8644#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8643#L10-2 assume !!(main_~i~0 < 100); 8642#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8641#L10-2 assume !!(main_~i~0 < 100); 8638#L10 [2021-10-28 09:00:15,565 INFO L793 eck$LassoCheckResult]: Loop: 8638#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 8639#L10-2 assume !!(main_~i~0 < 100); 8642#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 8641#L10-2 assume !!(main_~i~0 < 100); 8638#L10 [2021-10-28 09:00:15,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:15,566 INFO L85 PathProgramCache]: Analyzing trace with hash 761988222, now seen corresponding path program 36 times [2021-10-28 09:00:15,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:15,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451005084] [2021-10-28 09:00:15,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:15,567 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:15,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:15,600 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:15,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:15,615 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:15,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:15,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 34 times [2021-10-28 09:00:15,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:15,616 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334822205] [2021-10-28 09:00:15,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:15,617 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:15,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:15,629 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:15,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:15,635 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:15,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:15,636 INFO L85 PathProgramCache]: Analyzing trace with hash -1086353866, now seen corresponding path program 36 times [2021-10-28 09:00:15,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:15,636 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303466749] [2021-10-28 09:00:15,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:15,637 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:15,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:16,405 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:16,405 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:16,410 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303466749] [2021-10-28 09:00:16,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303466749] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:16,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1203826958] [2021-10-28 09:00:16,411 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 09:00:16,411 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:16,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:16,414 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:16,430 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-10-28 09:00:17,039 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2021-10-28 09:00:17,039 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:17,040 INFO L263 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 38 conjunts are in the unsatisfiable core [2021-10-28 09:00:17,042 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:17,313 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:17,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1203826958] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:17,314 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:17,314 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2021-10-28 09:00:17,314 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537036498] [2021-10-28 09:00:17,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:17,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-10-28 09:00:17,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2021-10-28 09:00:17,352 INFO L87 Difference]: Start difference. First operand 77 states and 79 transitions. cyclomatic complexity: 3 Second operand has 39 states, 39 states have (on average 1.9743589743589745) internal successors, (77), 38 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:17,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:17,473 INFO L93 Difference]: Finished difference Result 81 states and 83 transitions. [2021-10-28 09:00:17,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-10-28 09:00:17,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 83 transitions. [2021-10-28 09:00:17,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:17,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 82 transitions. [2021-10-28 09:00:17,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:17,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:17,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 82 transitions. [2021-10-28 09:00:17,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:17,476 INFO L681 BuchiCegarLoop]: Abstraction has 80 states and 82 transitions. [2021-10-28 09:00:17,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 82 transitions. [2021-10-28 09:00:17,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 79. [2021-10-28 09:00:17,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.0253164556962024) internal successors, (81), 78 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:17,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 81 transitions. [2021-10-28 09:00:17,479 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2021-10-28 09:00:17,479 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2021-10-28 09:00:17,479 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-10-28 09:00:17,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 81 transitions. [2021-10-28 09:00:17,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:17,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:17,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:17,481 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [38, 37, 1] [2021-10-28 09:00:17,481 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:17,482 INFO L791 eck$LassoCheckResult]: Stem: 9070#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 9066#L10-2 assume !!(main_~i~0 < 100); 9067#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9068#L10-2 assume !!(main_~i~0 < 100); 9069#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9073#L10-2 assume !!(main_~i~0 < 100); 9144#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9143#L10-2 assume !!(main_~i~0 < 100); 9142#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9141#L10-2 assume !!(main_~i~0 < 100); 9140#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9139#L10-2 assume !!(main_~i~0 < 100); 9138#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9137#L10-2 assume !!(main_~i~0 < 100); 9136#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9135#L10-2 assume !!(main_~i~0 < 100); 9134#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9133#L10-2 assume !!(main_~i~0 < 100); 9132#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9131#L10-2 assume !!(main_~i~0 < 100); 9130#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9129#L10-2 assume !!(main_~i~0 < 100); 9128#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9127#L10-2 assume !!(main_~i~0 < 100); 9126#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9125#L10-2 assume !!(main_~i~0 < 100); 9124#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9123#L10-2 assume !!(main_~i~0 < 100); 9122#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9121#L10-2 assume !!(main_~i~0 < 100); 9120#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9119#L10-2 assume !!(main_~i~0 < 100); 9118#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9117#L10-2 assume !!(main_~i~0 < 100); 9116#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9115#L10-2 assume !!(main_~i~0 < 100); 9114#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9113#L10-2 assume !!(main_~i~0 < 100); 9112#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9111#L10-2 assume !!(main_~i~0 < 100); 9110#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9109#L10-2 assume !!(main_~i~0 < 100); 9108#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9107#L10-2 assume !!(main_~i~0 < 100); 9106#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9105#L10-2 assume !!(main_~i~0 < 100); 9104#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9103#L10-2 assume !!(main_~i~0 < 100); 9102#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9101#L10-2 assume !!(main_~i~0 < 100); 9100#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9099#L10-2 assume !!(main_~i~0 < 100); 9098#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9097#L10-2 assume !!(main_~i~0 < 100); 9096#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9095#L10-2 assume !!(main_~i~0 < 100); 9094#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9093#L10-2 assume !!(main_~i~0 < 100); 9092#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9091#L10-2 assume !!(main_~i~0 < 100); 9090#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9089#L10-2 assume !!(main_~i~0 < 100); 9088#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9087#L10-2 assume !!(main_~i~0 < 100); 9086#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9085#L10-2 assume !!(main_~i~0 < 100); 9084#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9083#L10-2 assume !!(main_~i~0 < 100); 9082#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9081#L10-2 assume !!(main_~i~0 < 100); 9080#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9079#L10-2 assume !!(main_~i~0 < 100); 9077#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9076#L10-2 assume !!(main_~i~0 < 100); 9075#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9074#L10-2 assume !!(main_~i~0 < 100); 9071#L10 [2021-10-28 09:00:17,482 INFO L793 eck$LassoCheckResult]: Loop: 9071#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 9072#L10-2 assume !!(main_~i~0 < 100); 9075#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9074#L10-2 assume !!(main_~i~0 < 100); 9071#L10 [2021-10-28 09:00:17,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:17,482 INFO L85 PathProgramCache]: Analyzing trace with hash 2126241435, now seen corresponding path program 37 times [2021-10-28 09:00:17,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:17,482 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061926690] [2021-10-28 09:00:17,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:17,483 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:17,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:17,504 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:17,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:17,518 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:17,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:17,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 35 times [2021-10-28 09:00:17,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:17,519 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495200014] [2021-10-28 09:00:17,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:17,519 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:17,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:17,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:17,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:17,533 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:17,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:17,534 INFO L85 PathProgramCache]: Analyzing trace with hash -366210605, now seen corresponding path program 37 times [2021-10-28 09:00:17,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:17,534 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954795150] [2021-10-28 09:00:17,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:17,534 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:17,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:18,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:18,370 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:18,371 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954795150] [2021-10-28 09:00:18,371 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1954795150] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:18,371 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261144773] [2021-10-28 09:00:18,371 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:00:18,371 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:18,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:18,372 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:18,373 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-10-28 09:00:18,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:18,980 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 39 conjunts are in the unsatisfiable core [2021-10-28 09:00:18,981 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:19,305 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:19,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [261144773] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:19,306 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:19,306 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2021-10-28 09:00:19,306 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666095178] [2021-10-28 09:00:19,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:19,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-10-28 09:00:19,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2021-10-28 09:00:19,340 INFO L87 Difference]: Start difference. First operand 79 states and 81 transitions. cyclomatic complexity: 3 Second operand has 40 states, 40 states have (on average 1.975) internal successors, (79), 39 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:19,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:19,460 INFO L93 Difference]: Finished difference Result 83 states and 85 transitions. [2021-10-28 09:00:19,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-10-28 09:00:19,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 85 transitions. [2021-10-28 09:00:19,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:19,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 82 states and 84 transitions. [2021-10-28 09:00:19,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:19,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:19,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 84 transitions. [2021-10-28 09:00:19,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:19,463 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 84 transitions. [2021-10-28 09:00:19,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 84 transitions. [2021-10-28 09:00:19,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2021-10-28 09:00:19,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.0246913580246915) internal successors, (83), 80 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:19,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 83 transitions. [2021-10-28 09:00:19,465 INFO L704 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2021-10-28 09:00:19,465 INFO L587 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2021-10-28 09:00:19,465 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-10-28 09:00:19,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 83 transitions. [2021-10-28 09:00:19,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:19,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:19,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:19,467 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [39, 38, 1] [2021-10-28 09:00:19,467 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:19,468 INFO L791 eck$LassoCheckResult]: Stem: 9514#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 9510#L10-2 assume !!(main_~i~0 < 100); 9511#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9512#L10-2 assume !!(main_~i~0 < 100); 9513#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9517#L10-2 assume !!(main_~i~0 < 100); 9590#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9589#L10-2 assume !!(main_~i~0 < 100); 9588#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9587#L10-2 assume !!(main_~i~0 < 100); 9586#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9585#L10-2 assume !!(main_~i~0 < 100); 9584#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9583#L10-2 assume !!(main_~i~0 < 100); 9582#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9581#L10-2 assume !!(main_~i~0 < 100); 9580#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9579#L10-2 assume !!(main_~i~0 < 100); 9578#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9577#L10-2 assume !!(main_~i~0 < 100); 9576#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9575#L10-2 assume !!(main_~i~0 < 100); 9574#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9573#L10-2 assume !!(main_~i~0 < 100); 9572#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9571#L10-2 assume !!(main_~i~0 < 100); 9570#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9569#L10-2 assume !!(main_~i~0 < 100); 9568#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9567#L10-2 assume !!(main_~i~0 < 100); 9566#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9565#L10-2 assume !!(main_~i~0 < 100); 9564#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9563#L10-2 assume !!(main_~i~0 < 100); 9562#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9561#L10-2 assume !!(main_~i~0 < 100); 9560#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9559#L10-2 assume !!(main_~i~0 < 100); 9558#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9557#L10-2 assume !!(main_~i~0 < 100); 9556#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9555#L10-2 assume !!(main_~i~0 < 100); 9554#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9553#L10-2 assume !!(main_~i~0 < 100); 9552#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9551#L10-2 assume !!(main_~i~0 < 100); 9550#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9549#L10-2 assume !!(main_~i~0 < 100); 9548#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9547#L10-2 assume !!(main_~i~0 < 100); 9546#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9545#L10-2 assume !!(main_~i~0 < 100); 9544#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9543#L10-2 assume !!(main_~i~0 < 100); 9542#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9541#L10-2 assume !!(main_~i~0 < 100); 9540#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9539#L10-2 assume !!(main_~i~0 < 100); 9538#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9537#L10-2 assume !!(main_~i~0 < 100); 9536#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9535#L10-2 assume !!(main_~i~0 < 100); 9534#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9533#L10-2 assume !!(main_~i~0 < 100); 9532#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9531#L10-2 assume !!(main_~i~0 < 100); 9530#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9529#L10-2 assume !!(main_~i~0 < 100); 9528#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9527#L10-2 assume !!(main_~i~0 < 100); 9526#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9525#L10-2 assume !!(main_~i~0 < 100); 9524#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9523#L10-2 assume !!(main_~i~0 < 100); 9521#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9520#L10-2 assume !!(main_~i~0 < 100); 9519#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9518#L10-2 assume !!(main_~i~0 < 100); 9515#L10 [2021-10-28 09:00:19,468 INFO L793 eck$LassoCheckResult]: Loop: 9515#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 9516#L10-2 assume !!(main_~i~0 < 100); 9519#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9518#L10-2 assume !!(main_~i~0 < 100); 9515#L10 [2021-10-28 09:00:19,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:19,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1086413448, now seen corresponding path program 38 times [2021-10-28 09:00:19,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:19,469 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288400259] [2021-10-28 09:00:19,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:19,469 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:19,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:19,486 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:19,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:19,500 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:19,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:19,500 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 36 times [2021-10-28 09:00:19,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:19,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873080785] [2021-10-28 09:00:19,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:19,501 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:19,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:19,508 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:19,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:19,510 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:19,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:19,510 INFO L85 PathProgramCache]: Analyzing trace with hash 201728560, now seen corresponding path program 38 times [2021-10-28 09:00:19,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:19,511 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077318874] [2021-10-28 09:00:19,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:19,511 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:19,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:20,307 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:20,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:20,307 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077318874] [2021-10-28 09:00:20,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077318874] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:20,307 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1773015903] [2021-10-28 09:00:20,307 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:00:20,308 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:20,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:20,309 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:20,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-10-28 09:00:20,989 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:00:20,989 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:20,991 INFO L263 TraceCheckSpWp]: Trace formula consists of 165 conjuncts, 40 conjunts are in the unsatisfiable core [2021-10-28 09:00:20,995 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:21,316 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:21,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1773015903] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:21,317 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:21,317 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2021-10-28 09:00:21,317 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585970654] [2021-10-28 09:00:21,340 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:21,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-10-28 09:00:21,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2021-10-28 09:00:21,341 INFO L87 Difference]: Start difference. First operand 81 states and 83 transitions. cyclomatic complexity: 3 Second operand has 41 states, 41 states have (on average 1.975609756097561) internal successors, (81), 40 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:21,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:21,477 INFO L93 Difference]: Finished difference Result 85 states and 87 transitions. [2021-10-28 09:00:21,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-10-28 09:00:21,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 87 transitions. [2021-10-28 09:00:21,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:21,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 86 transitions. [2021-10-28 09:00:21,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:21,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:21,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 86 transitions. [2021-10-28 09:00:21,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:21,480 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 86 transitions. [2021-10-28 09:00:21,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 86 transitions. [2021-10-28 09:00:21,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 83. [2021-10-28 09:00:21,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.0240963855421688) internal successors, (85), 82 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:21,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 85 transitions. [2021-10-28 09:00:21,483 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2021-10-28 09:00:21,483 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2021-10-28 09:00:21,483 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-10-28 09:00:21,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 85 transitions. [2021-10-28 09:00:21,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:21,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:21,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:21,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [40, 39, 1] [2021-10-28 09:00:21,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:21,486 INFO L791 eck$LassoCheckResult]: Stem: 9969#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 9965#L10-2 assume !!(main_~i~0 < 100); 9966#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9967#L10-2 assume !!(main_~i~0 < 100); 9968#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9972#L10-2 assume !!(main_~i~0 < 100); 10047#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10046#L10-2 assume !!(main_~i~0 < 100); 10045#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10044#L10-2 assume !!(main_~i~0 < 100); 10043#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10042#L10-2 assume !!(main_~i~0 < 100); 10041#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10040#L10-2 assume !!(main_~i~0 < 100); 10039#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10038#L10-2 assume !!(main_~i~0 < 100); 10037#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10036#L10-2 assume !!(main_~i~0 < 100); 10035#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10034#L10-2 assume !!(main_~i~0 < 100); 10033#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10032#L10-2 assume !!(main_~i~0 < 100); 10031#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10030#L10-2 assume !!(main_~i~0 < 100); 10029#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10028#L10-2 assume !!(main_~i~0 < 100); 10027#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10026#L10-2 assume !!(main_~i~0 < 100); 10025#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10024#L10-2 assume !!(main_~i~0 < 100); 10023#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10022#L10-2 assume !!(main_~i~0 < 100); 10021#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10020#L10-2 assume !!(main_~i~0 < 100); 10019#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10018#L10-2 assume !!(main_~i~0 < 100); 10017#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10016#L10-2 assume !!(main_~i~0 < 100); 10015#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10014#L10-2 assume !!(main_~i~0 < 100); 10013#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10012#L10-2 assume !!(main_~i~0 < 100); 10011#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10010#L10-2 assume !!(main_~i~0 < 100); 10009#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10008#L10-2 assume !!(main_~i~0 < 100); 10007#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10006#L10-2 assume !!(main_~i~0 < 100); 10005#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10004#L10-2 assume !!(main_~i~0 < 100); 10003#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10002#L10-2 assume !!(main_~i~0 < 100); 10001#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10000#L10-2 assume !!(main_~i~0 < 100); 9999#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9998#L10-2 assume !!(main_~i~0 < 100); 9997#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9996#L10-2 assume !!(main_~i~0 < 100); 9995#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9994#L10-2 assume !!(main_~i~0 < 100); 9993#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9992#L10-2 assume !!(main_~i~0 < 100); 9991#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9990#L10-2 assume !!(main_~i~0 < 100); 9989#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9988#L10-2 assume !!(main_~i~0 < 100); 9987#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9986#L10-2 assume !!(main_~i~0 < 100); 9985#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9984#L10-2 assume !!(main_~i~0 < 100); 9983#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9982#L10-2 assume !!(main_~i~0 < 100); 9981#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9980#L10-2 assume !!(main_~i~0 < 100); 9979#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9978#L10-2 assume !!(main_~i~0 < 100); 9976#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9975#L10-2 assume !!(main_~i~0 < 100); 9974#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9973#L10-2 assume !!(main_~i~0 < 100); 9970#L10 [2021-10-28 09:00:21,486 INFO L793 eck$LassoCheckResult]: Loop: 9970#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 9971#L10-2 assume !!(main_~i~0 < 100); 9974#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 9973#L10-2 assume !!(main_~i~0 < 100); 9970#L10 [2021-10-28 09:00:21,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:21,486 INFO L85 PathProgramCache]: Analyzing trace with hash -366270187, now seen corresponding path program 39 times [2021-10-28 09:00:21,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:21,487 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021368389] [2021-10-28 09:00:21,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:21,487 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:21,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:21,503 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:21,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:21,518 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:21,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:21,519 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 37 times [2021-10-28 09:00:21,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:21,519 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111427347] [2021-10-28 09:00:21,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:21,519 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:21,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:21,528 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:21,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:21,530 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:21,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:21,531 INFO L85 PathProgramCache]: Analyzing trace with hash 530419533, now seen corresponding path program 39 times [2021-10-28 09:00:21,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:21,531 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382929886] [2021-10-28 09:00:21,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:21,531 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:21,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:22,362 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:22,362 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:22,362 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382929886] [2021-10-28 09:00:22,362 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382929886] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:22,363 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2130576858] [2021-10-28 09:00:22,363 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:00:22,363 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:22,363 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:22,366 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:22,367 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-10-28 09:00:23,059 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2021-10-28 09:00:23,059 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:23,061 INFO L263 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 41 conjunts are in the unsatisfiable core [2021-10-28 09:00:23,062 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:23,429 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:23,429 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2130576858] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:23,429 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:23,429 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2021-10-28 09:00:23,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567170799] [2021-10-28 09:00:23,456 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:23,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-10-28 09:00:23,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2021-10-28 09:00:23,457 INFO L87 Difference]: Start difference. First operand 83 states and 85 transitions. cyclomatic complexity: 3 Second operand has 42 states, 42 states have (on average 1.9761904761904763) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:23,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:23,573 INFO L93 Difference]: Finished difference Result 87 states and 89 transitions. [2021-10-28 09:00:23,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-10-28 09:00:23,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 89 transitions. [2021-10-28 09:00:23,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:23,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 86 states and 88 transitions. [2021-10-28 09:00:23,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:23,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:23,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 88 transitions. [2021-10-28 09:00:23,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:23,576 INFO L681 BuchiCegarLoop]: Abstraction has 86 states and 88 transitions. [2021-10-28 09:00:23,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 88 transitions. [2021-10-28 09:00:23,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 85. [2021-10-28 09:00:23,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.0235294117647058) internal successors, (87), 84 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:23,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 87 transitions. [2021-10-28 09:00:23,579 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2021-10-28 09:00:23,579 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2021-10-28 09:00:23,579 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-10-28 09:00:23,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 87 transitions. [2021-10-28 09:00:23,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:23,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:23,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:23,582 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [41, 40, 1] [2021-10-28 09:00:23,582 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:23,582 INFO L791 eck$LassoCheckResult]: Stem: 10435#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 10431#L10-2 assume !!(main_~i~0 < 100); 10432#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10433#L10-2 assume !!(main_~i~0 < 100); 10434#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10438#L10-2 assume !!(main_~i~0 < 100); 10515#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10514#L10-2 assume !!(main_~i~0 < 100); 10513#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10512#L10-2 assume !!(main_~i~0 < 100); 10511#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10510#L10-2 assume !!(main_~i~0 < 100); 10509#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10508#L10-2 assume !!(main_~i~0 < 100); 10507#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10506#L10-2 assume !!(main_~i~0 < 100); 10505#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10504#L10-2 assume !!(main_~i~0 < 100); 10503#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10502#L10-2 assume !!(main_~i~0 < 100); 10501#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10500#L10-2 assume !!(main_~i~0 < 100); 10499#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10498#L10-2 assume !!(main_~i~0 < 100); 10497#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10496#L10-2 assume !!(main_~i~0 < 100); 10495#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10494#L10-2 assume !!(main_~i~0 < 100); 10493#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10492#L10-2 assume !!(main_~i~0 < 100); 10491#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10490#L10-2 assume !!(main_~i~0 < 100); 10489#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10488#L10-2 assume !!(main_~i~0 < 100); 10487#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10486#L10-2 assume !!(main_~i~0 < 100); 10485#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10484#L10-2 assume !!(main_~i~0 < 100); 10483#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10482#L10-2 assume !!(main_~i~0 < 100); 10481#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10480#L10-2 assume !!(main_~i~0 < 100); 10479#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10478#L10-2 assume !!(main_~i~0 < 100); 10477#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10476#L10-2 assume !!(main_~i~0 < 100); 10475#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10474#L10-2 assume !!(main_~i~0 < 100); 10473#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10472#L10-2 assume !!(main_~i~0 < 100); 10471#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10470#L10-2 assume !!(main_~i~0 < 100); 10469#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10468#L10-2 assume !!(main_~i~0 < 100); 10467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10466#L10-2 assume !!(main_~i~0 < 100); 10465#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10464#L10-2 assume !!(main_~i~0 < 100); 10463#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10462#L10-2 assume !!(main_~i~0 < 100); 10461#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10460#L10-2 assume !!(main_~i~0 < 100); 10459#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10458#L10-2 assume !!(main_~i~0 < 100); 10457#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10456#L10-2 assume !!(main_~i~0 < 100); 10455#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10454#L10-2 assume !!(main_~i~0 < 100); 10453#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10452#L10-2 assume !!(main_~i~0 < 100); 10451#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10450#L10-2 assume !!(main_~i~0 < 100); 10449#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10448#L10-2 assume !!(main_~i~0 < 100); 10447#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10446#L10-2 assume !!(main_~i~0 < 100); 10445#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10444#L10-2 assume !!(main_~i~0 < 100); 10442#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10441#L10-2 assume !!(main_~i~0 < 100); 10440#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10439#L10-2 assume !!(main_~i~0 < 100); 10436#L10 [2021-10-28 09:00:23,583 INFO L793 eck$LassoCheckResult]: Loop: 10436#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 10437#L10-2 assume !!(main_~i~0 < 100); 10440#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10439#L10-2 assume !!(main_~i~0 < 100); 10436#L10 [2021-10-28 09:00:23,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:23,583 INFO L85 PathProgramCache]: Analyzing trace with hash 201668978, now seen corresponding path program 40 times [2021-10-28 09:00:23,583 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:23,583 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764623577] [2021-10-28 09:00:23,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:23,584 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:23,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:23,600 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:23,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:23,613 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:23,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:23,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 38 times [2021-10-28 09:00:23,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:23,614 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874424274] [2021-10-28 09:00:23,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:23,615 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:23,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:23,623 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:23,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:23,625 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:23,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:23,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1425135318, now seen corresponding path program 40 times [2021-10-28 09:00:23,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:23,626 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177940912] [2021-10-28 09:00:23,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:23,626 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:23,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:24,455 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:24,456 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:24,456 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177940912] [2021-10-28 09:00:24,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177940912] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:24,456 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1148346402] [2021-10-28 09:00:24,456 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 09:00:24,456 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:24,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:24,458 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:24,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-10-28 09:00:25,165 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 09:00:25,165 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:25,167 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 42 conjunts are in the unsatisfiable core [2021-10-28 09:00:25,169 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:25,562 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:25,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1148346402] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:25,562 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:25,562 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2021-10-28 09:00:25,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853137726] [2021-10-28 09:00:25,589 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:25,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-10-28 09:00:25,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2021-10-28 09:00:25,591 INFO L87 Difference]: Start difference. First operand 85 states and 87 transitions. cyclomatic complexity: 3 Second operand has 43 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 42 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:25,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:25,737 INFO L93 Difference]: Finished difference Result 89 states and 91 transitions. [2021-10-28 09:00:25,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-10-28 09:00:25,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 91 transitions. [2021-10-28 09:00:25,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:25,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 88 states and 90 transitions. [2021-10-28 09:00:25,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:25,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:25,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 90 transitions. [2021-10-28 09:00:25,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:25,741 INFO L681 BuchiCegarLoop]: Abstraction has 88 states and 90 transitions. [2021-10-28 09:00:25,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 90 transitions. [2021-10-28 09:00:25,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2021-10-28 09:00:25,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.0229885057471264) internal successors, (89), 86 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:25,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 89 transitions. [2021-10-28 09:00:25,744 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2021-10-28 09:00:25,744 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2021-10-28 09:00:25,744 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-10-28 09:00:25,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 89 transitions. [2021-10-28 09:00:25,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:25,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:25,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:25,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [42, 41, 1] [2021-10-28 09:00:25,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:25,748 INFO L791 eck$LassoCheckResult]: Stem: 10912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 10908#L10-2 assume !!(main_~i~0 < 100); 10909#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10910#L10-2 assume !!(main_~i~0 < 100); 10911#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10915#L10-2 assume !!(main_~i~0 < 100); 10994#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10993#L10-2 assume !!(main_~i~0 < 100); 10992#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10991#L10-2 assume !!(main_~i~0 < 100); 10990#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10989#L10-2 assume !!(main_~i~0 < 100); 10988#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10987#L10-2 assume !!(main_~i~0 < 100); 10986#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10985#L10-2 assume !!(main_~i~0 < 100); 10984#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10983#L10-2 assume !!(main_~i~0 < 100); 10982#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10981#L10-2 assume !!(main_~i~0 < 100); 10980#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10979#L10-2 assume !!(main_~i~0 < 100); 10978#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10977#L10-2 assume !!(main_~i~0 < 100); 10976#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10975#L10-2 assume !!(main_~i~0 < 100); 10974#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10973#L10-2 assume !!(main_~i~0 < 100); 10972#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10971#L10-2 assume !!(main_~i~0 < 100); 10970#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10969#L10-2 assume !!(main_~i~0 < 100); 10968#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10967#L10-2 assume !!(main_~i~0 < 100); 10966#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10965#L10-2 assume !!(main_~i~0 < 100); 10964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10963#L10-2 assume !!(main_~i~0 < 100); 10962#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10961#L10-2 assume !!(main_~i~0 < 100); 10960#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10959#L10-2 assume !!(main_~i~0 < 100); 10958#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10957#L10-2 assume !!(main_~i~0 < 100); 10956#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10955#L10-2 assume !!(main_~i~0 < 100); 10954#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10953#L10-2 assume !!(main_~i~0 < 100); 10952#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10951#L10-2 assume !!(main_~i~0 < 100); 10950#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10949#L10-2 assume !!(main_~i~0 < 100); 10948#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10947#L10-2 assume !!(main_~i~0 < 100); 10946#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10945#L10-2 assume !!(main_~i~0 < 100); 10944#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10943#L10-2 assume !!(main_~i~0 < 100); 10942#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10941#L10-2 assume !!(main_~i~0 < 100); 10940#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10939#L10-2 assume !!(main_~i~0 < 100); 10938#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10937#L10-2 assume !!(main_~i~0 < 100); 10936#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10935#L10-2 assume !!(main_~i~0 < 100); 10934#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10933#L10-2 assume !!(main_~i~0 < 100); 10932#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10931#L10-2 assume !!(main_~i~0 < 100); 10930#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10929#L10-2 assume !!(main_~i~0 < 100); 10928#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10927#L10-2 assume !!(main_~i~0 < 100); 10926#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10925#L10-2 assume !!(main_~i~0 < 100); 10924#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10923#L10-2 assume !!(main_~i~0 < 100); 10922#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10921#L10-2 assume !!(main_~i~0 < 100); 10919#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10918#L10-2 assume !!(main_~i~0 < 100); 10917#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10916#L10-2 assume !!(main_~i~0 < 100); 10913#L10 [2021-10-28 09:00:25,748 INFO L793 eck$LassoCheckResult]: Loop: 10913#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 10914#L10-2 assume !!(main_~i~0 < 100); 10917#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 10916#L10-2 assume !!(main_~i~0 < 100); 10913#L10 [2021-10-28 09:00:25,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:25,748 INFO L85 PathProgramCache]: Analyzing trace with hash 530359951, now seen corresponding path program 41 times [2021-10-28 09:00:25,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:25,749 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78194269] [2021-10-28 09:00:25,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:25,749 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:25,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:25,776 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:25,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:25,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:25,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:25,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 39 times [2021-10-28 09:00:25,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:25,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104543715] [2021-10-28 09:00:25,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:25,791 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:25,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:25,808 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:25,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:25,810 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:25,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:25,811 INFO L85 PathProgramCache]: Analyzing trace with hash 482328519, now seen corresponding path program 41 times [2021-10-28 09:00:25,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:25,812 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425965501] [2021-10-28 09:00:25,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:25,812 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:25,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:26,911 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:26,911 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:26,911 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425965501] [2021-10-28 09:00:26,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425965501] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:26,912 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1453281825] [2021-10-28 09:00:26,912 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 09:00:26,912 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:26,912 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:26,915 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:26,929 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-10-28 09:00:28,000 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 44 check-sat command(s) [2021-10-28 09:00:28,000 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:28,002 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 43 conjunts are in the unsatisfiable core [2021-10-28 09:00:28,004 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:28,335 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:28,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1453281825] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:28,335 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:28,335 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2021-10-28 09:00:28,336 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462430916] [2021-10-28 09:00:28,368 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:28,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-10-28 09:00:28,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2021-10-28 09:00:28,370 INFO L87 Difference]: Start difference. First operand 87 states and 89 transitions. cyclomatic complexity: 3 Second operand has 44 states, 44 states have (on average 1.9772727272727273) internal successors, (87), 43 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:28,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:28,481 INFO L93 Difference]: Finished difference Result 91 states and 93 transitions. [2021-10-28 09:00:28,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-10-28 09:00:28,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 93 transitions. [2021-10-28 09:00:28,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:28,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 90 states and 92 transitions. [2021-10-28 09:00:28,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:28,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:28,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 92 transitions. [2021-10-28 09:00:28,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:28,483 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 92 transitions. [2021-10-28 09:00:28,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 92 transitions. [2021-10-28 09:00:28,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 89. [2021-10-28 09:00:28,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.0224719101123596) internal successors, (91), 88 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:28,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 91 transitions. [2021-10-28 09:00:28,486 INFO L704 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2021-10-28 09:00:28,486 INFO L587 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2021-10-28 09:00:28,486 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-10-28 09:00:28,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 91 transitions. [2021-10-28 09:00:28,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:28,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:28,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:28,488 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [43, 42, 1] [2021-10-28 09:00:28,488 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:28,489 INFO L791 eck$LassoCheckResult]: Stem: 11400#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 11396#L10-2 assume !!(main_~i~0 < 100); 11397#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11398#L10-2 assume !!(main_~i~0 < 100); 11399#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11403#L10-2 assume !!(main_~i~0 < 100); 11484#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11483#L10-2 assume !!(main_~i~0 < 100); 11482#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11481#L10-2 assume !!(main_~i~0 < 100); 11480#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11479#L10-2 assume !!(main_~i~0 < 100); 11478#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11477#L10-2 assume !!(main_~i~0 < 100); 11476#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11475#L10-2 assume !!(main_~i~0 < 100); 11474#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11473#L10-2 assume !!(main_~i~0 < 100); 11472#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11471#L10-2 assume !!(main_~i~0 < 100); 11470#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11469#L10-2 assume !!(main_~i~0 < 100); 11468#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11467#L10-2 assume !!(main_~i~0 < 100); 11466#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11465#L10-2 assume !!(main_~i~0 < 100); 11464#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11463#L10-2 assume !!(main_~i~0 < 100); 11462#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11461#L10-2 assume !!(main_~i~0 < 100); 11460#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11459#L10-2 assume !!(main_~i~0 < 100); 11458#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11457#L10-2 assume !!(main_~i~0 < 100); 11456#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11455#L10-2 assume !!(main_~i~0 < 100); 11454#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11453#L10-2 assume !!(main_~i~0 < 100); 11452#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11451#L10-2 assume !!(main_~i~0 < 100); 11450#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11449#L10-2 assume !!(main_~i~0 < 100); 11448#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11447#L10-2 assume !!(main_~i~0 < 100); 11446#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11445#L10-2 assume !!(main_~i~0 < 100); 11444#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11443#L10-2 assume !!(main_~i~0 < 100); 11442#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11441#L10-2 assume !!(main_~i~0 < 100); 11440#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11439#L10-2 assume !!(main_~i~0 < 100); 11438#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11437#L10-2 assume !!(main_~i~0 < 100); 11436#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11435#L10-2 assume !!(main_~i~0 < 100); 11434#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11433#L10-2 assume !!(main_~i~0 < 100); 11432#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11431#L10-2 assume !!(main_~i~0 < 100); 11430#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11429#L10-2 assume !!(main_~i~0 < 100); 11428#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11427#L10-2 assume !!(main_~i~0 < 100); 11426#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11425#L10-2 assume !!(main_~i~0 < 100); 11424#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11423#L10-2 assume !!(main_~i~0 < 100); 11422#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11421#L10-2 assume !!(main_~i~0 < 100); 11420#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11419#L10-2 assume !!(main_~i~0 < 100); 11418#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11417#L10-2 assume !!(main_~i~0 < 100); 11416#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11415#L10-2 assume !!(main_~i~0 < 100); 11414#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11413#L10-2 assume !!(main_~i~0 < 100); 11412#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11411#L10-2 assume !!(main_~i~0 < 100); 11410#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11409#L10-2 assume !!(main_~i~0 < 100); 11407#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11406#L10-2 assume !!(main_~i~0 < 100); 11405#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11404#L10-2 assume !!(main_~i~0 < 100); 11401#L10 [2021-10-28 09:00:28,489 INFO L793 eck$LassoCheckResult]: Loop: 11401#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 11402#L10-2 assume !!(main_~i~0 < 100); 11405#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11404#L10-2 assume !!(main_~i~0 < 100); 11401#L10 [2021-10-28 09:00:28,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:28,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1425194900, now seen corresponding path program 42 times [2021-10-28 09:00:28,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:28,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31805732] [2021-10-28 09:00:28,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:28,490 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:28,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:28,518 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:28,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:28,534 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:28,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:28,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 40 times [2021-10-28 09:00:28,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:28,535 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335116771] [2021-10-28 09:00:28,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:28,536 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:28,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:28,551 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:28,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:28,553 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:28,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:28,553 INFO L85 PathProgramCache]: Analyzing trace with hash -395959516, now seen corresponding path program 42 times [2021-10-28 09:00:28,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:28,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175967848] [2021-10-28 09:00:28,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:28,554 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:28,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:29,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:29,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:29,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175967848] [2021-10-28 09:00:29,716 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175967848] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:29,716 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [868518648] [2021-10-28 09:00:29,716 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 09:00:29,716 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:29,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:29,724 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:29,744 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-10-28 09:00:30,489 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2021-10-28 09:00:30,489 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:30,490 INFO L263 TraceCheckSpWp]: Trace formula consists of 181 conjuncts, 44 conjunts are in the unsatisfiable core [2021-10-28 09:00:30,491 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:30,791 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:30,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [868518648] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:30,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:30,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2021-10-28 09:00:30,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635141997] [2021-10-28 09:00:30,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:30,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-10-28 09:00:30,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2021-10-28 09:00:30,819 INFO L87 Difference]: Start difference. First operand 89 states and 91 transitions. cyclomatic complexity: 3 Second operand has 45 states, 45 states have (on average 1.9777777777777779) internal successors, (89), 44 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:30,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:30,925 INFO L93 Difference]: Finished difference Result 93 states and 95 transitions. [2021-10-28 09:00:30,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-10-28 09:00:30,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 95 transitions. [2021-10-28 09:00:30,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:30,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 92 states and 94 transitions. [2021-10-28 09:00:30,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:30,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:30,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 94 transitions. [2021-10-28 09:00:30,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:30,929 INFO L681 BuchiCegarLoop]: Abstraction has 92 states and 94 transitions. [2021-10-28 09:00:30,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 94 transitions. [2021-10-28 09:00:30,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 91. [2021-10-28 09:00:30,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.021978021978022) internal successors, (93), 90 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:30,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 93 transitions. [2021-10-28 09:00:30,932 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2021-10-28 09:00:30,932 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2021-10-28 09:00:30,932 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-10-28 09:00:30,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 93 transitions. [2021-10-28 09:00:30,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:30,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:30,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:30,935 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [44, 43, 1] [2021-10-28 09:00:30,935 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:30,935 INFO L791 eck$LassoCheckResult]: Stem: 11899#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 11895#L10-2 assume !!(main_~i~0 < 100); 11896#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11897#L10-2 assume !!(main_~i~0 < 100); 11898#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11902#L10-2 assume !!(main_~i~0 < 100); 11985#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11984#L10-2 assume !!(main_~i~0 < 100); 11983#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11982#L10-2 assume !!(main_~i~0 < 100); 11981#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11980#L10-2 assume !!(main_~i~0 < 100); 11979#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11978#L10-2 assume !!(main_~i~0 < 100); 11977#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11976#L10-2 assume !!(main_~i~0 < 100); 11975#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11974#L10-2 assume !!(main_~i~0 < 100); 11973#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11972#L10-2 assume !!(main_~i~0 < 100); 11971#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11970#L10-2 assume !!(main_~i~0 < 100); 11969#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11968#L10-2 assume !!(main_~i~0 < 100); 11967#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11966#L10-2 assume !!(main_~i~0 < 100); 11965#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11964#L10-2 assume !!(main_~i~0 < 100); 11963#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11962#L10-2 assume !!(main_~i~0 < 100); 11961#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11960#L10-2 assume !!(main_~i~0 < 100); 11959#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11958#L10-2 assume !!(main_~i~0 < 100); 11957#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11956#L10-2 assume !!(main_~i~0 < 100); 11955#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11954#L10-2 assume !!(main_~i~0 < 100); 11953#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11952#L10-2 assume !!(main_~i~0 < 100); 11951#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11950#L10-2 assume !!(main_~i~0 < 100); 11949#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11948#L10-2 assume !!(main_~i~0 < 100); 11947#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11946#L10-2 assume !!(main_~i~0 < 100); 11945#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11944#L10-2 assume !!(main_~i~0 < 100); 11943#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11942#L10-2 assume !!(main_~i~0 < 100); 11941#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11940#L10-2 assume !!(main_~i~0 < 100); 11939#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11938#L10-2 assume !!(main_~i~0 < 100); 11937#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11936#L10-2 assume !!(main_~i~0 < 100); 11935#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11934#L10-2 assume !!(main_~i~0 < 100); 11933#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11932#L10-2 assume !!(main_~i~0 < 100); 11931#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11930#L10-2 assume !!(main_~i~0 < 100); 11929#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11928#L10-2 assume !!(main_~i~0 < 100); 11927#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11926#L10-2 assume !!(main_~i~0 < 100); 11925#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11924#L10-2 assume !!(main_~i~0 < 100); 11923#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11922#L10-2 assume !!(main_~i~0 < 100); 11921#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11920#L10-2 assume !!(main_~i~0 < 100); 11919#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11918#L10-2 assume !!(main_~i~0 < 100); 11917#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11916#L10-2 assume !!(main_~i~0 < 100); 11915#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11914#L10-2 assume !!(main_~i~0 < 100); 11913#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11912#L10-2 assume !!(main_~i~0 < 100); 11911#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11910#L10-2 assume !!(main_~i~0 < 100); 11909#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11908#L10-2 assume !!(main_~i~0 < 100); 11906#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11905#L10-2 assume !!(main_~i~0 < 100); 11904#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11903#L10-2 assume !!(main_~i~0 < 100); 11900#L10 [2021-10-28 09:00:30,936 INFO L793 eck$LassoCheckResult]: Loop: 11900#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 11901#L10-2 assume !!(main_~i~0 < 100); 11904#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 11903#L10-2 assume !!(main_~i~0 < 100); 11900#L10 [2021-10-28 09:00:30,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:30,936 INFO L85 PathProgramCache]: Analyzing trace with hash 482268937, now seen corresponding path program 43 times [2021-10-28 09:00:30,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:30,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860848082] [2021-10-28 09:00:30,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:30,937 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:30,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:30,955 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:30,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:30,970 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:30,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:30,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 41 times [2021-10-28 09:00:30,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:30,971 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115888590] [2021-10-28 09:00:30,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:30,971 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:30,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:30,980 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:30,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:30,982 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:30,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:30,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1677796161, now seen corresponding path program 43 times [2021-10-28 09:00:30,983 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:30,983 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609489016] [2021-10-28 09:00:30,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:30,983 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:31,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:32,046 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:32,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:32,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609489016] [2021-10-28 09:00:32,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609489016] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:32,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2099290028] [2021-10-28 09:00:32,046 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:00:32,047 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:32,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:32,048 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:32,049 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-10-28 09:00:32,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:32,902 INFO L263 TraceCheckSpWp]: Trace formula consists of 185 conjuncts, 45 conjunts are in the unsatisfiable core [2021-10-28 09:00:32,904 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:33,188 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:33,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2099290028] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:33,188 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:33,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2021-10-28 09:00:33,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477037177] [2021-10-28 09:00:33,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:33,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-10-28 09:00:33,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2021-10-28 09:00:33,216 INFO L87 Difference]: Start difference. First operand 91 states and 93 transitions. cyclomatic complexity: 3 Second operand has 46 states, 46 states have (on average 1.9782608695652173) internal successors, (91), 45 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:33,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:33,323 INFO L93 Difference]: Finished difference Result 95 states and 97 transitions. [2021-10-28 09:00:33,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-10-28 09:00:33,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 97 transitions. [2021-10-28 09:00:33,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:33,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 94 states and 96 transitions. [2021-10-28 09:00:33,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:33,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:33,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 96 transitions. [2021-10-28 09:00:33,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:33,325 INFO L681 BuchiCegarLoop]: Abstraction has 94 states and 96 transitions. [2021-10-28 09:00:33,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 96 transitions. [2021-10-28 09:00:33,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2021-10-28 09:00:33,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.021505376344086) internal successors, (95), 92 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:33,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 95 transitions. [2021-10-28 09:00:33,328 INFO L704 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2021-10-28 09:00:33,328 INFO L587 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2021-10-28 09:00:33,328 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-10-28 09:00:33,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 95 transitions. [2021-10-28 09:00:33,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:33,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:33,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:33,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [45, 44, 1] [2021-10-28 09:00:33,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:33,331 INFO L791 eck$LassoCheckResult]: Stem: 12409#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 12405#L10-2 assume !!(main_~i~0 < 100); 12406#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12407#L10-2 assume !!(main_~i~0 < 100); 12408#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12412#L10-2 assume !!(main_~i~0 < 100); 12497#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12496#L10-2 assume !!(main_~i~0 < 100); 12495#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12494#L10-2 assume !!(main_~i~0 < 100); 12493#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12492#L10-2 assume !!(main_~i~0 < 100); 12491#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12490#L10-2 assume !!(main_~i~0 < 100); 12489#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12488#L10-2 assume !!(main_~i~0 < 100); 12487#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12486#L10-2 assume !!(main_~i~0 < 100); 12485#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12484#L10-2 assume !!(main_~i~0 < 100); 12483#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12482#L10-2 assume !!(main_~i~0 < 100); 12481#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12480#L10-2 assume !!(main_~i~0 < 100); 12479#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12478#L10-2 assume !!(main_~i~0 < 100); 12477#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12476#L10-2 assume !!(main_~i~0 < 100); 12475#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12474#L10-2 assume !!(main_~i~0 < 100); 12473#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12472#L10-2 assume !!(main_~i~0 < 100); 12471#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12470#L10-2 assume !!(main_~i~0 < 100); 12469#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12468#L10-2 assume !!(main_~i~0 < 100); 12467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12466#L10-2 assume !!(main_~i~0 < 100); 12465#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12464#L10-2 assume !!(main_~i~0 < 100); 12463#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12462#L10-2 assume !!(main_~i~0 < 100); 12461#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12460#L10-2 assume !!(main_~i~0 < 100); 12459#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12458#L10-2 assume !!(main_~i~0 < 100); 12457#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12456#L10-2 assume !!(main_~i~0 < 100); 12455#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12454#L10-2 assume !!(main_~i~0 < 100); 12453#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12452#L10-2 assume !!(main_~i~0 < 100); 12451#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12450#L10-2 assume !!(main_~i~0 < 100); 12449#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12448#L10-2 assume !!(main_~i~0 < 100); 12447#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12446#L10-2 assume !!(main_~i~0 < 100); 12445#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12444#L10-2 assume !!(main_~i~0 < 100); 12443#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12442#L10-2 assume !!(main_~i~0 < 100); 12441#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12440#L10-2 assume !!(main_~i~0 < 100); 12439#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12438#L10-2 assume !!(main_~i~0 < 100); 12437#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12436#L10-2 assume !!(main_~i~0 < 100); 12435#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12434#L10-2 assume !!(main_~i~0 < 100); 12433#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12432#L10-2 assume !!(main_~i~0 < 100); 12431#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12430#L10-2 assume !!(main_~i~0 < 100); 12429#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12428#L10-2 assume !!(main_~i~0 < 100); 12427#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12426#L10-2 assume !!(main_~i~0 < 100); 12425#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12424#L10-2 assume !!(main_~i~0 < 100); 12423#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12422#L10-2 assume !!(main_~i~0 < 100); 12421#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12420#L10-2 assume !!(main_~i~0 < 100); 12419#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12418#L10-2 assume !!(main_~i~0 < 100); 12416#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12415#L10-2 assume !!(main_~i~0 < 100); 12414#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12413#L10-2 assume !!(main_~i~0 < 100); 12410#L10 [2021-10-28 09:00:33,331 INFO L793 eck$LassoCheckResult]: Loop: 12410#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 12411#L10-2 assume !!(main_~i~0 < 100); 12414#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12413#L10-2 assume !!(main_~i~0 < 100); 12410#L10 [2021-10-28 09:00:33,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:33,332 INFO L85 PathProgramCache]: Analyzing trace with hash -396019098, now seen corresponding path program 44 times [2021-10-28 09:00:33,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:33,332 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477057827] [2021-10-28 09:00:33,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:33,333 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:33,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:33,352 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:33,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:33,366 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:33,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:33,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 42 times [2021-10-28 09:00:33,367 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:33,367 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022820239] [2021-10-28 09:00:33,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:33,368 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:33,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:33,376 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:33,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:33,378 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:33,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:33,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1692176414, now seen corresponding path program 44 times [2021-10-28 09:00:33,379 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:33,379 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404220653] [2021-10-28 09:00:33,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:33,379 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:33,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:34,432 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:34,433 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:34,433 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404220653] [2021-10-28 09:00:34,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404220653] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:34,433 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [126422937] [2021-10-28 09:00:34,433 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:00:34,433 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:34,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:34,438 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:34,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-10-28 09:00:35,355 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:00:35,355 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:35,356 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 46 conjunts are in the unsatisfiable core [2021-10-28 09:00:35,357 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:35,654 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:35,654 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [126422937] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:35,654 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:35,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2021-10-28 09:00:35,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269880929] [2021-10-28 09:00:35,681 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:35,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-10-28 09:00:35,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2021-10-28 09:00:35,682 INFO L87 Difference]: Start difference. First operand 93 states and 95 transitions. cyclomatic complexity: 3 Second operand has 47 states, 47 states have (on average 1.9787234042553192) internal successors, (93), 46 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:35,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:35,785 INFO L93 Difference]: Finished difference Result 97 states and 99 transitions. [2021-10-28 09:00:35,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-10-28 09:00:35,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 99 transitions. [2021-10-28 09:00:35,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:35,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 96 states and 98 transitions. [2021-10-28 09:00:35,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:35,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:35,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 98 transitions. [2021-10-28 09:00:35,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:35,788 INFO L681 BuchiCegarLoop]: Abstraction has 96 states and 98 transitions. [2021-10-28 09:00:35,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 98 transitions. [2021-10-28 09:00:35,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 95. [2021-10-28 09:00:35,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.0210526315789474) internal successors, (97), 94 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:35,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 97 transitions. [2021-10-28 09:00:35,791 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2021-10-28 09:00:35,791 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2021-10-28 09:00:35,791 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-10-28 09:00:35,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 97 transitions. [2021-10-28 09:00:35,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:35,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:35,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:35,793 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 45, 1] [2021-10-28 09:00:35,794 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:35,794 INFO L791 eck$LassoCheckResult]: Stem: 12930#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 12926#L10-2 assume !!(main_~i~0 < 100); 12927#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12928#L10-2 assume !!(main_~i~0 < 100); 12929#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12933#L10-2 assume !!(main_~i~0 < 100); 13020#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13019#L10-2 assume !!(main_~i~0 < 100); 13018#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13017#L10-2 assume !!(main_~i~0 < 100); 13016#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13015#L10-2 assume !!(main_~i~0 < 100); 13014#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13013#L10-2 assume !!(main_~i~0 < 100); 13012#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13011#L10-2 assume !!(main_~i~0 < 100); 13010#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13009#L10-2 assume !!(main_~i~0 < 100); 13008#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13007#L10-2 assume !!(main_~i~0 < 100); 13006#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13005#L10-2 assume !!(main_~i~0 < 100); 13004#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13003#L10-2 assume !!(main_~i~0 < 100); 13002#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13001#L10-2 assume !!(main_~i~0 < 100); 13000#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12999#L10-2 assume !!(main_~i~0 < 100); 12998#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12997#L10-2 assume !!(main_~i~0 < 100); 12996#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12995#L10-2 assume !!(main_~i~0 < 100); 12994#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12993#L10-2 assume !!(main_~i~0 < 100); 12992#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12991#L10-2 assume !!(main_~i~0 < 100); 12990#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12989#L10-2 assume !!(main_~i~0 < 100); 12988#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12987#L10-2 assume !!(main_~i~0 < 100); 12986#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12985#L10-2 assume !!(main_~i~0 < 100); 12984#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12983#L10-2 assume !!(main_~i~0 < 100); 12982#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12981#L10-2 assume !!(main_~i~0 < 100); 12980#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12979#L10-2 assume !!(main_~i~0 < 100); 12978#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12977#L10-2 assume !!(main_~i~0 < 100); 12976#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12975#L10-2 assume !!(main_~i~0 < 100); 12974#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12973#L10-2 assume !!(main_~i~0 < 100); 12972#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12971#L10-2 assume !!(main_~i~0 < 100); 12970#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12969#L10-2 assume !!(main_~i~0 < 100); 12968#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12967#L10-2 assume !!(main_~i~0 < 100); 12966#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12965#L10-2 assume !!(main_~i~0 < 100); 12964#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12963#L10-2 assume !!(main_~i~0 < 100); 12962#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12961#L10-2 assume !!(main_~i~0 < 100); 12960#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12959#L10-2 assume !!(main_~i~0 < 100); 12958#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12957#L10-2 assume !!(main_~i~0 < 100); 12956#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12955#L10-2 assume !!(main_~i~0 < 100); 12954#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12953#L10-2 assume !!(main_~i~0 < 100); 12952#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12951#L10-2 assume !!(main_~i~0 < 100); 12950#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12949#L10-2 assume !!(main_~i~0 < 100); 12948#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12947#L10-2 assume !!(main_~i~0 < 100); 12946#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12945#L10-2 assume !!(main_~i~0 < 100); 12944#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12943#L10-2 assume !!(main_~i~0 < 100); 12942#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12941#L10-2 assume !!(main_~i~0 < 100); 12940#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12939#L10-2 assume !!(main_~i~0 < 100); 12937#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12936#L10-2 assume !!(main_~i~0 < 100); 12935#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12934#L10-2 assume !!(main_~i~0 < 100); 12931#L10 [2021-10-28 09:00:35,794 INFO L793 eck$LassoCheckResult]: Loop: 12931#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 12932#L10-2 assume !!(main_~i~0 < 100); 12935#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 12934#L10-2 assume !!(main_~i~0 < 100); 12931#L10 [2021-10-28 09:00:35,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:35,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1677736579, now seen corresponding path program 45 times [2021-10-28 09:00:35,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:35,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039795389] [2021-10-28 09:00:35,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:35,796 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:35,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:35,890 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:35,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:35,900 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:35,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:35,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 43 times [2021-10-28 09:00:35,901 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:35,901 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793427856] [2021-10-28 09:00:35,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:35,901 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:35,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:35,908 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:35,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:35,909 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:35,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:35,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1668269637, now seen corresponding path program 45 times [2021-10-28 09:00:35,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:35,910 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082545121] [2021-10-28 09:00:35,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:35,910 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:35,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:37,083 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:37,084 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:37,084 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082545121] [2021-10-28 09:00:37,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082545121] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:37,084 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2017657538] [2021-10-28 09:00:37,084 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:00:37,084 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:37,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:37,124 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:37,134 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-10-28 09:00:37,990 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2021-10-28 09:00:37,990 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:37,992 INFO L263 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 47 conjunts are in the unsatisfiable core [2021-10-28 09:00:37,993 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:38,327 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:38,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2017657538] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:38,327 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:38,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2021-10-28 09:00:38,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342674607] [2021-10-28 09:00:38,351 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:38,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-10-28 09:00:38,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2021-10-28 09:00:38,353 INFO L87 Difference]: Start difference. First operand 95 states and 97 transitions. cyclomatic complexity: 3 Second operand has 48 states, 48 states have (on average 1.9791666666666667) internal successors, (95), 47 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:38,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:38,507 INFO L93 Difference]: Finished difference Result 99 states and 101 transitions. [2021-10-28 09:00:38,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-10-28 09:00:38,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 101 transitions. [2021-10-28 09:00:38,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:38,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 98 states and 100 transitions. [2021-10-28 09:00:38,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:38,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:38,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 100 transitions. [2021-10-28 09:00:38,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:38,510 INFO L681 BuchiCegarLoop]: Abstraction has 98 states and 100 transitions. [2021-10-28 09:00:38,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 100 transitions. [2021-10-28 09:00:38,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 97. [2021-10-28 09:00:38,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0206185567010309) internal successors, (99), 96 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:38,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 99 transitions. [2021-10-28 09:00:38,513 INFO L704 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2021-10-28 09:00:38,513 INFO L587 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2021-10-28 09:00:38,513 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-10-28 09:00:38,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 99 transitions. [2021-10-28 09:00:38,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:38,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:38,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:38,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [47, 46, 1] [2021-10-28 09:00:38,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:38,516 INFO L791 eck$LassoCheckResult]: Stem: 13462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 13458#L10-2 assume !!(main_~i~0 < 100); 13459#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13460#L10-2 assume !!(main_~i~0 < 100); 13461#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13465#L10-2 assume !!(main_~i~0 < 100); 13554#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13553#L10-2 assume !!(main_~i~0 < 100); 13552#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13551#L10-2 assume !!(main_~i~0 < 100); 13550#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13549#L10-2 assume !!(main_~i~0 < 100); 13548#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13547#L10-2 assume !!(main_~i~0 < 100); 13546#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13545#L10-2 assume !!(main_~i~0 < 100); 13544#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13543#L10-2 assume !!(main_~i~0 < 100); 13542#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13541#L10-2 assume !!(main_~i~0 < 100); 13540#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13539#L10-2 assume !!(main_~i~0 < 100); 13538#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13537#L10-2 assume !!(main_~i~0 < 100); 13536#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13535#L10-2 assume !!(main_~i~0 < 100); 13534#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13533#L10-2 assume !!(main_~i~0 < 100); 13532#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13531#L10-2 assume !!(main_~i~0 < 100); 13530#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13529#L10-2 assume !!(main_~i~0 < 100); 13528#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13527#L10-2 assume !!(main_~i~0 < 100); 13526#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13525#L10-2 assume !!(main_~i~0 < 100); 13524#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13523#L10-2 assume !!(main_~i~0 < 100); 13522#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13521#L10-2 assume !!(main_~i~0 < 100); 13520#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13519#L10-2 assume !!(main_~i~0 < 100); 13518#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13517#L10-2 assume !!(main_~i~0 < 100); 13516#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13515#L10-2 assume !!(main_~i~0 < 100); 13514#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13513#L10-2 assume !!(main_~i~0 < 100); 13512#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13511#L10-2 assume !!(main_~i~0 < 100); 13510#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13509#L10-2 assume !!(main_~i~0 < 100); 13508#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13507#L10-2 assume !!(main_~i~0 < 100); 13506#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13505#L10-2 assume !!(main_~i~0 < 100); 13504#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13503#L10-2 assume !!(main_~i~0 < 100); 13502#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13501#L10-2 assume !!(main_~i~0 < 100); 13500#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13499#L10-2 assume !!(main_~i~0 < 100); 13498#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13497#L10-2 assume !!(main_~i~0 < 100); 13496#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13495#L10-2 assume !!(main_~i~0 < 100); 13494#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13493#L10-2 assume !!(main_~i~0 < 100); 13492#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13491#L10-2 assume !!(main_~i~0 < 100); 13490#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13489#L10-2 assume !!(main_~i~0 < 100); 13488#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13487#L10-2 assume !!(main_~i~0 < 100); 13486#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13485#L10-2 assume !!(main_~i~0 < 100); 13484#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13483#L10-2 assume !!(main_~i~0 < 100); 13482#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13481#L10-2 assume !!(main_~i~0 < 100); 13480#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13479#L10-2 assume !!(main_~i~0 < 100); 13478#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13477#L10-2 assume !!(main_~i~0 < 100); 13476#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13475#L10-2 assume !!(main_~i~0 < 100); 13474#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13473#L10-2 assume !!(main_~i~0 < 100); 13472#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13471#L10-2 assume !!(main_~i~0 < 100); 13469#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13468#L10-2 assume !!(main_~i~0 < 100); 13467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13466#L10-2 assume !!(main_~i~0 < 100); 13463#L10 [2021-10-28 09:00:38,516 INFO L793 eck$LassoCheckResult]: Loop: 13463#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 13464#L10-2 assume !!(main_~i~0 < 100); 13467#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 13466#L10-2 assume !!(main_~i~0 < 100); 13463#L10 [2021-10-28 09:00:38,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:38,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1692116832, now seen corresponding path program 46 times [2021-10-28 09:00:38,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:38,517 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515937285] [2021-10-28 09:00:38,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:38,517 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:38,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:38,537 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:38,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:38,551 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:38,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:38,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 44 times [2021-10-28 09:00:38,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:38,552 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840600056] [2021-10-28 09:00:38,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:38,552 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:38,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:38,663 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:38,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:38,665 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:38,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:38,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1241518056, now seen corresponding path program 46 times [2021-10-28 09:00:38,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:38,666 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415965962] [2021-10-28 09:00:38,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:38,666 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:38,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:39,811 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:39,811 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:39,811 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415965962] [2021-10-28 09:00:39,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415965962] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:39,811 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [243295337] [2021-10-28 09:00:39,812 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 09:00:39,812 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:39,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:39,814 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:39,815 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-10-28 09:00:40,740 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 09:00:40,740 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:40,742 INFO L263 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 48 conjunts are in the unsatisfiable core [2021-10-28 09:00:40,743 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:41,080 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:41,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [243295337] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:41,080 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:41,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2021-10-28 09:00:41,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920187319] [2021-10-28 09:00:41,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:41,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-10-28 09:00:41,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-10-28 09:00:41,139 INFO L87 Difference]: Start difference. First operand 97 states and 99 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 48 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:41,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:41,258 INFO L93 Difference]: Finished difference Result 101 states and 103 transitions. [2021-10-28 09:00:41,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-10-28 09:00:41,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 103 transitions. [2021-10-28 09:00:41,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:41,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 100 states and 102 transitions. [2021-10-28 09:00:41,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:41,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:41,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 102 transitions. [2021-10-28 09:00:41,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:41,261 INFO L681 BuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2021-10-28 09:00:41,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 102 transitions. [2021-10-28 09:00:41,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2021-10-28 09:00:41,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.02020202020202) internal successors, (101), 98 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:41,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 101 transitions. [2021-10-28 09:00:41,265 INFO L704 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2021-10-28 09:00:41,265 INFO L587 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2021-10-28 09:00:41,265 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-10-28 09:00:41,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 101 transitions. [2021-10-28 09:00:41,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:41,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:41,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:41,267 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [48, 47, 1] [2021-10-28 09:00:41,268 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:41,268 INFO L791 eck$LassoCheckResult]: Stem: 14005#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 14001#L10-2 assume !!(main_~i~0 < 100); 14002#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14003#L10-2 assume !!(main_~i~0 < 100); 14004#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14008#L10-2 assume !!(main_~i~0 < 100); 14099#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14098#L10-2 assume !!(main_~i~0 < 100); 14097#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14096#L10-2 assume !!(main_~i~0 < 100); 14095#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14094#L10-2 assume !!(main_~i~0 < 100); 14093#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14092#L10-2 assume !!(main_~i~0 < 100); 14091#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14090#L10-2 assume !!(main_~i~0 < 100); 14089#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14088#L10-2 assume !!(main_~i~0 < 100); 14087#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14086#L10-2 assume !!(main_~i~0 < 100); 14085#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14084#L10-2 assume !!(main_~i~0 < 100); 14083#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14082#L10-2 assume !!(main_~i~0 < 100); 14081#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14080#L10-2 assume !!(main_~i~0 < 100); 14079#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14078#L10-2 assume !!(main_~i~0 < 100); 14077#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14076#L10-2 assume !!(main_~i~0 < 100); 14075#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14074#L10-2 assume !!(main_~i~0 < 100); 14073#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14072#L10-2 assume !!(main_~i~0 < 100); 14071#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14070#L10-2 assume !!(main_~i~0 < 100); 14069#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14068#L10-2 assume !!(main_~i~0 < 100); 14067#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14066#L10-2 assume !!(main_~i~0 < 100); 14065#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14064#L10-2 assume !!(main_~i~0 < 100); 14063#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14062#L10-2 assume !!(main_~i~0 < 100); 14061#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14060#L10-2 assume !!(main_~i~0 < 100); 14059#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14058#L10-2 assume !!(main_~i~0 < 100); 14057#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14056#L10-2 assume !!(main_~i~0 < 100); 14055#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14054#L10-2 assume !!(main_~i~0 < 100); 14053#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14052#L10-2 assume !!(main_~i~0 < 100); 14051#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14050#L10-2 assume !!(main_~i~0 < 100); 14049#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14048#L10-2 assume !!(main_~i~0 < 100); 14047#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14046#L10-2 assume !!(main_~i~0 < 100); 14045#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14044#L10-2 assume !!(main_~i~0 < 100); 14043#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14042#L10-2 assume !!(main_~i~0 < 100); 14041#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14040#L10-2 assume !!(main_~i~0 < 100); 14039#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14038#L10-2 assume !!(main_~i~0 < 100); 14037#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14036#L10-2 assume !!(main_~i~0 < 100); 14035#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14034#L10-2 assume !!(main_~i~0 < 100); 14033#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14032#L10-2 assume !!(main_~i~0 < 100); 14031#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14030#L10-2 assume !!(main_~i~0 < 100); 14029#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14028#L10-2 assume !!(main_~i~0 < 100); 14027#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14026#L10-2 assume !!(main_~i~0 < 100); 14025#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14024#L10-2 assume !!(main_~i~0 < 100); 14023#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14022#L10-2 assume !!(main_~i~0 < 100); 14021#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14020#L10-2 assume !!(main_~i~0 < 100); 14019#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14018#L10-2 assume !!(main_~i~0 < 100); 14017#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14016#L10-2 assume !!(main_~i~0 < 100); 14015#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14014#L10-2 assume !!(main_~i~0 < 100); 14012#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14011#L10-2 assume !!(main_~i~0 < 100); 14010#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14009#L10-2 assume !!(main_~i~0 < 100); 14006#L10 [2021-10-28 09:00:41,268 INFO L793 eck$LassoCheckResult]: Loop: 14006#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 14007#L10-2 assume !!(main_~i~0 < 100); 14010#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14009#L10-2 assume !!(main_~i~0 < 100); 14006#L10 [2021-10-28 09:00:41,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:41,269 INFO L85 PathProgramCache]: Analyzing trace with hash -1668329219, now seen corresponding path program 47 times [2021-10-28 09:00:41,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:41,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717347616] [2021-10-28 09:00:41,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:41,270 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:41,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:41,297 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:41,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:41,313 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:41,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:41,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 45 times [2021-10-28 09:00:41,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:41,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005671865] [2021-10-28 09:00:41,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:41,314 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:41,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:41,331 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:41,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:41,333 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:41,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:41,334 INFO L85 PathProgramCache]: Analyzing trace with hash 844858165, now seen corresponding path program 47 times [2021-10-28 09:00:41,334 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:41,334 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593275945] [2021-10-28 09:00:41,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:41,335 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:41,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:42,590 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:42,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:42,591 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593275945] [2021-10-28 09:00:42,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593275945] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:42,591 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [293876144] [2021-10-28 09:00:42,591 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 09:00:42,591 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:42,591 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:42,594 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:42,594 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-10-28 09:00:43,633 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 50 check-sat command(s) [2021-10-28 09:00:43,633 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:43,635 INFO L263 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 49 conjunts are in the unsatisfiable core [2021-10-28 09:00:43,636 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:43,969 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:43,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [293876144] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:43,970 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:43,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2021-10-28 09:00:43,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647906233] [2021-10-28 09:00:43,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:43,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-10-28 09:00:43,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2021-10-28 09:00:43,995 INFO L87 Difference]: Start difference. First operand 99 states and 101 transitions. cyclomatic complexity: 3 Second operand has 50 states, 50 states have (on average 1.98) internal successors, (99), 49 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:44,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:44,117 INFO L93 Difference]: Finished difference Result 103 states and 105 transitions. [2021-10-28 09:00:44,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-10-28 09:00:44,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 105 transitions. [2021-10-28 09:00:44,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:44,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 102 states and 104 transitions. [2021-10-28 09:00:44,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:44,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:44,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 104 transitions. [2021-10-28 09:00:44,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:44,120 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 104 transitions. [2021-10-28 09:00:44,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 104 transitions. [2021-10-28 09:00:44,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 101. [2021-10-28 09:00:44,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.0198019801980198) internal successors, (103), 100 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:44,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 103 transitions. [2021-10-28 09:00:44,123 INFO L704 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2021-10-28 09:00:44,123 INFO L587 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2021-10-28 09:00:44,124 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-10-28 09:00:44,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 103 transitions. [2021-10-28 09:00:44,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:44,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:44,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:44,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [49, 48, 1] [2021-10-28 09:00:44,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:44,126 INFO L791 eck$LassoCheckResult]: Stem: 14559#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 14555#L10-2 assume !!(main_~i~0 < 100); 14556#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14557#L10-2 assume !!(main_~i~0 < 100); 14558#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14562#L10-2 assume !!(main_~i~0 < 100); 14655#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14654#L10-2 assume !!(main_~i~0 < 100); 14653#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14652#L10-2 assume !!(main_~i~0 < 100); 14651#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14650#L10-2 assume !!(main_~i~0 < 100); 14649#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14648#L10-2 assume !!(main_~i~0 < 100); 14647#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14646#L10-2 assume !!(main_~i~0 < 100); 14645#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14644#L10-2 assume !!(main_~i~0 < 100); 14643#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14642#L10-2 assume !!(main_~i~0 < 100); 14641#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14640#L10-2 assume !!(main_~i~0 < 100); 14639#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14638#L10-2 assume !!(main_~i~0 < 100); 14637#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14636#L10-2 assume !!(main_~i~0 < 100); 14635#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14634#L10-2 assume !!(main_~i~0 < 100); 14633#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14632#L10-2 assume !!(main_~i~0 < 100); 14631#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14630#L10-2 assume !!(main_~i~0 < 100); 14629#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14628#L10-2 assume !!(main_~i~0 < 100); 14627#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14626#L10-2 assume !!(main_~i~0 < 100); 14625#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14624#L10-2 assume !!(main_~i~0 < 100); 14623#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14622#L10-2 assume !!(main_~i~0 < 100); 14621#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14620#L10-2 assume !!(main_~i~0 < 100); 14619#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14618#L10-2 assume !!(main_~i~0 < 100); 14617#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14616#L10-2 assume !!(main_~i~0 < 100); 14615#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14614#L10-2 assume !!(main_~i~0 < 100); 14613#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14612#L10-2 assume !!(main_~i~0 < 100); 14611#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14610#L10-2 assume !!(main_~i~0 < 100); 14609#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14608#L10-2 assume !!(main_~i~0 < 100); 14607#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14606#L10-2 assume !!(main_~i~0 < 100); 14605#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14604#L10-2 assume !!(main_~i~0 < 100); 14603#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14602#L10-2 assume !!(main_~i~0 < 100); 14601#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14600#L10-2 assume !!(main_~i~0 < 100); 14599#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14598#L10-2 assume !!(main_~i~0 < 100); 14597#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14596#L10-2 assume !!(main_~i~0 < 100); 14595#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14594#L10-2 assume !!(main_~i~0 < 100); 14593#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14592#L10-2 assume !!(main_~i~0 < 100); 14591#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14590#L10-2 assume !!(main_~i~0 < 100); 14589#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14588#L10-2 assume !!(main_~i~0 < 100); 14587#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14586#L10-2 assume !!(main_~i~0 < 100); 14585#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14584#L10-2 assume !!(main_~i~0 < 100); 14583#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14582#L10-2 assume !!(main_~i~0 < 100); 14581#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14580#L10-2 assume !!(main_~i~0 < 100); 14579#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14578#L10-2 assume !!(main_~i~0 < 100); 14577#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14576#L10-2 assume !!(main_~i~0 < 100); 14575#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14574#L10-2 assume !!(main_~i~0 < 100); 14573#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14572#L10-2 assume !!(main_~i~0 < 100); 14571#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14570#L10-2 assume !!(main_~i~0 < 100); 14569#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14568#L10-2 assume !!(main_~i~0 < 100); 14566#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14565#L10-2 assume !!(main_~i~0 < 100); 14564#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14563#L10-2 assume !!(main_~i~0 < 100); 14560#L10 [2021-10-28 09:00:44,126 INFO L793 eck$LassoCheckResult]: Loop: 14560#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 14561#L10-2 assume !!(main_~i~0 < 100); 14564#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 14563#L10-2 assume !!(main_~i~0 < 100); 14560#L10 [2021-10-28 09:00:44,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:44,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1241577638, now seen corresponding path program 48 times [2021-10-28 09:00:44,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:44,127 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814112993] [2021-10-28 09:00:44,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:44,128 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:44,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:44,166 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:44,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:44,181 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:44,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:44,181 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 46 times [2021-10-28 09:00:44,182 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:44,182 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955212899] [2021-10-28 09:00:44,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:44,182 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:44,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:44,192 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:44,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:44,194 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:44,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:44,195 INFO L85 PathProgramCache]: Analyzing trace with hash 102679314, now seen corresponding path program 48 times [2021-10-28 09:00:44,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:44,195 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761359383] [2021-10-28 09:00:44,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:44,195 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:44,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:45,319 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:45,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:45,319 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761359383] [2021-10-28 09:00:45,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761359383] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:45,319 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [549099147] [2021-10-28 09:00:45,319 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 09:00:45,319 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:45,320 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:45,322 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:45,342 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-10-28 09:00:46,306 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2021-10-28 09:00:46,306 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:00:46,308 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 50 conjunts are in the unsatisfiable core [2021-10-28 09:00:46,309 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:46,648 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:46,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [549099147] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:46,648 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:46,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2021-10-28 09:00:46,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894875778] [2021-10-28 09:00:46,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:46,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-10-28 09:00:46,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2021-10-28 09:00:46,698 INFO L87 Difference]: Start difference. First operand 101 states and 103 transitions. cyclomatic complexity: 3 Second operand has 51 states, 51 states have (on average 1.9803921568627452) internal successors, (101), 50 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:46,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:46,829 INFO L93 Difference]: Finished difference Result 105 states and 107 transitions. [2021-10-28 09:00:46,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2021-10-28 09:00:46,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 107 transitions. [2021-10-28 09:00:46,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:46,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 106 transitions. [2021-10-28 09:00:46,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:46,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:46,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 106 transitions. [2021-10-28 09:00:46,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:46,832 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 106 transitions. [2021-10-28 09:00:46,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 106 transitions. [2021-10-28 09:00:46,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 103. [2021-10-28 09:00:46,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.0194174757281553) internal successors, (105), 102 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:46,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 105 transitions. [2021-10-28 09:00:46,835 INFO L704 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2021-10-28 09:00:46,835 INFO L587 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2021-10-28 09:00:46,835 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-10-28 09:00:46,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 105 transitions. [2021-10-28 09:00:46,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:46,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:46,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:46,837 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [50, 49, 1] [2021-10-28 09:00:46,837 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:46,837 INFO L791 eck$LassoCheckResult]: Stem: 15124#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 15120#L10-2 assume !!(main_~i~0 < 100); 15121#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15122#L10-2 assume !!(main_~i~0 < 100); 15123#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15127#L10-2 assume !!(main_~i~0 < 100); 15222#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15221#L10-2 assume !!(main_~i~0 < 100); 15220#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15219#L10-2 assume !!(main_~i~0 < 100); 15218#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15217#L10-2 assume !!(main_~i~0 < 100); 15216#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15215#L10-2 assume !!(main_~i~0 < 100); 15214#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15213#L10-2 assume !!(main_~i~0 < 100); 15212#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15211#L10-2 assume !!(main_~i~0 < 100); 15210#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15209#L10-2 assume !!(main_~i~0 < 100); 15208#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15207#L10-2 assume !!(main_~i~0 < 100); 15206#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15205#L10-2 assume !!(main_~i~0 < 100); 15204#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15203#L10-2 assume !!(main_~i~0 < 100); 15202#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15201#L10-2 assume !!(main_~i~0 < 100); 15200#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15199#L10-2 assume !!(main_~i~0 < 100); 15198#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15197#L10-2 assume !!(main_~i~0 < 100); 15196#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15195#L10-2 assume !!(main_~i~0 < 100); 15194#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15193#L10-2 assume !!(main_~i~0 < 100); 15192#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15191#L10-2 assume !!(main_~i~0 < 100); 15190#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15189#L10-2 assume !!(main_~i~0 < 100); 15188#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15187#L10-2 assume !!(main_~i~0 < 100); 15186#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15185#L10-2 assume !!(main_~i~0 < 100); 15184#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15183#L10-2 assume !!(main_~i~0 < 100); 15182#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15181#L10-2 assume !!(main_~i~0 < 100); 15180#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15179#L10-2 assume !!(main_~i~0 < 100); 15178#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15177#L10-2 assume !!(main_~i~0 < 100); 15176#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15175#L10-2 assume !!(main_~i~0 < 100); 15174#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15173#L10-2 assume !!(main_~i~0 < 100); 15172#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15171#L10-2 assume !!(main_~i~0 < 100); 15170#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15169#L10-2 assume !!(main_~i~0 < 100); 15168#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15167#L10-2 assume !!(main_~i~0 < 100); 15166#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15165#L10-2 assume !!(main_~i~0 < 100); 15164#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15163#L10-2 assume !!(main_~i~0 < 100); 15162#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15161#L10-2 assume !!(main_~i~0 < 100); 15160#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15159#L10-2 assume !!(main_~i~0 < 100); 15158#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15157#L10-2 assume !!(main_~i~0 < 100); 15156#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15155#L10-2 assume !!(main_~i~0 < 100); 15154#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15153#L10-2 assume !!(main_~i~0 < 100); 15152#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15151#L10-2 assume !!(main_~i~0 < 100); 15150#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15149#L10-2 assume !!(main_~i~0 < 100); 15148#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15147#L10-2 assume !!(main_~i~0 < 100); 15146#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15145#L10-2 assume !!(main_~i~0 < 100); 15144#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15143#L10-2 assume !!(main_~i~0 < 100); 15142#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15141#L10-2 assume !!(main_~i~0 < 100); 15140#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15139#L10-2 assume !!(main_~i~0 < 100); 15138#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15137#L10-2 assume !!(main_~i~0 < 100); 15136#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15135#L10-2 assume !!(main_~i~0 < 100); 15134#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15133#L10-2 assume !!(main_~i~0 < 100); 15131#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15130#L10-2 assume !!(main_~i~0 < 100); 15129#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15128#L10-2 assume !!(main_~i~0 < 100); 15125#L10 [2021-10-28 09:00:46,837 INFO L793 eck$LassoCheckResult]: Loop: 15125#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 15126#L10-2 assume !!(main_~i~0 < 100); 15129#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15128#L10-2 assume !!(main_~i~0 < 100); 15125#L10 [2021-10-28 09:00:46,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:46,838 INFO L85 PathProgramCache]: Analyzing trace with hash 844798583, now seen corresponding path program 49 times [2021-10-28 09:00:46,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:46,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794723543] [2021-10-28 09:00:46,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:46,838 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:46,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:46,859 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:46,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:46,873 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:46,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:46,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 47 times [2021-10-28 09:00:46,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:46,874 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035858133] [2021-10-28 09:00:46,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:46,874 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:46,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:46,996 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:46,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:46,997 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:46,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:46,998 INFO L85 PathProgramCache]: Analyzing trace with hash -166625361, now seen corresponding path program 49 times [2021-10-28 09:00:46,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:46,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576109033] [2021-10-28 09:00:46,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:46,998 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:47,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:48,217 INFO L134 CoverageAnalysis]: Checked inductivity of 2601 backedges. 150 proven. 2450 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:48,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:00:48,218 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576109033] [2021-10-28 09:00:48,218 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [576109033] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:48,218 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1055593092] [2021-10-28 09:00:48,218 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:00:48,218 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:00:48,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:00:48,220 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:00:48,221 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-10-28 09:00:49,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:00:49,185 INFO L263 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 51 conjunts are in the unsatisfiable core [2021-10-28 09:00:49,186 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:00:49,538 INFO L134 CoverageAnalysis]: Checked inductivity of 2601 backedges. 150 proven. 2450 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 09:00:49,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1055593092] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:00:49,538 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:00:49,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2021-10-28 09:00:49,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659262413] [2021-10-28 09:00:49,569 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:00:49,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-10-28 09:00:49,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2021-10-28 09:00:49,572 INFO L87 Difference]: Start difference. First operand 103 states and 105 transitions. cyclomatic complexity: 3 Second operand has 52 states, 52 states have (on average 1.9807692307692308) internal successors, (103), 51 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:49,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:00:49,690 INFO L93 Difference]: Finished difference Result 107 states and 109 transitions. [2021-10-28 09:00:49,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2021-10-28 09:00:49,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 109 transitions. [2021-10-28 09:00:49,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:49,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 106 states and 108 transitions. [2021-10-28 09:00:49,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2021-10-28 09:00:49,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2021-10-28 09:00:49,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 108 transitions. [2021-10-28 09:00:49,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:00:49,692 INFO L681 BuchiCegarLoop]: Abstraction has 106 states and 108 transitions. [2021-10-28 09:00:49,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 108 transitions. [2021-10-28 09:00:49,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2021-10-28 09:00:49,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.019047619047619) internal successors, (107), 104 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:00:49,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 107 transitions. [2021-10-28 09:00:49,695 INFO L704 BuchiCegarLoop]: Abstraction has 105 states and 107 transitions. [2021-10-28 09:00:49,695 INFO L587 BuchiCegarLoop]: Abstraction has 105 states and 107 transitions. [2021-10-28 09:00:49,695 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-10-28 09:00:49,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 107 transitions. [2021-10-28 09:00:49,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 09:00:49,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:00:49,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:00:49,697 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [51, 50, 1] [2021-10-28 09:00:49,697 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2021-10-28 09:00:49,697 INFO L791 eck$LassoCheckResult]: Stem: 15700#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0;havoc main_~i~0;main_~i~0 := 0; 15696#L10-2 assume !!(main_~i~0 < 100); 15697#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15698#L10-2 assume !!(main_~i~0 < 100); 15699#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15703#L10-2 assume !!(main_~i~0 < 100); 15800#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15799#L10-2 assume !!(main_~i~0 < 100); 15798#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15797#L10-2 assume !!(main_~i~0 < 100); 15796#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15795#L10-2 assume !!(main_~i~0 < 100); 15794#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15793#L10-2 assume !!(main_~i~0 < 100); 15792#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15791#L10-2 assume !!(main_~i~0 < 100); 15790#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15789#L10-2 assume !!(main_~i~0 < 100); 15788#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15787#L10-2 assume !!(main_~i~0 < 100); 15786#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15785#L10-2 assume !!(main_~i~0 < 100); 15784#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15783#L10-2 assume !!(main_~i~0 < 100); 15782#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15781#L10-2 assume !!(main_~i~0 < 100); 15780#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15779#L10-2 assume !!(main_~i~0 < 100); 15778#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15777#L10-2 assume !!(main_~i~0 < 100); 15776#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15775#L10-2 assume !!(main_~i~0 < 100); 15774#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15773#L10-2 assume !!(main_~i~0 < 100); 15772#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15771#L10-2 assume !!(main_~i~0 < 100); 15770#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15769#L10-2 assume !!(main_~i~0 < 100); 15768#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15767#L10-2 assume !!(main_~i~0 < 100); 15766#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15765#L10-2 assume !!(main_~i~0 < 100); 15764#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15763#L10-2 assume !!(main_~i~0 < 100); 15762#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15761#L10-2 assume !!(main_~i~0 < 100); 15760#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15759#L10-2 assume !!(main_~i~0 < 100); 15758#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15757#L10-2 assume !!(main_~i~0 < 100); 15756#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15755#L10-2 assume !!(main_~i~0 < 100); 15754#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15753#L10-2 assume !!(main_~i~0 < 100); 15752#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15751#L10-2 assume !!(main_~i~0 < 100); 15750#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15749#L10-2 assume !!(main_~i~0 < 100); 15748#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15747#L10-2 assume !!(main_~i~0 < 100); 15746#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15745#L10-2 assume !!(main_~i~0 < 100); 15744#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15743#L10-2 assume !!(main_~i~0 < 100); 15742#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15741#L10-2 assume !!(main_~i~0 < 100); 15740#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15739#L10-2 assume !!(main_~i~0 < 100); 15738#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15737#L10-2 assume !!(main_~i~0 < 100); 15736#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15735#L10-2 assume !!(main_~i~0 < 100); 15734#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15733#L10-2 assume !!(main_~i~0 < 100); 15732#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15731#L10-2 assume !!(main_~i~0 < 100); 15730#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15729#L10-2 assume !!(main_~i~0 < 100); 15728#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15727#L10-2 assume !!(main_~i~0 < 100); 15726#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15725#L10-2 assume !!(main_~i~0 < 100); 15724#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15723#L10-2 assume !!(main_~i~0 < 100); 15722#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15721#L10-2 assume !!(main_~i~0 < 100); 15720#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15719#L10-2 assume !!(main_~i~0 < 100); 15718#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15717#L10-2 assume !!(main_~i~0 < 100); 15716#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15715#L10-2 assume !!(main_~i~0 < 100); 15714#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15713#L10-2 assume !!(main_~i~0 < 100); 15712#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15711#L10-2 assume !!(main_~i~0 < 100); 15710#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15709#L10-2 assume !!(main_~i~0 < 100); 15707#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15706#L10-2 assume !!(main_~i~0 < 100); 15705#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15704#L10-2 assume !!(main_~i~0 < 100); 15701#L10 [2021-10-28 09:00:49,697 INFO L793 eck$LassoCheckResult]: Loop: 15701#L10 assume !(main_~i~0 < 50);main_~i~0 := main_~i~0 - 1; 15702#L10-2 assume !!(main_~i~0 < 100); 15705#L10 assume main_~i~0 < 50;main_~i~0 := 1 + main_~i~0; 15704#L10-2 assume !!(main_~i~0 < 100); 15701#L10 [2021-10-28 09:00:49,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:49,697 INFO L85 PathProgramCache]: Analyzing trace with hash 102619732, now seen corresponding path program 50 times [2021-10-28 09:00:49,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:49,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946930282] [2021-10-28 09:00:49,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:49,698 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:49,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,718 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:49,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,732 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:49,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:49,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 48 times [2021-10-28 09:00:49,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:49,733 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264350904] [2021-10-28 09:00:49,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:49,733 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:49,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,745 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:49,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,746 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:49,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:00:49,747 INFO L85 PathProgramCache]: Analyzing trace with hash -1270380276, now seen corresponding path program 50 times [2021-10-28 09:00:49,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:00:49,747 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252342848] [2021-10-28 09:00:49,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:00:49,747 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:00:49,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,769 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:00:49,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:00:49,785 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:00:51,232 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 09:00:51 BoogieIcfgContainer [2021-10-28 09:00:51,233 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 09:00:51,234 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 09:00:51,234 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 09:00:51,234 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 09:00:51,235 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:59:40" (3/4) ... [2021-10-28 09:00:51,238 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 09:00:51,312 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/witness.graphml [2021-10-28 09:00:51,313 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 09:00:51,315 INFO L168 Benchmark]: Toolchain (without parser) took 71888.19 ms. Allocated memory was 100.7 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 66.1 MB in the beginning and 460.6 MB in the end (delta: -394.6 MB). Peak memory consumption was 960.7 MB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,315 INFO L168 Benchmark]: CDTParser took 0.38 ms. Allocated memory is still 100.7 MB. Free memory is still 56.9 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:00:51,317 INFO L168 Benchmark]: CACSL2BoogieTranslator took 285.60 ms. Allocated memory is still 100.7 MB. Free memory was 65.9 MB in the beginning and 76.5 MB in the end (delta: -10.6 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,317 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.60 ms. Allocated memory is still 100.7 MB. Free memory was 76.5 MB in the beginning and 75.3 MB in the end (delta: 1.2 MB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:00:51,318 INFO L168 Benchmark]: Boogie Preprocessor took 23.77 ms. Allocated memory is still 100.7 MB. Free memory was 75.3 MB in the beginning and 74.4 MB in the end (delta: 852.1 kB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,318 INFO L168 Benchmark]: RCFGBuilder took 272.44 ms. Allocated memory is still 100.7 MB. Free memory was 74.4 MB in the beginning and 67.2 MB in the end (delta: 7.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,319 INFO L168 Benchmark]: BuchiAutomizer took 71172.33 ms. Allocated memory was 100.7 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 66.9 MB in the beginning and 464.7 MB in the end (delta: -397.9 MB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,326 INFO L168 Benchmark]: Witness Printer took 79.32 ms. Allocated memory is still 1.5 GB. Free memory was 463.8 MB in the beginning and 460.6 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:00:51,329 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.38 ms. Allocated memory is still 100.7 MB. Free memory is still 56.9 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 285.60 ms. Allocated memory is still 100.7 MB. Free memory was 65.9 MB in the beginning and 76.5 MB in the end (delta: -10.6 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 38.60 ms. Allocated memory is still 100.7 MB. Free memory was 76.5 MB in the beginning and 75.3 MB in the end (delta: 1.2 MB). There was no memory consumed. Max. memory is 16.1 GB. * Boogie Preprocessor took 23.77 ms. Allocated memory is still 100.7 MB. Free memory was 75.3 MB in the beginning and 74.4 MB in the end (delta: 852.1 kB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 272.44 ms. Allocated memory is still 100.7 MB. Free memory was 74.4 MB in the beginning and 67.2 MB in the end (delta: 7.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 71172.33 ms. Allocated memory was 100.7 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 66.9 MB in the beginning and 464.7 MB in the end (delta: -397.9 MB). Peak memory consumption was 1.1 GB. Max. memory is 16.1 GB. * Witness Printer took 79.32 ms. Allocated memory is still 1.5 GB. Free memory was 463.8 MB in the beginning and 460.6 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 54 terminating modules (50 trivial, 2 deterministic, 2 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -2 * i + 99 and consists of 4 locations. One deterministic module has affine ranking function -2 * i + 99 and consists of 3 locations. One nondeterministic module has affine ranking function -2 * i + 99 and consists of 3 locations. One nondeterministic module has affine ranking function i and consists of 3 locations. 50 modules have a trivial ranking function, the largest among these consists of 52 locations. The remainder module has 105 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 71.0s and 52 iterations. TraceHistogramMax:51. Analysis of lassos took 65.2s. Construction of modules took 2.6s. Büchi inclusion checks took 2.4s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 54. Automata minimization 0.2s AutomataMinimizationTime, 54 MinimizatonAttempts, 58 StatesRemovedByMinimization, 52 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 105 states and ocurred in iteration 51. Nontrivial modules had stage [2, 0, 2, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 128 SDtfs, 29 SDslu, 3 SDs, 0 SdLazy, 2875 SolverSat, 175 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.6s Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc47 concLT1 SILN0 SILU0 SILI0 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital10 mio100 ax213 hnf100 lsp47 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq156 hnf93 smp100 dnf100 smp100 tf112 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 54ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.8s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 10]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, i=50} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 10]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] i = 0 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 Loop: [L10] COND FALSE !(i < 50) [L11] i = i-1 [L9] COND TRUE i < 100 [L10] COND TRUE i < 50 [L10] i = i+1 [L9] COND TRUE i < 100 End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 09:00:51,424 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:51,613 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Ended with exit code 0 [2021-10-28 09:00:51,812 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:52,011 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2021-10-28 09:00:52,211 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Ended with exit code 0 [2021-10-28 09:00:52,411 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2021-10-28 09:00:52,611 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2021-10-28 09:00:52,812 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2021-10-28 09:00:53,012 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:53,212 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:53,412 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2021-10-28 09:00:53,611 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Ended with exit code 0 [2021-10-28 09:00:53,811 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2021-10-28 09:00:54,012 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2021-10-28 09:00:54,214 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:54,413 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2021-10-28 09:00:54,612 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Ended with exit code 0 [2021-10-28 09:00:54,813 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:55,013 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Ended with exit code 0 [2021-10-28 09:00:55,213 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2021-10-28 09:00:55,413 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2021-10-28 09:00:55,639 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:55,813 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2021-10-28 09:00:56,013 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Ended with exit code 0 [2021-10-28 09:00:56,213 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2021-10-28 09:00:56,414 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2021-10-28 09:00:56,614 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2021-10-28 09:00:56,814 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:57,016 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2021-10-28 09:00:57,214 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Ended with exit code 0 [2021-10-28 09:00:57,415 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2021-10-28 09:00:57,615 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2021-10-28 09:00:57,815 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:58,017 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:58,216 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:58,415 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:58,615 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:58,815 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2021-10-28 09:00:59,016 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2021-10-28 09:00:59,217 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2021-10-28 09:00:59,415 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2021-10-28 09:00:59,616 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2021-10-28 09:00:59,816 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2021-10-28 09:01:00,017 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2021-10-28 09:01:00,216 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2021-10-28 09:01:00,416 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2021-10-28 09:01:00,616 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2021-10-28 09:01:00,817 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2021-10-28 09:01:01,018 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2021-10-28 09:01:01,222 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2b8f111d-9b9c-4ca9-8872-50cf3f14385f/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...