./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-memory-alloca/java_Continue1-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-memory-alloca/java_Continue1-alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 337340cdf38da99928295b0c576766fb8f09c8634f9763511165b0f7240edd89 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 09:12:25,990 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 09:12:25,994 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 09:12:26,060 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 09:12:26,061 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 09:12:26,067 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 09:12:26,069 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 09:12:26,074 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 09:12:26,077 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 09:12:26,084 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 09:12:26,085 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 09:12:26,087 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 09:12:26,088 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 09:12:26,091 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 09:12:26,093 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 09:12:26,100 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 09:12:26,104 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 09:12:26,105 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 09:12:26,108 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 09:12:26,120 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 09:12:26,122 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 09:12:26,125 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 09:12:26,129 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 09:12:26,130 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 09:12:26,141 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 09:12:26,141 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 09:12:26,142 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 09:12:26,144 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 09:12:26,145 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 09:12:26,147 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 09:12:26,147 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 09:12:26,148 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 09:12:26,151 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 09:12:26,152 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 09:12:26,154 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 09:12:26,154 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 09:12:26,155 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 09:12:26,155 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 09:12:26,155 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 09:12:26,157 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 09:12:26,157 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 09:12:26,158 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-10-28 09:12:26,215 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 09:12:26,215 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 09:12:26,216 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 09:12:26,216 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 09:12:26,218 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 09:12:26,218 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 09:12:26,218 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 09:12:26,218 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 09:12:26,219 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 09:12:26,219 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 09:12:26,220 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 09:12:26,221 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 09:12:26,221 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 09:12:26,221 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 09:12:26,221 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 09:12:26,222 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 09:12:26,222 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 09:12:26,222 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 09:12:26,222 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 09:12:26,222 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 09:12:26,223 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 09:12:26,223 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 09:12:26,223 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 09:12:26,223 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 09:12:26,224 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 09:12:26,224 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 09:12:26,226 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 09:12:26,227 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 09:12:26,227 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 09:12:26,228 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 09:12:26,229 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 337340cdf38da99928295b0c576766fb8f09c8634f9763511165b0f7240edd89 [2021-10-28 09:12:26,589 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 09:12:26,632 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 09:12:26,635 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 09:12:26,637 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 09:12:26,638 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 09:12:26,639 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/termination-memory-alloca/java_Continue1-alloca.i [2021-10-28 09:12:26,719 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/data/733e1ba66/81967e4e04cb464ca3eae3df9ffdd424/FLAGdf77f1867 [2021-10-28 09:12:27,420 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 09:12:27,423 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/sv-benchmarks/c/termination-memory-alloca/java_Continue1-alloca.i [2021-10-28 09:12:27,450 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/data/733e1ba66/81967e4e04cb464ca3eae3df9ffdd424/FLAGdf77f1867 [2021-10-28 09:12:27,628 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/data/733e1ba66/81967e4e04cb464ca3eae3df9ffdd424 [2021-10-28 09:12:27,632 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 09:12:27,635 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 09:12:27,640 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 09:12:27,640 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 09:12:27,644 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 09:12:27,645 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:12:27" (1/1) ... [2021-10-28 09:12:27,647 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ade788d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:27, skipping insertion in model container [2021-10-28 09:12:27,648 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:12:27" (1/1) ... [2021-10-28 09:12:27,657 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 09:12:27,722 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 09:12:28,118 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:12:28,131 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 09:12:28,200 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:12:28,237 INFO L208 MainTranslator]: Completed translation [2021-10-28 09:12:28,238 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28 WrapperNode [2021-10-28 09:12:28,238 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 09:12:28,239 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 09:12:28,239 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 09:12:28,239 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 09:12:28,250 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,284 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,313 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 09:12:28,315 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 09:12:28,315 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 09:12:28,315 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 09:12:28,324 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,325 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,351 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,352 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,356 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,360 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,364 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,374 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 09:12:28,375 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 09:12:28,375 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 09:12:28,376 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 09:12:28,380 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (1/1) ... [2021-10-28 09:12:28,389 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:28,403 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:28,421 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:28,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 09:12:28,483 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-10-28 09:12:28,484 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-10-28 09:12:28,484 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 09:12:28,484 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-10-28 09:12:28,485 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 09:12:28,485 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 09:12:28,792 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 09:12:28,792 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2021-10-28 09:12:28,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:12:28 BoogieIcfgContainer [2021-10-28 09:12:28,794 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 09:12:28,795 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 09:12:28,796 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 09:12:28,799 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 09:12:28,800 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:12:28,800 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 09:12:27" (1/3) ... [2021-10-28 09:12:28,802 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3fc8728f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:12:28, skipping insertion in model container [2021-10-28 09:12:28,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:12:28,803 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:12:28" (2/3) ... [2021-10-28 09:12:28,803 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3fc8728f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:12:28, skipping insertion in model container [2021-10-28 09:12:28,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:12:28,804 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:12:28" (3/3) ... [2021-10-28 09:12:28,805 INFO L389 chiAutomizerObserver]: Analyzing ICFG java_Continue1-alloca.i [2021-10-28 09:12:28,854 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 09:12:28,854 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 09:12:28,855 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 09:12:28,855 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 09:12:28,855 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 09:12:28,855 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 09:12:28,855 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 09:12:28,855 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 09:12:28,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.3333333333333333) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:28,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:28,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:28,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:28,931 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-10-28 09:12:28,931 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:28,931 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 09:12:28,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.3333333333333333) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:28,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:28,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:28,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:28,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-10-28 09:12:28,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:28,941 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 9#L-1true havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 5#L552-3true [2021-10-28 09:12:28,942 INFO L793 eck$LassoCheckResult]: Loop: 5#L552-3true goto; 8#L554-1true call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 10#L552-1true assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 11#L554true assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 5#L552-3true [2021-10-28 09:12:28,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:28,949 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-10-28 09:12:28,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:28,960 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665913409] [2021-10-28 09:12:28,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:28,961 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,089 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:29,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,176 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:29,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:29,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1109383, now seen corresponding path program 1 times [2021-10-28 09:12:29,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:29,181 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539820307] [2021-10-28 09:12:29,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:29,182 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,222 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:29,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,257 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:29,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:29,259 INFO L85 PathProgramCache]: Analyzing trace with hash 889536585, now seen corresponding path program 1 times [2021-10-28 09:12:29,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:29,260 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578945212] [2021-10-28 09:12:29,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:29,261 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:29,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:29,508 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:29,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578945212] [2021-10-28 09:12:29,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578945212] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:12:29,512 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:12:29,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:12:29,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429117990] [2021-10-28 09:12:29,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:29,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:12:29,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:12:29,740 INFO L87 Difference]: Start difference. First operand has 10 states, 9 states have (on average 1.3333333333333333) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 4 states have (on average 1.5) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:29,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:29,785 INFO L93 Difference]: Finished difference Result 14 states and 15 transitions. [2021-10-28 09:12:29,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:12:29,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 15 transitions. [2021-10-28 09:12:29,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:29,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 10 states and 11 transitions. [2021-10-28 09:12:29,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-10-28 09:12:29,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2021-10-28 09:12:29,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 11 transitions. [2021-10-28 09:12:29,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:12:29,800 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-10-28 09:12:29,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 11 transitions. [2021-10-28 09:12:29,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-10-28 09:12:29,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.1) internal successors, (11), 9 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:29,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 11 transitions. [2021-10-28 09:12:29,832 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-10-28 09:12:29,832 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-10-28 09:12:29,832 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 09:12:29,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 11 transitions. [2021-10-28 09:12:29,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:29,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:29,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:29,835 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-10-28 09:12:29,836 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-10-28 09:12:29,836 INFO L791 eck$LassoCheckResult]: Stem: 39#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 40#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 37#L552-3 goto; 38#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 41#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 42#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 43#L554-1 [2021-10-28 09:12:29,836 INFO L793 eck$LassoCheckResult]: Loop: 43#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 46#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 44#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 43#L554-1 [2021-10-28 09:12:29,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:29,838 INFO L85 PathProgramCache]: Analyzing trace with hash 889536583, now seen corresponding path program 1 times [2021-10-28 09:12:29,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:29,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167509111] [2021-10-28 09:12:29,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:29,839 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,881 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:29,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,916 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:29,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:29,918 INFO L85 PathProgramCache]: Analyzing trace with hash 36905, now seen corresponding path program 1 times [2021-10-28 09:12:29,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:29,918 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434084467] [2021-10-28 09:12:29,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:29,919 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,927 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:29,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,936 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:29,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:29,937 INFO L85 PathProgramCache]: Analyzing trace with hash 236134947, now seen corresponding path program 2 times [2021-10-28 09:12:29,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:29,938 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069096538] [2021-10-28 09:12:29,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:29,939 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:29,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,959 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:29,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:29,992 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:30,548 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 09:12:30,549 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 09:12:30,549 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 09:12:30,549 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 09:12:30,549 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 09:12:30,549 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:30,550 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 09:12:30,550 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 09:12:30,550 INFO L133 ssoRankerPreferences]: Filename of dumped script: java_Continue1-alloca.i_Iteration2_Lasso [2021-10-28 09:12:30,550 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 09:12:30,550 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 09:12:30,570 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,780 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,784 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,788 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,791 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,796 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,800 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,803 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,806 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,810 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,812 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,820 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,822 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:30,825 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:31,208 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 09:12:31,213 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 09:12:31,215 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:31,215 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:31,217 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:31,222 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-10-28 09:12:31,222 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:31,231 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:31,231 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:31,231 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:31,231 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:31,237 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:31,237 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:31,252 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:31,291 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2021-10-28 09:12:31,292 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:31,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:31,296 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:31,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-10-28 09:12:31,303 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:31,313 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:31,313 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:31,313 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:31,313 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:31,324 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:31,324 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:31,339 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:31,364 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:31,365 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:31,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:31,371 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:31,372 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-10-28 09:12:31,373 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:31,385 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:31,386 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:31,386 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:31,386 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:31,389 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:31,390 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:31,439 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 09:12:31,454 INFO L443 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2021-10-28 09:12:31,454 INFO L444 ModelExtractionUtils]: 0 out of 7 variables were initially zero. Simplification set additionally 4 variables to zero. [2021-10-28 09:12:31,456 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:31,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:31,472 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:31,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-10-28 09:12:31,544 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 09:12:31,575 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-10-28 09:12:31,576 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 09:12:31,576 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select (select #memory_int ULTIMATE.start_main_~i~0.base) ULTIMATE.start_main_~i~0.offset)_1) = -2*v_rep(select (select #memory_int ULTIMATE.start_main_~i~0.base) ULTIMATE.start_main_~i~0.offset)_1 + 19 Supporting invariants [] [2021-10-28 09:12:31,614 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:31,648 INFO L297 tatePredicateManager]: 10 out of 10 supporting invariants were superfluous and have been removed [2021-10-28 09:12:31,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:31,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:31,723 INFO L263 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 09:12:31,725 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:31,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:31,772 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 09:12:31,773 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:31,843 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 17 [2021-10-28 09:12:31,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:31,863 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 09:12:31,864 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 10 states and 11 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:31,927 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 10 states and 11 transitions. cyclomatic complexity: 2. Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 17 states and 20 transitions. Complement of second has 6 states. [2021-10-28 09:12:31,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-10-28 09:12:31,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:31,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 12 transitions. [2021-10-28 09:12:31,929 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 6 letters. Loop has 3 letters. [2021-10-28 09:12:31,930 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:31,930 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 9 letters. Loop has 3 letters. [2021-10-28 09:12:31,931 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:31,931 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 6 letters. Loop has 6 letters. [2021-10-28 09:12:31,931 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:31,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 20 transitions. [2021-10-28 09:12:31,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:31,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 17 states and 20 transitions. [2021-10-28 09:12:31,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:31,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-10-28 09:12:31,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 20 transitions. [2021-10-28 09:12:31,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:31,935 INFO L681 BuchiCegarLoop]: Abstraction has 17 states and 20 transitions. [2021-10-28 09:12:31,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 20 transitions. [2021-10-28 09:12:31,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2021-10-28 09:12:31,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.1875) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:31,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 19 transitions. [2021-10-28 09:12:31,937 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-10-28 09:12:31,937 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-10-28 09:12:31,937 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 09:12:31,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 19 transitions. [2021-10-28 09:12:31,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:31,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:31,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:31,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1] [2021-10-28 09:12:31,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:31,940 INFO L791 eck$LassoCheckResult]: Stem: 158#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 159#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 162#L552-3 goto; 169#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 168#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 167#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 166#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 160#L552-1 [2021-10-28 09:12:31,940 INFO L793 eck$LassoCheckResult]: Loop: 160#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 163#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 154#L552-3 goto; 155#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 160#L552-1 [2021-10-28 09:12:31,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:31,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1805830304, now seen corresponding path program 3 times [2021-10-28 09:12:31,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:31,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755853278] [2021-10-28 09:12:31,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:31,941 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:31,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:31,959 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:31,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:31,978 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:31,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:31,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 2 times [2021-10-28 09:12:31,979 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:31,979 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411282213] [2021-10-28 09:12:31,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:31,979 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:31,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:31,987 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:31,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:31,997 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:31,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:31,998 INFO L85 PathProgramCache]: Analyzing trace with hash -707580506, now seen corresponding path program 1 times [2021-10-28 09:12:31,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:31,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119677234] [2021-10-28 09:12:31,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:31,999 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:32,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:32,148 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2021-10-28 09:12:32,203 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:32,204 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:32,204 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119677234] [2021-10-28 09:12:32,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119677234] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:32,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [925238448] [2021-10-28 09:12:32,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:32,207 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:32,207 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:32,208 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:32,219 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2021-10-28 09:12:32,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:32,274 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 13 conjunts are in the unsatisfiable core [2021-10-28 09:12:32,275 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:32,307 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:32,308 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:32,378 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:32,449 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:32,458 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:32,459 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [925238448] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:32,459 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:32,459 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 9 [2021-10-28 09:12:32,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35859829] [2021-10-28 09:12:32,588 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:32,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-10-28 09:12:32,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2021-10-28 09:12:32,589 INFO L87 Difference]: Start difference. First operand 16 states and 19 transitions. cyclomatic complexity: 5 Second operand has 9 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:32,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:32,678 INFO L93 Difference]: Finished difference Result 20 states and 22 transitions. [2021-10-28 09:12:32,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 09:12:32,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 22 transitions. [2021-10-28 09:12:32,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:32,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 18 states and 20 transitions. [2021-10-28 09:12:32,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:32,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:32,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 20 transitions. [2021-10-28 09:12:32,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:32,683 INFO L681 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2021-10-28 09:12:32,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 20 transitions. [2021-10-28 09:12:32,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2021-10-28 09:12:32,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.1111111111111112) internal successors, (20), 17 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:32,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 20 transitions. [2021-10-28 09:12:32,686 INFO L704 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2021-10-28 09:12:32,686 INFO L587 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2021-10-28 09:12:32,686 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 09:12:32,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 20 transitions. [2021-10-28 09:12:32,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:32,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:32,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:32,692 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 2, 1, 1, 1] [2021-10-28 09:12:32,693 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:32,693 INFO L791 eck$LassoCheckResult]: Stem: 242#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 243#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 247#L552-3 goto; 255#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 254#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 253#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 244#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 245#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 250#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 251#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 248#L552-1 [2021-10-28 09:12:32,693 INFO L793 eck$LassoCheckResult]: Loop: 248#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 249#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 238#L552-3 goto; 239#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 248#L552-1 [2021-10-28 09:12:32,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:32,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1269751228, now seen corresponding path program 4 times [2021-10-28 09:12:32,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:32,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827372272] [2021-10-28 09:12:32,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:32,695 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:32,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:32,744 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:32,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:32,764 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:32,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:32,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 3 times [2021-10-28 09:12:32,765 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:32,766 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635786220] [2021-10-28 09:12:32,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:32,766 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:32,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:32,773 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:32,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:32,791 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:32,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:32,792 INFO L85 PathProgramCache]: Analyzing trace with hash 112465226, now seen corresponding path program 2 times [2021-10-28 09:12:32,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:32,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242272986] [2021-10-28 09:12:32,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:32,793 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:32,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:32,971 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:32,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:32,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242272986] [2021-10-28 09:12:32,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242272986] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:32,973 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1754018741] [2021-10-28 09:12:32,973 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:12:32,973 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:32,973 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:32,974 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:32,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2021-10-28 09:12:33,046 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:12:33,047 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:33,051 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 09:12:33,052 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:33,080 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:33,081 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:33,148 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:33,193 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:33,242 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:33,250 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:33,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1754018741] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:33,258 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:33,258 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 6] total 12 [2021-10-28 09:12:33,259 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937564842] [2021-10-28 09:12:33,375 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:33,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-10-28 09:12:33,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2021-10-28 09:12:33,377 INFO L87 Difference]: Start difference. First operand 18 states and 20 transitions. cyclomatic complexity: 4 Second operand has 12 states, 12 states have (on average 2.0) internal successors, (24), 12 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:33,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:33,485 INFO L93 Difference]: Finished difference Result 23 states and 25 transitions. [2021-10-28 09:12:33,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-10-28 09:12:33,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 25 transitions. [2021-10-28 09:12:33,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:33,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 21 states and 23 transitions. [2021-10-28 09:12:33,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:33,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:33,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 23 transitions. [2021-10-28 09:12:33,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:33,489 INFO L681 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-28 09:12:33,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 23 transitions. [2021-10-28 09:12:33,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2021-10-28 09:12:33,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.0952380952380953) internal successors, (23), 20 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:33,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 23 transitions. [2021-10-28 09:12:33,492 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-28 09:12:33,492 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2021-10-28 09:12:33,492 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 09:12:33,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 23 transitions. [2021-10-28 09:12:33,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:33,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:33,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:33,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 3, 1, 1, 1] [2021-10-28 09:12:33,494 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:33,495 INFO L791 eck$LassoCheckResult]: Stem: 345#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 346#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 351#L552-3 goto; 361#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 360#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 359#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 347#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 348#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 354#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 349#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 350#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 358#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 356#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 352#L552-1 [2021-10-28 09:12:33,495 INFO L793 eck$LassoCheckResult]: Loop: 352#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 353#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 341#L552-3 goto; 342#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 352#L552-1 [2021-10-28 09:12:33,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:33,495 INFO L85 PathProgramCache]: Analyzing trace with hash -1381845472, now seen corresponding path program 5 times [2021-10-28 09:12:33,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:33,496 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544459828] [2021-10-28 09:12:33,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:33,496 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:33,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:33,511 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:33,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:33,540 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:33,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:33,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 4 times [2021-10-28 09:12:33,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:33,542 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128272141] [2021-10-28 09:12:33,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:33,546 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:33,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:33,555 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:33,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:33,572 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:33,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:33,573 INFO L85 PathProgramCache]: Analyzing trace with hash 320887590, now seen corresponding path program 3 times [2021-10-28 09:12:33,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:33,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791653244] [2021-10-28 09:12:33,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:33,574 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:33,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:33,742 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 5 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:33,742 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:33,742 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791653244] [2021-10-28 09:12:33,742 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791653244] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:33,743 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1250938621] [2021-10-28 09:12:33,743 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:12:33,743 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:33,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:33,792 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:33,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2021-10-28 09:12:33,893 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-10-28 09:12:33,893 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:33,895 INFO L263 TraceCheckSpWp]: Trace formula consists of 112 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 09:12:33,897 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:33,926 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:33,927 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:34,008 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:34,057 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:34,104 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:34,165 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:34,178 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 5 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:34,179 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1250938621] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:34,179 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:34,179 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 15 [2021-10-28 09:12:34,183 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003311095] [2021-10-28 09:12:34,300 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:34,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-10-28 09:12:34,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2021-10-28 09:12:34,302 INFO L87 Difference]: Start difference. First operand 21 states and 23 transitions. cyclomatic complexity: 4 Second operand has 15 states, 15 states have (on average 2.0) internal successors, (30), 15 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:34,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:34,463 INFO L93 Difference]: Finished difference Result 26 states and 28 transitions. [2021-10-28 09:12:34,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:12:34,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 28 transitions. [2021-10-28 09:12:34,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:34,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 24 states and 26 transitions. [2021-10-28 09:12:34,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:34,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:34,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 26 transitions. [2021-10-28 09:12:34,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:34,469 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2021-10-28 09:12:34,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 26 transitions. [2021-10-28 09:12:34,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2021-10-28 09:12:34,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.0833333333333333) internal successors, (26), 23 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:34,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 26 transitions. [2021-10-28 09:12:34,476 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2021-10-28 09:12:34,476 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2021-10-28 09:12:34,476 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 09:12:34,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 26 transitions. [2021-10-28 09:12:34,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:34,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:34,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:34,479 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 4, 1, 1, 1] [2021-10-28 09:12:34,479 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:34,479 INFO L791 eck$LassoCheckResult]: Stem: 468#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 469#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 474#L552-3 goto; 484#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 483#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 478#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 470#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 471#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 487#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 472#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 473#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 477#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 479#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 486#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 485#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 481#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 475#L552-1 [2021-10-28 09:12:34,479 INFO L793 eck$LassoCheckResult]: Loop: 475#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 476#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 464#L552-3 goto; 465#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 475#L552-1 [2021-10-28 09:12:34,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:34,480 INFO L85 PathProgramCache]: Analyzing trace with hash 703087812, now seen corresponding path program 6 times [2021-10-28 09:12:34,480 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:34,480 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027294057] [2021-10-28 09:12:34,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:34,481 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:34,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:34,496 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:34,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:34,519 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:34,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:34,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 5 times [2021-10-28 09:12:34,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:34,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458297016] [2021-10-28 09:12:34,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:34,526 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:34,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:34,534 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:34,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:34,548 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:34,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:34,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1091176502, now seen corresponding path program 4 times [2021-10-28 09:12:34,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:34,550 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560690583] [2021-10-28 09:12:34,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:34,550 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:34,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:34,790 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:34,790 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:34,791 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560690583] [2021-10-28 09:12:34,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560690583] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:34,791 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1286504839] [2021-10-28 09:12:34,791 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 09:12:34,791 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:34,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:34,795 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:34,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-10-28 09:12:34,898 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 09:12:34,898 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:34,900 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 09:12:34,902 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:34,926 INFO L354 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2021-10-28 09:12:34,926 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 23 [2021-10-28 09:12:34,932 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-10-28 09:12:35,047 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:35,047 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:35,146 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:35,147 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:35,250 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:35,251 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:35,340 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:35,341 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:35,454 INFO L354 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2021-10-28 09:12:35,455 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 16 [2021-10-28 09:12:35,463 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:35,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1286504839] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:35,463 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:35,464 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 18 [2021-10-28 09:12:35,467 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753622074] [2021-10-28 09:12:35,553 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:35,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-10-28 09:12:35,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=223, Unknown=0, NotChecked=0, Total=306 [2021-10-28 09:12:35,554 INFO L87 Difference]: Start difference. First operand 24 states and 26 transitions. cyclomatic complexity: 4 Second operand has 18 states, 18 states have (on average 2.0) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:35,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:35,765 INFO L93 Difference]: Finished difference Result 29 states and 31 transitions. [2021-10-28 09:12:35,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-10-28 09:12:35,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 31 transitions. [2021-10-28 09:12:35,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:35,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 27 states and 29 transitions. [2021-10-28 09:12:35,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:35,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:35,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 29 transitions. [2021-10-28 09:12:35,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:35,768 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-28 09:12:35,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 29 transitions. [2021-10-28 09:12:35,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2021-10-28 09:12:35,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.0740740740740742) internal successors, (29), 26 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:35,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 29 transitions. [2021-10-28 09:12:35,771 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-28 09:12:35,771 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2021-10-28 09:12:35,771 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 09:12:35,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 29 transitions. [2021-10-28 09:12:35,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:35,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:35,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:35,773 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 5, 1, 1, 1] [2021-10-28 09:12:35,773 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:35,774 INFO L791 eck$LassoCheckResult]: Stem: 611#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 612#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 617#L552-3 goto; 626#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 625#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 621#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 613#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 614#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 620#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 615#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 616#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 633#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 632#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 631#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 630#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 629#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 628#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 627#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 623#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 618#L552-1 [2021-10-28 09:12:35,774 INFO L793 eck$LassoCheckResult]: Loop: 618#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 619#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 607#L552-3 goto; 608#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 618#L552-1 [2021-10-28 09:12:35,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:35,774 INFO L85 PathProgramCache]: Analyzing trace with hash -866483296, now seen corresponding path program 7 times [2021-10-28 09:12:35,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:35,775 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302998261] [2021-10-28 09:12:35,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:35,775 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:35,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:35,787 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:35,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:35,802 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:35,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:35,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 6 times [2021-10-28 09:12:35,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:35,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990051808] [2021-10-28 09:12:35,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:35,804 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:35,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:35,808 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:35,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:35,813 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:35,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:35,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1312123046, now seen corresponding path program 5 times [2021-10-28 09:12:35,814 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:35,814 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927522264] [2021-10-28 09:12:35,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:35,815 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:35,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:36,008 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 7 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:36,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:36,008 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927522264] [2021-10-28 09:12:36,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927522264] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:36,009 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [607337787] [2021-10-28 09:12:36,009 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 09:12:36,009 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:36,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:36,010 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:36,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-10-28 09:12:36,144 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2021-10-28 09:12:36,144 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:36,146 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 17 conjunts are in the unsatisfiable core [2021-10-28 09:12:36,148 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:36,170 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:36,170 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:36,229 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:36,271 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:36,313 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:36,363 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:36,412 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:36,464 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:36,474 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 7 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:36,474 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [607337787] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:36,475 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:36,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 9] total 21 [2021-10-28 09:12:36,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103674180] [2021-10-28 09:12:36,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:36,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-28 09:12:36,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=309, Unknown=0, NotChecked=0, Total=420 [2021-10-28 09:12:36,588 INFO L87 Difference]: Start difference. First operand 27 states and 29 transitions. cyclomatic complexity: 4 Second operand has 21 states, 21 states have (on average 2.0) internal successors, (42), 21 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:36,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:36,835 INFO L93 Difference]: Finished difference Result 32 states and 34 transitions. [2021-10-28 09:12:36,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-10-28 09:12:36,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 34 transitions. [2021-10-28 09:12:36,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:36,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 30 states and 32 transitions. [2021-10-28 09:12:36,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:36,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:36,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 32 transitions. [2021-10-28 09:12:36,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:36,838 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2021-10-28 09:12:36,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 32 transitions. [2021-10-28 09:12:36,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2021-10-28 09:12:36,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.0666666666666667) internal successors, (32), 29 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:36,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2021-10-28 09:12:36,842 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2021-10-28 09:12:36,842 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2021-10-28 09:12:36,842 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 09:12:36,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 32 transitions. [2021-10-28 09:12:36,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:36,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:36,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:36,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 6, 1, 1, 1] [2021-10-28 09:12:36,844 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:36,844 INFO L791 eck$LassoCheckResult]: Stem: 770#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 771#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 780#L552-3 goto; 790#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 789#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 784#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 776#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 777#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 799#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 778#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 779#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 783#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 785#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 798#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 797#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 796#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 795#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 794#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 793#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 792#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 791#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 787#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 781#L552-1 [2021-10-28 09:12:36,844 INFO L793 eck$LassoCheckResult]: Loop: 781#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 782#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 772#L552-3 goto; 773#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 781#L552-1 [2021-10-28 09:12:36,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:36,845 INFO L85 PathProgramCache]: Analyzing trace with hash -650410172, now seen corresponding path program 8 times [2021-10-28 09:12:36,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:36,845 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161206375] [2021-10-28 09:12:36,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:36,845 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:36,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:36,861 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:36,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:36,903 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:36,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:36,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 7 times [2021-10-28 09:12:36,904 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:36,905 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833220884] [2021-10-28 09:12:36,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:36,905 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:36,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:36,912 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:36,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:36,918 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:36,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:36,924 INFO L85 PathProgramCache]: Analyzing trace with hash 904133194, now seen corresponding path program 6 times [2021-10-28 09:12:36,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:36,924 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034738160] [2021-10-28 09:12:36,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:36,925 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:36,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:37,191 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 8 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:37,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:37,192 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034738160] [2021-10-28 09:12:37,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034738160] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:37,193 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1576653926] [2021-10-28 09:12:37,193 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 09:12:37,193 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:37,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:37,219 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:37,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-10-28 09:12:37,406 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-10-28 09:12:37,406 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:37,408 INFO L263 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 18 conjunts are in the unsatisfiable core [2021-10-28 09:12:37,410 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:37,437 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:37,438 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:37,492 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,532 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,572 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,617 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,653 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,692 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:37,736 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:37,744 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 8 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:37,744 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1576653926] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:37,744 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:37,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 10] total 24 [2021-10-28 09:12:37,745 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385992105] [2021-10-28 09:12:37,846 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:37,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-10-28 09:12:37,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=409, Unknown=0, NotChecked=0, Total=552 [2021-10-28 09:12:37,847 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. cyclomatic complexity: 4 Second operand has 24 states, 24 states have (on average 2.0) internal successors, (48), 24 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:38,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:38,144 INFO L93 Difference]: Finished difference Result 35 states and 37 transitions. [2021-10-28 09:12:38,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-10-28 09:12:38,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 37 transitions. [2021-10-28 09:12:38,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:38,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 33 states and 35 transitions. [2021-10-28 09:12:38,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:38,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:38,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 35 transitions. [2021-10-28 09:12:38,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:38,147 INFO L681 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-28 09:12:38,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 35 transitions. [2021-10-28 09:12:38,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2021-10-28 09:12:38,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.0606060606060606) internal successors, (35), 32 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:38,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2021-10-28 09:12:38,151 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-28 09:12:38,151 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2021-10-28 09:12:38,152 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 09:12:38,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 35 transitions. [2021-10-28 09:12:38,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:38,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:38,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:38,154 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 7, 1, 1, 1] [2021-10-28 09:12:38,154 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:38,154 INFO L791 eck$LassoCheckResult]: Stem: 953#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 954#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 963#L552-3 goto; 972#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 971#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 967#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 959#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 960#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 966#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 961#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 962#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 985#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 984#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 983#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 982#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 981#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 980#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 979#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 978#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 977#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 976#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 975#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 974#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 973#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 969#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 964#L552-1 [2021-10-28 09:12:38,154 INFO L793 eck$LassoCheckResult]: Loop: 964#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 965#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 955#L552-3 goto; 956#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 964#L552-1 [2021-10-28 09:12:38,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:38,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1771949792, now seen corresponding path program 9 times [2021-10-28 09:12:38,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:38,155 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039790893] [2021-10-28 09:12:38,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:38,156 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:38,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:38,172 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:38,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:38,192 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:38,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:38,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 8 times [2021-10-28 09:12:38,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:38,194 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76438257] [2021-10-28 09:12:38,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:38,194 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:38,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:38,200 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:38,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:38,205 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:38,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:38,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1235899942, now seen corresponding path program 7 times [2021-10-28 09:12:38,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:38,206 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300789947] [2021-10-28 09:12:38,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:38,207 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:38,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:38,528 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 9 proven. 84 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:38,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:38,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300789947] [2021-10-28 09:12:38,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300789947] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:38,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2052495050] [2021-10-28 09:12:38,528 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:12:38,529 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:38,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:38,531 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:38,551 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-10-28 09:12:38,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:38,698 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 09:12:38,700 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:38,729 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:38,730 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:38,780 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:38,823 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:38,875 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:38,922 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:38,976 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:39,023 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:39,075 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:39,131 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:39,140 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 9 proven. 84 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:39,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2052495050] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:39,141 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:39,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 11] total 27 [2021-10-28 09:12:39,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550326577] [2021-10-28 09:12:39,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:39,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-10-28 09:12:39,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=523, Unknown=0, NotChecked=0, Total=702 [2021-10-28 09:12:39,255 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. cyclomatic complexity: 4 Second operand has 27 states, 27 states have (on average 2.0) internal successors, (54), 27 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:39,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:39,624 INFO L93 Difference]: Finished difference Result 38 states and 40 transitions. [2021-10-28 09:12:39,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-10-28 09:12:39,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 40 transitions. [2021-10-28 09:12:39,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:39,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 36 states and 38 transitions. [2021-10-28 09:12:39,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:39,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:39,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 38 transitions. [2021-10-28 09:12:39,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:39,627 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2021-10-28 09:12:39,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 38 transitions. [2021-10-28 09:12:39,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2021-10-28 09:12:39,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.0555555555555556) internal successors, (38), 35 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:39,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2021-10-28 09:12:39,630 INFO L704 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2021-10-28 09:12:39,630 INFO L587 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2021-10-28 09:12:39,630 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 09:12:39,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 38 transitions. [2021-10-28 09:12:39,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:39,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:39,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:39,632 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 8, 1, 1, 1] [2021-10-28 09:12:39,632 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:39,633 INFO L791 eck$LassoCheckResult]: Stem: 1160#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1161#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 1166#L552-3 goto; 1176#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1175#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1170#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1162#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1163#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1191#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1164#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1165#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1169#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1171#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1190#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1189#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1188#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1187#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1186#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1185#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1184#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1183#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1182#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1181#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1180#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1179#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1178#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1177#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1173#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1167#L552-1 [2021-10-28 09:12:39,633 INFO L793 eck$LassoCheckResult]: Loop: 1167#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1168#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 1156#L552-3 goto; 1157#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1167#L552-1 [2021-10-28 09:12:39,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:39,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1286793668, now seen corresponding path program 10 times [2021-10-28 09:12:39,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:39,633 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801336048] [2021-10-28 09:12:39,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:39,634 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:39,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:39,657 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:39,700 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:39,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:39,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 9 times [2021-10-28 09:12:39,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:39,702 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859634750] [2021-10-28 09:12:39,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:39,702 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:39,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:39,709 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:39,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:39,716 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:39,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:39,718 INFO L85 PathProgramCache]: Analyzing trace with hash -2115625782, now seen corresponding path program 8 times [2021-10-28 09:12:39,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:39,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081101671] [2021-10-28 09:12:39,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:39,719 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:39,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:40,051 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 10 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:40,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:40,051 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081101671] [2021-10-28 09:12:40,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081101671] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:40,051 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [130742218] [2021-10-28 09:12:40,051 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 09:12:40,052 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:40,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:40,059 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:40,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-10-28 09:12:40,271 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 09:12:40,271 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:40,272 INFO L263 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 09:12:40,275 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:40,302 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:40,303 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:40,363 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,408 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,466 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,514 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,566 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,631 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,686 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,741 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:40,803 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:12:40,813 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 10 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:40,813 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [130742218] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:40,813 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:40,814 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 12] total 30 [2021-10-28 09:12:40,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649562261] [2021-10-28 09:12:40,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:40,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-10-28 09:12:40,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=651, Unknown=0, NotChecked=0, Total=870 [2021-10-28 09:12:40,934 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. cyclomatic complexity: 4 Second operand has 30 states, 30 states have (on average 2.0) internal successors, (60), 30 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:41,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:41,326 INFO L93 Difference]: Finished difference Result 41 states and 43 transitions. [2021-10-28 09:12:41,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-10-28 09:12:41,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 43 transitions. [2021-10-28 09:12:41,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:41,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 39 states and 41 transitions. [2021-10-28 09:12:41,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:41,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:41,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 41 transitions. [2021-10-28 09:12:41,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:41,330 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-28 09:12:41,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 41 transitions. [2021-10-28 09:12:41,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2021-10-28 09:12:41,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.0512820512820513) internal successors, (41), 38 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:41,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 41 transitions. [2021-10-28 09:12:41,333 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-28 09:12:41,333 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2021-10-28 09:12:41,333 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 09:12:41,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 41 transitions. [2021-10-28 09:12:41,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:41,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:41,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:41,335 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 9, 1, 1, 1] [2021-10-28 09:12:41,335 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:41,336 INFO L791 eck$LassoCheckResult]: Stem: 1383#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1384#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 1389#L552-3 goto; 1399#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1398#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1393#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1385#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1386#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1417#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1387#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1388#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1392#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1394#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1416#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1415#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1414#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1413#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1412#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1411#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1410#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1409#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1408#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1407#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1406#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1405#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1404#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1403#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1402#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1401#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1400#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1396#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1390#L552-1 [2021-10-28 09:12:41,336 INFO L793 eck$LassoCheckResult]: Loop: 1390#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1391#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 1379#L552-3 goto; 1380#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1390#L552-1 [2021-10-28 09:12:41,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:41,336 INFO L85 PathProgramCache]: Analyzing trace with hash -2007908704, now seen corresponding path program 11 times [2021-10-28 09:12:41,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:41,337 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354459795] [2021-10-28 09:12:41,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:41,337 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:41,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:41,372 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:41,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:41,424 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:41,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:41,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 10 times [2021-10-28 09:12:41,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:41,426 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684783121] [2021-10-28 09:12:41,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:41,426 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:41,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:41,444 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:41,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:41,449 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:41,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:41,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1981227942, now seen corresponding path program 9 times [2021-10-28 09:12:41,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:41,452 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248159960] [2021-10-28 09:12:41,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:41,452 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:41,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:41,920 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 11 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:41,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:41,920 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248159960] [2021-10-28 09:12:41,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248159960] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:41,921 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [381578431] [2021-10-28 09:12:41,921 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 09:12:41,921 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:41,921 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:41,928 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:41,931 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-10-28 09:12:42,179 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2021-10-28 09:12:42,180 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 09:12:42,181 INFO L263 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 09:12:42,183 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:42,201 INFO L354 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2021-10-28 09:12:42,202 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 23 [2021-10-28 09:12:42,204 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2021-10-28 09:12:42,319 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,319 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,400 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,401 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,490 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,490 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,583 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,583 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,667 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,668 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,753 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,754 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,839 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,840 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:42,934 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:42,934 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:43,047 INFO L354 Elim1Store]: treesize reduction 39, result has 15.2 percent of original size [2021-10-28 09:12:43,047 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 27 [2021-10-28 09:12:43,135 INFO L354 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2021-10-28 09:12:43,136 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 16 [2021-10-28 09:12:43,144 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 11 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:43,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [381578431] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:43,144 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:12:43,145 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 13] total 33 [2021-10-28 09:12:43,145 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774281997] [2021-10-28 09:12:43,264 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:12:43,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-10-28 09:12:43,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=263, Invalid=793, Unknown=0, NotChecked=0, Total=1056 [2021-10-28 09:12:43,266 INFO L87 Difference]: Start difference. First operand 39 states and 41 transitions. cyclomatic complexity: 4 Second operand has 33 states, 33 states have (on average 2.0) internal successors, (66), 33 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:43,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:12:43,803 INFO L93 Difference]: Finished difference Result 44 states and 46 transitions. [2021-10-28 09:12:43,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-10-28 09:12:43,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 46 transitions. [2021-10-28 09:12:43,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:43,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 42 states and 44 transitions. [2021-10-28 09:12:43,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 09:12:43,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:43,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 44 transitions. [2021-10-28 09:12:43,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:43,809 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2021-10-28 09:12:43,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 44 transitions. [2021-10-28 09:12:43,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2021-10-28 09:12:43,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.0476190476190477) internal successors, (44), 41 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:43,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 44 transitions. [2021-10-28 09:12:43,821 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2021-10-28 09:12:43,821 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2021-10-28 09:12:43,822 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 09:12:43,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 44 transitions. [2021-10-28 09:12:43,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:43,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:43,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:43,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 10, 10, 1, 1, 1] [2021-10-28 09:12:43,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:43,829 INFO L791 eck$LassoCheckResult]: Stem: 1626#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1627#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 1632#L552-3 goto; 1642#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1641#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1636#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1628#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1629#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1663#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1630#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1631#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1635#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1637#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1662#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1661#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1660#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1659#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1658#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1657#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1656#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1655#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1654#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1653#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1652#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1651#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1650#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1649#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1648#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1647#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1646#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1645#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1644#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1643#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 1639#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1633#L552-1 [2021-10-28 09:12:43,830 INFO L793 eck$LassoCheckResult]: Loop: 1633#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1634#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 1622#L552-3 goto; 1623#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 1633#L552-1 [2021-10-28 09:12:43,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:43,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1598657468, now seen corresponding path program 12 times [2021-10-28 09:12:43,831 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:43,831 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822572014] [2021-10-28 09:12:43,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:43,831 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:43,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,851 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:43,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,874 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:43,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:43,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 11 times [2021-10-28 09:12:43,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:43,875 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929881174] [2021-10-28 09:12:43,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:43,875 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:43,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,882 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:43,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,887 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:43,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:43,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1264869194, now seen corresponding path program 10 times [2021-10-28 09:12:43,888 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:43,888 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421183898] [2021-10-28 09:12:43,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:43,888 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:43,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,911 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:12:43,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:12:43,935 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:12:54,365 WARN L207 SmtUtils]: Spent 10.32 s on a formula simplification. DAG size of input: 204 DAG size of output: 172 [2021-10-28 09:12:54,595 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 09:12:54,596 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 09:12:54,596 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 09:12:54,596 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 09:12:54,596 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 09:12:54,596 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:54,596 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 09:12:54,596 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 09:12:54,596 INFO L133 ssoRankerPreferences]: Filename of dumped script: java_Continue1-alloca.i_Iteration12_Lasso [2021-10-28 09:12:54,596 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 09:12:54,596 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 09:12:54,600 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,846 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,851 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,853 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,856 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,858 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,861 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,863 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,866 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,868 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:54,871 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 09:12:55,178 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 09:12:55,178 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 09:12:55,178 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,178 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,183 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-10-28 09:12:55,187 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,198 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 09:12:55,198 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,198 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,198 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,199 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 09:12:55,199 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 09:12:55,206 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,255 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,255 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,255 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,260 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,268 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,278 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,279 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 09:12:55,279 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,279 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,279 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,280 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 09:12:55,281 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 09:12:55,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-10-28 09:12:55,295 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,323 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,323 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,324 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2021-10-28 09:12:55,331 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,339 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,339 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,339 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,339 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,342 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,342 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,346 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,373 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,374 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,375 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,380 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-10-28 09:12:55,381 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,389 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,389 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,389 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,389 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,394 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,394 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,398 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,424 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,425 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,426 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,427 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2021-10-28 09:12:55,432 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,447 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,447 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,448 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,448 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,452 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,452 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,468 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,495 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,495 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,495 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,498 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,512 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2021-10-28 09:12:55,516 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,524 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,524 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,524 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,524 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,531 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,532 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,555 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,597 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,598 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,600 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,606 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2021-10-28 09:12:55,616 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,616 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,616 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,616 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,618 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,618 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,620 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,643 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,643 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,643 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,644 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,645 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2021-10-28 09:12:55,646 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,654 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,654 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,654 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,654 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,657 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,657 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,663 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 09:12:55,693 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,693 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,693 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,694 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,695 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-10-28 09:12:55,699 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 09:12:55,707 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 09:12:55,707 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 09:12:55,707 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 09:12:55,708 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 09:12:55,710 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 09:12:55,711 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 09:12:55,716 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 09:12:55,726 INFO L443 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2021-10-28 09:12:55,726 INFO L444 ModelExtractionUtils]: 1 out of 10 variables were initially zero. Simplification set additionally 4 variables to zero. [2021-10-28 09:12:55,727 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:12:55,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:55,728 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:12:55,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-10-28 09:12:55,736 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 09:12:55,749 INFO L438 nArgumentSynthesizer]: Removed 1 redundant supporting invariants from a total of 2. [2021-10-28 09:12:55,749 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 09:12:55,749 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_#t~mem4) = -41*ULTIMATE.start_main_#t~mem4 + 790 Supporting invariants [-40*ULTIMATE.start_main_#t~mem4 + 41*v_rep(select (select #memory_int ULTIMATE.start_main_~i~0.base) ULTIMATE.start_main_~i~0.offset)_2 >= 0] [2021-10-28 09:12:55,771 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-10-28 09:12:55,801 INFO L297 tatePredicateManager]: 11 out of 12 supporting invariants were superfluous and have been removed [2021-10-28 09:12:55,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:55,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:55,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 09:12:55,879 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:55,903 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:55,903 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:55,966 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,019 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,076 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,126 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,175 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,229 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,298 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,348 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2021-10-28 09:12:56,356 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,417 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,482 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:56,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:56,531 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 09:12:56,532 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:56,554 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 27 [2021-10-28 09:12:56,645 INFO L354 Elim1Store]: treesize reduction 18, result has 60.9 percent of original size [2021-10-28 09:12:56,645 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 42 treesize of output 53 [2021-10-28 09:12:56,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:56,835 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.12 stem predicates 3 loop predicates [2021-10-28 09:12:56,835 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4 Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:56,899 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4. Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 43 states and 45 transitions. Complement of second has 6 states. [2021-10-28 09:12:56,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 09:12:56,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:56,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 5 transitions. [2021-10-28 09:12:56,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 5 transitions. Stem has 34 letters. Loop has 4 letters. [2021-10-28 09:12:56,900 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:56,901 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 09:12:56,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:56,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:56,966 INFO L263 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 09:12:56,967 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:56,999 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:57,000 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:57,067 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,124 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,179 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,242 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,301 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,367 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,433 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,493 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,561 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,627 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:57,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:57,681 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 09:12:57,681 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:57,698 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 27 [2021-10-28 09:12:57,790 INFO L354 Elim1Store]: treesize reduction 18, result has 60.9 percent of original size [2021-10-28 09:12:57,790 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 42 treesize of output 53 [2021-10-28 09:12:57,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:57,918 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.12 stem predicates 3 loop predicates [2021-10-28 09:12:57,918 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4 Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:57,978 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4. Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 43 states and 45 transitions. Complement of second has 6 states. [2021-10-28 09:12:57,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 09:12:57,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:57,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 5 transitions. [2021-10-28 09:12:57,981 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 5 transitions. Stem has 34 letters. Loop has 4 letters. [2021-10-28 09:12:57,981 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:57,981 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 09:12:58,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:58,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:58,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 09:12:58,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:58,067 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:58,068 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:12:58,137 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,197 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,249 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,302 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,359 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,419 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,480 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,544 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,608 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,675 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:12:58,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:58,727 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 09:12:58,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:58,744 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 27 [2021-10-28 09:12:58,818 INFO L354 Elim1Store]: treesize reduction 18, result has 60.9 percent of original size [2021-10-28 09:12:58,818 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 42 treesize of output 53 [2021-10-28 09:12:58,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:58,920 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.12 stem predicates 3 loop predicates [2021-10-28 09:12:58,920 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4 Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:59,198 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 42 states and 44 transitions. cyclomatic complexity: 4. Second operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 69 states and 75 transitions. Complement of second has 49 states. [2021-10-28 09:12:59,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 16 states 12 stem states 2 non-accepting loop states 2 accepting loop states [2021-10-28 09:12:59,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 2.533333333333333) internal successors, (38), 15 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:59,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 56 transitions. [2021-10-28 09:12:59,200 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 56 transitions. Stem has 34 letters. Loop has 4 letters. [2021-10-28 09:12:59,201 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:59,201 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 56 transitions. Stem has 38 letters. Loop has 4 letters. [2021-10-28 09:12:59,202 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:59,202 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 56 transitions. Stem has 34 letters. Loop has 8 letters. [2021-10-28 09:12:59,203 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 09:12:59,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 75 transitions. [2021-10-28 09:12:59,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:59,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 49 states and 53 transitions. [2021-10-28 09:12:59,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-10-28 09:12:59,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 09:12:59,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 53 transitions. [2021-10-28 09:12:59,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 09:12:59,206 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 53 transitions. [2021-10-28 09:12:59,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 53 transitions. [2021-10-28 09:12:59,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 47. [2021-10-28 09:12:59,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0638297872340425) internal successors, (50), 46 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:12:59,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 50 transitions. [2021-10-28 09:12:59,209 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 50 transitions. [2021-10-28 09:12:59,210 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 50 transitions. [2021-10-28 09:12:59,210 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 09:12:59,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 50 transitions. [2021-10-28 09:12:59,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-10-28 09:12:59,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:12:59,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:12:59,214 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 11, 1, 1, 1] [2021-10-28 09:12:59,214 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-10-28 09:12:59,215 INFO L791 eck$LassoCheckResult]: Stem: 2355#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2356#L-1 havoc main_#res;havoc main_#t~malloc2.base, main_#t~malloc2.offset, main_#t~malloc3.base, main_#t~malloc3.offset, main_#t~mem5, main_#t~post6, main_#t~mem7, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~mem10, main_~i~0.base, main_~i~0.offset, main_~c~0.base, main_~c~0.offset;call main_#t~malloc2.base, main_#t~malloc2.offset := #Ultimate.allocOnStack(4);main_~i~0.base, main_~i~0.offset := main_#t~malloc2.base, main_#t~malloc2.offset;call main_#t~malloc3.base, main_#t~malloc3.offset := #Ultimate.allocOnStack(4);main_~c~0.base, main_~c~0.offset := main_#t~malloc3.base, main_#t~malloc3.offset;call write~int(0, main_~i~0.base, main_~i~0.offset, 4);call write~int(0, main_~c~0.base, main_~c~0.offset, 4); 2351#L552-3 goto; 2352#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2361#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2362#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2357#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2358#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2363#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2359#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2360#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2397#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2396#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2395#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2394#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2393#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2392#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2391#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2390#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2389#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2388#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2387#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2386#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2385#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2384#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2383#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2382#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2381#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2380#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2379#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2378#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2377#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2376#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2354#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2365#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2366#L554 assume main_#t~mem7 <= 10;havoc main_#t~mem7; 2367#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2368#L552-1 [2021-10-28 09:12:59,215 INFO L793 eck$LassoCheckResult]: Loop: 2368#L552-1 assume !!(main_#t~mem4 < 20);havoc main_#t~mem4;call main_#t~mem5 := read~int(main_~i~0.base, main_~i~0.offset, 4);main_#t~post6 := main_#t~mem5;call write~int(1 + main_#t~post6, main_~i~0.base, main_~i~0.offset, 4);havoc main_#t~mem5;havoc main_#t~post6;call main_#t~mem7 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2370#L554 assume !(main_#t~mem7 <= 10);havoc main_#t~mem7;call main_#t~mem8 := read~int(main_~c~0.base, main_~c~0.offset, 4);main_#t~post9 := main_#t~mem8;call write~int(1 + main_#t~post9, main_~c~0.base, main_~c~0.offset, 4);havoc main_#t~mem8;havoc main_#t~post9; 2371#L552-3 goto; 2374#L554-1 call main_#t~mem4 := read~int(main_~i~0.base, main_~i~0.offset, 4); 2368#L552-1 [2021-10-28 09:12:59,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:12:59,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1287728160, now seen corresponding path program 13 times [2021-10-28 09:12:59,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:12:59,217 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201480637] [2021-10-28 09:12:59,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:12:59,217 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:12:59,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:59,562 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 146 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:12:59,563 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:12:59,563 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201480637] [2021-10-28 09:12:59,563 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201480637] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:12:59,563 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2058218235] [2021-10-28 09:12:59,563 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 09:12:59,563 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:12:59,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:12:59,583 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:12:59,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-10-28 09:12:59,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:12:59,961 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 09:12:59,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:12:59,997 INFO L354 Elim1Store]: treesize reduction 17, result has 29.2 percent of original size [2021-10-28 09:12:59,997 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 15 [2021-10-28 09:13:00,056 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,098 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,146 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,194 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,264 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,316 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,374 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,418 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,467 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,519 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2021-10-28 09:13:00,579 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2021-10-28 09:13:00,585 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 11 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:13:00,586 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2058218235] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:13:00,586 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:13:00,586 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14] total 36 [2021-10-28 09:13:00,586 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430802224] [2021-10-28 09:13:00,587 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:13:00,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:13:00,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1297543, now seen corresponding path program 12 times [2021-10-28 09:13:00,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:13:00,588 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720162206] [2021-10-28 09:13:00,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:13:00,588 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:13:00,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:13:00,595 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:13:00,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:13:00,599 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:13:00,704 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:13:00,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-10-28 09:13:00,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=989, Unknown=0, NotChecked=0, Total=1260 [2021-10-28 09:13:00,706 INFO L87 Difference]: Start difference. First operand 47 states and 50 transitions. cyclomatic complexity: 6 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 36 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:13:01,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:13:01,228 INFO L93 Difference]: Finished difference Result 40 states and 41 transitions. [2021-10-28 09:13:01,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-10-28 09:13:01,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 41 transitions. [2021-10-28 09:13:01,237 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2021-10-28 09:13:01,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 0 states and 0 transitions. [2021-10-28 09:13:01,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2021-10-28 09:13:01,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2021-10-28 09:13:01,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2021-10-28 09:13:01,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:13:01,237 INFO L681 BuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2021-10-28 09:13:01,238 INFO L704 BuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2021-10-28 09:13:01,238 INFO L587 BuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2021-10-28 09:13:01,238 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 09:13:01,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2021-10-28 09:13:01,238 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2021-10-28 09:13:01,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2021-10-28 09:13:01,243 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 09:13:01 BoogieIcfgContainer [2021-10-28 09:13:01,243 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 09:13:01,247 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 09:13:01,248 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 09:13:01,248 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 09:13:01,248 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:12:28" (3/4) ... [2021-10-28 09:13:01,252 INFO L140 WitnessPrinter]: No result that supports witness generation found [2021-10-28 09:13:01,252 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 09:13:01,253 INFO L168 Benchmark]: Toolchain (without parser) took 33618.22 ms. Allocated memory was 130.0 MB in the beginning and 255.9 MB in the end (delta: 125.8 MB). Free memory was 89.7 MB in the beginning and 113.6 MB in the end (delta: -23.9 MB). Peak memory consumption was 102.9 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,254 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 130.0 MB. Free memory is still 107.0 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:13:01,254 INFO L168 Benchmark]: CACSL2BoogieTranslator took 598.66 ms. Allocated memory is still 130.0 MB. Free memory was 89.6 MB in the beginning and 98.3 MB in the end (delta: -8.7 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,255 INFO L168 Benchmark]: Boogie Procedure Inliner took 74.74 ms. Allocated memory is still 130.0 MB. Free memory was 98.3 MB in the beginning and 96.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,255 INFO L168 Benchmark]: Boogie Preprocessor took 59.73 ms. Allocated memory is still 130.0 MB. Free memory was 96.4 MB in the beginning and 95.2 MB in the end (delta: 1.2 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,256 INFO L168 Benchmark]: RCFGBuilder took 419.35 ms. Allocated memory is still 130.0 MB. Free memory was 95.2 MB in the beginning and 85.8 MB in the end (delta: 9.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,256 INFO L168 Benchmark]: BuchiAutomizer took 32447.85 ms. Allocated memory was 130.0 MB in the beginning and 255.9 MB in the end (delta: 125.8 MB). Free memory was 85.2 MB in the beginning and 114.7 MB in the end (delta: -29.5 MB). Peak memory consumption was 96.9 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,257 INFO L168 Benchmark]: Witness Printer took 5.16 ms. Allocated memory is still 255.9 MB. Free memory was 114.7 MB in the beginning and 113.6 MB in the end (delta: 1.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:13:01,265 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 130.0 MB. Free memory is still 107.0 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 598.66 ms. Allocated memory is still 130.0 MB. Free memory was 89.6 MB in the beginning and 98.3 MB in the end (delta: -8.7 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 74.74 ms. Allocated memory is still 130.0 MB. Free memory was 98.3 MB in the beginning and 96.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 59.73 ms. Allocated memory is still 130.0 MB. Free memory was 96.4 MB in the beginning and 95.2 MB in the end (delta: 1.2 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 419.35 ms. Allocated memory is still 130.0 MB. Free memory was 95.2 MB in the beginning and 85.8 MB in the end (delta: 9.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 32447.85 ms. Allocated memory was 130.0 MB in the beginning and 255.9 MB in the end (delta: 125.8 MB). Free memory was 85.2 MB in the beginning and 114.7 MB in the end (delta: -29.5 MB). Peak memory consumption was 96.9 MB. Max. memory is 16.1 GB. * Witness Printer took 5.16 ms. Allocated memory is still 255.9 MB. Free memory was 114.7 MB in the beginning and 113.6 MB in the end (delta: 1.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (11 trivial, 1 deterministic, 1 nondeterministic). One deterministic module has affine ranking function 19 + -2 * unknown-#memory_int-unknown[i][i] and consists of 4 locations. One nondeterministic module has affine ranking function -41 * aux-i-aux + 790 and consists of 16 locations. 11 modules have a trivial ranking function, the largest among these consists of 36 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 32.4s and 14 iterations. TraceHistogramMax:12. Analysis of lassos took 25.4s. Construction of modules took 1.5s. Büchi inclusion checks took 5.1s. Highest rank in rank-based complementation 3. Minimization of det autom 2. Minimization of nondet autom 11. Automata minimization 0.0s AutomataMinimizationTime, 12 MinimizatonAttempts, 3 StatesRemovedByMinimization, 2 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 47 states and ocurred in iteration 12. Nontrivial modules had stage [1, 0, 1, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 76 SDtfs, 75 SDslu, 339 SDs, 0 SdLazy, 2198 SolverSat, 209 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc10 concLT0 SILN0 SILU1 SILI0 SILT0 lasso2 LassoPreprocessingBenchmarks: Lassos: inital250 mio100 ax107 hnf100 lsp89 ukn47 mio100 lsp42 div100 bol100 ite100 ukn100 eq175 hnf89 smp91 dnf100 smp100 tf100 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 37ms VariablesStem: 1 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2021-10-28 09:13:01,312 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:01,517 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:01,722 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:01,927 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:02,122 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:02,325 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:02,523 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2021-10-28 09:13:02,722 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2021-10-28 09:13:02,923 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2021-10-28 09:13:03,123 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2021-10-28 09:13:03,305 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e65a32b9-1542-4da2-a96e-943d112942e7/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...