./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 949942bcd30c11cd050737185c4313ee1459089f9da346d697b721e3407e41e2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 08:51:53,288 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 08:51:53,292 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 08:51:53,354 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 08:51:53,355 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 08:51:53,359 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 08:51:53,361 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 08:51:53,365 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 08:51:53,368 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 08:51:53,376 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 08:51:53,377 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 08:51:53,379 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 08:51:53,380 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 08:51:53,383 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 08:51:53,386 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 08:51:53,394 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 08:51:53,396 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 08:51:53,398 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 08:51:53,400 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 08:51:53,404 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 08:51:53,409 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 08:51:53,410 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 08:51:53,414 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 08:51:53,415 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 08:51:53,425 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 08:51:53,427 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 08:51:53,428 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 08:51:53,429 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 08:51:53,429 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 08:51:53,430 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 08:51:53,430 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 08:51:53,431 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 08:51:53,431 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 08:51:53,432 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 08:51:53,434 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 08:51:53,434 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 08:51:53,435 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 08:51:53,435 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 08:51:53,436 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 08:51:53,437 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 08:51:53,438 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 08:51:53,439 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 08:51:53,494 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 08:51:53,495 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 08:51:53,496 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 08:51:53,496 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 08:51:53,497 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 08:51:53,498 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 08:51:53,498 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 08:51:53,499 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 08:51:53,499 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 08:51:53,499 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 08:51:53,500 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 08:51:53,500 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 08:51:53,501 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 08:51:53,501 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 08:51:53,501 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 08:51:53,501 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 08:51:53,502 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 08:51:53,502 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 08:51:53,502 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 08:51:53,502 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 08:51:53,503 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 08:51:53,503 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 08:51:53,503 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 08:51:53,503 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 08:51:53,504 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 08:51:53,504 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 08:51:53,505 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 08:51:53,506 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 08:51:53,506 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 08:51:53,506 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 08:51:53,507 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 08:51:53,507 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 08:51:53,508 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 08:51:53,508 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 949942bcd30c11cd050737185c4313ee1459089f9da346d697b721e3407e41e2 [2021-10-28 08:51:53,787 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 08:51:53,809 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 08:51:53,812 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 08:51:53,813 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 08:51:53,814 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 08:51:53,815 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-10-28 08:51:53,881 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/data/9069c974f/e957f557bbe44c49aa356595a38802cd/FLAG81039ca5e [2021-10-28 08:51:54,500 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 08:51:54,503 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-10-28 08:51:54,528 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/data/9069c974f/e957f557bbe44c49aa356595a38802cd/FLAG81039ca5e [2021-10-28 08:51:54,805 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/data/9069c974f/e957f557bbe44c49aa356595a38802cd [2021-10-28 08:51:54,808 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 08:51:54,810 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 08:51:54,812 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 08:51:54,812 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 08:51:54,816 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 08:51:54,817 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 08:51:54" (1/1) ... [2021-10-28 08:51:54,819 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@d498b92 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:54, skipping insertion in model container [2021-10-28 08:51:54,819 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 08:51:54" (1/1) ... [2021-10-28 08:51:54,827 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 08:51:54,864 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 08:51:55,037 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[366,379] [2021-10-28 08:51:55,092 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 08:51:55,102 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 08:51:55,115 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[366,379] [2021-10-28 08:51:55,147 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 08:51:55,163 INFO L208 MainTranslator]: Completed translation [2021-10-28 08:51:55,163 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55 WrapperNode [2021-10-28 08:51:55,163 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 08:51:55,164 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 08:51:55,165 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 08:51:55,165 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 08:51:55,171 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,181 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,227 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 08:51:55,229 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 08:51:55,229 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 08:51:55,229 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 08:51:55,238 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,238 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,244 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,244 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,256 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,267 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,271 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,278 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 08:51:55,280 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 08:51:55,280 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 08:51:55,280 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 08:51:55,281 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (1/1) ... [2021-10-28 08:51:55,300 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 08:51:55,314 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 08:51:55,329 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 08:51:55,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 08:51:55,372 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 08:51:55,373 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 08:51:55,373 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 08:51:55,373 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 08:51:56,157 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 08:51:56,158 INFO L299 CfgBuilder]: Removed 103 assume(true) statements. [2021-10-28 08:51:56,162 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:51:56 BoogieIcfgContainer [2021-10-28 08:51:56,162 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 08:51:56,164 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 08:51:56,164 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 08:51:56,168 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 08:51:56,168 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:51:56,168 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 08:51:54" (1/3) ... [2021-10-28 08:51:56,170 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@757fc81e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 08:51:56, skipping insertion in model container [2021-10-28 08:51:56,170 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:51:56,170 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 08:51:55" (2/3) ... [2021-10-28 08:51:56,171 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@757fc81e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 08:51:56, skipping insertion in model container [2021-10-28 08:51:56,171 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 08:51:56,171 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:51:56" (3/3) ... [2021-10-28 08:51:56,173 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2021-10-28 08:51:56,219 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 08:51:56,219 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 08:51:56,219 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 08:51:56,219 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 08:51:56,219 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 08:51:56,219 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 08:51:56,220 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 08:51:56,220 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 08:51:56,243 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:56,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2021-10-28 08:51:56,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:56,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:56,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,289 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 08:51:56,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:56,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2021-10-28 08:51:56,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:56,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:56,312 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,313 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,324 INFO L791 eck$LassoCheckResult]: Stem: 206#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 125#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26#L508true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 186#L216true assume !(1 == ~m_i~0);~m_st~0 := 2; 100#L223-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 44#L228-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 53#L233-1true assume !(0 == ~M_E~0); 101#L336-1true assume !(0 == ~T1_E~0); 95#L341-1true assume !(0 == ~T2_E~0); 19#L346-1true assume !(0 == ~E_M~0); 120#L351-1true assume !(0 == ~E_1~0); 22#L356-1true assume !(0 == ~E_2~0); 111#L361-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 109#L158true assume 1 == ~m_pc~0; 156#L159true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 140#L169true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L170true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35#L417true assume !(0 != activate_threads_~tmp~1); 152#L417-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 137#L177true assume 1 == ~t1_pc~0; 25#L178true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14#L188true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73#L189true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 188#L425true assume !(0 != activate_threads_~tmp___0~0); 210#L425-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50#L196true assume !(1 == ~t2_pc~0); 211#L196-2true is_transmit2_triggered_~__retres1~2 := 0; 57#L207true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 190#L208true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54#L433true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 135#L433-2true assume !(1 == ~M_E~0); 180#L374-1true assume !(1 == ~T1_E~0); 29#L379-1true assume !(1 == ~T2_E~0); 24#L384-1true assume !(1 == ~E_M~0); 142#L389-1true assume 1 == ~E_1~0;~E_1~0 := 2; 131#L394-1true assume !(1 == ~E_2~0); 214#L545-1true [2021-10-28 08:51:56,330 INFO L793 eck$LassoCheckResult]: Loop: 214#L545-1true assume !false; 31#L546true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 39#L311true assume false; 122#L326true start_simulation_~kernel_st~0 := 2; 48#L216-1true start_simulation_~kernel_st~0 := 3; 158#L336-2true assume 0 == ~M_E~0;~M_E~0 := 1; 201#L336-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 112#L341-3true assume !(0 == ~T2_E~0); 139#L346-3true assume 0 == ~E_M~0;~E_M~0 := 1; 61#L351-3true assume 0 == ~E_1~0;~E_1~0 := 1; 161#L356-3true assume 0 == ~E_2~0;~E_2~0 := 1; 102#L361-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124#L158-12true assume 1 == ~m_pc~0; 145#L159-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 110#L169-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 81#L170-4true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21#L417-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 72#L417-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4#L177-12true assume !(1 == ~t1_pc~0); 15#L177-14true is_transmit1_triggered_~__retres1~1 := 0; 114#L188-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90#L189-4true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 47#L425-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 88#L425-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203#L196-12true assume !(1 == ~t2_pc~0); 215#L196-14true is_transmit2_triggered_~__retres1~2 := 0; 157#L207-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41#L208-4true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 171#L433-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 103#L433-14true assume !(1 == ~M_E~0); 134#L374-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 56#L379-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 64#L384-3true assume 1 == ~E_M~0;~E_M~0 := 2; 117#L389-3true assume 1 == ~E_1~0;~E_1~0 := 2; 216#L394-3true assume 1 == ~E_2~0;~E_2~0 := 2; 16#L399-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17#L246-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 217#L263-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 163#L264-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 13#L564true assume !(0 == start_simulation_~tmp~3); 153#L564-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 108#L246-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 174#L263-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 209#L264-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 165#L519true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 175#L526true stop_simulation_#res := stop_simulation_~__retres2~0; 173#L527true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 143#L577true assume !(0 != start_simulation_~tmp___0~1); 214#L545-1true [2021-10-28 08:51:56,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:56,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2021-10-28 08:51:56,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:56,348 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670771240] [2021-10-28 08:51:56,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:56,349 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:56,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:56,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:56,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:56,538 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670771240] [2021-10-28 08:51:56,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670771240] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:56,539 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:56,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:56,541 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396616506] [2021-10-28 08:51:56,547 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:56,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:56,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1944420535, now seen corresponding path program 1 times [2021-10-28 08:51:56,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:56,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961786828] [2021-10-28 08:51:56,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:56,550 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:56,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:56,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:56,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:56,629 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961786828] [2021-10-28 08:51:56,629 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961786828] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:56,629 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:56,629 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 08:51:56,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101840675] [2021-10-28 08:51:56,631 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:56,632 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:56,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:56,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:56,678 INFO L87 Difference]: Start difference. First operand has 217 states, 216 states have (on average 1.5694444444444444) internal successors, (339), 216 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:56,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:56,750 INFO L93 Difference]: Finished difference Result 217 states and 327 transitions. [2021-10-28 08:51:56,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:56,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 327 transitions. [2021-10-28 08:51:56,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-28 08:51:56,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 212 states and 322 transitions. [2021-10-28 08:51:56,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2021-10-28 08:51:56,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2021-10-28 08:51:56,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 322 transitions. [2021-10-28 08:51:56,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:56,786 INFO L681 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-28 08:51:56,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 322 transitions. [2021-10-28 08:51:56,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2021-10-28 08:51:56,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.5188679245283019) internal successors, (322), 211 states have internal predecessors, (322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:56,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 322 transitions. [2021-10-28 08:51:56,843 INFO L704 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-28 08:51:56,844 INFO L587 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2021-10-28 08:51:56,844 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 08:51:56,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 322 transitions. [2021-10-28 08:51:56,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-28 08:51:56,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:56,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:56,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,855 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:56,856 INFO L791 eck$LassoCheckResult]: Stem: 654#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 617#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 489#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 490#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 595#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 522#L228-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 523#L233-1 assume !(0 == ~M_E~0); 539#L336-1 assume !(0 == ~T1_E~0); 589#L341-1 assume !(0 == ~T2_E~0); 475#L346-1 assume !(0 == ~E_M~0); 476#L351-1 assume !(0 == ~E_1~0); 481#L356-1 assume !(0 == ~E_2~0); 482#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 606#L158 assume 1 == ~m_pc~0; 607#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 604#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 628#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 505#L417 assume !(0 != activate_threads_~tmp~1); 506#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 627#L177 assume 1 == ~t1_pc~0; 487#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 466#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 467#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 565#L425 assume !(0 != activate_threads_~tmp___0~0); 652#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 532#L196 assume !(1 == ~t2_pc~0); 533#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 546#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 547#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 540#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 541#L433-2 assume !(1 == ~M_E~0); 626#L374-1 assume !(1 == ~T1_E~0); 496#L379-1 assume !(1 == ~T2_E~0); 485#L384-1 assume !(1 == ~E_M~0); 486#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 621#L394-1 assume !(1 == ~E_2~0); 622#L545-1 [2021-10-28 08:51:56,857 INFO L793 eck$LassoCheckResult]: Loop: 622#L545-1 assume !false; 498#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 494#L311 assume !false; 512#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 535#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 518#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 629#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 591#L278 assume !(0 != eval_~tmp~0); 592#L326 start_simulation_~kernel_st~0 := 2; 529#L216-1 start_simulation_~kernel_st~0 := 3; 530#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 638#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 609#L341-3 assume !(0 == ~T2_E~0); 610#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 551#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 552#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 596#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 597#L158-12 assume !(1 == ~m_pc~0); 615#L158-14 is_master_triggered_~__retres1~0 := 0; 608#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 570#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 479#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 480#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 446#L177-12 assume !(1 == ~t1_pc~0); 448#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 468#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 582#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 527#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 528#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 579#L196-12 assume 1 == ~t2_pc~0; 649#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 637#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 515#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 516#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 598#L433-14 assume !(1 == ~M_E~0); 599#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 544#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 545#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 555#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 613#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 469#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 470#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 455#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 640#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 464#L564 assume !(0 == start_simulation_~tmp~3); 465#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 605#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 484#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 648#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 642#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 643#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 647#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 630#L577 assume !(0 != start_simulation_~tmp___0~1); 622#L545-1 [2021-10-28 08:51:56,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:56,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2021-10-28 08:51:56,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:56,859 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409524756] [2021-10-28 08:51:56,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:56,860 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:56,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:56,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:56,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:56,963 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409524756] [2021-10-28 08:51:56,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409524756] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:56,965 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:56,965 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:56,966 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574931151] [2021-10-28 08:51:56,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:56,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:56,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 1 times [2021-10-28 08:51:56,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:56,973 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814521190] [2021-10-28 08:51:56,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:56,974 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,094 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814521190] [2021-10-28 08:51:57,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814521190] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,096 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,096 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669191374] [2021-10-28 08:51:57,096 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:57,097 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:57,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:57,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:57,100 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:57,122 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2021-10-28 08:51:57,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:57,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 321 transitions. [2021-10-28 08:51:57,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-28 08:51:57,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 321 transitions. [2021-10-28 08:51:57,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2021-10-28 08:51:57,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2021-10-28 08:51:57,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 321 transitions. [2021-10-28 08:51:57,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:57,139 INFO L681 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-28 08:51:57,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 321 transitions. [2021-10-28 08:51:57,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2021-10-28 08:51:57,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.5141509433962264) internal successors, (321), 211 states have internal predecessors, (321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 321 transitions. [2021-10-28 08:51:57,157 INFO L704 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-28 08:51:57,157 INFO L587 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2021-10-28 08:51:57,157 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 08:51:57,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 321 transitions. [2021-10-28 08:51:57,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2021-10-28 08:51:57,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:57,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:57,161 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,161 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,162 INFO L791 eck$LassoCheckResult]: Stem: 1085#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1048#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 920#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 921#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1026#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 953#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 954#L233-1 assume !(0 == ~M_E~0); 970#L336-1 assume !(0 == ~T1_E~0); 1020#L341-1 assume !(0 == ~T2_E~0); 906#L346-1 assume !(0 == ~E_M~0); 907#L351-1 assume !(0 == ~E_1~0); 912#L356-1 assume !(0 == ~E_2~0); 913#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1037#L158 assume 1 == ~m_pc~0; 1038#L159 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1035#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1059#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 936#L417 assume !(0 != activate_threads_~tmp~1); 937#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1058#L177 assume 1 == ~t1_pc~0; 918#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 897#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 898#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 996#L425 assume !(0 != activate_threads_~tmp___0~0); 1083#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 963#L196 assume !(1 == ~t2_pc~0); 964#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 977#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 978#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 971#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 972#L433-2 assume !(1 == ~M_E~0); 1057#L374-1 assume !(1 == ~T1_E~0); 927#L379-1 assume !(1 == ~T2_E~0); 916#L384-1 assume !(1 == ~E_M~0); 917#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1052#L394-1 assume !(1 == ~E_2~0); 1053#L545-1 [2021-10-28 08:51:57,162 INFO L793 eck$LassoCheckResult]: Loop: 1053#L545-1 assume !false; 929#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 925#L311 assume !false; 943#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 966#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 949#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1060#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1022#L278 assume !(0 != eval_~tmp~0); 1023#L326 start_simulation_~kernel_st~0 := 2; 960#L216-1 start_simulation_~kernel_st~0 := 3; 961#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1069#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1040#L341-3 assume !(0 == ~T2_E~0); 1041#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 982#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 983#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1027#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1028#L158-12 assume !(1 == ~m_pc~0); 1046#L158-14 is_master_triggered_~__retres1~0 := 0; 1039#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1001#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 910#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 911#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 877#L177-12 assume 1 == ~t1_pc~0; 878#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 899#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1013#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 958#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 959#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1010#L196-12 assume 1 == ~t2_pc~0; 1080#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1068#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 946#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 947#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1029#L433-14 assume !(1 == ~M_E~0); 1030#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 976#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 986#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1044#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 900#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 901#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 886#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1071#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 895#L564 assume !(0 == start_simulation_~tmp~3); 896#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1036#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 915#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1079#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1073#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1074#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 1078#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1061#L577 assume !(0 != start_simulation_~tmp___0~1); 1053#L545-1 [2021-10-28 08:51:57,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2021-10-28 08:51:57,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,164 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227403093] [2021-10-28 08:51:57,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,164 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,213 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,213 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227403093] [2021-10-28 08:51:57,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227403093] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,214 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 08:51:57,214 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962573340] [2021-10-28 08:51:57,215 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:57,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,215 INFO L85 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 1 times [2021-10-28 08:51:57,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,216 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975272262] [2021-10-28 08:51:57,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,216 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,266 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975272262] [2021-10-28 08:51:57,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975272262] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,266 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710329931] [2021-10-28 08:51:57,267 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:57,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:57,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:57,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:57,269 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. cyclomatic complexity: 110 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:57,318 INFO L93 Difference]: Finished difference Result 377 states and 559 transitions. [2021-10-28 08:51:57,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:57,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 559 transitions. [2021-10-28 08:51:57,323 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 338 [2021-10-28 08:51:57,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 559 transitions. [2021-10-28 08:51:57,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2021-10-28 08:51:57,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2021-10-28 08:51:57,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 377 states and 559 transitions. [2021-10-28 08:51:57,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:57,329 INFO L681 BuchiCegarLoop]: Abstraction has 377 states and 559 transitions. [2021-10-28 08:51:57,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states and 559 transitions. [2021-10-28 08:51:57,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 358. [2021-10-28 08:51:57,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 358 states, 358 states have (on average 1.488826815642458) internal successors, (533), 357 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 533 transitions. [2021-10-28 08:51:57,344 INFO L704 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2021-10-28 08:51:57,344 INFO L587 BuchiCegarLoop]: Abstraction has 358 states and 533 transitions. [2021-10-28 08:51:57,344 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 08:51:57,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 358 states and 533 transitions. [2021-10-28 08:51:57,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2021-10-28 08:51:57,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:57,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:57,350 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,350 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,350 INFO L791 eck$LassoCheckResult]: Stem: 1693#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1650#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1517#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1518#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 1627#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1552#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1553#L233-1 assume !(0 == ~M_E~0); 1569#L336-1 assume !(0 == ~T1_E~0); 1621#L341-1 assume !(0 == ~T2_E~0); 1503#L346-1 assume !(0 == ~E_M~0); 1504#L351-1 assume !(0 == ~E_1~0); 1509#L356-1 assume !(0 == ~E_2~0); 1510#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1639#L158 assume !(1 == ~m_pc~0); 1636#L158-2 is_master_triggered_~__retres1~0 := 0; 1637#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1660#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1535#L417 assume !(0 != activate_threads_~tmp~1); 1536#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1659#L177 assume 1 == ~t1_pc~0; 1515#L178 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1494#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1495#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1595#L425 assume !(0 != activate_threads_~tmp___0~0); 1690#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1562#L196 assume !(1 == ~t2_pc~0); 1563#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 1576#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1577#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1570#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1571#L433-2 assume !(1 == ~M_E~0); 1658#L374-1 assume !(1 == ~T1_E~0); 1524#L379-1 assume !(1 == ~T2_E~0); 1513#L384-1 assume !(1 == ~E_M~0); 1514#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1653#L394-1 assume !(1 == ~E_2~0); 1654#L545-1 [2021-10-28 08:51:57,351 INFO L793 eck$LassoCheckResult]: Loop: 1654#L545-1 assume !false; 1526#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1522#L311 assume !false; 1542#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1565#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1548#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1661#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1623#L278 assume !(0 != eval_~tmp~0); 1624#L326 start_simulation_~kernel_st~0 := 2; 1825#L216-1 start_simulation_~kernel_st~0 := 3; 1824#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1823#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1822#L341-3 assume !(0 == ~T2_E~0); 1821#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1820#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1674#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1628#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1629#L158-12 assume !(1 == ~m_pc~0); 1649#L158-14 is_master_triggered_~__retres1~0 := 0; 1640#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1600#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1507#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1508#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1472#L177-12 assume 1 == ~t1_pc~0; 1473#L178-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1496#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1614#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1557#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1558#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1611#L196-12 assume 1 == ~t2_pc~0; 1687#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1672#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1545#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1546#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1630#L433-14 assume !(1 == ~M_E~0); 1631#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1575#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1585#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1645#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1497#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1498#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1482#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1675#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1491#L564 assume !(0 == start_simulation_~tmp~3); 1492#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1638#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1512#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1686#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1677#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1678#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 1685#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1662#L577 assume !(0 != start_simulation_~tmp___0~1); 1654#L545-1 [2021-10-28 08:51:57,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,351 INFO L85 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2021-10-28 08:51:57,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,352 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732733961] [2021-10-28 08:51:57,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,352 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,399 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732733961] [2021-10-28 08:51:57,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1732733961] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,400 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584540138] [2021-10-28 08:51:57,401 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:57,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1012220855, now seen corresponding path program 2 times [2021-10-28 08:51:57,402 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,403 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262268109] [2021-10-28 08:51:57,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,403 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,443 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,444 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262268109] [2021-10-28 08:51:57,444 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1262268109] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,444 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,444 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,445 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377173398] [2021-10-28 08:51:57,445 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:57,445 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:57,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 08:51:57,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 08:51:57,447 INFO L87 Difference]: Start difference. First operand 358 states and 533 transitions. cyclomatic complexity: 177 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:57,570 INFO L93 Difference]: Finished difference Result 792 states and 1155 transitions. [2021-10-28 08:51:57,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 08:51:57,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1155 transitions. [2021-10-28 08:51:57,580 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 727 [2021-10-28 08:51:57,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1155 transitions. [2021-10-28 08:51:57,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2021-10-28 08:51:57,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2021-10-28 08:51:57,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1155 transitions. [2021-10-28 08:51:57,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:57,593 INFO L681 BuchiCegarLoop]: Abstraction has 792 states and 1155 transitions. [2021-10-28 08:51:57,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1155 transitions. [2021-10-28 08:51:57,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 623. [2021-10-28 08:51:57,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 623 states, 623 states have (on average 1.4751203852327448) internal successors, (919), 622 states have internal predecessors, (919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 919 transitions. [2021-10-28 08:51:57,613 INFO L704 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2021-10-28 08:51:57,613 INFO L587 BuchiCegarLoop]: Abstraction has 623 states and 919 transitions. [2021-10-28 08:51:57,613 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 08:51:57,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 623 states and 919 transitions. [2021-10-28 08:51:57,618 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 584 [2021-10-28 08:51:57,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:57,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:57,620 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,620 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,621 INFO L791 eck$LassoCheckResult]: Stem: 2867#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2810#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2674#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2675#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 2786#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2707#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2708#L233-1 assume !(0 == ~M_E~0); 2725#L336-1 assume !(0 == ~T1_E~0); 2780#L341-1 assume !(0 == ~T2_E~0); 2660#L346-1 assume !(0 == ~E_M~0); 2661#L351-1 assume !(0 == ~E_1~0); 2666#L356-1 assume !(0 == ~E_2~0); 2667#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2799#L158 assume !(1 == ~m_pc~0); 2796#L158-2 is_master_triggered_~__retres1~0 := 0; 2797#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2825#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2690#L417 assume !(0 != activate_threads_~tmp~1); 2691#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2823#L177 assume !(1 == ~t1_pc~0); 2824#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 2651#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2652#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2756#L425 assume !(0 != activate_threads_~tmp___0~0); 2859#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2722#L196 assume !(1 == ~t2_pc~0); 2723#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 2732#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2733#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2726#L433 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2727#L433-2 assume !(1 == ~M_E~0); 2822#L374-1 assume !(1 == ~T1_E~0); 2679#L379-1 assume !(1 == ~T2_E~0); 2670#L384-1 assume !(1 == ~E_M~0); 2671#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2816#L394-1 assume !(1 == ~E_2~0); 2817#L545-1 [2021-10-28 08:51:57,621 INFO L793 eck$LassoCheckResult]: Loop: 2817#L545-1 assume !false; 2681#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2677#L311 assume !false; 2697#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2718#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2703#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2826#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2782#L278 assume !(0 != eval_~tmp~0); 2783#L326 start_simulation_~kernel_st~0 := 2; 2715#L216-1 start_simulation_~kernel_st~0 := 3; 2716#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2838#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2801#L341-3 assume !(0 == ~T2_E~0); 2802#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2737#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2738#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2789#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2790#L158-12 assume !(1 == ~m_pc~0); 2809#L158-14 is_master_triggered_~__retres1~0 := 0; 2800#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2760#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2664#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2665#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2632#L177-12 assume !(1 == ~t1_pc~0); 2633#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 2653#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2773#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2713#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2714#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2770#L196-12 assume 1 == ~t2_pc~0; 2854#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2837#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2700#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2701#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2787#L433-14 assume !(1 == ~M_E~0); 2788#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2730#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2731#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2741#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2806#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2654#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2655#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2640#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2843#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2649#L564 assume !(0 == start_simulation_~tmp~3); 2650#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2798#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2669#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2852#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2845#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2846#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 2851#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2827#L577 assume !(0 != start_simulation_~tmp___0~1); 2817#L545-1 [2021-10-28 08:51:57,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,622 INFO L85 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2021-10-28 08:51:57,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,622 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481965561] [2021-10-28 08:51:57,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,623 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,712 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481965561] [2021-10-28 08:51:57,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481965561] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,712 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 08:51:57,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825330644] [2021-10-28 08:51:57,713 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:57,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 2 times [2021-10-28 08:51:57,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,714 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892069446] [2021-10-28 08:51:57,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,715 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,752 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892069446] [2021-10-28 08:51:57,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892069446] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,753 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,753 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801362174] [2021-10-28 08:51:57,754 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:57,754 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:57,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 08:51:57,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 08:51:57,755 INFO L87 Difference]: Start difference. First operand 623 states and 919 transitions. cyclomatic complexity: 298 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:57,875 INFO L93 Difference]: Finished difference Result 1454 states and 2154 transitions. [2021-10-28 08:51:57,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 08:51:57,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1454 states and 2154 transitions. [2021-10-28 08:51:57,891 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1396 [2021-10-28 08:51:57,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1454 states to 1454 states and 2154 transitions. [2021-10-28 08:51:57,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1454 [2021-10-28 08:51:57,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1454 [2021-10-28 08:51:57,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1454 states and 2154 transitions. [2021-10-28 08:51:57,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:57,910 INFO L681 BuchiCegarLoop]: Abstraction has 1454 states and 2154 transitions. [2021-10-28 08:51:57,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1454 states and 2154 transitions. [2021-10-28 08:51:57,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1454 to 674. [2021-10-28 08:51:57,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.4391691394658754) internal successors, (970), 673 states have internal predecessors, (970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:57,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 970 transitions. [2021-10-28 08:51:57,930 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2021-10-28 08:51:57,930 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 970 transitions. [2021-10-28 08:51:57,930 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 08:51:57,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 970 transitions. [2021-10-28 08:51:57,935 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-28 08:51:57,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:57,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:57,937 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,937 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:57,937 INFO L791 eck$LassoCheckResult]: Stem: 4980#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4912#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4765#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4766#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 4886#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4801#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4802#L233-1 assume !(0 == ~M_E~0); 4819#L336-1 assume !(0 == ~T1_E~0); 4879#L341-1 assume !(0 == ~T2_E~0); 4753#L346-1 assume !(0 == ~E_M~0); 4754#L351-1 assume !(0 == ~E_1~0); 4759#L356-1 assume !(0 == ~E_2~0); 4760#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4899#L158 assume !(1 == ~m_pc~0); 4896#L158-2 is_master_triggered_~__retres1~0 := 0; 4897#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4928#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4784#L417 assume !(0 != activate_threads_~tmp~1); 4785#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4926#L177 assume !(1 == ~t1_pc~0); 4927#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 4743#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4744#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4851#L425 assume !(0 != activate_threads_~tmp___0~0); 4968#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4814#L196 assume !(1 == ~t2_pc~0); 4815#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 4826#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4827#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4820#L433 assume !(0 != activate_threads_~tmp___1~0); 4821#L433-2 assume !(1 == ~M_E~0); 4923#L374-1 assume !(1 == ~T1_E~0); 4772#L379-1 assume !(1 == ~T2_E~0); 4763#L384-1 assume !(1 == ~E_M~0); 4764#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4918#L394-1 assume !(1 == ~E_2~0); 4919#L545-1 [2021-10-28 08:51:57,938 INFO L793 eck$LassoCheckResult]: Loop: 4919#L545-1 assume !false; 5146#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5143#L311 assume !false; 4852#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4817#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4800#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4929#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4882#L278 assume !(0 != eval_~tmp~0); 4883#L326 start_simulation_~kernel_st~0 := 2; 5098#L216-1 start_simulation_~kernel_st~0 := 3; 5092#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5090#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5088#L341-3 assume !(0 == ~T2_E~0); 5087#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5086#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5082#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5080#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5078#L158-12 assume !(1 == ~m_pc~0); 5079#L158-14 is_master_triggered_~__retres1~0 := 0; 5322#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5321#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5320#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5319#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5318#L177-12 assume !(1 == ~t1_pc~0); 5287#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 5317#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5316#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5315#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5314#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5313#L196-12 assume !(1 == ~t2_pc~0); 5312#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 5310#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5308#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5306#L433-12 assume !(0 != activate_threads_~tmp___1~0); 5304#L433-14 assume !(1 == ~M_E~0); 5270#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5268#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5266#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5264#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5262#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5260#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5256#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5254#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5250#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5247#L564 assume !(0 == start_simulation_~tmp~3); 5248#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5351#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5346#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5303#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5302#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5300#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 5295#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5292#L577 assume !(0 != start_simulation_~tmp___0~1); 4919#L545-1 [2021-10-28 08:51:57,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,938 INFO L85 PathProgramCache]: Analyzing trace with hash -1974330394, now seen corresponding path program 1 times [2021-10-28 08:51:57,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,939 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857868253] [2021-10-28 08:51:57,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,939 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:57,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:57,979 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:57,979 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857868253] [2021-10-28 08:51:57,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857868253] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:57,979 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:57,979 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:57,980 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745484484] [2021-10-28 08:51:57,980 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:57,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:57,981 INFO L85 PathProgramCache]: Analyzing trace with hash 817558789, now seen corresponding path program 1 times [2021-10-28 08:51:57,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:57,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339582243] [2021-10-28 08:51:57,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:57,982 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:57,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,009 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,010 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339582243] [2021-10-28 08:51:58,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339582243] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,010 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:58,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604151296] [2021-10-28 08:51:58,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 08:51:58,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 08:51:58,012 INFO L87 Difference]: Start difference. First operand 674 states and 970 transitions. cyclomatic complexity: 298 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:58,134 INFO L93 Difference]: Finished difference Result 1102 states and 1558 transitions. [2021-10-28 08:51:58,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 08:51:58,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1102 states and 1558 transitions. [2021-10-28 08:51:58,146 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 994 [2021-10-28 08:51:58,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1102 states to 1102 states and 1558 transitions. [2021-10-28 08:51:58,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1102 [2021-10-28 08:51:58,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1102 [2021-10-28 08:51:58,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1102 states and 1558 transitions. [2021-10-28 08:51:58,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:58,159 INFO L681 BuchiCegarLoop]: Abstraction has 1102 states and 1558 transitions. [2021-10-28 08:51:58,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1102 states and 1558 transitions. [2021-10-28 08:51:58,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1102 to 1080. [2021-10-28 08:51:58,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1080 states, 1080 states have (on average 1.4185185185185185) internal successors, (1532), 1079 states have internal predecessors, (1532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1080 states to 1080 states and 1532 transitions. [2021-10-28 08:51:58,182 INFO L704 BuchiCegarLoop]: Abstraction has 1080 states and 1532 transitions. [2021-10-28 08:51:58,182 INFO L587 BuchiCegarLoop]: Abstraction has 1080 states and 1532 transitions. [2021-10-28 08:51:58,182 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 08:51:58,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1080 states and 1532 transitions. [2021-10-28 08:51:58,190 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 980 [2021-10-28 08:51:58,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:58,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:58,191 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,191 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,192 INFO L791 eck$LassoCheckResult]: Stem: 6774#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6701#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6550#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6551#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 6673#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6587#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6588#L233-1 assume !(0 == ~M_E~0); 6605#L336-1 assume !(0 == ~T1_E~0); 6666#L341-1 assume !(0 == ~T2_E~0); 6537#L346-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6538#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6698#L356-1 assume !(0 == ~E_2~0); 7256#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6686#L158 assume !(1 == ~m_pc~0); 6687#L158-2 is_master_triggered_~__retres1~0 := 0; 7250#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7237#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7238#L417 assume !(0 != activate_threads_~tmp~1); 7231#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7232#L177 assume !(1 == ~t1_pc~0); 7230#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 7229#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7227#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7225#L425 assume !(0 != activate_threads_~tmp___0~0); 7223#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7221#L196 assume !(1 == ~t2_pc~0); 7219#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 7236#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7233#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7210#L433 assume !(0 != activate_threads_~tmp___1~0); 6712#L433-2 assume !(1 == ~M_E~0); 6713#L374-1 assume !(1 == ~T1_E~0); 6557#L379-1 assume !(1 == ~T2_E~0); 6548#L384-1 assume !(1 == ~E_M~0); 6549#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6706#L394-1 assume !(1 == ~E_2~0); 6707#L545-1 [2021-10-28 08:51:58,192 INFO L793 eck$LassoCheckResult]: Loop: 6707#L545-1 assume !false; 7182#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7475#L311 assume !false; 7474#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7172#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7173#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7162#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7163#L278 assume !(0 != eval_~tmp~0); 7469#L326 start_simulation_~kernel_st~0 := 2; 7585#L216-1 start_simulation_~kernel_st~0 := 3; 7584#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7583#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7582#L341-3 assume !(0 == ~T2_E~0); 7581#L346-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6718#L351-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6620#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6676#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6677#L158-12 assume !(1 == ~m_pc~0); 6700#L158-14 is_master_triggered_~__retres1~0 := 0; 6688#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6689#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6542#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6543#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6508#L177-12 assume !(1 == ~t1_pc~0); 6509#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 6530#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6658#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6659#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7531#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7530#L196-12 assume !(1 == ~t2_pc~0); 7526#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 7524#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7522#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7520#L433-12 assume !(0 != activate_threads_~tmp___1~0); 7518#L433-14 assume !(1 == ~M_E~0); 7517#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7513#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7511#L384-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7507#L389-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7504#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7502#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7498#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7495#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7493#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7491#L564 assume !(0 == start_simulation_~tmp~3); 7489#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7487#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7485#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7484#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7483#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7482#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 7481#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7195#L577 assume !(0 != start_simulation_~tmp___0~1); 6707#L545-1 [2021-10-28 08:51:58,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,192 INFO L85 PathProgramCache]: Analyzing trace with hash 335369254, now seen corresponding path program 1 times [2021-10-28 08:51:58,193 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,193 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993652959] [2021-10-28 08:51:58,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,193 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993652959] [2021-10-28 08:51:58,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993652959] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,228 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,228 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 08:51:58,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032405390] [2021-10-28 08:51:58,228 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:58,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,229 INFO L85 PathProgramCache]: Analyzing trace with hash 817558789, now seen corresponding path program 2 times [2021-10-28 08:51:58,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855825937] [2021-10-28 08:51:58,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,230 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,269 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855825937] [2021-10-28 08:51:58,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855825937] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,269 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,269 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:58,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049559042] [2021-10-28 08:51:58,270 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,270 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:58,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:58,271 INFO L87 Difference]: Start difference. First operand 1080 states and 1532 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:58,302 INFO L93 Difference]: Finished difference Result 1051 states and 1463 transitions. [2021-10-28 08:51:58,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:58,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1051 states and 1463 transitions. [2021-10-28 08:51:58,312 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 980 [2021-10-28 08:51:58,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1051 states to 1051 states and 1463 transitions. [2021-10-28 08:51:58,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1051 [2021-10-28 08:51:58,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1051 [2021-10-28 08:51:58,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1051 states and 1463 transitions. [2021-10-28 08:51:58,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:58,325 INFO L681 BuchiCegarLoop]: Abstraction has 1051 states and 1463 transitions. [2021-10-28 08:51:58,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1051 states and 1463 transitions. [2021-10-28 08:51:58,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1051 to 816. [2021-10-28 08:51:58,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 816 states, 816 states have (on average 1.3848039215686274) internal successors, (1130), 815 states have internal predecessors, (1130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 816 states to 816 states and 1130 transitions. [2021-10-28 08:51:58,342 INFO L704 BuchiCegarLoop]: Abstraction has 816 states and 1130 transitions. [2021-10-28 08:51:58,343 INFO L587 BuchiCegarLoop]: Abstraction has 816 states and 1130 transitions. [2021-10-28 08:51:58,343 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 08:51:58,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 816 states and 1130 transitions. [2021-10-28 08:51:58,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 746 [2021-10-28 08:51:58,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:58,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:58,352 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,352 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,352 INFO L791 eck$LassoCheckResult]: Stem: 8889#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8830#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8687#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8688#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 8805#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8721#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8722#L233-1 assume !(0 == ~M_E~0); 8739#L336-1 assume !(0 == ~T1_E~0); 8798#L341-1 assume !(0 == ~T2_E~0); 8675#L346-1 assume !(0 == ~E_M~0); 8676#L351-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8828#L356-1 assume !(0 == ~E_2~0); 9448#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9447#L158 assume !(1 == ~m_pc~0); 9446#L158-2 is_master_triggered_~__retres1~0 := 0; 9445#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9444#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9443#L417 assume !(0 != activate_threads_~tmp~1); 9442#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9441#L177 assume !(1 == ~t1_pc~0); 9440#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 9439#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9438#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9437#L425 assume !(0 != activate_threads_~tmp___0~0); 9436#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9435#L196 assume !(1 == ~t2_pc~0); 9434#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 9450#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9449#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9427#L433 assume !(0 != activate_threads_~tmp___1~0); 9426#L433-2 assume !(1 == ~M_E~0); 9425#L374-1 assume !(1 == ~T1_E~0); 9424#L379-1 assume !(1 == ~T2_E~0); 9423#L384-1 assume !(1 == ~E_M~0); 9422#L389-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8834#L394-1 assume !(1 == ~E_2~0); 8835#L545-1 [2021-10-28 08:51:58,352 INFO L793 eck$LassoCheckResult]: Loop: 8835#L545-1 assume !false; 9311#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9288#L311 assume !false; 9286#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9280#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9278#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9276#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9271#L278 assume !(0 != eval_~tmp~0); 9272#L326 start_simulation_~kernel_st~0 := 2; 9412#L216-1 start_simulation_~kernel_st~0 := 3; 9411#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9410#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9409#L341-3 assume !(0 == ~T2_E~0); 9408#L346-3 assume !(0 == ~E_M~0); 9407#L351-3 assume !(0 == ~E_1~0); 8860#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8808#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8809#L158-12 assume !(1 == ~m_pc~0); 8829#L158-14 is_master_triggered_~__retres1~0 := 0; 8818#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8776#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8679#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8680#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8646#L177-12 assume !(1 == ~t1_pc~0); 8647#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 9362#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9360#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9357#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9355#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9353#L196-12 assume !(1 == ~t2_pc~0); 9349#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 9347#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9345#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9343#L433-12 assume !(0 != activate_threads_~tmp___1~0); 9341#L433-14 assume !(1 == ~M_E~0); 9340#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9336#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9315#L384-3 assume !(1 == ~E_M~0); 9291#L389-3 assume !(1 == ~E_1~0); 9289#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9287#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9284#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9279#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9277#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9274#L564 assume !(0 == start_simulation_~tmp~3); 9275#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9338#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9335#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9334#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9333#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9321#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 9319#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9318#L577 assume !(0 != start_simulation_~tmp___0~1); 8835#L545-1 [2021-10-28 08:51:58,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,353 INFO L85 PathProgramCache]: Analyzing trace with hash -2036370008, now seen corresponding path program 1 times [2021-10-28 08:51:58,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,353 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761737130] [2021-10-28 08:51:58,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,354 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,399 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761737130] [2021-10-28 08:51:58,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761737130] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,399 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:58,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235530876] [2021-10-28 08:51:58,400 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:58,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,401 INFO L85 PathProgramCache]: Analyzing trace with hash -405580411, now seen corresponding path program 1 times [2021-10-28 08:51:58,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,402 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444259067] [2021-10-28 08:51:58,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,402 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,435 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444259067] [2021-10-28 08:51:58,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444259067] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,442 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,443 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:58,443 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572873773] [2021-10-28 08:51:58,443 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,443 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 08:51:58,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 08:51:58,444 INFO L87 Difference]: Start difference. First operand 816 states and 1130 transitions. cyclomatic complexity: 316 Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:58,513 INFO L93 Difference]: Finished difference Result 916 states and 1264 transitions. [2021-10-28 08:51:58,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 08:51:58,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 916 states and 1264 transitions. [2021-10-28 08:51:58,526 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 866 [2021-10-28 08:51:58,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 916 states to 916 states and 1264 transitions. [2021-10-28 08:51:58,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 916 [2021-10-28 08:51:58,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 916 [2021-10-28 08:51:58,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 916 states and 1264 transitions. [2021-10-28 08:51:58,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:58,541 INFO L681 BuchiCegarLoop]: Abstraction has 916 states and 1264 transitions. [2021-10-28 08:51:58,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states and 1264 transitions. [2021-10-28 08:51:58,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 674. [2021-10-28 08:51:58,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.3753709198813056) internal successors, (927), 673 states have internal predecessors, (927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 927 transitions. [2021-10-28 08:51:58,557 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 927 transitions. [2021-10-28 08:51:58,558 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 927 transitions. [2021-10-28 08:51:58,558 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 08:51:58,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 927 transitions. [2021-10-28 08:51:58,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-28 08:51:58,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:58,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:58,564 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,564 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,564 INFO L791 eck$LassoCheckResult]: Stem: 10634#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10573#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10430#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10431#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 10546#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10465#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10466#L233-1 assume !(0 == ~M_E~0); 10483#L336-1 assume !(0 == ~T1_E~0); 10540#L341-1 assume !(0 == ~T2_E~0); 10418#L346-1 assume !(0 == ~E_M~0); 10419#L351-1 assume !(0 == ~E_1~0); 10424#L356-1 assume !(0 == ~E_2~0); 10425#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10558#L158 assume !(1 == ~m_pc~0); 10555#L158-2 is_master_triggered_~__retres1~0 := 0; 10556#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10586#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10447#L417 assume !(0 != activate_threads_~tmp~1); 10448#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10583#L177 assume !(1 == ~t1_pc~0); 10584#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 10408#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10409#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10512#L425 assume !(0 != activate_threads_~tmp___0~0); 10623#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10476#L196 assume !(1 == ~t2_pc~0); 10477#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 10635#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10652#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10484#L433 assume !(0 != activate_threads_~tmp___1~0); 10485#L433-2 assume !(1 == ~M_E~0); 10582#L374-1 assume !(1 == ~T1_E~0); 10437#L379-1 assume !(1 == ~T2_E~0); 10428#L384-1 assume !(1 == ~E_M~0); 10429#L389-1 assume !(1 == ~E_1~0); 10576#L394-1 assume !(1 == ~E_2~0); 10577#L545-1 [2021-10-28 08:51:58,564 INFO L793 eck$LassoCheckResult]: Loop: 10577#L545-1 assume !false; 11001#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10454#L311 assume !false; 10455#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10998#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10997#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10996#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10982#L278 assume !(0 != eval_~tmp~0); 10571#L326 start_simulation_~kernel_st~0 := 2; 10473#L216-1 start_simulation_~kernel_st~0 := 3; 10474#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10600#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10561#L341-3 assume !(0 == ~T2_E~0); 10562#L346-3 assume !(0 == ~E_M~0); 10497#L351-3 assume !(0 == ~E_1~0); 10498#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10547#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10548#L158-12 assume !(1 == ~m_pc~0); 10572#L158-14 is_master_triggered_~__retres1~0 := 0; 10559#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10518#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10422#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10423#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10388#L177-12 assume !(1 == ~t1_pc~0); 10389#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 11032#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10534#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10471#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10472#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10530#L196-12 assume 1 == ~t2_pc~0; 10632#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11028#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11026#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11024#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10614#L433-14 assume !(1 == ~M_E~0); 11021#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10488#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10489#L384-3 assume !(1 == ~E_M~0); 10501#L389-3 assume !(1 == ~E_1~0); 10565#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10412#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10413#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10396#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10637#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11011#L564 assume !(0 == start_simulation_~tmp~3); 11012#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11038#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11036#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11035#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 11034#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11006#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 11005#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 11004#L577 assume !(0 != start_simulation_~tmp___0~1); 10577#L545-1 [2021-10-28 08:51:58,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,565 INFO L85 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2021-10-28 08:51:58,565 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,565 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122148079] [2021-10-28 08:51:58,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,566 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:58,582 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:58,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:58,630 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:58,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,631 INFO L85 PathProgramCache]: Analyzing trace with hash 2002463016, now seen corresponding path program 1 times [2021-10-28 08:51:58,632 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538206525] [2021-10-28 08:51:58,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,634 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,666 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,666 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538206525] [2021-10-28 08:51:58,666 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538206525] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,666 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,666 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:58,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211928163] [2021-10-28 08:51:58,667 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,667 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:58,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:58,668 INFO L87 Difference]: Start difference. First operand 674 states and 927 transitions. cyclomatic complexity: 255 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:58,691 INFO L93 Difference]: Finished difference Result 818 states and 1111 transitions. [2021-10-28 08:51:58,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:58,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 818 states and 1111 transitions. [2021-10-28 08:51:58,705 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 748 [2021-10-28 08:51:58,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 818 states to 818 states and 1111 transitions. [2021-10-28 08:51:58,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 818 [2021-10-28 08:51:58,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 818 [2021-10-28 08:51:58,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 818 states and 1111 transitions. [2021-10-28 08:51:58,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:58,715 INFO L681 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-28 08:51:58,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 818 states and 1111 transitions. [2021-10-28 08:51:58,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 818 to 818. [2021-10-28 08:51:58,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 818 states, 818 states have (on average 1.3581907090464547) internal successors, (1111), 817 states have internal predecessors, (1111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 818 states to 818 states and 1111 transitions. [2021-10-28 08:51:58,733 INFO L704 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-28 08:51:58,733 INFO L587 BuchiCegarLoop]: Abstraction has 818 states and 1111 transitions. [2021-10-28 08:51:58,733 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 08:51:58,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 818 states and 1111 transitions. [2021-10-28 08:51:58,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 748 [2021-10-28 08:51:58,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:58,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:58,740 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,740 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,740 INFO L791 eck$LassoCheckResult]: Stem: 12138#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12072#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11928#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11929#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 12047#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11961#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11962#L233-1 assume 0 == ~M_E~0;~M_E~0 := 1; 11979#L336-1 assume !(0 == ~T1_E~0); 12039#L341-1 assume !(0 == ~T2_E~0); 11916#L346-1 assume !(0 == ~E_M~0); 11917#L351-1 assume !(0 == ~E_1~0); 11922#L356-1 assume !(0 == ~E_2~0); 11923#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12059#L158 assume !(1 == ~m_pc~0); 12056#L158-2 is_master_triggered_~__retres1~0 := 0; 12057#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12083#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11943#L417 assume !(0 != activate_threads_~tmp~1); 11944#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12081#L177 assume !(1 == ~t1_pc~0); 12082#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 11907#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11908#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12011#L425 assume !(0 != activate_threads_~tmp___0~0); 12128#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11972#L196 assume !(1 == ~t2_pc~0); 11973#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 11987#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11988#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11981#L433 assume !(0 != activate_threads_~tmp___1~0); 11982#L433-2 assume 1 == ~M_E~0;~M_E~0 := 2; 12080#L374-1 assume !(1 == ~T1_E~0); 11935#L379-1 assume !(1 == ~T2_E~0); 11926#L384-1 assume !(1 == ~E_M~0); 11927#L389-1 assume !(1 == ~E_1~0); 12075#L394-1 assume !(1 == ~E_2~0); 12076#L545-1 [2021-10-28 08:51:58,740 INFO L793 eck$LassoCheckResult]: Loop: 12076#L545-1 assume !false; 12350#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12326#L311 assume !false; 12349#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11975#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11957#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12084#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12085#L278 assume !(0 != eval_~tmp~0); 12070#L326 start_simulation_~kernel_st~0 := 2; 11969#L216-1 start_simulation_~kernel_st~0 := 3; 11970#L336-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12099#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12061#L341-3 assume !(0 == ~T2_E~0); 12062#L346-3 assume !(0 == ~E_M~0); 11993#L351-3 assume !(0 == ~E_1~0); 11994#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12048#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12049#L158-12 assume !(1 == ~m_pc~0); 12071#L158-14 is_master_triggered_~__retres1~0 := 0; 12060#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12017#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11920#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11921#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12010#L177-12 assume !(1 == ~t1_pc~0); 12518#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 12516#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12514#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12512#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12510#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12506#L196-12 assume !(1 == ~t2_pc~0); 12502#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 12500#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12498#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12495#L433-12 assume !(0 != activate_threads_~tmp___1~0); 12493#L433-14 assume 1 == ~M_E~0;~M_E~0 := 2; 12489#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12487#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12485#L384-3 assume !(1 == ~E_M~0); 12483#L389-3 assume !(1 == ~E_1~0); 12481#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12479#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12475#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12472#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12470#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 12467#L564 assume !(0 == start_simulation_~tmp~3); 12464#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12372#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12367#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12365#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 12105#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12106#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 12115#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12116#L577 assume !(0 != start_simulation_~tmp___0~1); 12076#L545-1 [2021-10-28 08:51:58,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,741 INFO L85 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2021-10-28 08:51:58,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,742 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136937902] [2021-10-28 08:51:58,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,742 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,770 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136937902] [2021-10-28 08:51:58,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136937902] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,770 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,770 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 08:51:58,770 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914985488] [2021-10-28 08:51:58,771 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:58,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1283363331, now seen corresponding path program 1 times [2021-10-28 08:51:58,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,773 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483894474] [2021-10-28 08:51:58,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,773 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,815 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483894474] [2021-10-28 08:51:58,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483894474] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,815 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 08:51:58,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250710270] [2021-10-28 08:51:58,816 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,816 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:58,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:58,817 INFO L87 Difference]: Start difference. First operand 818 states and 1111 transitions. cyclomatic complexity: 295 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 2 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:58,831 INFO L93 Difference]: Finished difference Result 674 states and 913 transitions. [2021-10-28 08:51:58,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:58,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 674 states and 913 transitions. [2021-10-28 08:51:58,837 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-28 08:51:58,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 674 states to 674 states and 913 transitions. [2021-10-28 08:51:58,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 674 [2021-10-28 08:51:58,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 674 [2021-10-28 08:51:58,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 674 states and 913 transitions. [2021-10-28 08:51:58,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:58,844 INFO L681 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-28 08:51:58,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states and 913 transitions. [2021-10-28 08:51:58,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 674. [2021-10-28 08:51:58,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.3545994065281899) internal successors, (913), 673 states have internal predecessors, (913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:58,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 913 transitions. [2021-10-28 08:51:58,857 INFO L704 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-28 08:51:58,857 INFO L587 BuchiCegarLoop]: Abstraction has 674 states and 913 transitions. [2021-10-28 08:51:58,857 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 08:51:58,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 913 transitions. [2021-10-28 08:51:58,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2021-10-28 08:51:58,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:58,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:58,865 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,866 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:58,866 INFO L791 eck$LassoCheckResult]: Stem: 13620#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13564#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13429#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13430#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 13540#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13461#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13462#L233-1 assume !(0 == ~M_E~0); 13480#L336-1 assume !(0 == ~T1_E~0); 13533#L341-1 assume !(0 == ~T2_E~0); 13417#L346-1 assume !(0 == ~E_M~0); 13418#L351-1 assume !(0 == ~E_1~0); 13423#L356-1 assume !(0 == ~E_2~0); 13424#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13552#L158 assume !(1 == ~m_pc~0); 13549#L158-2 is_master_triggered_~__retres1~0 := 0; 13550#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13579#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13444#L417 assume !(0 != activate_threads_~tmp~1); 13445#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13576#L177 assume !(1 == ~t1_pc~0); 13577#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 13407#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13408#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13509#L425 assume !(0 != activate_threads_~tmp___0~0); 13614#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13473#L196 assume !(1 == ~t2_pc~0); 13474#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 13621#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13616#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13481#L433 assume !(0 != activate_threads_~tmp___1~0); 13482#L433-2 assume !(1 == ~M_E~0); 13575#L374-1 assume !(1 == ~T1_E~0); 13436#L379-1 assume !(1 == ~T2_E~0); 13427#L384-1 assume !(1 == ~E_M~0); 13428#L389-1 assume !(1 == ~E_1~0); 13570#L394-1 assume !(1 == ~E_2~0); 13571#L545-1 [2021-10-28 08:51:58,866 INFO L793 eck$LassoCheckResult]: Loop: 13571#L545-1 assume !false; 13877#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13875#L311 assume !false; 13871#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13868#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13736#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13732#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 13729#L278 assume !(0 != eval_~tmp~0); 13730#L326 start_simulation_~kernel_st~0 := 2; 14026#L216-1 start_simulation_~kernel_st~0 := 3; 14025#L336-2 assume !(0 == ~M_E~0); 14024#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14023#L341-3 assume !(0 == ~T2_E~0); 13578#L346-3 assume !(0 == ~E_M~0); 13493#L351-3 assume !(0 == ~E_1~0); 13494#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13541#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13542#L158-12 assume !(1 == ~m_pc~0); 13563#L158-14 is_master_triggered_~__retres1~0 := 0; 13553#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13514#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13421#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13422#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13508#L177-12 assume !(1 == ~t1_pc~0); 13828#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 13964#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13962#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13960#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13958#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13951#L196-12 assume !(1 == ~t2_pc~0); 13947#L196-14 is_transmit2_triggered_~__retres1~2 := 0; 13945#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13943#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13941#L433-12 assume !(0 != activate_threads_~tmp___1~0); 13939#L433-14 assume !(1 == ~M_E~0); 13935#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13933#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13931#L384-3 assume !(1 == ~E_M~0); 13929#L389-3 assume !(1 == ~E_1~0); 13926#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13924#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13920#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13917#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13915#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 13913#L564 assume !(0 == start_simulation_~tmp~3); 13908#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13900#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13897#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13894#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 13892#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13890#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 13888#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 13886#L577 assume !(0 != start_simulation_~tmp___0~1); 13571#L545-1 [2021-10-28 08:51:58,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2021-10-28 08:51:58,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,872 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908498336] [2021-10-28 08:51:58,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,872 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:58,882 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:58,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:58,904 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:58,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:58,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1302973689, now seen corresponding path program 1 times [2021-10-28 08:51:58,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:58,905 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189263748] [2021-10-28 08:51:58,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:58,906 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:58,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:58,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:58,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:58,936 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189263748] [2021-10-28 08:51:58,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189263748] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:58,936 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:58,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 08:51:58,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744856568] [2021-10-28 08:51:58,937 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:58,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:58,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 08:51:58,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 08:51:58,939 INFO L87 Difference]: Start difference. First operand 674 states and 913 transitions. cyclomatic complexity: 241 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:59,026 INFO L93 Difference]: Finished difference Result 1156 states and 1546 transitions. [2021-10-28 08:51:59,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 08:51:59,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1156 states and 1546 transitions. [2021-10-28 08:51:59,037 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1112 [2021-10-28 08:51:59,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1156 states to 1156 states and 1546 transitions. [2021-10-28 08:51:59,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1156 [2021-10-28 08:51:59,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1156 [2021-10-28 08:51:59,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1156 states and 1546 transitions. [2021-10-28 08:51:59,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:59,051 INFO L681 BuchiCegarLoop]: Abstraction has 1156 states and 1546 transitions. [2021-10-28 08:51:59,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states and 1546 transitions. [2021-10-28 08:51:59,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 686. [2021-10-28 08:51:59,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.348396501457726) internal successors, (925), 685 states have internal predecessors, (925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 925 transitions. [2021-10-28 08:51:59,068 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 925 transitions. [2021-10-28 08:51:59,068 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 925 transitions. [2021-10-28 08:51:59,068 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 08:51:59,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 925 transitions. [2021-10-28 08:51:59,072 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 644 [2021-10-28 08:51:59,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:59,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:59,073 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,073 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,073 INFO L791 eck$LassoCheckResult]: Stem: 15485#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 15418#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15276#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15277#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 15391#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15309#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15310#L233-1 assume !(0 == ~M_E~0); 15327#L336-1 assume !(0 == ~T1_E~0); 15386#L341-1 assume !(0 == ~T2_E~0); 15262#L346-1 assume !(0 == ~E_M~0); 15263#L351-1 assume !(0 == ~E_1~0); 15268#L356-1 assume !(0 == ~E_2~0); 15269#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15403#L158 assume !(1 == ~m_pc~0); 15400#L158-2 is_master_triggered_~__retres1~0 := 0; 15401#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15430#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15291#L417 assume !(0 != activate_threads_~tmp~1); 15292#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15428#L177 assume !(1 == ~t1_pc~0); 15429#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 15253#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15254#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15361#L425 assume !(0 != activate_threads_~tmp___0~0); 15474#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15324#L196 assume !(1 == ~t2_pc~0); 15325#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 15486#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15475#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15328#L433 assume !(0 != activate_threads_~tmp___1~0); 15329#L433-2 assume !(1 == ~M_E~0); 15427#L374-1 assume !(1 == ~T1_E~0); 15281#L379-1 assume !(1 == ~T2_E~0); 15272#L384-1 assume !(1 == ~E_M~0); 15273#L389-1 assume !(1 == ~E_1~0); 15421#L394-1 assume !(1 == ~E_2~0); 15422#L545-1 [2021-10-28 08:51:59,074 INFO L793 eck$LassoCheckResult]: Loop: 15422#L545-1 assume !false; 15284#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15279#L311 assume !false; 15298#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15320#L246 assume !(0 == ~m_st~0); 15321#L250 assume !(0 == ~t1_st~0); 15306#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 15308#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15487#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 15895#L278 assume !(0 != eval_~tmp~0); 15414#L326 start_simulation_~kernel_st~0 := 2; 15317#L216-1 start_simulation_~kernel_st~0 := 3; 15318#L336-2 assume !(0 == ~M_E~0); 15446#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15406#L341-3 assume !(0 == ~T2_E~0); 15407#L346-3 assume !(0 == ~E_M~0); 15339#L351-3 assume !(0 == ~E_1~0); 15340#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15392#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15393#L158-12 assume !(1 == ~m_pc~0); 15417#L158-14 is_master_triggered_~__retres1~0 := 0; 15404#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15405#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15266#L417-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15267#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15233#L177-12 assume !(1 == ~t1_pc~0); 15234#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 15255#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15379#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15315#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15316#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15376#L196-12 assume 1 == ~t2_pc~0; 15852#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15850#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15848#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15846#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15845#L433-14 assume !(1 == ~M_E~0); 15844#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15843#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15842#L384-3 assume !(1 == ~E_M~0); 15841#L389-3 assume !(1 == ~E_1~0); 15840#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15839#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15837#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15833#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15830#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 15824#L564 assume !(0 == start_simulation_~tmp~3); 15820#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15402#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15271#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15461#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 15451#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15452#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 15756#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15432#L577 assume !(0 != start_simulation_~tmp___0~1); 15422#L545-1 [2021-10-28 08:51:59,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2021-10-28 08:51:59,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128231373] [2021-10-28 08:51:59,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,075 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,085 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:59,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,110 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:59,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1261903409, now seen corresponding path program 1 times [2021-10-28 08:51:59,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16481064] [2021-10-28 08:51:59,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,113 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:59,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:59,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:59,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16481064] [2021-10-28 08:51:59,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16481064] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:59,191 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:59,191 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 08:51:59,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507489020] [2021-10-28 08:51:59,191 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:59,191 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:59,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 08:51:59,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 08:51:59,193 INFO L87 Difference]: Start difference. First operand 686 states and 925 transitions. cyclomatic complexity: 241 Second operand has 5 states, 5 states have (on average 11.0) internal successors, (55), 5 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:59,295 INFO L93 Difference]: Finished difference Result 928 states and 1244 transitions. [2021-10-28 08:51:59,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 08:51:59,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 928 states and 1244 transitions. [2021-10-28 08:51:59,304 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 886 [2021-10-28 08:51:59,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 928 states to 928 states and 1244 transitions. [2021-10-28 08:51:59,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 928 [2021-10-28 08:51:59,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 928 [2021-10-28 08:51:59,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 928 states and 1244 transitions. [2021-10-28 08:51:59,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:59,314 INFO L681 BuchiCegarLoop]: Abstraction has 928 states and 1244 transitions. [2021-10-28 08:51:59,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 928 states and 1244 transitions. [2021-10-28 08:51:59,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 928 to 692. [2021-10-28 08:51:59,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 692 states, 692 states have (on average 1.323699421965318) internal successors, (916), 691 states have internal predecessors, (916), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 692 states to 692 states and 916 transitions. [2021-10-28 08:51:59,350 INFO L704 BuchiCegarLoop]: Abstraction has 692 states and 916 transitions. [2021-10-28 08:51:59,350 INFO L587 BuchiCegarLoop]: Abstraction has 692 states and 916 transitions. [2021-10-28 08:51:59,350 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 08:51:59,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 692 states and 916 transitions. [2021-10-28 08:51:59,354 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 650 [2021-10-28 08:51:59,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:59,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:59,355 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,355 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,355 INFO L791 eck$LassoCheckResult]: Stem: 17141#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17053#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16903#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16904#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 17025#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16938#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16939#L233-1 assume !(0 == ~M_E~0); 16957#L336-1 assume !(0 == ~T1_E~0); 17019#L341-1 assume !(0 == ~T2_E~0); 16891#L346-1 assume !(0 == ~E_M~0); 16892#L351-1 assume !(0 == ~E_1~0); 16897#L356-1 assume !(0 == ~E_2~0); 16898#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17038#L158 assume !(1 == ~m_pc~0); 17035#L158-2 is_master_triggered_~__retres1~0 := 0; 17036#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17070#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16920#L417 assume !(0 != activate_threads_~tmp~1); 16921#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17067#L177 assume !(1 == ~t1_pc~0); 17068#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 16882#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16883#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16992#L425 assume !(0 != activate_threads_~tmp___0~0); 17121#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16954#L196 assume !(1 == ~t2_pc~0); 16955#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 17144#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17125#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16958#L433 assume !(0 != activate_threads_~tmp___1~0); 16959#L433-2 assume !(1 == ~M_E~0); 17064#L374-1 assume !(1 == ~T1_E~0); 16910#L379-1 assume !(1 == ~T2_E~0); 16901#L384-1 assume !(1 == ~E_M~0); 16902#L389-1 assume !(1 == ~E_1~0); 17058#L394-1 assume !(1 == ~E_2~0); 17059#L545-1 [2021-10-28 08:51:59,356 INFO L793 eck$LassoCheckResult]: Loop: 17059#L545-1 assume !false; 17445#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 17443#L311 assume !false; 17418#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17413#L246 assume !(0 == ~m_st~0); 17414#L250 assume !(0 == ~t1_st~0); 17415#L254 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 17416#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17403#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 17404#L278 assume !(0 != eval_~tmp~0); 17500#L326 start_simulation_~kernel_st~0 := 2; 17499#L216-1 start_simulation_~kernel_st~0 := 3; 17498#L336-2 assume !(0 == ~M_E~0); 17497#L336-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17496#L341-3 assume !(0 == ~T2_E~0); 17495#L346-3 assume !(0 == ~E_M~0); 17494#L351-3 assume !(0 == ~E_1~0); 17092#L356-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17026#L361-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17027#L158-12 assume !(1 == ~m_pc~0); 17052#L158-14 is_master_triggered_~__retres1~0 := 0; 17039#L169-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16997#L170-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16895#L417-12 assume !(0 != activate_threads_~tmp~1); 16896#L417-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16860#L177-12 assume !(1 == ~t1_pc~0); 16861#L177-14 is_transmit1_triggered_~__retres1~1 := 0; 16884#L188-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17011#L189-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16944#L425-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16945#L425-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17008#L196-12 assume 1 == ~t2_pc~0; 17136#L197-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17391#L207-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17388#L208-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17385#L433-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17382#L433-14 assume !(1 == ~M_E~0); 17063#L374-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16962#L379-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16963#L384-3 assume !(1 == ~E_M~0); 16974#L389-3 assume !(1 == ~E_1~0); 17047#L394-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17375#L399-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17372#L246-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17369#L263-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17093#L264-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 17094#L564 assume !(0 == start_simulation_~tmp~3); 17364#L564-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 17466#L246-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 17463#L263-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 17461#L264-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 17459#L519 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17456#L526 stop_simulation_#res := stop_simulation_~__retres2~0; 17453#L527 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 17450#L577 assume !(0 != start_simulation_~tmp___0~1); 17059#L545-1 [2021-10-28 08:51:59,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,356 INFO L85 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2021-10-28 08:51:59,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,356 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080377691] [2021-10-28 08:51:59,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,357 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,365 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:59,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,387 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:59,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,388 INFO L85 PathProgramCache]: Analyzing trace with hash 1536663023, now seen corresponding path program 1 times [2021-10-28 08:51:59,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,388 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678304903] [2021-10-28 08:51:59,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,389 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:59,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:59,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:59,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678304903] [2021-10-28 08:51:59,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678304903] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:59,412 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:59,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:59,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369185791] [2021-10-28 08:51:59,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 08:51:59,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:59,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:59,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:59,417 INFO L87 Difference]: Start difference. First operand 692 states and 916 transitions. cyclomatic complexity: 226 Second operand has 3 states, 3 states have (on average 18.333333333333332) internal successors, (55), 3 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:59,441 INFO L93 Difference]: Finished difference Result 917 states and 1198 transitions. [2021-10-28 08:51:59,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:59,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 917 states and 1198 transitions. [2021-10-28 08:51:59,452 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 873 [2021-10-28 08:51:59,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 917 states to 917 states and 1198 transitions. [2021-10-28 08:51:59,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 917 [2021-10-28 08:51:59,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 917 [2021-10-28 08:51:59,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 917 states and 1198 transitions. [2021-10-28 08:51:59,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:59,462 INFO L681 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-28 08:51:59,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 917 states and 1198 transitions. [2021-10-28 08:51:59,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 917 to 917. [2021-10-28 08:51:59,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 917 states, 917 states have (on average 1.306434023991276) internal successors, (1198), 916 states have internal predecessors, (1198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 917 states to 917 states and 1198 transitions. [2021-10-28 08:51:59,483 INFO L704 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-28 08:51:59,484 INFO L587 BuchiCegarLoop]: Abstraction has 917 states and 1198 transitions. [2021-10-28 08:51:59,484 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 08:51:59,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 917 states and 1198 transitions. [2021-10-28 08:51:59,490 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 873 [2021-10-28 08:51:59,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:59,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:59,491 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,491 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,491 INFO L791 eck$LassoCheckResult]: Stem: 18724#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18659#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18516#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18517#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 18633#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18552#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18553#L233-1 assume !(0 == ~M_E~0); 18571#L336-1 assume !(0 == ~T1_E~0); 18628#L341-1 assume !(0 == ~T2_E~0); 18504#L346-1 assume !(0 == ~E_M~0); 18505#L351-1 assume !(0 == ~E_1~0); 18510#L356-1 assume !(0 == ~E_2~0); 18511#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18646#L158 assume !(1 == ~m_pc~0); 18642#L158-2 is_master_triggered_~__retres1~0 := 0; 18643#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18675#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18534#L417 assume !(0 != activate_threads_~tmp~1); 18535#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18672#L177 assume !(1 == ~t1_pc~0); 18673#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 18494#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18495#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18601#L425 assume !(0 != activate_threads_~tmp___0~0); 18714#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18564#L196 assume !(1 == ~t2_pc~0); 18565#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 18578#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18579#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18572#L433 assume !(0 != activate_threads_~tmp___1~0); 18573#L433-2 assume !(1 == ~M_E~0); 18671#L374-1 assume !(1 == ~T1_E~0); 18523#L379-1 assume !(1 == ~T2_E~0); 18514#L384-1 assume !(1 == ~E_M~0); 18515#L389-1 assume !(1 == ~E_1~0); 18666#L394-1 assume !(1 == ~E_2~0); 18667#L545-1 assume !false; 18768#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 18763#L311 [2021-10-28 08:51:59,491 INFO L793 eck$LassoCheckResult]: Loop: 18763#L311 assume !false; 18761#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18759#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18756#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18754#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 18752#L278 assume 0 != eval_~tmp~0; 18750#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 18747#L286 assume !(0 != eval_~tmp_ndt_1~0); 18748#L283 assume !(0 == ~t1_st~0); 18772#L297 assume !(0 == ~t2_st~0); 18763#L311 [2021-10-28 08:51:59,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2021-10-28 08:51:59,492 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,493 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643486251] [2021-10-28 08:51:59,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,493 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,505 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:59,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,526 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:59,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1924965839, now seen corresponding path program 1 times [2021-10-28 08:51:59,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,527 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24898824] [2021-10-28 08:51:59,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,528 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:59,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,537 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:59,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,538 INFO L85 PathProgramCache]: Analyzing trace with hash -460324554, now seen corresponding path program 1 times [2021-10-28 08:51:59,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,538 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281433343] [2021-10-28 08:51:59,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,539 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:59,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:59,565 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:59,565 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281433343] [2021-10-28 08:51:59,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281433343] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:59,566 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:59,566 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:59,566 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425676682] [2021-10-28 08:51:59,688 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:59,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:59,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:59,689 INFO L87 Difference]: Start difference. First operand 917 states and 1198 transitions. cyclomatic complexity: 284 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:51:59,733 INFO L93 Difference]: Finished difference Result 1643 states and 2118 transitions. [2021-10-28 08:51:59,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:51:59,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1643 states and 2118 transitions. [2021-10-28 08:51:59,745 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1560 [2021-10-28 08:51:59,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1643 states to 1643 states and 2118 transitions. [2021-10-28 08:51:59,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1643 [2021-10-28 08:51:59,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1643 [2021-10-28 08:51:59,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1643 states and 2118 transitions. [2021-10-28 08:51:59,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:51:59,765 INFO L681 BuchiCegarLoop]: Abstraction has 1643 states and 2118 transitions. [2021-10-28 08:51:59,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1643 states and 2118 transitions. [2021-10-28 08:51:59,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1643 to 1591. [2021-10-28 08:51:59,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1591 states, 1591 states have (on average 1.2910119421747328) internal successors, (2054), 1590 states have internal predecessors, (2054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:51:59,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1591 states to 1591 states and 2054 transitions. [2021-10-28 08:51:59,813 INFO L704 BuchiCegarLoop]: Abstraction has 1591 states and 2054 transitions. [2021-10-28 08:51:59,813 INFO L587 BuchiCegarLoop]: Abstraction has 1591 states and 2054 transitions. [2021-10-28 08:51:59,813 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 08:51:59,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1591 states and 2054 transitions. [2021-10-28 08:51:59,822 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-28 08:51:59,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:51:59,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:51:59,823 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,823 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:51:59,824 INFO L791 eck$LassoCheckResult]: Stem: 21305#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21234#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21086#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21087#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 21208#L223-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 21122#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21123#L233-1 assume !(0 == ~M_E~0); 21141#L336-1 assume !(0 == ~T1_E~0); 21202#L341-1 assume !(0 == ~T2_E~0); 21074#L346-1 assume !(0 == ~E_M~0); 21075#L351-1 assume !(0 == ~E_1~0); 21080#L356-1 assume !(0 == ~E_2~0); 21081#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21222#L158 assume !(1 == ~m_pc~0); 21219#L158-2 is_master_triggered_~__retres1~0 := 0; 21220#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21252#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21104#L417 assume !(0 != activate_threads_~tmp~1); 21105#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21246#L177 assume !(1 == ~t1_pc~0); 21247#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 21306#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22188#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22187#L425 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21300#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21138#L196 assume !(1 == ~t2_pc~0); 21139#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 21148#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21149#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21142#L433 assume !(0 != activate_threads_~tmp___1~0); 21143#L433-2 assume !(1 == ~M_E~0); 21245#L374-1 assume !(1 == ~T1_E~0); 21093#L379-1 assume !(1 == ~T2_E~0); 21094#L384-1 assume !(1 == ~E_M~0); 21254#L389-1 assume !(1 == ~E_1~0); 21255#L394-1 assume !(1 == ~E_2~0); 22161#L545-1 assume !false; 22151#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22149#L311 [2021-10-28 08:51:59,826 INFO L793 eck$LassoCheckResult]: Loop: 22149#L311 assume !false; 22147#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22146#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22145#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22143#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 22140#L278 assume 0 != eval_~tmp~0; 22136#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 22131#L286 assume !(0 != eval_~tmp_ndt_1~0); 22132#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 22162#L300 assume !(0 != eval_~tmp_ndt_2~0); 22155#L297 assume !(0 == ~t2_st~0); 22149#L311 [2021-10-28 08:51:59,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,827 INFO L85 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2021-10-28 08:51:59,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,827 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358046393] [2021-10-28 08:51:59,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,828 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:51:59,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:51:59,874 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:51:59,874 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358046393] [2021-10-28 08:51:59,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [358046393] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:51:59,874 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:51:59,875 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 08:51:59,875 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181740372] [2021-10-28 08:51:59,875 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 08:51:59,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:51:59,875 INFO L85 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 1 times [2021-10-28 08:51:59,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:51:59,876 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523535358] [2021-10-28 08:51:59,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:51:59,876 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:51:59,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,880 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:51:59,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:51:59,884 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:51:59,988 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:51:59,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:51:59,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:51:59,989 INFO L87 Difference]: Start difference. First operand 1591 states and 2054 transitions. cyclomatic complexity: 466 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:52:00,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:52:00,003 INFO L93 Difference]: Finished difference Result 1554 states and 2006 transitions. [2021-10-28 08:52:00,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:52:00,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1554 states and 2006 transitions. [2021-10-28 08:52:00,014 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-28 08:52:00,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1554 states to 1554 states and 2006 transitions. [2021-10-28 08:52:00,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1554 [2021-10-28 08:52:00,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1554 [2021-10-28 08:52:00,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1554 states and 2006 transitions. [2021-10-28 08:52:00,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:52:00,033 INFO L681 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-28 08:52:00,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1554 states and 2006 transitions. [2021-10-28 08:52:00,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1554 to 1554. [2021-10-28 08:52:00,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1554 states, 1554 states have (on average 1.2908622908622909) internal successors, (2006), 1553 states have internal predecessors, (2006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:52:00,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 1554 states and 2006 transitions. [2021-10-28 08:52:00,078 INFO L704 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-28 08:52:00,078 INFO L587 BuchiCegarLoop]: Abstraction has 1554 states and 2006 transitions. [2021-10-28 08:52:00,078 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 08:52:00,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1554 states and 2006 transitions. [2021-10-28 08:52:00,085 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1508 [2021-10-28 08:52:00,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:52:00,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:52:00,086 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:52:00,086 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:52:00,087 INFO L791 eck$LassoCheckResult]: Stem: 24444#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24377#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24236#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24237#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 24353#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24271#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24272#L233-1 assume !(0 == ~M_E~0); 24290#L336-1 assume !(0 == ~T1_E~0); 24347#L341-1 assume !(0 == ~T2_E~0); 24224#L346-1 assume !(0 == ~E_M~0); 24225#L351-1 assume !(0 == ~E_1~0); 24230#L356-1 assume !(0 == ~E_2~0); 24231#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24365#L158 assume !(1 == ~m_pc~0); 24362#L158-2 is_master_triggered_~__retres1~0 := 0; 24363#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24392#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 24253#L417 assume !(0 != activate_threads_~tmp~1); 24254#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24389#L177 assume !(1 == ~t1_pc~0); 24390#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 24214#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24215#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 24319#L425 assume !(0 != activate_threads_~tmp___0~0); 24436#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24283#L196 assume !(1 == ~t2_pc~0); 24284#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 24297#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24298#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 24291#L433 assume !(0 != activate_threads_~tmp___1~0); 24292#L433-2 assume !(1 == ~M_E~0); 24388#L374-1 assume !(1 == ~T1_E~0); 24243#L379-1 assume !(1 == ~T2_E~0); 24234#L384-1 assume !(1 == ~E_M~0); 24235#L389-1 assume !(1 == ~E_1~0); 24382#L394-1 assume !(1 == ~E_2~0); 24383#L545-1 assume !false; 25105#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 24989#L311 [2021-10-28 08:52:00,087 INFO L793 eck$LassoCheckResult]: Loop: 24989#L311 assume !false; 24988#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 24880#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 24881#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 24902#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 24901#L278 assume 0 != eval_~tmp~0; 24900#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 24644#L286 assume !(0 != eval_~tmp_ndt_1~0); 24640#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 24636#L300 assume !(0 != eval_~tmp_ndt_2~0); 24638#L297 assume !(0 == ~t2_st~0); 24989#L311 [2021-10-28 08:52:00,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2021-10-28 08:52:00,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,088 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319313503] [2021-10-28 08:52:00,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,088 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,097 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:52:00,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,112 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:52:00,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,113 INFO L85 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 2 times [2021-10-28 08:52:00,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881687803] [2021-10-28 08:52:00,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,113 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,117 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:52:00,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,123 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:52:00,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,124 INFO L85 PathProgramCache]: Analyzing trace with hash -1385264103, now seen corresponding path program 1 times [2021-10-28 08:52:00,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,124 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786939568] [2021-10-28 08:52:00,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,124 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 08:52:00,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 08:52:00,158 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 08:52:00,158 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786939568] [2021-10-28 08:52:00,158 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786939568] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 08:52:00,158 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 08:52:00,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 08:52:00,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984015130] [2021-10-28 08:52:00,251 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 08:52:00,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 08:52:00,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 08:52:00,252 INFO L87 Difference]: Start difference. First operand 1554 states and 2006 transitions. cyclomatic complexity: 455 Second operand has 3 states, 2 states have (on average 24.5) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:52:00,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 08:52:00,298 INFO L93 Difference]: Finished difference Result 2438 states and 3112 transitions. [2021-10-28 08:52:00,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 08:52:00,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2438 states and 3112 transitions. [2021-10-28 08:52:00,316 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2388 [2021-10-28 08:52:00,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2438 states to 2438 states and 3112 transitions. [2021-10-28 08:52:00,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2438 [2021-10-28 08:52:00,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2438 [2021-10-28 08:52:00,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2438 states and 3112 transitions. [2021-10-28 08:52:00,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 08:52:00,381 INFO L681 BuchiCegarLoop]: Abstraction has 2438 states and 3112 transitions. [2021-10-28 08:52:00,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states and 3112 transitions. [2021-10-28 08:52:00,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2390. [2021-10-28 08:52:00,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2390 states, 2390 states have (on average 1.2820083682008367) internal successors, (3064), 2389 states have internal predecessors, (3064), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 08:52:00,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2390 states to 2390 states and 3064 transitions. [2021-10-28 08:52:00,437 INFO L704 BuchiCegarLoop]: Abstraction has 2390 states and 3064 transitions. [2021-10-28 08:52:00,437 INFO L587 BuchiCegarLoop]: Abstraction has 2390 states and 3064 transitions. [2021-10-28 08:52:00,437 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 08:52:00,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2390 states and 3064 transitions. [2021-10-28 08:52:00,448 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2340 [2021-10-28 08:52:00,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 08:52:00,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 08:52:00,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:52:00,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 08:52:00,449 INFO L791 eck$LassoCheckResult]: Stem: 28462#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 28387#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28237#L508 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28238#L216 assume 1 == ~m_i~0;~m_st~0 := 0; 28360#L223-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28272#L228-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28273#L233-1 assume !(0 == ~M_E~0); 28291#L336-1 assume !(0 == ~T1_E~0); 28354#L341-1 assume !(0 == ~T2_E~0); 28225#L346-1 assume !(0 == ~E_M~0); 28226#L351-1 assume !(0 == ~E_1~0); 28231#L356-1 assume !(0 == ~E_2~0); 28232#L361-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28372#L158 assume !(1 == ~m_pc~0); 28369#L158-2 is_master_triggered_~__retres1~0 := 0; 28370#L169 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28404#L170 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 28254#L417 assume !(0 != activate_threads_~tmp~1); 28255#L417-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28401#L177 assume !(1 == ~t1_pc~0); 28402#L177-2 is_transmit1_triggered_~__retres1~1 := 0; 28214#L188 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28215#L189 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28322#L425 assume !(0 != activate_threads_~tmp___0~0); 28451#L425-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28284#L196 assume !(1 == ~t2_pc~0); 28285#L196-2 is_transmit2_triggered_~__retres1~2 := 0; 28298#L207 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28299#L208 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28292#L433 assume !(0 != activate_threads_~tmp___1~0); 28293#L433-2 assume !(1 == ~M_E~0); 28398#L374-1 assume !(1 == ~T1_E~0); 28243#L379-1 assume !(1 == ~T2_E~0); 28235#L384-1 assume !(1 == ~E_M~0); 28236#L389-1 assume !(1 == ~E_1~0); 28392#L394-1 assume !(1 == ~E_2~0); 28393#L545-1 assume !false; 29509#L546 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29507#L311 [2021-10-28 08:52:00,449 INFO L793 eck$LassoCheckResult]: Loop: 29507#L311 assume !false; 29505#L274 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29502#L246 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29496#L263 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29493#L264 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 29489#L278 assume 0 != eval_~tmp~0; 29304#L278-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 29301#L286 assume !(0 != eval_~tmp_ndt_1~0); 29298#L283 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 29239#L300 assume !(0 != eval_~tmp_ndt_2~0); 29240#L297 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 29510#L314 assume !(0 != eval_~tmp_ndt_3~0); 29507#L311 [2021-10-28 08:52:00,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,450 INFO L85 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2021-10-28 08:52:00,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241418567] [2021-10-28 08:52:00,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,452 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,463 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:52:00,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,489 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:52:00,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,489 INFO L85 PathProgramCache]: Analyzing trace with hash 1235481233, now seen corresponding path program 1 times [2021-10-28 08:52:00,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111853902] [2021-10-28 08:52:00,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,490 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,494 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:52:00,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,499 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:52:00,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 08:52:00,500 INFO L85 PathProgramCache]: Analyzing trace with hash 6483030, now seen corresponding path program 1 times [2021-10-28 08:52:00,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 08:52:00,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409499520] [2021-10-28 08:52:00,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 08:52:00,501 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 08:52:00,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,519 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 08:52:00,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 08:52:00,539 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 08:52:01,861 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 08:52:01 BoogieIcfgContainer [2021-10-28 08:52:01,861 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 08:52:01,862 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 08:52:01,862 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 08:52:01,862 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 08:52:01,862 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 08:51:56" (3/4) ... [2021-10-28 08:52:01,865 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 08:52:01,911 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/witness.graphml [2021-10-28 08:52:01,911 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 08:52:01,913 INFO L168 Benchmark]: Toolchain (without parser) took 7102.20 ms. Allocated memory was 163.6 MB in the beginning and 205.5 MB in the end (delta: 41.9 MB). Free memory was 133.5 MB in the beginning and 63.0 MB in the end (delta: 70.5 MB). Peak memory consumption was 111.8 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,913 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 96.5 MB. Free memory is still 51.5 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 08:52:01,914 INFO L168 Benchmark]: CACSL2BoogieTranslator took 351.68 ms. Allocated memory is still 163.6 MB. Free memory was 133.1 MB in the beginning and 135.5 MB in the end (delta: -2.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,914 INFO L168 Benchmark]: Boogie Procedure Inliner took 63.48 ms. Allocated memory is still 163.6 MB. Free memory was 135.5 MB in the beginning and 132.5 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,915 INFO L168 Benchmark]: Boogie Preprocessor took 50.09 ms. Allocated memory is still 163.6 MB. Free memory was 132.5 MB in the beginning and 130.4 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,915 INFO L168 Benchmark]: RCFGBuilder took 882.50 ms. Allocated memory is still 163.6 MB. Free memory was 129.9 MB in the beginning and 106.2 MB in the end (delta: 23.7 MB). Peak memory consumption was 25.2 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,915 INFO L168 Benchmark]: BuchiAutomizer took 5697.39 ms. Allocated memory was 163.6 MB in the beginning and 205.5 MB in the end (delta: 41.9 MB). Free memory was 105.7 MB in the beginning and 66.1 MB in the end (delta: 39.6 MB). Peak memory consumption was 83.5 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,916 INFO L168 Benchmark]: Witness Printer took 49.90 ms. Allocated memory is still 205.5 MB. Free memory was 66.1 MB in the beginning and 63.0 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 08:52:01,918 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 96.5 MB. Free memory is still 51.5 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 351.68 ms. Allocated memory is still 163.6 MB. Free memory was 133.1 MB in the beginning and 135.5 MB in the end (delta: -2.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 63.48 ms. Allocated memory is still 163.6 MB. Free memory was 135.5 MB in the beginning and 132.5 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 50.09 ms. Allocated memory is still 163.6 MB. Free memory was 132.5 MB in the beginning and 130.4 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 882.50 ms. Allocated memory is still 163.6 MB. Free memory was 129.9 MB in the beginning and 106.2 MB in the end (delta: 23.7 MB). Peak memory consumption was 25.2 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 5697.39 ms. Allocated memory was 163.6 MB in the beginning and 205.5 MB in the end (delta: 41.9 MB). Free memory was 105.7 MB in the beginning and 66.1 MB in the end (delta: 39.6 MB). Peak memory consumption was 83.5 MB. Max. memory is 16.1 GB. * Witness Printer took 49.90 ms. Allocated memory is still 205.5 MB. Free memory was 66.1 MB in the beginning and 63.0 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2390 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 3.4s. Construction of modules took 0.4s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 16 MinimizatonAttempts, 2273 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 2390 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5205 SDtfs, 6133 SDslu, 4842 SDs, 0 SdLazy, 453 SolverSat, 162 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 273]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=21807} State at position 1 is {NULL=0, token=0, NULL=21807, tmp=1, __retres1=0, kernel_st=1, t2_st=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@374691ad=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f62cbc=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12b1ae=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@62fb64f0=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17e7739a=0, NULL=21810, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=21809, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=21808, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@adc08a=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7db501f1=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7b75ddd3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2454b27b=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 273]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int M_E = 2; [L26] int T1_E = 2; [L27] int T2_E = 2; [L28] int E_M = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L35] int token ; [L37] int local ; [L590] int __retres1 ; [L504] m_i = 1 [L505] t1_i = 1 [L506] t2_i = 1 [L531] int kernel_st ; [L532] int tmp ; [L533] int tmp___0 ; [L537] kernel_st = 0 [L223] COND TRUE m_i == 1 [L224] m_st = 0 [L228] COND TRUE t1_i == 1 [L229] t1_st = 0 [L233] COND TRUE t2_i == 1 [L234] t2_st = 0 [L336] COND FALSE !(M_E == 0) [L341] COND FALSE !(T1_E == 0) [L346] COND FALSE !(T2_E == 0) [L351] COND FALSE !(E_M == 0) [L356] COND FALSE !(E_1 == 0) [L361] COND FALSE !(E_2 == 0) [L409] int tmp ; [L410] int tmp___0 ; [L411] int tmp___1 ; [L155] int __retres1 ; [L158] COND FALSE !(m_pc == 1) [L168] __retres1 = 0 [L170] return (__retres1); [L415] tmp = is_master_triggered() [L417] COND FALSE !(\read(tmp)) [L174] int __retres1 ; [L177] COND FALSE !(t1_pc == 1) [L187] __retres1 = 0 [L189] return (__retres1); [L423] tmp___0 = is_transmit1_triggered() [L425] COND FALSE !(\read(tmp___0)) [L193] int __retres1 ; [L196] COND FALSE !(t2_pc == 1) [L206] __retres1 = 0 [L208] return (__retres1); [L431] tmp___1 = is_transmit2_triggered() [L433] COND FALSE !(\read(tmp___1)) [L374] COND FALSE !(M_E == 1) [L379] COND FALSE !(T1_E == 1) [L384] COND FALSE !(T2_E == 1) [L389] COND FALSE !(E_M == 1) [L394] COND FALSE !(E_1 == 1) [L399] COND FALSE !(E_2 == 1) [L545] COND TRUE 1 [L548] kernel_st = 1 [L269] int tmp ; Loop: [L273] COND TRUE 1 [L243] int __retres1 ; [L246] COND TRUE m_st == 0 [L247] __retres1 = 1 [L264] return (__retres1); [L276] tmp = exists_runnable_thread() [L278] COND TRUE \read(tmp) [L283] COND TRUE m_st == 0 [L284] int tmp_ndt_1; [L285] tmp_ndt_1 = __VERIFIER_nondet_int() [L286] COND FALSE !(\read(tmp_ndt_1)) [L297] COND TRUE t1_st == 0 [L298] int tmp_ndt_2; [L299] tmp_ndt_2 = __VERIFIER_nondet_int() [L300] COND FALSE !(\read(tmp_ndt_2)) [L311] COND TRUE t2_st == 0 [L312] int tmp_ndt_3; [L313] tmp_ndt_3 = __VERIFIER_nondet_int() [L314] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 08:52:01,980 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d896df86-07a3-4467-ac00-12eeb870341c/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...