./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash baf2862afdca861ecfab5536f844964e557a2feed6de3725a6fb79b602497014 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 09:37:52,561 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 09:37:52,565 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 09:37:52,652 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 09:37:52,656 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 09:37:52,659 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 09:37:52,661 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 09:37:52,665 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 09:37:52,668 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 09:37:52,670 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 09:37:52,672 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 09:37:52,674 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 09:37:52,675 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 09:37:52,677 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 09:37:52,680 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 09:37:52,682 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 09:37:52,684 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 09:37:52,685 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 09:37:52,688 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 09:37:52,692 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 09:37:52,694 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 09:37:52,696 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 09:37:52,699 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 09:37:52,700 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 09:37:52,705 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 09:37:52,706 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 09:37:52,707 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 09:37:52,708 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 09:37:52,709 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 09:37:52,711 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 09:37:52,711 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 09:37:52,713 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 09:37:52,714 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 09:37:52,716 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 09:37:52,718 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 09:37:52,718 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 09:37:52,719 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 09:37:52,720 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 09:37:52,721 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 09:37:52,722 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 09:37:52,723 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 09:37:52,725 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 09:37:52,759 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 09:37:52,759 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 09:37:52,760 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 09:37:52,760 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 09:37:52,761 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 09:37:52,762 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 09:37:52,762 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 09:37:52,763 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 09:37:52,763 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 09:37:52,763 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 09:37:52,764 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 09:37:52,764 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 09:37:52,764 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 09:37:52,765 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 09:37:52,765 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 09:37:52,765 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 09:37:52,765 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 09:37:52,766 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 09:37:52,766 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 09:37:52,766 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 09:37:52,767 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 09:37:52,767 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 09:37:52,767 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 09:37:52,767 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 09:37:52,768 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 09:37:52,768 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 09:37:52,768 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 09:37:52,769 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 09:37:52,769 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 09:37:52,769 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 09:37:52,770 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 09:37:52,770 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 09:37:52,772 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 09:37:52,772 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> baf2862afdca861ecfab5536f844964e557a2feed6de3725a6fb79b602497014 [2021-10-28 09:37:53,074 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 09:37:53,105 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 09:37:53,108 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 09:37:53,111 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 09:37:53,113 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 09:37:53,115 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-10-28 09:37:53,206 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/data/99985c9c6/08464f55e3254727ab0289c746849072/FLAG00f7aa964 [2021-10-28 09:37:53,873 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 09:37:53,882 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-10-28 09:37:53,901 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/data/99985c9c6/08464f55e3254727ab0289c746849072/FLAG00f7aa964 [2021-10-28 09:37:54,197 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/data/99985c9c6/08464f55e3254727ab0289c746849072 [2021-10-28 09:37:54,200 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 09:37:54,202 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 09:37:54,204 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 09:37:54,204 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 09:37:54,209 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 09:37:54,210 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,212 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b25da71 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54, skipping insertion in model container [2021-10-28 09:37:54,212 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,221 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 09:37:54,267 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 09:37:54,515 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/sv-benchmarks/c/systemc/transmitter.02.cil.c[401,414] [2021-10-28 09:37:54,597 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:37:54,613 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 09:37:54,638 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/sv-benchmarks/c/systemc/transmitter.02.cil.c[401,414] [2021-10-28 09:37:54,707 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:37:54,728 INFO L208 MainTranslator]: Completed translation [2021-10-28 09:37:54,728 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54 WrapperNode [2021-10-28 09:37:54,729 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 09:37:54,730 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 09:37:54,730 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 09:37:54,730 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 09:37:54,737 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,748 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,807 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 09:37:54,807 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 09:37:54,808 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 09:37:54,808 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 09:37:54,818 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,818 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,824 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,824 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,837 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,863 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,867 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,882 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 09:37:54,883 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 09:37:54,883 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 09:37:54,883 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 09:37:54,893 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (1/1) ... [2021-10-28 09:37:54,918 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:37:54,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:37:54,946 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:37:54,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 09:37:55,016 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 09:37:55,017 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 09:37:55,017 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 09:37:55,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 09:37:55,857 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 09:37:55,857 INFO L299 CfgBuilder]: Removed 94 assume(true) statements. [2021-10-28 09:37:55,860 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:37:55 BoogieIcfgContainer [2021-10-28 09:37:55,860 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 09:37:55,861 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 09:37:55,861 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 09:37:55,865 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 09:37:55,865 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:37:55,866 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 09:37:54" (1/3) ... [2021-10-28 09:37:55,867 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fff4238 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:37:55, skipping insertion in model container [2021-10-28 09:37:55,867 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:37:55,867 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:37:54" (2/3) ... [2021-10-28 09:37:55,868 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fff4238 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:37:55, skipping insertion in model container [2021-10-28 09:37:55,868 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:37:55,868 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:37:55" (3/3) ... [2021-10-28 09:37:55,869 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2021-10-28 09:37:55,910 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 09:37:55,911 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 09:37:55,911 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 09:37:55,911 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 09:37:55,911 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 09:37:55,911 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 09:37:55,911 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 09:37:55,911 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 09:37:55,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:55,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-10-28 09:37:55,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:55,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:55,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:55,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:55,997 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 09:37:55,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:56,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-10-28 09:37:56,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:56,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:56,013 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,021 INFO L791 eck$LassoCheckResult]: Stem: 167#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 62#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 146#L483true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 50#L206true assume !(1 == ~m_i~0);~m_st~0 := 2; 164#L213-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 65#L218-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6#L223-1true assume !(0 == ~M_E~0); 34#L326-1true assume !(0 == ~T1_E~0); 38#L331-1true assume !(0 == ~T2_E~0); 8#L336-1true assume !(0 == ~E_1~0); 188#L341-1true assume !(0 == ~E_2~0); 33#L346-1true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45#L148true assume !(1 == ~m_pc~0); 57#L148-2true is_master_triggered_~__retres1~0 := 0; 103#L159true is_master_triggered_#res := is_master_triggered_~__retres1~0; 128#L160true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 179#L397true assume !(0 != activate_threads_~tmp~1); 23#L397-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27#L167true assume 1 == ~t1_pc~0; 7#L168true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 43#L178true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 177#L179true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114#L405true assume !(0 != activate_threads_~tmp___0~0); 91#L405-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 92#L186true assume !(1 == ~t2_pc~0); 12#L186-2true is_transmit2_triggered_~__retres1~2 := 0; 104#L197true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 99#L198true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 180#L413true assume !(0 != activate_threads_~tmp___1~0); 133#L413-2true assume !(1 == ~M_E~0); 123#L359-1true assume !(1 == ~T1_E~0); 61#L364-1true assume !(1 == ~T2_E~0); 70#L369-1true assume !(1 == ~E_1~0); 142#L374-1true assume !(1 == ~E_2~0); 21#L520-1true [2021-10-28 09:37:56,022 INFO L793 eck$LassoCheckResult]: Loop: 21#L520-1true assume !false; 132#L521true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 125#L301true assume false; 159#L316true start_simulation_~kernel_st~0 := 2; 117#L206-1true start_simulation_~kernel_st~0 := 3; 22#L326-2true assume 0 == ~M_E~0;~M_E~0 := 1; 175#L326-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 74#L331-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 15#L336-3true assume 0 == ~E_1~0;~E_1~0 := 1; 26#L341-3true assume !(0 == ~E_2~0); 79#L346-3true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53#L148-9true assume 1 == ~m_pc~0; 63#L149-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 155#L159-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 193#L160-3true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 190#L397-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 47#L397-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 136#L167-9true assume !(1 == ~t1_pc~0); 169#L167-11true is_transmit1_triggered_~__retres1~1 := 0; 59#L178-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9#L179-3true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 185#L405-9true assume !(0 != activate_threads_~tmp___0~0); 30#L405-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48#L186-9true assume 1 == ~t2_pc~0; 170#L187-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 77#L197-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145#L198-3true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 56#L413-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41#L413-11true assume 1 == ~M_E~0;~M_E~0 := 2; 144#L359-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 113#L364-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 111#L369-3true assume !(1 == ~E_1~0); 71#L374-3true assume 1 == ~E_2~0;~E_2~0 := 2; 101#L379-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 192#L236-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 32#L253-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 14#L254-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 72#L539true assume !(0 == start_simulation_~tmp~3); 75#L539-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 84#L236-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 181#L253-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 42#L254-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 110#L494true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 68#L501true stop_simulation_#res := stop_simulation_~__retres2~0; 64#L502true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 66#L552true assume !(0 != start_simulation_~tmp___0~1); 21#L520-1true [2021-10-28 09:37:56,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2021-10-28 09:37:56,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141521654] [2021-10-28 09:37:56,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,043 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,320 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,320 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141521654] [2021-10-28 09:37:56,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141521654] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,322 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:56,326 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619112674] [2021-10-28 09:37:56,337 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:37:56,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1231104429, now seen corresponding path program 1 times [2021-10-28 09:37:56,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,342 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542499743] [2021-10-28 09:37:56,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,343 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,384 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,385 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542499743] [2021-10-28 09:37:56,385 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542499743] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,385 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:37:56,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386778447] [2021-10-28 09:37:56,391 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:56,392 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:56,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:56,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:56,413 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:56,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:56,479 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2021-10-28 09:37:56,479 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:56,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2021-10-28 09:37:56,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 09:37:56,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2021-10-28 09:37:56,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-10-28 09:37:56,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-10-28 09:37:56,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2021-10-28 09:37:56,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:56,514 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 09:37:56,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2021-10-28 09:37:56,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-10-28 09:37:56,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.510752688172043) internal successors, (281), 185 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:56,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2021-10-28 09:37:56,556 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 09:37:56,557 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 09:37:56,557 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 09:37:56,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2021-10-28 09:37:56,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 09:37:56,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:56,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:56,562 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,563 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,563 INFO L791 eck$LassoCheckResult]: Stem: 574#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 493#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 494#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 471#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 495#L218-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 396#L223-1 assume !(0 == ~M_E~0); 397#L326-1 assume !(0 == ~T1_E~0); 450#L331-1 assume !(0 == ~T2_E~0); 403#L336-1 assume !(0 == ~E_1~0); 404#L341-1 assume !(0 == ~E_2~0); 447#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 448#L148 assume !(1 == ~m_pc~0); 462#L148-2 is_master_triggered_~__retres1~0 := 0; 484#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 543#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 560#L397 assume !(0 != activate_threads_~tmp~1); 432#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 433#L167 assume 1 == ~t1_pc~0; 398#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 399#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 461#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 552#L405 assume !(0 != activate_threads_~tmp___0~0); 526#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 527#L186 assume !(1 == ~t2_pc~0); 409#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 410#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 536#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 537#L413 assume !(0 != activate_threads_~tmp___1~0); 562#L413-2 assume !(1 == ~M_E~0); 558#L359-1 assume !(1 == ~T1_E~0); 488#L364-1 assume !(1 == ~T2_E~0); 489#L369-1 assume !(1 == ~E_1~0); 500#L374-1 assume !(1 == ~E_2~0); 428#L520-1 [2021-10-28 09:37:56,564 INFO L793 eck$LassoCheckResult]: Loop: 428#L520-1 assume !false; 429#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 530#L301 assume !false; 523#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 518#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 412#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 507#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 440#L268 assume !(0 != eval_~tmp~0); 442#L316 start_simulation_~kernel_st~0 := 2; 555#L206-1 start_simulation_~kernel_st~0 := 3; 430#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 431#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 504#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 418#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 419#L341-3 assume !(0 == ~E_2~0); 438#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 476#L148-9 assume 1 == ~m_pc~0; 477#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 490#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 571#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 576#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 465#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 466#L167-9 assume 1 == ~t1_pc~0; 541#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 485#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 401#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 402#L405-9 assume !(0 != activate_threads_~tmp___0~0); 444#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 445#L186-9 assume 1 == ~t2_pc~0; 467#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 406#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 506#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 482#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 455#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 456#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 551#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 549#L369-3 assume !(1 == ~E_1~0); 501#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 502#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 538#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 446#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 413#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 414#L539 assume !(0 == start_simulation_~tmp~3); 499#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 505#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 470#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 457#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 458#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 497#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 491#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 492#L552 assume !(0 != start_simulation_~tmp___0~1); 428#L520-1 [2021-10-28 09:37:56,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,565 INFO L85 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2021-10-28 09:37:56,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,566 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818528244] [2021-10-28 09:37:56,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,567 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,617 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818528244] [2021-10-28 09:37:56,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818528244] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,617 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,618 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:56,618 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714205405] [2021-10-28 09:37:56,618 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:37:56,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,619 INFO L85 PathProgramCache]: Analyzing trace with hash -2087706241, now seen corresponding path program 1 times [2021-10-28 09:37:56,620 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,620 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511896619] [2021-10-28 09:37:56,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,733 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,739 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511896619] [2021-10-28 09:37:56,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511896619] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,740 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:56,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047752140] [2021-10-28 09:37:56,741 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:56,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:56,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:56,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:56,743 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:56,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:56,774 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2021-10-28 09:37:56,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:56,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2021-10-28 09:37:56,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 09:37:56,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2021-10-28 09:37:56,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-10-28 09:37:56,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-10-28 09:37:56,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2021-10-28 09:37:56,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:56,783 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 09:37:56,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2021-10-28 09:37:56,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-10-28 09:37:56,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.5053763440860215) internal successors, (280), 185 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:56,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2021-10-28 09:37:56,803 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 09:37:56,803 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 09:37:56,803 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 09:37:56,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2021-10-28 09:37:56,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 09:37:56,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:56,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:56,808 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,808 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:56,808 INFO L791 eck$LassoCheckResult]: Stem: 953#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 869#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 870#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 848#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 849#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 775#L223-1 assume !(0 == ~M_E~0); 776#L326-1 assume !(0 == ~T1_E~0); 828#L331-1 assume !(0 == ~T2_E~0); 780#L336-1 assume !(0 == ~E_1~0); 781#L341-1 assume !(0 == ~E_2~0); 826#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 827#L148 assume !(1 == ~m_pc~0); 841#L148-2 is_master_triggered_~__retres1~0 := 0; 862#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 920#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 939#L397 assume !(0 != activate_threads_~tmp~1); 811#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 812#L167 assume 1 == ~t1_pc~0; 777#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 778#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 838#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 931#L405 assume !(0 != activate_threads_~tmp___0~0); 905#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 906#L186 assume !(1 == ~t2_pc~0); 788#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 789#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 913#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 914#L413 assume !(0 != activate_threads_~tmp___1~0); 941#L413-2 assume !(1 == ~M_E~0); 937#L359-1 assume !(1 == ~T1_E~0); 867#L364-1 assume !(1 == ~T2_E~0); 868#L369-1 assume !(1 == ~E_1~0); 879#L374-1 assume !(1 == ~E_2~0); 807#L520-1 [2021-10-28 09:37:56,808 INFO L793 eck$LassoCheckResult]: Loop: 807#L520-1 assume !false; 808#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 909#L301 assume !false; 902#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 897#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 791#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 885#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 819#L268 assume !(0 != eval_~tmp~0); 821#L316 start_simulation_~kernel_st~0 := 2; 932#L206-1 start_simulation_~kernel_st~0 := 3; 809#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 810#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 883#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 797#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 798#L341-3 assume !(0 == ~E_2~0); 817#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 855#L148-9 assume 1 == ~m_pc~0; 856#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 871#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 950#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 955#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 844#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 845#L167-9 assume 1 == ~t1_pc~0; 921#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 864#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 782#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 783#L405-9 assume !(0 != activate_threads_~tmp___0~0); 823#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 824#L186-9 assume !(1 == ~t2_pc~0); 784#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 785#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 886#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 861#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 834#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 835#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 930#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 928#L369-3 assume !(1 == ~E_1~0); 880#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 881#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 917#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 825#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 792#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 793#L539 assume !(0 == start_simulation_~tmp~3); 878#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 884#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 851#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 836#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 837#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 876#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 872#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 873#L552 assume !(0 != start_simulation_~tmp___0~1); 807#L520-1 [2021-10-28 09:37:56,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,809 INFO L85 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2021-10-28 09:37:56,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,810 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593255877] [2021-10-28 09:37:56,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,810 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,879 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,880 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593255877] [2021-10-28 09:37:56,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593255877] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,880 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,880 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:56,880 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779318584] [2021-10-28 09:37:56,881 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:37:56,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:56,882 INFO L85 PathProgramCache]: Analyzing trace with hash -1307725312, now seen corresponding path program 1 times [2021-10-28 09:37:56,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:56,882 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671624122] [2021-10-28 09:37:56,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:56,883 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:56,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:56,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:56,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:56,930 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671624122] [2021-10-28 09:37:56,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671624122] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:56,931 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:56,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:56,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348262890] [2021-10-28 09:37:56,932 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:56,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:56,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:37:56,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:37:56,933 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:57,115 INFO L93 Difference]: Finished difference Result 441 states and 644 transitions. [2021-10-28 09:37:57,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:37:57,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 644 transitions. [2021-10-28 09:37:57,124 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 377 [2021-10-28 09:37:57,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 441 states and 644 transitions. [2021-10-28 09:37:57,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 [2021-10-28 09:37:57,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 [2021-10-28 09:37:57,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 441 states and 644 transitions. [2021-10-28 09:37:57,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:57,146 INFO L681 BuchiCegarLoop]: Abstraction has 441 states and 644 transitions. [2021-10-28 09:37:57,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states and 644 transitions. [2021-10-28 09:37:57,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 403. [2021-10-28 09:37:57,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 403 states, 403 states have (on average 1.478908188585608) internal successors, (596), 402 states have internal predecessors, (596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 596 transitions. [2021-10-28 09:37:57,174 INFO L704 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-10-28 09:37:57,174 INFO L587 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-10-28 09:37:57,174 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 09:37:57,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 596 transitions. [2021-10-28 09:37:57,178 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2021-10-28 09:37:57,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:57,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:57,181 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,181 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,181 INFO L791 eck$LassoCheckResult]: Stem: 1607#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1509#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1510#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1486#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 1487#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1511#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1412#L223-1 assume !(0 == ~M_E~0); 1413#L326-1 assume !(0 == ~T1_E~0); 1465#L331-1 assume !(0 == ~T2_E~0); 1416#L336-1 assume !(0 == ~E_1~0); 1417#L341-1 assume !(0 == ~E_2~0); 1463#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1464#L148 assume !(1 == ~m_pc~0); 1478#L148-2 is_master_triggered_~__retres1~0 := 0; 1498#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1564#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1582#L397 assume !(0 != activate_threads_~tmp~1); 1445#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1446#L167 assume !(1 == ~t1_pc~0); 1454#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 1470#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1477#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1574#L405 assume !(0 != activate_threads_~tmp___0~0); 1544#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1545#L186 assume !(1 == ~t2_pc~0); 1424#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 1425#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1555#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1556#L413 assume !(0 != activate_threads_~tmp___1~0); 1585#L413-2 assume !(1 == ~M_E~0); 1580#L359-1 assume !(1 == ~T1_E~0); 1502#L364-1 assume !(1 == ~T2_E~0); 1503#L369-1 assume !(1 == ~E_1~0); 1516#L374-1 assume !(1 == ~E_2~0); 1441#L520-1 [2021-10-28 09:37:57,182 INFO L793 eck$LassoCheckResult]: Loop: 1441#L520-1 assume !false; 1442#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1749#L301 assume !false; 1694#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1688#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1684#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1680#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1677#L268 assume !(0 != eval_~tmp~0); 1603#L316 start_simulation_~kernel_st~0 := 2; 1575#L206-1 start_simulation_~kernel_st~0 := 3; 1443#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1444#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1521#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1428#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1429#L341-3 assume !(0 == ~E_2~0); 1772#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1489#L148-9 assume !(1 == ~m_pc~0); 1490#L148-11 is_master_triggered_~__retres1~0 := 0; 1568#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1599#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1615#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1480#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1481#L167-9 assume !(1 == ~t1_pc~0); 1587#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 1499#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1414#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1415#L405-9 assume !(0 != activate_threads_~tmp___0~0); 1458#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1459#L186-9 assume 1 == ~t2_pc~0; 1482#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1419#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1524#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1496#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1471#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 1472#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1573#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1571#L369-3 assume !(1 == ~E_1~0); 1517#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1518#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1616#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1461#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1462#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1756#L539 assume !(0 == start_simulation_~tmp~3); 1515#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1770#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1767#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1473#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1474#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1513#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 1507#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1508#L552 assume !(0 != start_simulation_~tmp___0~1); 1441#L520-1 [2021-10-28 09:37:57,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,183 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2021-10-28 09:37:57,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362459610] [2021-10-28 09:37:57,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,184 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:57,206 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:57,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:57,272 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:57,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,275 INFO L85 PathProgramCache]: Analyzing trace with hash -2007931839, now seen corresponding path program 1 times [2021-10-28 09:37:57,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,276 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021847154] [2021-10-28 09:37:57,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,278 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:57,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:57,379 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:57,379 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021847154] [2021-10-28 09:37:57,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021847154] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:57,383 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:57,383 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:57,383 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23919778] [2021-10-28 09:37:57,384 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:57,384 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:57,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:57,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:57,391 INFO L87 Difference]: Start difference. First operand 403 states and 596 transitions. cyclomatic complexity: 195 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:57,453 INFO L93 Difference]: Finished difference Result 570 states and 836 transitions. [2021-10-28 09:37:57,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:57,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 570 states and 836 transitions. [2021-10-28 09:37:57,467 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2021-10-28 09:37:57,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 570 states to 570 states and 836 transitions. [2021-10-28 09:37:57,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 570 [2021-10-28 09:37:57,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 570 [2021-10-28 09:37:57,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 570 states and 836 transitions. [2021-10-28 09:37:57,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:57,478 INFO L681 BuchiCegarLoop]: Abstraction has 570 states and 836 transitions. [2021-10-28 09:37:57,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states and 836 transitions. [2021-10-28 09:37:57,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 568. [2021-10-28 09:37:57,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 568 states, 568 states have (on average 1.4683098591549295) internal successors, (834), 567 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 834 transitions. [2021-10-28 09:37:57,505 INFO L704 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-10-28 09:37:57,505 INFO L587 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-10-28 09:37:57,505 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 09:37:57,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 568 states and 834 transitions. [2021-10-28 09:37:57,510 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 504 [2021-10-28 09:37:57,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:57,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:57,520 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,520 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,521 INFO L791 eck$LassoCheckResult]: Stem: 2601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2491#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2492#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2467#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 2468#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2493#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2391#L223-1 assume !(0 == ~M_E~0); 2392#L326-1 assume !(0 == ~T1_E~0); 2445#L331-1 assume !(0 == ~T2_E~0); 2395#L336-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2396#L341-1 assume !(0 == ~E_2~0); 2443#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2444#L148 assume !(1 == ~m_pc~0); 2458#L148-2 is_master_triggered_~__retres1~0 := 0; 2480#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2545#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2567#L397 assume !(0 != activate_threads_~tmp~1); 2426#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2427#L167 assume !(1 == ~t1_pc~0); 2435#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 2450#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2457#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2555#L405 assume !(0 != activate_threads_~tmp___0~0); 2525#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2526#L186 assume !(1 == ~t2_pc~0); 2404#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 2405#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2538#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2539#L413 assume !(0 != activate_threads_~tmp___1~0); 2570#L413-2 assume !(1 == ~M_E~0); 2565#L359-1 assume !(1 == ~T1_E~0); 2484#L364-1 assume !(1 == ~T2_E~0); 2485#L369-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2499#L374-1 assume !(1 == ~E_2~0); 2494#L520-1 [2021-10-28 09:37:57,522 INFO L793 eck$LassoCheckResult]: Loop: 2494#L520-1 assume !false; 2730#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2729#L301 assume !false; 2727#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2725#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2723#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2721#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2719#L268 assume !(0 != eval_~tmp~0); 2594#L316 start_simulation_~kernel_st~0 := 2; 2557#L206-1 start_simulation_~kernel_st~0 := 3; 2424#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2425#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2503#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2408#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2409#L341-3 assume !(0 == ~E_2~0); 2433#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2509#L148-9 assume !(1 == ~m_pc~0); 2952#L148-11 is_master_triggered_~__retres1~0 := 0; 2951#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2950#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2918#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2914#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2909#L167-9 assume !(1 == ~t1_pc~0); 2906#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 2902#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2899#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2896#L405-9 assume !(0 != activate_threads_~tmp___0~0); 2440#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2441#L186-9 assume 1 == ~t2_pc~0; 2883#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2879#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2876#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2477#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2451#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2452#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2553#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2552#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2500#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2501#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2540#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2442#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2406#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2407#L539 assume !(0 == start_simulation_~tmp~3); 2498#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2504#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2466#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2453#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2454#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2496#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 2486#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2487#L552 assume !(0 != start_simulation_~tmp___0~1); 2494#L520-1 [2021-10-28 09:37:57,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,523 INFO L85 PathProgramCache]: Analyzing trace with hash 713469919, now seen corresponding path program 1 times [2021-10-28 09:37:57,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682663858] [2021-10-28 09:37:57,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,526 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:57,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:57,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:57,573 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682663858] [2021-10-28 09:37:57,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682663858] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:57,574 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:57,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:37:57,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897842161] [2021-10-28 09:37:57,575 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:37:57,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,575 INFO L85 PathProgramCache]: Analyzing trace with hash -728068161, now seen corresponding path program 1 times [2021-10-28 09:37:57,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,576 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563623199] [2021-10-28 09:37:57,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,577 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:57,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:57,629 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:57,629 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563623199] [2021-10-28 09:37:57,629 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563623199] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:57,629 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:57,630 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:37:57,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729729644] [2021-10-28 09:37:57,631 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:57,631 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:57,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:57,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:57,635 INFO L87 Difference]: Start difference. First operand 568 states and 834 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 2 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:57,669 INFO L93 Difference]: Finished difference Result 402 states and 580 transitions. [2021-10-28 09:37:57,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:57,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402 states and 580 transitions. [2021-10-28 09:37:57,674 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-10-28 09:37:57,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402 states to 402 states and 580 transitions. [2021-10-28 09:37:57,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402 [2021-10-28 09:37:57,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 402 [2021-10-28 09:37:57,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 402 states and 580 transitions. [2021-10-28 09:37:57,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:57,683 INFO L681 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 09:37:57,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states and 580 transitions. [2021-10-28 09:37:57,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 402. [2021-10-28 09:37:57,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 402 states have (on average 1.4427860696517414) internal successors, (580), 401 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 580 transitions. [2021-10-28 09:37:57,697 INFO L704 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 09:37:57,697 INFO L587 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 09:37:57,697 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 09:37:57,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402 states and 580 transitions. [2021-10-28 09:37:57,701 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-10-28 09:37:57,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:57,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:57,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:57,706 INFO L791 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3465#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3466#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3442#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 3443#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3467#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3370#L223-1 assume !(0 == ~M_E~0); 3371#L326-1 assume !(0 == ~T1_E~0); 3421#L331-1 assume !(0 == ~T2_E~0); 3374#L336-1 assume !(0 == ~E_1~0); 3375#L341-1 assume !(0 == ~E_2~0); 3419#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3420#L148 assume !(1 == ~m_pc~0); 3434#L148-2 is_master_triggered_~__retres1~0 := 0; 3453#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3517#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3537#L397 assume !(0 != activate_threads_~tmp~1); 3403#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3404#L167 assume !(1 == ~t1_pc~0); 3411#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 3426#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3433#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3527#L405 assume !(0 != activate_threads_~tmp___0~0); 3499#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3500#L186 assume !(1 == ~t2_pc~0); 3382#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 3383#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3510#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3511#L413 assume !(0 != activate_threads_~tmp___1~0); 3539#L413-2 assume !(1 == ~M_E~0); 3535#L359-1 assume !(1 == ~T1_E~0); 3458#L364-1 assume !(1 == ~T2_E~0); 3459#L369-1 assume !(1 == ~E_1~0); 3473#L374-1 assume !(1 == ~E_2~0); 3542#L520-1 [2021-10-28 09:37:57,708 INFO L793 eck$LassoCheckResult]: Loop: 3542#L520-1 assume !false; 3738#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3737#L301 assume !false; 3726#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3724#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3532#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3480#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3412#L268 assume !(0 != eval_~tmp~0); 3414#L316 start_simulation_~kernel_st~0 := 2; 3528#L206-1 start_simulation_~kernel_st~0 := 3; 3401#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3402#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3477#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3389#L336-3 assume !(0 == ~E_1~0); 3390#L341-3 assume !(0 == ~E_2~0); 3409#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3447#L148-9 assume !(1 == ~m_pc~0); 3448#L148-11 is_master_triggered_~__retres1~0 := 0; 3521#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3553#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3566#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3437#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3438#L167-9 assume !(1 == ~t1_pc~0); 3540#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 3455#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3372#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3373#L405-9 assume !(0 != activate_threads_~tmp___0~0); 3415#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3416#L186-9 assume !(1 == ~t2_pc~0); 3376#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 3377#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3479#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3452#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3427#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3428#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3526#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3524#L369-3 assume !(1 == ~E_1~0); 3474#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3475#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3512#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3418#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3384#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3385#L539 assume !(0 == start_simulation_~tmp~3); 3472#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3478#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3441#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3429#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3430#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3470#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 3463#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3464#L552 assume !(0 != start_simulation_~tmp___0~1); 3542#L520-1 [2021-10-28 09:37:57,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,709 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2021-10-28 09:37:57,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,710 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71802077] [2021-10-28 09:37:57,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,710 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:57,734 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:57,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:57,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:57,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:57,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2037657088, now seen corresponding path program 1 times [2021-10-28 09:37:57,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:57,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836157424] [2021-10-28 09:37:57,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:57,790 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:57,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:57,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:57,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:57,870 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836157424] [2021-10-28 09:37:57,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836157424] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:57,871 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:57,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:37:57,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255249652] [2021-10-28 09:37:57,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:57,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:57,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:37:57,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:37:57,880 INFO L87 Difference]: Start difference. First operand 402 states and 580 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.2) internal successors, (51), 5 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:57,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:57,990 INFO L93 Difference]: Finished difference Result 670 states and 947 transitions. [2021-10-28 09:37:57,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 09:37:57,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 670 states and 947 transitions. [2021-10-28 09:37:57,999 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2021-10-28 09:37:58,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 670 states to 670 states and 947 transitions. [2021-10-28 09:37:58,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 670 [2021-10-28 09:37:58,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 670 [2021-10-28 09:37:58,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 670 states and 947 transitions. [2021-10-28 09:37:58,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:58,013 INFO L681 BuchiCegarLoop]: Abstraction has 670 states and 947 transitions. [2021-10-28 09:37:58,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 670 states and 947 transitions. [2021-10-28 09:37:58,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 670 to 411. [2021-10-28 09:37:58,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.4330900243309002) internal successors, (589), 410 states have internal predecessors, (589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 589 transitions. [2021-10-28 09:37:58,029 INFO L704 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-10-28 09:37:58,029 INFO L587 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-10-28 09:37:58,029 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 09:37:58,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 589 transitions. [2021-10-28 09:37:58,033 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 371 [2021-10-28 09:37:58,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:58,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:58,037 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,039 INFO L791 eck$LassoCheckResult]: Stem: 4659#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4557#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4558#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4533#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 4534#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4559#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4458#L223-1 assume !(0 == ~M_E~0); 4459#L326-1 assume !(0 == ~T1_E~0); 4510#L331-1 assume !(0 == ~T2_E~0); 4462#L336-1 assume !(0 == ~E_1~0); 4463#L341-1 assume !(0 == ~E_2~0); 4508#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4509#L148 assume !(1 == ~m_pc~0); 4523#L148-2 is_master_triggered_~__retres1~0 := 0; 4545#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4611#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4635#L397 assume !(0 != activate_threads_~tmp~1); 4492#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4493#L167 assume !(1 == ~t1_pc~0); 4501#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 4515#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4522#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4623#L405 assume !(0 != activate_threads_~tmp___0~0); 4595#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4596#L186 assume !(1 == ~t2_pc~0); 4471#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 4472#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4603#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4604#L413 assume !(0 != activate_threads_~tmp___1~0); 4638#L413-2 assume !(1 == ~M_E~0); 4632#L359-1 assume !(1 == ~T1_E~0); 4550#L364-1 assume !(1 == ~T2_E~0); 4551#L369-1 assume !(1 == ~E_1~0); 4564#L374-1 assume !(1 == ~E_2~0); 4488#L520-1 [2021-10-28 09:37:58,040 INFO L793 eck$LassoCheckResult]: Loop: 4488#L520-1 assume !false; 4489#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4796#L301 assume !false; 4591#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4585#L236 assume !(0 == ~m_st~0); 4511#L240 assume !(0 == ~t1_st~0); 4468#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4469#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4692#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4689#L268 assume !(0 != eval_~tmp~0); 4690#L316 start_simulation_~kernel_st~0 := 2; 4624#L206-1 start_simulation_~kernel_st~0 := 3; 4625#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4740#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4569#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4570#L336-3 assume !(0 == ~E_1~0); 4498#L341-3 assume !(0 == ~E_2~0); 4499#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4538#L148-9 assume !(1 == ~m_pc~0); 4539#L148-11 is_master_triggered_~__retres1~0 := 0; 4794#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4793#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4792#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4791#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4790#L167-9 assume !(1 == ~t1_pc~0); 4789#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 4788#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4787#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4786#L405-9 assume !(0 != activate_threads_~tmp___0~0); 4785#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4525#L186-9 assume 1 == ~t2_pc~0; 4526#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4573#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4574#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4784#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4516#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 4517#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4783#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4782#L369-3 assume !(1 == ~E_1~0); 4565#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4566#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4668#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4507#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4473#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4474#L539 assume !(0 == start_simulation_~tmp~3); 4567#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4829#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4825#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4518#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4519#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4561#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 4552#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4553#L552 assume !(0 != start_simulation_~tmp___0~1); 4488#L520-1 [2021-10-28 09:37:58,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,043 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2021-10-28 09:37:58,043 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,044 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379818358] [2021-10-28 09:37:58,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,044 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,080 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:58,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,108 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:58,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,113 INFO L85 PathProgramCache]: Analyzing trace with hash 805723206, now seen corresponding path program 1 times [2021-10-28 09:37:58,114 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,119 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301737918] [2021-10-28 09:37:58,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,120 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:58,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:58,199 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:58,199 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301737918] [2021-10-28 09:37:58,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301737918] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:58,200 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:58,200 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:37:58,200 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099421961] [2021-10-28 09:37:58,200 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:58,200 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:58,201 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:37:58,201 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:37:58,202 INFO L87 Difference]: Start difference. First operand 411 states and 589 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:58,324 INFO L93 Difference]: Finished difference Result 1194 states and 1698 transitions. [2021-10-28 09:37:58,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 09:37:58,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1698 transitions. [2021-10-28 09:37:58,337 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1139 [2021-10-28 09:37:58,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1698 transitions. [2021-10-28 09:37:58,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2021-10-28 09:37:58,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2021-10-28 09:37:58,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1698 transitions. [2021-10-28 09:37:58,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:58,355 INFO L681 BuchiCegarLoop]: Abstraction has 1194 states and 1698 transitions. [2021-10-28 09:37:58,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1698 transitions. [2021-10-28 09:37:58,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 420. [2021-10-28 09:37:58,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 420 states, 420 states have (on average 1.4238095238095239) internal successors, (598), 419 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 598 transitions. [2021-10-28 09:37:58,375 INFO L704 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-10-28 09:37:58,375 INFO L587 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-10-28 09:37:58,375 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 09:37:58,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 420 states and 598 transitions. [2021-10-28 09:37:58,379 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 380 [2021-10-28 09:37:58,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:58,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:58,380 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,380 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,380 INFO L791 eck$LassoCheckResult]: Stem: 6296#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6179#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6180#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6156#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 6157#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6184#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6080#L223-1 assume !(0 == ~M_E~0); 6081#L326-1 assume !(0 == ~T1_E~0); 6132#L331-1 assume !(0 == ~T2_E~0); 6082#L336-1 assume !(0 == ~E_1~0); 6083#L341-1 assume !(0 == ~E_2~0); 6130#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6131#L148 assume !(1 == ~m_pc~0); 6148#L148-2 is_master_triggered_~__retres1~0 := 0; 6171#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6241#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6268#L397 assume !(0 != activate_threads_~tmp~1); 6114#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6115#L167 assume !(1 == ~t1_pc~0); 6122#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 6138#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6145#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6255#L405 assume !(0 != activate_threads_~tmp___0~0); 6225#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6226#L186 assume !(1 == ~t2_pc~0); 6090#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 6091#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6233#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6234#L413 assume !(0 != activate_threads_~tmp___1~0); 6270#L413-2 assume !(1 == ~M_E~0); 6264#L359-1 assume !(1 == ~T1_E~0); 6177#L364-1 assume !(1 == ~T2_E~0); 6178#L369-1 assume !(1 == ~E_1~0); 6192#L374-1 assume !(1 == ~E_2~0); 6185#L520-1 [2021-10-28 09:37:58,380 INFO L793 eck$LassoCheckResult]: Loop: 6185#L520-1 assume !false; 6434#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6433#L301 assume !false; 6220#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6221#L236 assume !(0 == ~m_st~0); 6432#L240 assume !(0 == ~t1_st~0); 6092#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6093#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6198#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6199#L268 assume !(0 != eval_~tmp~0); 6420#L316 start_simulation_~kernel_st~0 := 2; 6256#L206-1 start_simulation_~kernel_st~0 := 3; 6257#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6300#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6301#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6473#L336-3 assume !(0 == ~E_1~0); 6120#L341-3 assume !(0 == ~E_2~0); 6121#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6472#L148-9 assume !(1 == ~m_pc~0); 6471#L148-11 is_master_triggered_~__retres1~0 := 0; 6286#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6287#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6306#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6307#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6272#L167-9 assume !(1 == ~t1_pc~0); 6273#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 6470#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6084#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6085#L405-9 assume !(0 != activate_threads_~tmp___0~0); 6469#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6152#L186-9 assume 1 == ~t2_pc~0; 6153#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6200#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6201#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6468#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6467#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 6276#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6277#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6250#L369-3 assume !(1 == ~E_1~0); 6251#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6237#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6238#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6129#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6095#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6096#L539 assume !(0 == start_simulation_~tmp~3); 6191#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6197#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6159#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6303#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 6440#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6189#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 6182#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6183#L552 assume !(0 != start_simulation_~tmp___0~1); 6185#L520-1 [2021-10-28 09:37:58,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,381 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2021-10-28 09:37:58,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,382 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851370153] [2021-10-28 09:37:58,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,382 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,399 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:58,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,432 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:58,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,433 INFO L85 PathProgramCache]: Analyzing trace with hash 805663624, now seen corresponding path program 1 times [2021-10-28 09:37:58,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752270335] [2021-10-28 09:37:58,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,433 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:58,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:58,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:58,541 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752270335] [2021-10-28 09:37:58,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752270335] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:58,542 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:58,542 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:37:58,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456445160] [2021-10-28 09:37:58,545 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:58,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:58,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:37:58,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:37:58,547 INFO L87 Difference]: Start difference. First operand 420 states and 598 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:58,700 INFO L93 Difference]: Finished difference Result 921 states and 1298 transitions. [2021-10-28 09:37:58,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 09:37:58,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 921 states and 1298 transitions. [2021-10-28 09:37:58,713 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2021-10-28 09:37:58,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 921 states to 921 states and 1298 transitions. [2021-10-28 09:37:58,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 921 [2021-10-28 09:37:58,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 921 [2021-10-28 09:37:58,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 921 states and 1298 transitions. [2021-10-28 09:37:58,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:58,728 INFO L681 BuchiCegarLoop]: Abstraction has 921 states and 1298 transitions. [2021-10-28 09:37:58,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 921 states and 1298 transitions. [2021-10-28 09:37:58,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 921 to 441. [2021-10-28 09:37:58,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 441 states have (on average 1.3968253968253967) internal successors, (616), 440 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 616 transitions. [2021-10-28 09:37:58,745 INFO L704 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-10-28 09:37:58,745 INFO L587 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-10-28 09:37:58,746 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 09:37:58,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 616 transitions. [2021-10-28 09:37:58,749 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 401 [2021-10-28 09:37:58,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:58,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:58,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,755 INFO L791 eck$LassoCheckResult]: Stem: 7635#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7526#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7527#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7504#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 7505#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7533#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7434#L223-1 assume !(0 == ~M_E~0); 7435#L326-1 assume !(0 == ~T1_E~0); 7485#L331-1 assume !(0 == ~T2_E~0); 7436#L336-1 assume !(0 == ~E_1~0); 7437#L341-1 assume !(0 == ~E_2~0); 7483#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7484#L148 assume !(1 == ~m_pc~0); 7498#L148-2 is_master_triggered_~__retres1~0 := 0; 7519#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7585#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7607#L397 assume !(0 != activate_threads_~tmp~1); 7468#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7469#L167 assume !(1 == ~t1_pc~0); 7475#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 7489#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7495#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7598#L405 assume !(0 != activate_threads_~tmp___0~0); 7568#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7569#L186 assume !(1 == ~t2_pc~0); 7444#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 7445#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7578#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7579#L413 assume !(0 != activate_threads_~tmp___1~0); 7609#L413-2 assume !(1 == ~M_E~0); 7604#L359-1 assume !(1 == ~T1_E~0); 7524#L364-1 assume !(1 == ~T2_E~0); 7525#L369-1 assume !(1 == ~E_1~0); 7538#L374-1 assume !(1 == ~E_2~0); 7614#L520-1 [2021-10-28 09:37:58,755 INFO L793 eck$LassoCheckResult]: Loop: 7614#L520-1 assume !false; 7674#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7673#L301 assume !false; 7672#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7671#L236 assume !(0 == ~m_st~0); 7670#L240 assume !(0 == ~t1_st~0); 7668#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 7667#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7666#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7664#L268 assume !(0 != eval_~tmp~0); 7663#L316 start_simulation_~kernel_st~0 := 2; 7662#L206-1 start_simulation_~kernel_st~0 := 3; 7661#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7660#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7659#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7658#L336-3 assume !(0 == ~E_1~0); 7657#L341-3 assume !(0 == ~E_2~0); 7656#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7513#L148-9 assume !(1 == ~m_pc~0); 7514#L148-11 is_master_triggered_~__retres1~0 := 0; 7742#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7741#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7740#L397-9 assume !(0 != activate_threads_~tmp~1); 7739#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7738#L167-9 assume !(1 == ~t1_pc~0); 7736#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 7734#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7732#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7730#L405-9 assume !(0 != activate_threads_~tmp___0~0); 7728#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7726#L186-9 assume 1 == ~t2_pc~0; 7723#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7721#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7719#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7717#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7715#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 7712#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7710#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7708#L369-3 assume !(1 == ~E_1~0); 7706#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7704#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7702#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7698#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7696#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7695#L539 assume !(0 == start_simulation_~tmp~3); 7693#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7692#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7688#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7686#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7685#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7683#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 7682#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7680#L552 assume !(0 != start_simulation_~tmp___0~1); 7614#L520-1 [2021-10-28 09:37:58,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,756 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 5 times [2021-10-28 09:37:58,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973667202] [2021-10-28 09:37:58,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,756 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,768 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:58,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,804 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:58,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1507263498, now seen corresponding path program 1 times [2021-10-28 09:37:58,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,806 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697423219] [2021-10-28 09:37:58,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,806 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:58,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:58,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:58,855 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697423219] [2021-10-28 09:37:58,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697423219] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:58,856 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:58,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:58,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686184847] [2021-10-28 09:37:58,857 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:37:58,857 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:58,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:58,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:58,858 INFO L87 Difference]: Start difference. First operand 441 states and 616 transitions. cyclomatic complexity: 177 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:58,908 INFO L93 Difference]: Finished difference Result 675 states and 925 transitions. [2021-10-28 09:37:58,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:58,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 675 states and 925 transitions. [2021-10-28 09:37:58,916 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 633 [2021-10-28 09:37:58,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 675 states to 675 states and 925 transitions. [2021-10-28 09:37:58,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 675 [2021-10-28 09:37:58,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 675 [2021-10-28 09:37:58,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 675 states and 925 transitions. [2021-10-28 09:37:58,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:58,927 INFO L681 BuchiCegarLoop]: Abstraction has 675 states and 925 transitions. [2021-10-28 09:37:58,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 675 states and 925 transitions. [2021-10-28 09:37:58,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 675 to 643. [2021-10-28 09:37:58,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 643 states, 643 states have (on average 1.374805598755832) internal successors, (884), 642 states have internal predecessors, (884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:58,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 884 transitions. [2021-10-28 09:37:58,946 INFO L704 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-10-28 09:37:58,946 INFO L587 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-10-28 09:37:58,946 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 09:37:58,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states and 884 transitions. [2021-10-28 09:37:58,952 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 601 [2021-10-28 09:37:58,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:58,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:58,953 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,953 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:58,953 INFO L791 eck$LassoCheckResult]: Stem: 8753#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8652#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8653#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8629#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 8630#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8654#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8556#L223-1 assume !(0 == ~M_E~0); 8557#L326-1 assume !(0 == ~T1_E~0); 8607#L331-1 assume !(0 == ~T2_E~0); 8558#L336-1 assume !(0 == ~E_1~0); 8559#L341-1 assume !(0 == ~E_2~0); 8605#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8606#L148 assume !(1 == ~m_pc~0); 8620#L148-2 is_master_triggered_~__retres1~0 := 0; 8640#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8706#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8730#L397 assume !(0 != activate_threads_~tmp~1); 8590#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8591#L167 assume !(1 == ~t1_pc~0); 8597#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 8612#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8619#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8719#L405 assume !(0 != activate_threads_~tmp___0~0); 8688#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8689#L186 assume !(1 == ~t2_pc~0); 8566#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 8567#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8699#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8700#L413 assume !(0 != activate_threads_~tmp___1~0); 8732#L413-2 assume !(1 == ~M_E~0); 8727#L359-1 assume !(1 == ~T1_E~0); 8645#L364-1 assume !(1 == ~T2_E~0); 8646#L369-1 assume !(1 == ~E_1~0); 8659#L374-1 assume !(1 == ~E_2~0); 8737#L520-1 assume !false; 8890#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 8886#L301 [2021-10-28 09:37:58,953 INFO L793 eck$LassoCheckResult]: Loop: 8886#L301 assume !false; 8883#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8879#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 8876#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8873#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8870#L268 assume 0 != eval_~tmp~0; 8867#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 8551#L276 assume !(0 != eval_~tmp_ndt_1~0); 8553#L273 assume !(0 == ~t1_st~0); 8893#L287 assume !(0 == ~t2_st~0); 8886#L301 [2021-10-28 09:37:58,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,954 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2021-10-28 09:37:58,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,955 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436673719] [2021-10-28 09:37:58,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,955 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,964 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:58,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,981 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:58,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1206180399, now seen corresponding path program 1 times [2021-10-28 09:37:58,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,982 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197305747] [2021-10-28 09:37:58,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,983 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:58,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,986 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:58,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:58,991 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:58,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:58,992 INFO L85 PathProgramCache]: Analyzing trace with hash 202160337, now seen corresponding path program 1 times [2021-10-28 09:37:58,992 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:58,992 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138240148] [2021-10-28 09:37:58,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:58,992 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:59,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:59,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:59,022 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138240148] [2021-10-28 09:37:59,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138240148] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:59,023 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:59,023 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:59,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22575552] [2021-10-28 09:37:59,132 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:59,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:59,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:59,133 INFO L87 Difference]: Start difference. First operand 643 states and 884 transitions. cyclomatic complexity: 244 Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:59,192 INFO L93 Difference]: Finished difference Result 1127 states and 1531 transitions. [2021-10-28 09:37:59,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:59,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1127 states and 1531 transitions. [2021-10-28 09:37:59,217 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 995 [2021-10-28 09:37:59,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1127 states to 1127 states and 1531 transitions. [2021-10-28 09:37:59,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1127 [2021-10-28 09:37:59,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1127 [2021-10-28 09:37:59,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1127 states and 1531 transitions. [2021-10-28 09:37:59,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:59,248 INFO L681 BuchiCegarLoop]: Abstraction has 1127 states and 1531 transitions. [2021-10-28 09:37:59,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1127 states and 1531 transitions. [2021-10-28 09:37:59,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1127 to 1058. [2021-10-28 09:37:59,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1058 states, 1058 states have (on average 1.3648393194706994) internal successors, (1444), 1057 states have internal predecessors, (1444), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1058 states to 1058 states and 1444 transitions. [2021-10-28 09:37:59,303 INFO L704 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-10-28 09:37:59,303 INFO L587 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-10-28 09:37:59,303 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 09:37:59,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1058 states and 1444 transitions. [2021-10-28 09:37:59,312 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2021-10-28 09:37:59,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:59,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:59,314 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,314 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,314 INFO L791 eck$LassoCheckResult]: Stem: 10557#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10430#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10431#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10408#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 10409#L213-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 10551#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11304#L223-1 assume !(0 == ~M_E~0); 11303#L326-1 assume !(0 == ~T1_E~0); 11302#L331-1 assume !(0 == ~T2_E~0); 11301#L336-1 assume !(0 == ~E_1~0); 11300#L341-1 assume !(0 == ~E_2~0); 11299#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11298#L148 assume !(1 == ~m_pc~0); 11297#L148-2 is_master_triggered_~__retres1~0 := 0; 11296#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11295#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11294#L397 assume !(0 != activate_threads_~tmp~1); 11293#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11292#L167 assume !(1 == ~t1_pc~0); 11291#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 11290#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11289#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11288#L405 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10476#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10477#L186 assume !(1 == ~t2_pc~0); 10344#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 10345#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10485#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10486#L413 assume !(0 != activate_threads_~tmp___1~0); 10523#L413-2 assume !(1 == ~M_E~0); 10524#L359-1 assume !(1 == ~T1_E~0); 11278#L364-1 assume !(1 == ~T2_E~0); 10443#L369-1 assume !(1 == ~E_1~0); 10444#L374-1 assume !(1 == ~E_2~0); 10530#L520-1 assume !false; 11245#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11243#L301 [2021-10-28 09:37:59,314 INFO L793 eck$LassoCheckResult]: Loop: 11243#L301 assume !false; 11241#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11239#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11238#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11237#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11235#L268 assume 0 != eval_~tmp~0; 11066#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 11067#L276 assume !(0 != eval_~tmp_ndt_1~0); 10794#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 10789#L290 assume !(0 != eval_~tmp_ndt_2~0); 10790#L287 assume !(0 == ~t2_st~0); 11243#L301 [2021-10-28 09:37:59,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2021-10-28 09:37:59,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,315 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439975012] [2021-10-28 09:37:59,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,316 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:59,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:59,336 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:59,336 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439975012] [2021-10-28 09:37:59,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439975012] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:59,336 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:59,337 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:37:59,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520356358] [2021-10-28 09:37:59,337 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:37:59,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 1 times [2021-10-28 09:37:59,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,338 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502649310] [2021-10-28 09:37:59,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,338 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,373 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:59,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,381 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:59,519 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:59,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:59,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:59,521 INFO L87 Difference]: Start difference. First operand 1058 states and 1444 transitions. cyclomatic complexity: 390 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:59,535 INFO L93 Difference]: Finished difference Result 890 states and 1214 transitions. [2021-10-28 09:37:59,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:59,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 890 states and 1214 transitions. [2021-10-28 09:37:59,547 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-10-28 09:37:59,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 890 states to 890 states and 1214 transitions. [2021-10-28 09:37:59,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 890 [2021-10-28 09:37:59,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 890 [2021-10-28 09:37:59,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 890 states and 1214 transitions. [2021-10-28 09:37:59,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:59,561 INFO L681 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 09:37:59,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states and 1214 transitions. [2021-10-28 09:37:59,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 890. [2021-10-28 09:37:59,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 890 states, 890 states have (on average 1.3640449438202247) internal successors, (1214), 889 states have internal predecessors, (1214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1214 transitions. [2021-10-28 09:37:59,593 INFO L704 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 09:37:59,593 INFO L587 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 09:37:59,593 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 09:37:59,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 890 states and 1214 transitions. [2021-10-28 09:37:59,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-10-28 09:37:59,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:59,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:59,603 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,603 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,603 INFO L791 eck$LassoCheckResult]: Stem: 12505#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12384#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12385#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12361#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 12362#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12391#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12288#L223-1 assume !(0 == ~M_E~0); 12289#L326-1 assume !(0 == ~T1_E~0); 12340#L331-1 assume !(0 == ~T2_E~0); 12290#L336-1 assume !(0 == ~E_1~0); 12291#L341-1 assume !(0 == ~E_2~0); 12338#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12339#L148 assume !(1 == ~m_pc~0); 12354#L148-2 is_master_triggered_~__retres1~0 := 0; 12377#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12451#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12476#L397 assume !(0 != activate_threads_~tmp~1); 12322#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12323#L167 assume !(1 == ~t1_pc~0); 12330#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 12345#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12351#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12464#L405 assume !(0 != activate_threads_~tmp___0~0); 12431#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12432#L186 assume !(1 == ~t2_pc~0); 12298#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 12299#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12443#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12444#L413 assume !(0 != activate_threads_~tmp___1~0); 12478#L413-2 assume !(1 == ~M_E~0); 12473#L359-1 assume !(1 == ~T1_E~0); 12382#L364-1 assume !(1 == ~T2_E~0); 12383#L369-1 assume !(1 == ~E_1~0); 12398#L374-1 assume !(1 == ~E_2~0); 12484#L520-1 assume !false; 12582#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12581#L301 [2021-10-28 09:37:59,603 INFO L793 eck$LassoCheckResult]: Loop: 12581#L301 assume !false; 12580#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12579#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12578#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12577#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 12576#L268 assume 0 != eval_~tmp~0; 12575#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 12573#L276 assume !(0 != eval_~tmp_ndt_1~0); 12574#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 12587#L290 assume !(0 != eval_~tmp_ndt_2~0); 12585#L287 assume !(0 == ~t2_st~0); 12581#L301 [2021-10-28 09:37:59,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,604 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2021-10-28 09:37:59,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,604 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439205768] [2021-10-28 09:37:59,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,605 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,614 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:59,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,631 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:59,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 2 times [2021-10-28 09:37:59,632 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,632 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838344613] [2021-10-28 09:37:59,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,633 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,637 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:59,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,642 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:59,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1971900397, now seen corresponding path program 1 times [2021-10-28 09:37:59,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,643 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822291615] [2021-10-28 09:37:59,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,644 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:37:59,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:37:59,680 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:37:59,680 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822291615] [2021-10-28 09:37:59,680 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822291615] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:37:59,680 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:37:59,680 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:37:59,681 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765954404] [2021-10-28 09:37:59,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:37:59,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:37:59,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:37:59,804 INFO L87 Difference]: Start difference. First operand 890 states and 1214 transitions. cyclomatic complexity: 326 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:37:59,858 INFO L93 Difference]: Finished difference Result 1558 states and 2113 transitions. [2021-10-28 09:37:59,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:37:59,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1558 states and 2113 transitions. [2021-10-28 09:37:59,876 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-10-28 09:37:59,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-10-28 09:37:59,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1558 [2021-10-28 09:37:59,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1558 [2021-10-28 09:37:59,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1558 states and 2113 transitions. [2021-10-28 09:37:59,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:37:59,899 INFO L681 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 09:37:59,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1558 states and 2113 transitions. [2021-10-28 09:37:59,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1558 to 1558. [2021-10-28 09:37:59,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1558 states, 1558 states have (on average 1.3562259306803595) internal successors, (2113), 1557 states have internal predecessors, (2113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:37:59,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-10-28 09:37:59,944 INFO L704 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 09:37:59,944 INFO L587 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 09:37:59,944 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 09:37:59,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1558 states and 2113 transitions. [2021-10-28 09:37:59,957 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-10-28 09:37:59,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:37:59,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:37:59,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:37:59,959 INFO L791 eck$LassoCheckResult]: Stem: 14958#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 14840#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14841#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14817#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 14818#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14847#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14744#L223-1 assume !(0 == ~M_E~0); 14745#L326-1 assume !(0 == ~T1_E~0); 14796#L331-1 assume !(0 == ~T2_E~0); 14746#L336-1 assume !(0 == ~E_1~0); 14747#L341-1 assume !(0 == ~E_2~0); 14794#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14795#L148 assume !(1 == ~m_pc~0); 14811#L148-2 is_master_triggered_~__retres1~0 := 0; 14833#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14902#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14929#L397 assume !(0 != activate_threads_~tmp~1); 14777#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14778#L167 assume !(1 == ~t1_pc~0); 14785#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 14801#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14808#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14915#L405 assume !(0 != activate_threads_~tmp___0~0); 14884#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14885#L186 assume !(1 == ~t2_pc~0); 14754#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 14755#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14895#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14896#L413 assume !(0 != activate_threads_~tmp___1~0); 14931#L413-2 assume !(1 == ~M_E~0); 14925#L359-1 assume !(1 == ~T1_E~0); 14838#L364-1 assume !(1 == ~T2_E~0); 14839#L369-1 assume !(1 == ~E_1~0); 14853#L374-1 assume !(1 == ~E_2~0); 14938#L520-1 assume !false; 16266#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16254#L301 [2021-10-28 09:37:59,959 INFO L793 eck$LassoCheckResult]: Loop: 16254#L301 assume !false; 16255#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16256#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 14922#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 14861#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 14788#L268 assume 0 != eval_~tmp~0; 14789#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 14739#L276 assume !(0 != eval_~tmp_ndt_1~0); 14741#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 15931#L290 assume !(0 != eval_~tmp_ndt_2~0); 15932#L287 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 16248#L304 assume !(0 != eval_~tmp_ndt_3~0); 16254#L301 [2021-10-28 09:37:59,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,959 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2021-10-28 09:37:59,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,960 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164151976] [2021-10-28 09:37:59,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,960 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,969 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:59,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:59,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,985 INFO L85 PathProgramCache]: Analyzing trace with hash 498620433, now seen corresponding path program 1 times [2021-10-28 09:37:59,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,986 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281673766] [2021-10-28 09:37:59,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,986 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:37:59,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,990 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:37:59,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:37:59,994 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:37:59,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:37:59,995 INFO L85 PathProgramCache]: Analyzing trace with hash 999369489, now seen corresponding path program 1 times [2021-10-28 09:37:59,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:37:59,996 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766527615] [2021-10-28 09:37:59,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:37:59,996 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:38:00,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:38:00,005 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:38:00,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:38:00,025 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:38:01,449 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 09:38:01 BoogieIcfgContainer [2021-10-28 09:38:01,450 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 09:38:01,450 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 09:38:01,450 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 09:38:01,450 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 09:38:01,451 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:37:55" (3/4) ... [2021-10-28 09:38:01,454 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 09:38:01,506 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/witness.graphml [2021-10-28 09:38:01,506 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 09:38:01,508 INFO L168 Benchmark]: Toolchain (without parser) took 7304.99 ms. Allocated memory was 100.7 MB in the beginning and 165.7 MB in the end (delta: 65.0 MB). Free memory was 70.2 MB in the beginning and 71.7 MB in the end (delta: -1.5 MB). Peak memory consumption was 63.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,508 INFO L168 Benchmark]: CDTParser took 0.38 ms. Allocated memory is still 100.7 MB. Free memory is still 58.5 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:38:01,509 INFO L168 Benchmark]: CACSL2BoogieTranslator took 525.07 ms. Allocated memory is still 100.7 MB. Free memory was 70.2 MB in the beginning and 75.2 MB in the end (delta: -5.0 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,509 INFO L168 Benchmark]: Boogie Procedure Inliner took 77.04 ms. Allocated memory is still 100.7 MB. Free memory was 75.2 MB in the beginning and 72.3 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,510 INFO L168 Benchmark]: Boogie Preprocessor took 74.56 ms. Allocated memory is still 100.7 MB. Free memory was 72.3 MB in the beginning and 70.2 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,510 INFO L168 Benchmark]: RCFGBuilder took 977.22 ms. Allocated memory is still 100.7 MB. Free memory was 70.2 MB in the beginning and 48.5 MB in the end (delta: 21.8 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,511 INFO L168 Benchmark]: BuchiAutomizer took 5588.70 ms. Allocated memory was 100.7 MB in the beginning and 165.7 MB in the end (delta: 65.0 MB). Free memory was 48.1 MB in the beginning and 74.7 MB in the end (delta: -26.7 MB). Peak memory consumption was 53.5 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,511 INFO L168 Benchmark]: Witness Printer took 55.89 ms. Allocated memory is still 165.7 MB. Free memory was 74.7 MB in the beginning and 71.7 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:38:01,514 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.38 ms. Allocated memory is still 100.7 MB. Free memory is still 58.5 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 525.07 ms. Allocated memory is still 100.7 MB. Free memory was 70.2 MB in the beginning and 75.2 MB in the end (delta: -5.0 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 77.04 ms. Allocated memory is still 100.7 MB. Free memory was 75.2 MB in the beginning and 72.3 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 74.56 ms. Allocated memory is still 100.7 MB. Free memory was 72.3 MB in the beginning and 70.2 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 977.22 ms. Allocated memory is still 100.7 MB. Free memory was 70.2 MB in the beginning and 48.5 MB in the end (delta: 21.8 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 5588.70 ms. Allocated memory was 100.7 MB in the beginning and 165.7 MB in the end (delta: 65.0 MB). Free memory was 48.1 MB in the beginning and 74.7 MB in the end (delta: -26.7 MB). Peak memory consumption was 53.5 MB. Max. memory is 16.1 GB. * Witness Printer took 55.89 ms. Allocated memory is still 165.7 MB. Free memory was 74.7 MB in the beginning and 71.7 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1558 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.5s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 3.6s. Construction of modules took 0.4s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 1654 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 1558 states and ocurred in iteration 12. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 3637 SDtfs, 4123 SDslu, 4299 SDs, 0 SdLazy, 293 SolverSat, 119 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 263]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=21208} State at position 1 is {NULL=0, NULL=21208, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e131436=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@14c3d104=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@435ae818=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3577f4be=0, NULL=21209, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=21210, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=21211, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5291244b=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32fc2e75=0, t2_pc=0, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a5f549a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ef796ee=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d8385df=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 263]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L565] int __retres1 ; [L479] m_i = 1 [L480] t1_i = 1 [L481] t2_i = 1 [L506] int kernel_st ; [L507] int tmp ; [L508] int tmp___0 ; [L512] kernel_st = 0 [L213] COND TRUE m_i == 1 [L214] m_st = 0 [L218] COND TRUE t1_i == 1 [L219] t1_st = 0 [L223] COND TRUE t2_i == 1 [L224] t2_st = 0 [L326] COND FALSE !(M_E == 0) [L331] COND FALSE !(T1_E == 0) [L336] COND FALSE !(T2_E == 0) [L341] COND FALSE !(E_1 == 0) [L346] COND FALSE !(E_2 == 0) [L389] int tmp ; [L390] int tmp___0 ; [L391] int tmp___1 ; [L145] int __retres1 ; [L148] COND FALSE !(m_pc == 1) [L158] __retres1 = 0 [L160] return (__retres1); [L395] tmp = is_master_triggered() [L397] COND FALSE !(\read(tmp)) [L164] int __retres1 ; [L167] COND FALSE !(t1_pc == 1) [L177] __retres1 = 0 [L179] return (__retres1); [L403] tmp___0 = is_transmit1_triggered() [L405] COND FALSE !(\read(tmp___0)) [L183] int __retres1 ; [L186] COND FALSE !(t2_pc == 1) [L196] __retres1 = 0 [L198] return (__retres1); [L411] tmp___1 = is_transmit2_triggered() [L413] COND FALSE !(\read(tmp___1)) [L359] COND FALSE !(M_E == 1) [L364] COND FALSE !(T1_E == 1) [L369] COND FALSE !(T2_E == 1) [L374] COND FALSE !(E_1 == 1) [L379] COND FALSE !(E_2 == 1) [L520] COND TRUE 1 [L523] kernel_st = 1 [L259] int tmp ; Loop: [L263] COND TRUE 1 [L233] int __retres1 ; [L236] COND TRUE m_st == 0 [L237] __retres1 = 1 [L254] return (__retres1); [L266] tmp = exists_runnable_thread() [L268] COND TRUE \read(tmp) [L273] COND TRUE m_st == 0 [L274] int tmp_ndt_1; [L275] tmp_ndt_1 = __VERIFIER_nondet_int() [L276] COND FALSE !(\read(tmp_ndt_1)) [L287] COND TRUE t1_st == 0 [L288] int tmp_ndt_2; [L289] tmp_ndt_2 = __VERIFIER_nondet_int() [L290] COND FALSE !(\read(tmp_ndt_2)) [L301] COND TRUE t2_st == 0 [L302] int tmp_ndt_3; [L303] tmp_ndt_3 = __VERIFIER_nondet_int() [L304] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 09:38:01,575 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d8981fce-fda5-4356-8617-18fe651f8485/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...