./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b22948af7969548f6325803b9ef465ae282132daf74eccf91e8f6f6583a87156 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 09:21:41,074 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 09:21:41,079 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 09:21:41,159 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 09:21:41,160 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 09:21:41,165 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 09:21:41,168 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 09:21:41,173 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 09:21:41,176 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 09:21:41,184 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 09:21:41,185 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 09:21:41,188 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 09:21:41,188 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 09:21:41,192 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 09:21:41,195 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 09:21:41,200 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 09:21:41,202 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 09:21:41,204 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 09:21:41,207 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 09:21:41,217 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 09:21:41,220 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 09:21:41,222 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 09:21:41,226 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 09:21:41,227 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 09:21:41,239 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 09:21:41,240 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 09:21:41,240 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 09:21:41,243 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 09:21:41,244 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 09:21:41,246 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 09:21:41,246 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 09:21:41,247 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 09:21:41,248 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 09:21:41,250 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 09:21:41,251 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 09:21:41,251 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 09:21:41,252 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 09:21:41,253 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 09:21:41,253 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 09:21:41,254 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 09:21:41,255 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 09:21:41,256 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 09:21:41,317 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 09:21:41,318 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 09:21:41,319 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 09:21:41,319 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 09:21:41,322 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 09:21:41,322 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 09:21:41,322 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 09:21:41,322 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 09:21:41,323 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 09:21:41,323 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 09:21:41,324 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 09:21:41,325 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 09:21:41,325 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 09:21:41,325 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 09:21:41,326 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 09:21:41,326 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 09:21:41,326 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 09:21:41,326 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 09:21:41,327 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 09:21:41,327 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 09:21:41,327 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 09:21:41,327 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 09:21:41,327 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 09:21:41,328 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 09:21:41,328 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 09:21:41,328 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 09:21:41,328 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 09:21:41,329 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 09:21:41,329 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 09:21:41,329 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 09:21:41,330 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 09:21:41,330 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 09:21:41,331 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 09:21:41,332 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b22948af7969548f6325803b9ef465ae282132daf74eccf91e8f6f6583a87156 [2021-10-28 09:21:41,704 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 09:21:41,743 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 09:21:41,749 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 09:21:41,751 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 09:21:41,752 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 09:21:41,754 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-10-28 09:21:41,869 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/data/36e82f5a4/8b2b3fcdd50c4130ae944f0ce485a72d/FLAG26da5677e [2021-10-28 09:21:42,558 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 09:21:42,559 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-10-28 09:21:42,579 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/data/36e82f5a4/8b2b3fcdd50c4130ae944f0ce485a72d/FLAG26da5677e [2021-10-28 09:21:42,886 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/data/36e82f5a4/8b2b3fcdd50c4130ae944f0ce485a72d [2021-10-28 09:21:42,890 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 09:21:42,893 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 09:21:42,896 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 09:21:42,896 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 09:21:42,909 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 09:21:42,910 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:21:42" (1/1) ... [2021-10-28 09:21:42,912 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@dd8a3fe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:42, skipping insertion in model container [2021-10-28 09:21:42,913 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:21:42" (1/1) ... [2021-10-28 09:21:42,925 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 09:21:42,974 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 09:21:43,209 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/sv-benchmarks/c/systemc/transmitter.03.cil.c[401,414] [2021-10-28 09:21:43,380 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:21:43,420 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 09:21:43,457 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/sv-benchmarks/c/systemc/transmitter.03.cil.c[401,414] [2021-10-28 09:21:43,566 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:21:43,601 INFO L208 MainTranslator]: Completed translation [2021-10-28 09:21:43,602 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43 WrapperNode [2021-10-28 09:21:43,603 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 09:21:43,605 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 09:21:43,605 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 09:21:43,605 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 09:21:43,617 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,650 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,729 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 09:21:43,730 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 09:21:43,730 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 09:21:43,730 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 09:21:43,743 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,744 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,763 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,763 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,792 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,822 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,829 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,838 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 09:21:43,840 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 09:21:43,840 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 09:21:43,840 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 09:21:43,842 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (1/1) ... [2021-10-28 09:21:43,877 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 09:21:43,898 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:21:43,920 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 09:21:43,933 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 09:21:43,982 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 09:21:43,982 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 09:21:43,983 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 09:21:43,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 09:21:45,021 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 09:21:45,021 INFO L299 CfgBuilder]: Removed 119 assume(true) statements. [2021-10-28 09:21:45,025 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:21:45 BoogieIcfgContainer [2021-10-28 09:21:45,025 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 09:21:45,031 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 09:21:45,031 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 09:21:45,044 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 09:21:45,045 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:21:45,045 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 09:21:42" (1/3) ... [2021-10-28 09:21:45,051 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da0d84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:21:45, skipping insertion in model container [2021-10-28 09:21:45,051 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:21:45,051 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:21:43" (2/3) ... [2021-10-28 09:21:45,052 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da0d84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 09:21:45, skipping insertion in model container [2021-10-28 09:21:45,052 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 09:21:45,053 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:21:45" (3/3) ... [2021-10-28 09:21:45,055 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2021-10-28 09:21:45,229 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 09:21:45,229 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 09:21:45,230 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 09:21:45,230 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 09:21:45,230 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 09:21:45,230 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 09:21:45,230 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 09:21:45,230 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 09:21:45,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 275 states, 274 states have (on average 1.572992700729927) internal successors, (431), 274 states have internal predecessors, (431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:45,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 222 [2021-10-28 09:21:45,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:45,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:45,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,385 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 09:21:45,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 275 states, 274 states have (on average 1.572992700729927) internal successors, (431), 274 states have internal predecessors, (431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:45,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 222 [2021-10-28 09:21:45,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:45,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:45,420 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,420 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,432 INFO L791 eck$LassoCheckResult]: Stem: 265#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 177#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 37#L607true havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18#L266true assume !(1 == ~m_i~0);~m_st~0 := 2; 195#L273-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 104#L278-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 73#L283-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 201#L288-1true assume !(0 == ~M_E~0); 126#L410-1true assume !(0 == ~T1_E~0); 154#L415-1true assume !(0 == ~T2_E~0); 55#L420-1true assume !(0 == ~T3_E~0); 84#L425-1true assume !(0 == ~E_1~0); 42#L430-1true assume 0 == ~E_2~0;~E_2~0 := 1; 131#L435-1true assume !(0 == ~E_3~0); 160#L440-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90#L189true assume !(1 == ~m_pc~0); 56#L189-2true is_master_triggered_~__retres1~0 := 0; 108#L200true is_master_triggered_#res := is_master_triggered_~__retres1~0; 198#L201true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 46#L502true assume !(0 != activate_threads_~tmp~1); 123#L502-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 252#L208true assume 1 == ~t1_pc~0; 256#L209true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 273#L219true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68#L220true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 221#L510true assume !(0 != activate_threads_~tmp___0~0); 10#L510-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 99#L227true assume !(1 == ~t2_pc~0); 43#L227-2true is_transmit2_triggered_~__retres1~2 := 0; 161#L238true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 163#L239true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11#L518true assume !(0 != activate_threads_~tmp___1~0); 116#L518-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69#L246true assume 1 == ~t3_pc~0; 109#L247true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 127#L257true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 166#L258true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 235#L526true assume !(0 != activate_threads_~tmp___2~0); 243#L526-2true assume !(1 == ~M_E~0); 172#L453-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 129#L458-1true assume !(1 == ~T2_E~0); 271#L463-1true assume !(1 == ~T3_E~0); 274#L468-1true assume !(1 == ~E_1~0); 97#L473-1true assume !(1 == ~E_2~0); 118#L478-1true assume !(1 == ~E_3~0); 119#L644-1true [2021-10-28 09:21:45,443 INFO L793 eck$LassoCheckResult]: Loop: 119#L644-1true assume !false; 138#L645true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 152#L385true assume false; 75#L400true start_simulation_~kernel_st~0 := 2; 164#L266-1true start_simulation_~kernel_st~0 := 3; 4#L410-2true assume 0 == ~M_E~0;~M_E~0 := 1; 165#L410-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 20#L415-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 232#L420-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 155#L425-3true assume 0 == ~E_1~0;~E_1~0 := 1; 204#L430-3true assume 0 == ~E_2~0;~E_2~0 := 1; 159#L435-3true assume 0 == ~E_3~0;~E_3~0 := 1; 158#L440-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44#L189-12true assume !(1 == ~m_pc~0); 156#L189-14true is_master_triggered_~__retres1~0 := 0; 176#L200-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 112#L201-4true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49#L502-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41#L502-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94#L208-12true assume !(1 == ~t1_pc~0); 122#L208-14true is_transmit1_triggered_~__retres1~1 := 0; 7#L219-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34#L220-4true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14#L510-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86#L510-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 185#L227-12true assume !(1 == ~t2_pc~0); 120#L227-14true is_transmit2_triggered_~__retres1~2 := 0; 171#L238-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 174#L239-4true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 61#L518-12true assume !(0 != activate_threads_~tmp___1~0); 32#L518-14true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 250#L246-12true assume !(1 == ~t3_pc~0); 143#L246-14true is_transmit3_triggered_~__retres1~3 := 0; 191#L257-4true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 219#L258-4true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 269#L526-12true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 106#L526-14true assume 1 == ~M_E~0;~M_E~0 := 2; 192#L453-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 59#L458-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 110#L463-3true assume !(1 == ~T3_E~0); 151#L468-3true assume 1 == ~E_1~0;~E_1~0 := 2; 101#L473-3true assume 1 == ~E_2~0;~E_2~0 := 2; 193#L478-3true assume 1 == ~E_3~0;~E_3~0 := 2; 89#L483-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 103#L301-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 98#L323-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 229#L324-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22#L663true assume !(0 == start_simulation_~tmp~3); 184#L663-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 31#L301-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 194#L323-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 144#L324-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 188#L618true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 125#L625true stop_simulation_#res := stop_simulation_~__retres2~0; 205#L626true start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 202#L676true assume !(0 != start_simulation_~tmp___0~1); 119#L644-1true [2021-10-28 09:21:45,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:45,450 INFO L85 PathProgramCache]: Analyzing trace with hash 1271326673, now seen corresponding path program 1 times [2021-10-28 09:21:45,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:45,463 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691594038] [2021-10-28 09:21:45,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:45,465 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:45,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:45,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:45,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:45,673 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691594038] [2021-10-28 09:21:45,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691594038] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:45,675 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:45,675 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:45,677 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353927945] [2021-10-28 09:21:45,684 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:45,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:45,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1071508586, now seen corresponding path program 1 times [2021-10-28 09:21:45,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:45,686 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223917765] [2021-10-28 09:21:45,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:45,686 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:45,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:45,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:45,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:45,719 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223917765] [2021-10-28 09:21:45,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223917765] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:45,719 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:45,720 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:21:45,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601637012] [2021-10-28 09:21:45,722 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:45,723 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:45,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:45,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:45,746 INFO L87 Difference]: Start difference. First operand has 275 states, 274 states have (on average 1.572992700729927) internal successors, (431), 274 states have internal predecessors, (431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:45,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:45,791 INFO L93 Difference]: Finished difference Result 275 states and 415 transitions. [2021-10-28 09:21:45,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:45,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 275 states and 415 transitions. [2021-10-28 09:21:45,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:45,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 275 states to 270 states and 410 transitions. [2021-10-28 09:21:45,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2021-10-28 09:21:45,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2021-10-28 09:21:45,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 410 transitions. [2021-10-28 09:21:45,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:45,817 INFO L681 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2021-10-28 09:21:45,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 410 transitions. [2021-10-28 09:21:45,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2021-10-28 09:21:45,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.5185185185185186) internal successors, (410), 269 states have internal predecessors, (410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:45,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 410 transitions. [2021-10-28 09:21:45,869 INFO L704 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2021-10-28 09:21:45,870 INFO L587 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2021-10-28 09:21:45,870 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 09:21:45,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 410 transitions. [2021-10-28 09:21:45,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:45,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:45,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:45,877 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,877 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:45,877 INFO L791 eck$LassoCheckResult]: Stem: 827#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 794#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 622#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 589#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 590#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 730#L278-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 694#L283-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 695#L288-1 assume !(0 == ~M_E~0); 753#L410-1 assume !(0 == ~T1_E~0); 754#L415-1 assume !(0 == ~T2_E~0); 659#L420-1 assume !(0 == ~T3_E~0); 660#L425-1 assume !(0 == ~E_1~0); 632#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 633#L435-1 assume !(0 == ~E_3~0); 762#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 718#L189 assume !(1 == ~m_pc~0); 661#L189-2 is_master_triggered_~__retres1~0 := 0; 662#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 737#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 641#L502 assume !(0 != activate_threads_~tmp~1); 642#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 749#L208 assume 1 == ~t1_pc~0; 821#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 823#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 681#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 682#L510 assume !(0 != activate_threads_~tmp___0~0); 575#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 576#L227 assume !(1 == ~t2_pc~0); 636#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 637#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 787#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 579#L518 assume !(0 != activate_threads_~tmp___1~0); 580#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 683#L246 assume 1 == ~t3_pc~0; 684#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 738#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 755#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 789#L526 assume !(0 != activate_threads_~tmp___2~0); 815#L526-2 assume !(1 == ~M_E~0); 792#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 758#L458-1 assume !(1 == ~T2_E~0); 759#L463-1 assume !(1 == ~T3_E~0); 828#L468-1 assume !(1 == ~E_1~0); 724#L473-1 assume !(1 == ~E_2~0); 725#L478-1 assume !(1 == ~E_3~0); 747#L644-1 [2021-10-28 09:21:45,878 INFO L793 eck$LassoCheckResult]: Loop: 747#L644-1 assume !false; 748#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 607#L385 assume !false; 623#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 624#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 562#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 563#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 594#L338 assume !(0 != eval_~tmp~0); 669#L400 start_simulation_~kernel_st~0 := 2; 696#L266-1 start_simulation_~kernel_st~0 := 3; 564#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 565#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 592#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 593#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 781#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 782#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 786#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 785#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 638#L189-12 assume !(1 == ~m_pc~0); 640#L189-14 is_master_triggered_~__retres1~0 := 0; 783#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 743#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 647#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 630#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 631#L208-12 assume 1 == ~t1_pc~0; 721#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 573#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 574#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 583#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 584#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 713#L227-12 assume 1 == ~t2_pc~0; 627#L228-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 628#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 791#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 670#L518-12 assume !(0 != activate_threads_~tmp___1~0); 615#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 616#L246-12 assume !(1 == ~t3_pc~0); 772#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 773#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 803#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 810#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 735#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 736#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 666#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 667#L463-3 assume !(1 == ~T3_E~0); 739#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 728#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 729#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 716#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 717#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 602#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 726#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 595#L663 assume !(0 == start_simulation_~tmp~3); 597#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 612#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 613#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 774#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 775#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 751#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 752#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 805#L676 assume !(0 != start_simulation_~tmp___0~1); 747#L644-1 [2021-10-28 09:21:45,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:45,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1023180179, now seen corresponding path program 1 times [2021-10-28 09:21:45,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:45,880 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6629881] [2021-10-28 09:21:45,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:45,880 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:45,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:45,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:45,992 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:45,992 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6629881] [2021-10-28 09:21:45,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6629881] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:45,993 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:45,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:45,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960684153] [2021-10-28 09:21:45,993 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:45,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:45,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1826274219, now seen corresponding path program 1 times [2021-10-28 09:21:45,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:45,995 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020338630] [2021-10-28 09:21:45,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:45,996 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,073 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,073 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020338630] [2021-10-28 09:21:46,074 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020338630] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,074 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,074 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:46,075 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034349150] [2021-10-28 09:21:46,075 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:46,076 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:46,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:46,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:46,077 INFO L87 Difference]: Start difference. First operand 270 states and 410 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:46,122 INFO L93 Difference]: Finished difference Result 270 states and 409 transitions. [2021-10-28 09:21:46,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:46,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 409 transitions. [2021-10-28 09:21:46,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 409 transitions. [2021-10-28 09:21:46,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2021-10-28 09:21:46,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2021-10-28 09:21:46,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 409 transitions. [2021-10-28 09:21:46,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:46,139 INFO L681 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2021-10-28 09:21:46,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 409 transitions. [2021-10-28 09:21:46,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2021-10-28 09:21:46,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.5148148148148148) internal successors, (409), 269 states have internal predecessors, (409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 409 transitions. [2021-10-28 09:21:46,158 INFO L704 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2021-10-28 09:21:46,158 INFO L587 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2021-10-28 09:21:46,158 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 09:21:46,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 409 transitions. [2021-10-28 09:21:46,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:46,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:46,164 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,165 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,165 INFO L791 eck$LassoCheckResult]: Stem: 1374#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1341#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1169#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1136#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 1137#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1277#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1241#L283-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1242#L288-1 assume !(0 == ~M_E~0); 1300#L410-1 assume !(0 == ~T1_E~0); 1301#L415-1 assume !(0 == ~T2_E~0); 1206#L420-1 assume !(0 == ~T3_E~0); 1207#L425-1 assume !(0 == ~E_1~0); 1179#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1180#L435-1 assume !(0 == ~E_3~0); 1309#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1265#L189 assume !(1 == ~m_pc~0); 1208#L189-2 is_master_triggered_~__retres1~0 := 0; 1209#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1284#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1188#L502 assume !(0 != activate_threads_~tmp~1); 1189#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1296#L208 assume 1 == ~t1_pc~0; 1368#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1370#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1228#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1229#L510 assume !(0 != activate_threads_~tmp___0~0); 1122#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1123#L227 assume !(1 == ~t2_pc~0); 1183#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 1184#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1334#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1126#L518 assume !(0 != activate_threads_~tmp___1~0); 1127#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1230#L246 assume 1 == ~t3_pc~0; 1231#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1285#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1302#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1336#L526 assume !(0 != activate_threads_~tmp___2~0); 1362#L526-2 assume !(1 == ~M_E~0); 1339#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1305#L458-1 assume !(1 == ~T2_E~0); 1306#L463-1 assume !(1 == ~T3_E~0); 1375#L468-1 assume !(1 == ~E_1~0); 1271#L473-1 assume !(1 == ~E_2~0); 1272#L478-1 assume !(1 == ~E_3~0); 1294#L644-1 [2021-10-28 09:21:46,166 INFO L793 eck$LassoCheckResult]: Loop: 1294#L644-1 assume !false; 1295#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1154#L385 assume !false; 1170#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1171#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1109#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1110#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1144#L338 assume !(0 != eval_~tmp~0); 1216#L400 start_simulation_~kernel_st~0 := 2; 1243#L266-1 start_simulation_~kernel_st~0 := 3; 1111#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1112#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1139#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1140#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1329#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1333#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1332#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1185#L189-12 assume 1 == ~m_pc~0; 1186#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1331#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1290#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1196#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1177#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1178#L208-12 assume 1 == ~t1_pc~0; 1268#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1120#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1121#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1130#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1131#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1260#L227-12 assume 1 == ~t2_pc~0; 1174#L228-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1175#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1338#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1217#L518-12 assume !(0 != activate_threads_~tmp___1~0); 1162#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1163#L246-12 assume 1 == ~t3_pc~0; 1360#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1318#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1350#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1357#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1278#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1279#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1213#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1214#L463-3 assume !(1 == ~T3_E~0); 1286#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1274#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1275#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1262#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1263#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1149#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1273#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1141#L663 assume !(0 == start_simulation_~tmp~3); 1143#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1159#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1160#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1321#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1322#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1298#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 1299#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1352#L676 assume !(0 != start_simulation_~tmp___0~1); 1294#L644-1 [2021-10-28 09:21:46,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,167 INFO L85 PathProgramCache]: Analyzing trace with hash -1899979819, now seen corresponding path program 1 times [2021-10-28 09:21:46,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:46,168 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757955806] [2021-10-28 09:21:46,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:46,168 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,235 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757955806] [2021-10-28 09:21:46,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757955806] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,235 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:46,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896574460] [2021-10-28 09:21:46,236 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:46,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1985347945, now seen corresponding path program 1 times [2021-10-28 09:21:46,237 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:46,237 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079807768] [2021-10-28 09:21:46,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:46,237 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,397 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,398 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079807768] [2021-10-28 09:21:46,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079807768] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,398 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:46,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211269332] [2021-10-28 09:21:46,399 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:46,400 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:46,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:46,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:46,401 INFO L87 Difference]: Start difference. First operand 270 states and 409 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:46,430 INFO L93 Difference]: Finished difference Result 270 states and 408 transitions. [2021-10-28 09:21:46,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:46,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 408 transitions. [2021-10-28 09:21:46,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 408 transitions. [2021-10-28 09:21:46,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2021-10-28 09:21:46,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2021-10-28 09:21:46,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 408 transitions. [2021-10-28 09:21:46,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:46,463 INFO L681 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2021-10-28 09:21:46,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 408 transitions. [2021-10-28 09:21:46,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2021-10-28 09:21:46,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.511111111111111) internal successors, (408), 269 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 408 transitions. [2021-10-28 09:21:46,488 INFO L704 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2021-10-28 09:21:46,488 INFO L587 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2021-10-28 09:21:46,488 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 09:21:46,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 408 transitions. [2021-10-28 09:21:46,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:46,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:46,495 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,496 INFO L791 eck$LassoCheckResult]: Stem: 1921#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1888#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1716#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1683#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 1684#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1824#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1788#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1789#L288-1 assume !(0 == ~M_E~0); 1847#L410-1 assume !(0 == ~T1_E~0); 1848#L415-1 assume !(0 == ~T2_E~0); 1753#L420-1 assume !(0 == ~T3_E~0); 1754#L425-1 assume !(0 == ~E_1~0); 1726#L430-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1727#L435-1 assume !(0 == ~E_3~0); 1856#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1812#L189 assume !(1 == ~m_pc~0); 1755#L189-2 is_master_triggered_~__retres1~0 := 0; 1756#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1831#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1735#L502 assume !(0 != activate_threads_~tmp~1); 1736#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1843#L208 assume 1 == ~t1_pc~0; 1915#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1917#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1775#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1776#L510 assume !(0 != activate_threads_~tmp___0~0); 1669#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1670#L227 assume !(1 == ~t2_pc~0); 1730#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 1731#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1881#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1673#L518 assume !(0 != activate_threads_~tmp___1~0); 1674#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1777#L246 assume 1 == ~t3_pc~0; 1778#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1832#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1849#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1883#L526 assume !(0 != activate_threads_~tmp___2~0); 1909#L526-2 assume !(1 == ~M_E~0); 1886#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1852#L458-1 assume !(1 == ~T2_E~0); 1853#L463-1 assume !(1 == ~T3_E~0); 1922#L468-1 assume !(1 == ~E_1~0); 1818#L473-1 assume !(1 == ~E_2~0); 1819#L478-1 assume !(1 == ~E_3~0); 1841#L644-1 [2021-10-28 09:21:46,497 INFO L793 eck$LassoCheckResult]: Loop: 1841#L644-1 assume !false; 1842#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1702#L385 assume !false; 1717#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1718#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1656#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1657#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1691#L338 assume !(0 != eval_~tmp~0); 1763#L400 start_simulation_~kernel_st~0 := 2; 1790#L266-1 start_simulation_~kernel_st~0 := 3; 1658#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1659#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1686#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1687#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1875#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1876#L430-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1880#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1879#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1732#L189-12 assume 1 == ~m_pc~0; 1733#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1878#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1837#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1743#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1724#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1725#L208-12 assume 1 == ~t1_pc~0; 1815#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1660#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1661#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1677#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1678#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1807#L227-12 assume 1 == ~t2_pc~0; 1721#L228-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1722#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1885#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1764#L518-12 assume !(0 != activate_threads_~tmp___1~0); 1709#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1710#L246-12 assume 1 == ~t3_pc~0; 1907#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1865#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1897#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1904#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1825#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1826#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1760#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1761#L463-3 assume !(1 == ~T3_E~0); 1833#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1821#L473-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1822#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1809#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1810#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1696#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1820#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1688#L663 assume !(0 == start_simulation_~tmp~3); 1690#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1706#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1707#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1868#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1869#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1845#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 1846#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1899#L676 assume !(0 != start_simulation_~tmp___0~1); 1841#L644-1 [2021-10-28 09:21:46,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,498 INFO L85 PathProgramCache]: Analyzing trace with hash -54612653, now seen corresponding path program 1 times [2021-10-28 09:21:46,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:46,499 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659130510] [2021-10-28 09:21:46,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:46,500 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,619 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659130510] [2021-10-28 09:21:46,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659130510] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,619 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,620 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:21:46,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980189515] [2021-10-28 09:21:46,620 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:46,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1985347945, now seen corresponding path program 2 times [2021-10-28 09:21:46,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:46,622 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864652511] [2021-10-28 09:21:46,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:46,623 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,737 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864652511] [2021-10-28 09:21:46,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864652511] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,737 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,738 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:46,738 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992401518] [2021-10-28 09:21:46,739 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:46,739 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:46,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:46,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:46,745 INFO L87 Difference]: Start difference. First operand 270 states and 408 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 2 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:46,816 INFO L93 Difference]: Finished difference Result 270 states and 398 transitions. [2021-10-28 09:21:46,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:46,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 398 transitions. [2021-10-28 09:21:46,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 398 transitions. [2021-10-28 09:21:46,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2021-10-28 09:21:46,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2021-10-28 09:21:46,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 398 transitions. [2021-10-28 09:21:46,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:46,831 INFO L681 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2021-10-28 09:21:46,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 398 transitions. [2021-10-28 09:21:46,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2021-10-28 09:21:46,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.474074074074074) internal successors, (398), 269 states have internal predecessors, (398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:46,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 398 transitions. [2021-10-28 09:21:46,864 INFO L704 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2021-10-28 09:21:46,864 INFO L587 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2021-10-28 09:21:46,865 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 09:21:46,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 398 transitions. [2021-10-28 09:21:46,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2021-10-28 09:21:46,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:46,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:46,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:46,872 INFO L791 eck$LassoCheckResult]: Stem: 2468#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2435#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2263#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2230#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 2231#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2370#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2334#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2335#L288-1 assume !(0 == ~M_E~0); 2394#L410-1 assume !(0 == ~T1_E~0); 2395#L415-1 assume !(0 == ~T2_E~0); 2299#L420-1 assume !(0 == ~T3_E~0); 2300#L425-1 assume !(0 == ~E_1~0); 2272#L430-1 assume !(0 == ~E_2~0); 2273#L435-1 assume !(0 == ~E_3~0); 2403#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2358#L189 assume !(1 == ~m_pc~0); 2301#L189-2 is_master_triggered_~__retres1~0 := 0; 2302#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2377#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2281#L502 assume !(0 != activate_threads_~tmp~1); 2282#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2390#L208 assume 1 == ~t1_pc~0; 2462#L209 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2464#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2321#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2322#L510 assume !(0 != activate_threads_~tmp___0~0); 2216#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2217#L227 assume !(1 == ~t2_pc~0); 2276#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 2277#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2429#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2220#L518 assume !(0 != activate_threads_~tmp___1~0); 2221#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2323#L246 assume 1 == ~t3_pc~0; 2324#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2378#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2396#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2430#L526 assume !(0 != activate_threads_~tmp___2~0); 2456#L526-2 assume !(1 == ~M_E~0); 2433#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2399#L458-1 assume !(1 == ~T2_E~0); 2400#L463-1 assume !(1 == ~T3_E~0); 2469#L468-1 assume !(1 == ~E_1~0); 2364#L473-1 assume !(1 == ~E_2~0); 2365#L478-1 assume !(1 == ~E_3~0); 2387#L644-1 [2021-10-28 09:21:46,873 INFO L793 eck$LassoCheckResult]: Loop: 2387#L644-1 assume !false; 2388#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2249#L385 assume !false; 2264#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2265#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2203#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2204#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2238#L338 assume !(0 != eval_~tmp~0); 2309#L400 start_simulation_~kernel_st~0 := 2; 2336#L266-1 start_simulation_~kernel_st~0 := 3; 2205#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2206#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2233#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2234#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2422#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2423#L430-3 assume !(0 == ~E_2~0); 2427#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2426#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2278#L189-12 assume 1 == ~m_pc~0; 2279#L190-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2424#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2381#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2287#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2270#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2271#L208-12 assume 1 == ~t1_pc~0; 2360#L209-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2209#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2210#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2224#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2225#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2353#L227-12 assume !(1 == ~t2_pc~0); 2269#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 2389#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2432#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2310#L518-12 assume !(0 != activate_threads_~tmp___1~0); 2256#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2257#L246-12 assume 1 == ~t3_pc~0; 2454#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2412#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2444#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2451#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2371#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 2372#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2306#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2307#L463-3 assume !(1 == ~T3_E~0); 2379#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2368#L473-3 assume !(1 == ~E_2~0); 2369#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2355#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2356#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2243#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2366#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2235#L663 assume !(0 == start_simulation_~tmp~3); 2237#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2253#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2254#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2415#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2416#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2392#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 2393#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2446#L676 assume !(0 != start_simulation_~tmp___0~1); 2387#L644-1 [2021-10-28 09:21:46,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,875 INFO L85 PathProgramCache]: Analyzing trace with hash -126999211, now seen corresponding path program 1 times [2021-10-28 09:21:46,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:46,876 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405838424] [2021-10-28 09:21:46,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:46,877 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:46,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:46,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:46,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:46,997 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405838424] [2021-10-28 09:21:46,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405838424] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:46,998 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:46,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:46,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788593824] [2021-10-28 09:21:46,999 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:46,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:46,999 INFO L85 PathProgramCache]: Analyzing trace with hash 862285994, now seen corresponding path program 1 times [2021-10-28 09:21:47,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:47,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403671179] [2021-10-28 09:21:47,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:47,000 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:47,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:47,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:47,068 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:47,069 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403671179] [2021-10-28 09:21:47,069 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403671179] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:47,069 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:47,070 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:47,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6424163] [2021-10-28 09:21:47,070 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:47,071 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:47,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:21:47,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:21:47,072 INFO L87 Difference]: Start difference. First operand 270 states and 398 transitions. cyclomatic complexity: 129 Second operand has 4 states, 4 states have (on average 11.25) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:47,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:47,273 INFO L93 Difference]: Finished difference Result 659 states and 947 transitions. [2021-10-28 09:21:47,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:21:47,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 947 transitions. [2021-10-28 09:21:47,286 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 576 [2021-10-28 09:21:47,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 947 transitions. [2021-10-28 09:21:47,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2021-10-28 09:21:47,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2021-10-28 09:21:47,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 947 transitions. [2021-10-28 09:21:47,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:47,301 INFO L681 BuchiCegarLoop]: Abstraction has 659 states and 947 transitions. [2021-10-28 09:21:47,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 947 transitions. [2021-10-28 09:21:47,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 607. [2021-10-28 09:21:47,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 607 states, 607 states have (on average 1.4497528830313016) internal successors, (880), 606 states have internal predecessors, (880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:47,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 880 transitions. [2021-10-28 09:21:47,335 INFO L704 BuchiCegarLoop]: Abstraction has 607 states and 880 transitions. [2021-10-28 09:21:47,335 INFO L587 BuchiCegarLoop]: Abstraction has 607 states and 880 transitions. [2021-10-28 09:21:47,335 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 09:21:47,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 607 states and 880 transitions. [2021-10-28 09:21:47,354 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 555 [2021-10-28 09:21:47,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:47,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:47,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:47,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:47,359 INFO L791 eck$LassoCheckResult]: Stem: 3434#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3388#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3201#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3168#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 3169#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3309#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3269#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3270#L288-1 assume !(0 == ~M_E~0); 3333#L410-1 assume !(0 == ~T1_E~0); 3334#L415-1 assume !(0 == ~T2_E~0); 3236#L420-1 assume !(0 == ~T3_E~0); 3237#L425-1 assume !(0 == ~E_1~0); 3210#L430-1 assume !(0 == ~E_2~0); 3211#L435-1 assume !(0 == ~E_3~0); 3343#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3295#L189 assume !(1 == ~m_pc~0); 3238#L189-2 is_master_triggered_~__retres1~0 := 0; 3239#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3316#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3218#L502 assume !(0 != activate_threads_~tmp~1); 3219#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3329#L208 assume !(1 == ~t1_pc~0); 3424#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 3425#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3258#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3259#L510 assume !(0 != activate_threads_~tmp___0~0); 3154#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3155#L227 assume !(1 == ~t2_pc~0); 3214#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 3215#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3373#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3156#L518 assume !(0 != activate_threads_~tmp___1~0); 3157#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3260#L246 assume 1 == ~t3_pc~0; 3261#L247 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3317#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3335#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3375#L526 assume !(0 != activate_threads_~tmp___2~0); 3414#L526-2 assume !(1 == ~M_E~0); 3386#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3339#L458-1 assume !(1 == ~T2_E~0); 3340#L463-1 assume !(1 == ~T3_E~0); 3436#L468-1 assume !(1 == ~E_1~0); 3303#L473-1 assume !(1 == ~E_2~0); 3304#L478-1 assume !(1 == ~E_3~0); 3326#L644-1 [2021-10-28 09:21:47,363 INFO L793 eck$LassoCheckResult]: Loop: 3326#L644-1 assume !false; 3327#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3365#L385 assume !false; 3202#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3203#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3141#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3142#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3173#L338 assume !(0 != eval_~tmp~0); 3246#L400 start_simulation_~kernel_st~0 := 2; 3273#L266-1 start_simulation_~kernel_st~0 := 3; 3143#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3144#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3171#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3172#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3366#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3367#L430-3 assume !(0 == ~E_2~0); 3636#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3370#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3216#L189-12 assume !(1 == ~m_pc~0); 3217#L189-14 is_master_triggered_~__retres1~0 := 0; 3368#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3320#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3224#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3208#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3209#L208-12 assume !(1 == ~t1_pc~0); 3300#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 3152#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3153#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3162#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3163#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3290#L227-12 assume !(1 == ~t2_pc~0); 3207#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 3328#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3385#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3247#L518-12 assume !(0 != activate_threads_~tmp___1~0); 3194#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3195#L246-12 assume 1 == ~t3_pc~0; 3412#L247-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3357#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3398#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3405#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3313#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 3314#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3243#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3244#L463-3 assume !(1 == ~T3_E~0); 3318#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3307#L473-3 assume !(1 == ~E_2~0); 3308#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3293#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3294#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3181#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3409#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3410#L663 assume !(0 == start_simulation_~tmp~3); 3302#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3191#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3192#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3358#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 3359#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3331#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 3332#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3400#L676 assume !(0 != start_simulation_~tmp___0~1); 3326#L644-1 [2021-10-28 09:21:47,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:47,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1717394188, now seen corresponding path program 1 times [2021-10-28 09:21:47,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:47,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525412403] [2021-10-28 09:21:47,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:47,367 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:47,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:47,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:47,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:47,475 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525412403] [2021-10-28 09:21:47,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [525412403] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:47,477 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:47,478 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:47,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542108038] [2021-10-28 09:21:47,480 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:47,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:47,481 INFO L85 PathProgramCache]: Analyzing trace with hash -408891028, now seen corresponding path program 1 times [2021-10-28 09:21:47,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:47,482 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123743211] [2021-10-28 09:21:47,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:47,483 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:47,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:47,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:47,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:47,530 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123743211] [2021-10-28 09:21:47,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123743211] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:47,531 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:47,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:47,532 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359407532] [2021-10-28 09:21:47,532 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:47,533 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:47,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:21:47,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:21:47,535 INFO L87 Difference]: Start difference. First operand 607 states and 880 transitions. cyclomatic complexity: 275 Second operand has 4 states, 4 states have (on average 11.25) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:47,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:47,763 INFO L93 Difference]: Finished difference Result 1687 states and 2396 transitions. [2021-10-28 09:21:47,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:21:47,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1687 states and 2396 transitions. [2021-10-28 09:21:47,793 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1551 [2021-10-28 09:21:47,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1687 states to 1687 states and 2396 transitions. [2021-10-28 09:21:47,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1687 [2021-10-28 09:21:47,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1687 [2021-10-28 09:21:47,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1687 states and 2396 transitions. [2021-10-28 09:21:47,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:47,844 INFO L681 BuchiCegarLoop]: Abstraction has 1687 states and 2396 transitions. [2021-10-28 09:21:47,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1687 states and 2396 transitions. [2021-10-28 09:21:47,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1687 to 1606. [2021-10-28 09:21:47,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1606 states, 1606 states have (on average 1.4290161892901618) internal successors, (2295), 1605 states have internal predecessors, (2295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:47,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2295 transitions. [2021-10-28 09:21:47,921 INFO L704 BuchiCegarLoop]: Abstraction has 1606 states and 2295 transitions. [2021-10-28 09:21:47,921 INFO L587 BuchiCegarLoop]: Abstraction has 1606 states and 2295 transitions. [2021-10-28 09:21:47,922 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 09:21:47,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2295 transitions. [2021-10-28 09:21:47,939 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2021-10-28 09:21:47,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:47,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:47,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:47,943 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:47,945 INFO L791 eck$LassoCheckResult]: Stem: 5743#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5687#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5508#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5473#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 5474#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5612#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5577#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5578#L288-1 assume !(0 == ~M_E~0); 5638#L410-1 assume !(0 == ~T1_E~0); 5639#L415-1 assume !(0 == ~T2_E~0); 5542#L420-1 assume !(0 == ~T3_E~0); 5543#L425-1 assume !(0 == ~E_1~0); 5515#L430-1 assume !(0 == ~E_2~0); 5516#L435-1 assume !(0 == ~E_3~0); 5649#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5602#L189 assume !(1 == ~m_pc~0); 5544#L189-2 is_master_triggered_~__retres1~0 := 0; 5545#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5618#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5524#L502 assume !(0 != activate_threads_~tmp~1); 5525#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5635#L208 assume !(1 == ~t1_pc~0); 5729#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 5730#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5565#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5566#L510 assume !(0 != activate_threads_~tmp___0~0); 5459#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5460#L227 assume !(1 == ~t2_pc~0); 5522#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 5523#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5677#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5463#L518 assume !(0 != activate_threads_~tmp___1~0); 5464#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5567#L246 assume !(1 == ~t3_pc~0); 5568#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 5640#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5641#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5681#L526 assume !(0 != activate_threads_~tmp___2~0); 5720#L526-2 assume !(1 == ~M_E~0); 5684#L453-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5644#L458-1 assume !(1 == ~T2_E~0); 5645#L463-1 assume !(1 == ~T3_E~0); 5745#L468-1 assume !(1 == ~E_1~0); 5606#L473-1 assume !(1 == ~E_2~0); 5607#L478-1 assume !(1 == ~E_3~0); 5628#L644-1 [2021-10-28 09:21:47,946 INFO L793 eck$LassoCheckResult]: Loop: 5628#L644-1 assume !false; 6665#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 6660#L385 assume !false; 6658#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6653#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6647#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6646#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6642#L338 assume !(0 != eval_~tmp~0); 6644#L400 start_simulation_~kernel_st~0 := 2; 7019#L266-1 start_simulation_~kernel_st~0 := 3; 7018#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7017#L410-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7016#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7015#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7014#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7013#L430-3 assume !(0 == ~E_2~0); 7012#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7011#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7010#L189-12 assume !(1 == ~m_pc~0); 7009#L189-14 is_master_triggered_~__retres1~0 := 0; 7008#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7007#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7006#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7005#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7004#L208-12 assume !(1 == ~t1_pc~0); 7003#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 7002#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7001#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7000#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6750#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6751#L227-12 assume !(1 == ~t2_pc~0); 6998#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 6997#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6996#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6995#L518-12 assume !(0 != activate_threads_~tmp___1~0); 6994#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6993#L246-12 assume !(1 == ~t3_pc~0); 6992#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 6991#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6990#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6989#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6988#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 6987#L453-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6986#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6985#L463-3 assume !(1 == ~T3_E~0); 6984#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6983#L473-3 assume !(1 == ~E_2~0); 6714#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6715#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6706#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6702#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6700#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6697#L663 assume !(0 == start_simulation_~tmp~3); 6694#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6685#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6682#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6679#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 6678#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6674#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 6672#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6671#L676 assume !(0 != start_simulation_~tmp___0~1); 5628#L644-1 [2021-10-28 09:21:47,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:47,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1289378579, now seen corresponding path program 1 times [2021-10-28 09:21:47,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:47,949 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812579147] [2021-10-28 09:21:47,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:47,949 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:47,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,037 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812579147] [2021-10-28 09:21:48,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812579147] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,038 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,038 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:21:48,038 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479928453] [2021-10-28 09:21:48,039 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:48,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1828472237, now seen corresponding path program 1 times [2021-10-28 09:21:48,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538062413] [2021-10-28 09:21:48,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,042 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,094 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538062413] [2021-10-28 09:21:48,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538062413] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:48,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481552551] [2021-10-28 09:21:48,096 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:48,096 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:48,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:48,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:48,097 INFO L87 Difference]: Start difference. First operand 1606 states and 2295 transitions. cyclomatic complexity: 693 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 2 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:48,134 INFO L93 Difference]: Finished difference Result 1606 states and 2266 transitions. [2021-10-28 09:21:48,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:48,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1606 states and 2266 transitions. [2021-10-28 09:21:48,155 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2021-10-28 09:21:48,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1606 states to 1606 states and 2266 transitions. [2021-10-28 09:21:48,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1606 [2021-10-28 09:21:48,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1606 [2021-10-28 09:21:48,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1606 states and 2266 transitions. [2021-10-28 09:21:48,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:48,183 INFO L681 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2021-10-28 09:21:48,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states and 2266 transitions. [2021-10-28 09:21:48,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 1606. [2021-10-28 09:21:48,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1606 states, 1606 states have (on average 1.4109589041095891) internal successors, (2266), 1605 states have internal predecessors, (2266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2266 transitions. [2021-10-28 09:21:48,243 INFO L704 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2021-10-28 09:21:48,243 INFO L587 BuchiCegarLoop]: Abstraction has 1606 states and 2266 transitions. [2021-10-28 09:21:48,243 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 09:21:48,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2266 transitions. [2021-10-28 09:21:48,261 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2021-10-28 09:21:48,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:48,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:48,268 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,268 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,268 INFO L791 eck$LassoCheckResult]: Stem: 8979#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8926#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8726#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8693#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 8694#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8839#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8797#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8798#L288-1 assume !(0 == ~M_E~0); 8865#L410-1 assume !(0 == ~T1_E~0); 8866#L415-1 assume !(0 == ~T2_E~0); 8761#L420-1 assume !(0 == ~T3_E~0); 8762#L425-1 assume !(0 == ~E_1~0); 8735#L430-1 assume !(0 == ~E_2~0); 8736#L435-1 assume !(0 == ~E_3~0); 8875#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8824#L189 assume !(1 == ~m_pc~0); 8763#L189-2 is_master_triggered_~__retres1~0 := 0; 8764#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8845#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8743#L502 assume !(0 != activate_threads_~tmp~1); 8744#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8861#L208 assume !(1 == ~t1_pc~0); 8966#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 8967#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8785#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8786#L510 assume !(0 != activate_threads_~tmp___0~0); 8677#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8678#L227 assume !(1 == ~t2_pc~0); 8741#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 8742#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8909#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8681#L518 assume !(0 != activate_threads_~tmp___1~0); 8682#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8787#L246 assume !(1 == ~t3_pc~0); 8788#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 8867#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8868#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8910#L526 assume !(0 != activate_threads_~tmp___2~0); 8953#L526-2 assume !(1 == ~M_E~0); 8921#L453-1 assume !(1 == ~T1_E~0); 8871#L458-1 assume !(1 == ~T2_E~0); 8872#L463-1 assume !(1 == ~T3_E~0); 8982#L468-1 assume !(1 == ~E_1~0); 8832#L473-1 assume !(1 == ~E_2~0); 8833#L478-1 assume !(1 == ~E_3~0); 8857#L644-1 [2021-10-28 09:21:48,269 INFO L793 eck$LassoCheckResult]: Loop: 8857#L644-1 assume !false; 8858#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 8886#L385 assume !false; 8727#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8728#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8664#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8665#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8701#L338 assume !(0 != eval_~tmp~0); 8771#L400 start_simulation_~kernel_st~0 := 2; 10267#L266-1 start_simulation_~kernel_st~0 := 3; 10266#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10265#L410-4 assume !(0 == ~T1_E~0); 10264#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10263#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10262#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10261#L430-3 assume !(0 == ~E_2~0); 10260#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10259#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10258#L189-12 assume !(1 == ~m_pc~0); 10257#L189-14 is_master_triggered_~__retres1~0 := 0; 10256#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10254#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10251#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10249#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10248#L208-12 assume !(1 == ~t1_pc~0); 10245#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 10244#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10243#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10241#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10239#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10237#L227-12 assume !(1 == ~t2_pc~0); 10234#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 10233#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8922#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8923#L518-12 assume !(0 != activate_threads_~tmp___1~0); 10230#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8964#L246-12 assume !(1 == ~t3_pc~0); 8965#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 10226#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10225#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10224#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8843#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 8844#L453-3 assume !(1 == ~T1_E~0); 8768#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8769#L463-3 assume !(1 == ~T3_E~0); 8846#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8835#L473-3 assume !(1 == ~E_2~0); 8836#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8822#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8823#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8706#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8834#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 8698#L663 assume !(0 == start_simulation_~tmp~3); 8700#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8716#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8717#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8894#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 8895#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8863#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 8864#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 8939#L676 assume !(0 != start_simulation_~tmp___0~1); 8857#L644-1 [2021-10-28 09:21:48,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 1 times [2021-10-28 09:21:48,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,270 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818532338] [2021-10-28 09:21:48,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,271 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:48,293 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:48,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:48,375 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:48,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,376 INFO L85 PathProgramCache]: Analyzing trace with hash -341551763, now seen corresponding path program 1 times [2021-10-28 09:21:48,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,376 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828095452] [2021-10-28 09:21:48,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,377 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,410 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828095452] [2021-10-28 09:21:48,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828095452] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,411 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,411 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:48,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779148073] [2021-10-28 09:21:48,415 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:48,415 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:48,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:48,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:48,419 INFO L87 Difference]: Start difference. First operand 1606 states and 2266 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 20.333333333333332) internal successors, (61), 3 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:48,459 INFO L93 Difference]: Finished difference Result 1936 states and 2706 transitions. [2021-10-28 09:21:48,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:48,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1936 states and 2706 transitions. [2021-10-28 09:21:48,483 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1843 [2021-10-28 09:21:48,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1936 states to 1936 states and 2706 transitions. [2021-10-28 09:21:48,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1936 [2021-10-28 09:21:48,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1936 [2021-10-28 09:21:48,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1936 states and 2706 transitions. [2021-10-28 09:21:48,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:48,533 INFO L681 BuchiCegarLoop]: Abstraction has 1936 states and 2706 transitions. [2021-10-28 09:21:48,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1936 states and 2706 transitions. [2021-10-28 09:21:48,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1936 to 1936. [2021-10-28 09:21:48,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1936 states, 1936 states have (on average 1.3977272727272727) internal successors, (2706), 1935 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1936 states to 1936 states and 2706 transitions. [2021-10-28 09:21:48,600 INFO L704 BuchiCegarLoop]: Abstraction has 1936 states and 2706 transitions. [2021-10-28 09:21:48,600 INFO L587 BuchiCegarLoop]: Abstraction has 1936 states and 2706 transitions. [2021-10-28 09:21:48,600 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 09:21:48,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1936 states and 2706 transitions. [2021-10-28 09:21:48,618 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1843 [2021-10-28 09:21:48,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:48,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:48,621 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,621 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,622 INFO L791 eck$LassoCheckResult]: Stem: 12535#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12470#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12274#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12240#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 12241#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12382#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12342#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12343#L288-1 assume !(0 == ~M_E~0); 12409#L410-1 assume !(0 == ~T1_E~0); 12410#L415-1 assume !(0 == ~T2_E~0); 12309#L420-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12310#L425-1 assume !(0 == ~E_1~0); 14107#L430-1 assume !(0 == ~E_2~0); 14106#L435-1 assume !(0 == ~E_3~0); 14105#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14104#L189 assume !(1 == ~m_pc~0); 14103#L189-2 is_master_triggered_~__retres1~0 := 0; 12389#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12390#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14081#L502 assume !(0 != activate_threads_~tmp~1); 14079#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12522#L208 assume !(1 == ~t1_pc~0); 12523#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 12524#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12332#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12333#L510 assume !(0 != activate_threads_~tmp___0~0); 12497#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12378#L227 assume !(1 == ~t2_pc~0); 12285#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 12286#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12453#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12228#L518 assume !(0 != activate_threads_~tmp___1~0); 12229#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12334#L246 assume !(1 == ~t3_pc~0); 12335#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 13999#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13998#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13997#L526 assume !(0 != activate_threads_~tmp___2~0); 13996#L526-2 assume !(1 == ~M_E~0); 13995#L453-1 assume !(1 == ~T1_E~0); 12546#L458-1 assume !(1 == ~T2_E~0); 12539#L463-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12540#L468-1 assume !(1 == ~E_1~0); 12375#L473-1 assume !(1 == ~E_2~0); 12376#L478-1 assume !(1 == ~E_3~0); 12400#L644-1 [2021-10-28 09:21:48,622 INFO L793 eck$LassoCheckResult]: Loop: 12400#L644-1 assume !false; 12822#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12817#L385 assume !false; 12811#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12805#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12799#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12797#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 12793#L338 assume !(0 != eval_~tmp~0); 12346#L400 start_simulation_~kernel_st~0 := 2; 12347#L266-1 start_simulation_~kernel_st~0 := 3; 12215#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12216#L410-4 assume !(0 == ~T1_E~0); 12243#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12244#L420-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12510#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14047#L430-3 assume !(0 == ~E_2~0); 14045#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14043#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14041#L189-12 assume !(1 == ~m_pc~0); 14040#L189-14 is_master_triggered_~__retres1~0 := 0; 14039#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14038#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14037#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14035#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14033#L208-12 assume !(1 == ~t1_pc~0); 14032#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 14031#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14030#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14029#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14028#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14026#L227-12 assume !(1 == ~t2_pc~0); 13983#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 13956#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13953#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12321#L518-12 assume !(0 != activate_threads_~tmp___1~0); 12267#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12268#L246-12 assume !(1 == ~t3_pc~0); 12435#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 12436#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12483#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12496#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12386#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 12387#L453-3 assume !(1 == ~T1_E~0); 12317#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12318#L463-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12391#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12379#L473-3 assume !(1 == ~E_2~0); 12380#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12368#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12369#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12254#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12377#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12246#L663 assume !(0 == start_simulation_~tmp~3); 12248#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12264#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12265#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12437#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 12438#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12479#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 13751#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13113#L676 assume !(0 != start_simulation_~tmp___0~1); 12400#L644-1 [2021-10-28 09:21:48,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,623 INFO L85 PathProgramCache]: Analyzing trace with hash -2104384495, now seen corresponding path program 1 times [2021-10-28 09:21:48,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,629 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307222924] [2021-10-28 09:21:48,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,630 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,668 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307222924] [2021-10-28 09:21:48,668 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307222924] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,669 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:21:48,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514962963] [2021-10-28 09:21:48,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:48,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1246796139, now seen corresponding path program 1 times [2021-10-28 09:21:48,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,674 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123735648] [2021-10-28 09:21:48,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,675 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,725 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123735648] [2021-10-28 09:21:48,725 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123735648] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,725 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,725 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:21:48,726 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877484683] [2021-10-28 09:21:48,726 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:48,726 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:48,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:48,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:48,728 INFO L87 Difference]: Start difference. First operand 1936 states and 2706 transitions. cyclomatic complexity: 774 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 2 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:48,765 INFO L93 Difference]: Finished difference Result 1606 states and 2237 transitions. [2021-10-28 09:21:48,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:48,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1606 states and 2237 transitions. [2021-10-28 09:21:48,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2021-10-28 09:21:48,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1606 states to 1606 states and 2237 transitions. [2021-10-28 09:21:48,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1606 [2021-10-28 09:21:48,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1606 [2021-10-28 09:21:48,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1606 states and 2237 transitions. [2021-10-28 09:21:48,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:48,808 INFO L681 BuchiCegarLoop]: Abstraction has 1606 states and 2237 transitions. [2021-10-28 09:21:48,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states and 2237 transitions. [2021-10-28 09:21:48,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 1606. [2021-10-28 09:21:48,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1606 states, 1606 states have (on average 1.3929016189290162) internal successors, (2237), 1605 states have internal predecessors, (2237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:48,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2237 transitions. [2021-10-28 09:21:48,848 INFO L704 BuchiCegarLoop]: Abstraction has 1606 states and 2237 transitions. [2021-10-28 09:21:48,848 INFO L587 BuchiCegarLoop]: Abstraction has 1606 states and 2237 transitions. [2021-10-28 09:21:48,848 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 09:21:48,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1606 states and 2237 transitions. [2021-10-28 09:21:48,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1545 [2021-10-28 09:21:48,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:48,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:48,861 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:48,861 INFO L791 eck$LassoCheckResult]: Stem: 16065#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16013#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15827#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15792#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 15793#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15935#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15895#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15896#L288-1 assume !(0 == ~M_E~0); 15962#L410-1 assume !(0 == ~T1_E~0); 15963#L415-1 assume !(0 == ~T2_E~0); 15863#L420-1 assume !(0 == ~T3_E~0); 15864#L425-1 assume !(0 == ~E_1~0); 15836#L430-1 assume !(0 == ~E_2~0); 15837#L435-1 assume !(0 == ~E_3~0); 15972#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15922#L189 assume !(1 == ~m_pc~0); 15865#L189-2 is_master_triggered_~__retres1~0 := 0; 15866#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15941#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15845#L502 assume !(0 != activate_threads_~tmp~1); 15846#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15958#L208 assume !(1 == ~t1_pc~0); 16054#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 16055#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15885#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15886#L510 assume !(0 != activate_threads_~tmp___0~0); 15776#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15777#L227 assume !(1 == ~t2_pc~0); 15838#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 15839#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16002#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15778#L518 assume !(0 != activate_threads_~tmp___1~0); 15779#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15887#L246 assume !(1 == ~t3_pc~0); 15888#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 15964#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15965#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16005#L526 assume !(0 != activate_threads_~tmp___2~0); 16040#L526-2 assume !(1 == ~M_E~0); 16011#L453-1 assume !(1 == ~T1_E~0); 15968#L458-1 assume !(1 == ~T2_E~0); 15969#L463-1 assume !(1 == ~T3_E~0); 16066#L468-1 assume !(1 == ~E_1~0); 15930#L473-1 assume !(1 == ~E_2~0); 15931#L478-1 assume !(1 == ~E_3~0); 15952#L644-1 [2021-10-28 09:21:48,862 INFO L793 eck$LassoCheckResult]: Loop: 15952#L644-1 assume !false; 16867#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 16620#L385 assume !false; 16866#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16861#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16857#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16855#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 16853#L338 assume !(0 != eval_~tmp~0); 16854#L400 start_simulation_~kernel_st~0 := 2; 17126#L266-1 start_simulation_~kernel_st~0 := 3; 17124#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17122#L410-4 assume !(0 == ~T1_E~0); 17120#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17118#L420-3 assume !(0 == ~T3_E~0); 17117#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17116#L430-3 assume !(0 == ~E_2~0); 17115#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17114#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17112#L189-12 assume !(1 == ~m_pc~0); 17110#L189-14 is_master_triggered_~__retres1~0 := 0; 17108#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17107#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17104#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17102#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17100#L208-12 assume !(1 == ~t1_pc~0); 17098#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 17096#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17094#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17092#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17090#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17088#L227-12 assume !(1 == ~t2_pc~0); 17082#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 17080#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17078#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17075#L518-12 assume !(0 != activate_threads_~tmp___1~0); 17073#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17072#L246-12 assume !(1 == ~t3_pc~0); 17071#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 17070#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17065#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17063#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17061#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 17059#L453-3 assume !(1 == ~T1_E~0); 17058#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17057#L463-3 assume !(1 == ~T3_E~0); 17055#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17053#L473-3 assume !(1 == ~E_2~0); 17051#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17049#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16959#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16954#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16952#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 16949#L663 assume !(0 == start_simulation_~tmp~3); 16946#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 16904#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 16898#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 16895#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 16880#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16874#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 16871#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16868#L676 assume !(0 != start_simulation_~tmp___0~1); 15952#L644-1 [2021-10-28 09:21:48,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 2 times [2021-10-28 09:21:48,863 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,863 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088660383] [2021-10-28 09:21:48,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,863 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:48,873 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:48,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:48,896 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:48,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:48,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1597610283, now seen corresponding path program 1 times [2021-10-28 09:21:48,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:48,897 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670115539] [2021-10-28 09:21:48,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:48,898 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:48,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:48,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:48,938 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:48,939 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670115539] [2021-10-28 09:21:48,939 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670115539] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:48,939 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:48,939 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:21:48,940 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958049485] [2021-10-28 09:21:48,940 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:48,940 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:48,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:21:48,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:21:48,942 INFO L87 Difference]: Start difference. First operand 1606 states and 2237 transitions. cyclomatic complexity: 635 Second operand has 5 states, 5 states have (on average 12.2) internal successors, (61), 5 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:49,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:49,073 INFO L93 Difference]: Finished difference Result 2760 states and 3790 transitions. [2021-10-28 09:21:49,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 09:21:49,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2760 states and 3790 transitions. [2021-10-28 09:21:49,145 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2684 [2021-10-28 09:21:49,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2760 states to 2760 states and 3790 transitions. [2021-10-28 09:21:49,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2760 [2021-10-28 09:21:49,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2760 [2021-10-28 09:21:49,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2760 states and 3790 transitions. [2021-10-28 09:21:49,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:49,185 INFO L681 BuchiCegarLoop]: Abstraction has 2760 states and 3790 transitions. [2021-10-28 09:21:49,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states and 3790 transitions. [2021-10-28 09:21:49,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1633. [2021-10-28 09:21:49,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1633 states, 1633 states have (on average 1.3864053888548684) internal successors, (2264), 1632 states have internal predecessors, (2264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:49,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1633 states to 1633 states and 2264 transitions. [2021-10-28 09:21:49,241 INFO L704 BuchiCegarLoop]: Abstraction has 1633 states and 2264 transitions. [2021-10-28 09:21:49,241 INFO L587 BuchiCegarLoop]: Abstraction has 1633 states and 2264 transitions. [2021-10-28 09:21:49,241 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 09:21:49,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1633 states and 2264 transitions. [2021-10-28 09:21:49,250 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1572 [2021-10-28 09:21:49,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:49,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:49,252 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:49,252 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:49,253 INFO L791 eck$LassoCheckResult]: Stem: 20497#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 20421#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20212#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20174#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 20175#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20324#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20280#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20281#L288-1 assume !(0 == ~M_E~0); 20353#L410-1 assume !(0 == ~T1_E~0); 20354#L415-1 assume !(0 == ~T2_E~0); 20248#L420-1 assume !(0 == ~T3_E~0); 20249#L425-1 assume !(0 == ~E_1~0); 20221#L430-1 assume !(0 == ~E_2~0); 20222#L435-1 assume !(0 == ~E_3~0); 20363#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20308#L189 assume !(1 == ~m_pc~0); 20250#L189-2 is_master_triggered_~__retres1~0 := 0; 20251#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20330#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20229#L502 assume !(0 != activate_threads_~tmp~1); 20230#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20349#L208 assume !(1 == ~t1_pc~0); 20486#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 20487#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20270#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20271#L510 assume !(0 != activate_threads_~tmp___0~0); 20158#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20159#L227 assume !(1 == ~t2_pc~0); 20223#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 20224#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20399#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20160#L518 assume !(0 != activate_threads_~tmp___1~0); 20161#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20272#L246 assume !(1 == ~t3_pc~0); 20273#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 20355#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20356#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20405#L526 assume !(0 != activate_threads_~tmp___2~0); 20472#L526-2 assume !(1 == ~M_E~0); 20415#L453-1 assume !(1 == ~T1_E~0); 20359#L458-1 assume !(1 == ~T2_E~0); 20360#L463-1 assume !(1 == ~T3_E~0); 20501#L468-1 assume !(1 == ~E_1~0); 20316#L473-1 assume !(1 == ~E_2~0); 20317#L478-1 assume !(1 == ~E_3~0); 20342#L644-1 [2021-10-28 09:21:49,253 INFO L793 eck$LassoCheckResult]: Loop: 20342#L644-1 assume !false; 21733#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 21393#L385 assume !false; 21654#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21651#L301 assume !(0 == ~m_st~0); 21652#L305 assume !(0 == ~t1_st~0); 21650#L309 assume !(0 == ~t2_st~0); 20197#L313 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 20199#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21301#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 21302#L338 assume !(0 != eval_~tmp~0); 21643#L400 start_simulation_~kernel_st~0 := 2; 20401#L266-1 start_simulation_~kernel_st~0 := 3; 20402#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20403#L410-4 assume !(0 == ~T1_E~0); 20404#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20470#L420-3 assume !(0 == ~T3_E~0); 20471#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20442#L430-3 assume !(0 == ~E_2~0); 20443#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20395#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20396#L189-12 assume !(1 == ~m_pc~0); 20392#L189-14 is_master_triggered_~__retres1~0 := 0; 20393#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20334#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20335#L502-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20219#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20220#L208-12 assume !(1 == ~t1_pc~0); 20347#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 20348#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20208#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20209#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20302#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20303#L227-12 assume !(1 == ~t2_pc~0); 20345#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 20346#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20416#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20417#L518-12 assume !(0 != activate_threads_~tmp___1~0); 20203#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20204#L246-12 assume !(1 == ~t3_pc~0); 20377#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 20378#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20456#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20457#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20327#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 20328#L453-3 assume !(1 == ~T1_E~0); 20255#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20256#L463-3 assume !(1 == ~T3_E~0); 20388#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20389#L473-3 assume !(1 == ~E_2~0); 20437#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20438#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20323#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20188#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20318#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 20180#L663 assume !(0 == start_simulation_~tmp~3); 20182#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20200#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20201#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21738#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 21737#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21736#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 21735#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 21734#L676 assume !(0 != start_simulation_~tmp___0~1); 20342#L644-1 [2021-10-28 09:21:49,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:49,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 3 times [2021-10-28 09:21:49,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:49,255 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120292833] [2021-10-28 09:21:49,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:49,255 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:49,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:49,266 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:49,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:49,290 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:49,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:49,291 INFO L85 PathProgramCache]: Analyzing trace with hash 66836469, now seen corresponding path program 1 times [2021-10-28 09:21:49,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:49,292 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867461288] [2021-10-28 09:21:49,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:49,292 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:49,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:49,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:49,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:49,383 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867461288] [2021-10-28 09:21:49,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867461288] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:49,384 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:49,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 09:21:49,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2073928481] [2021-10-28 09:21:49,385 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:49,385 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:49,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:21:49,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:21:49,386 INFO L87 Difference]: Start difference. First operand 1633 states and 2264 transitions. cyclomatic complexity: 635 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:49,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:49,598 INFO L93 Difference]: Finished difference Result 3089 states and 4255 transitions. [2021-10-28 09:21:49,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 09:21:49,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3089 states and 4255 transitions. [2021-10-28 09:21:49,624 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3028 [2021-10-28 09:21:49,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3089 states to 3089 states and 4255 transitions. [2021-10-28 09:21:49,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3089 [2021-10-28 09:21:49,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3089 [2021-10-28 09:21:49,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3089 states and 4255 transitions. [2021-10-28 09:21:49,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:49,669 INFO L681 BuchiCegarLoop]: Abstraction has 3089 states and 4255 transitions. [2021-10-28 09:21:49,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3089 states and 4255 transitions. [2021-10-28 09:21:49,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3089 to 1687. [2021-10-28 09:21:49,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1687 states, 1687 states have (on average 1.3639596917605217) internal successors, (2301), 1686 states have internal predecessors, (2301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:49,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1687 states to 1687 states and 2301 transitions. [2021-10-28 09:21:49,733 INFO L704 BuchiCegarLoop]: Abstraction has 1687 states and 2301 transitions. [2021-10-28 09:21:49,734 INFO L587 BuchiCegarLoop]: Abstraction has 1687 states and 2301 transitions. [2021-10-28 09:21:49,734 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 09:21:49,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1687 states and 2301 transitions. [2021-10-28 09:21:49,743 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1626 [2021-10-28 09:21:49,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:49,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:49,745 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:49,745 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:49,745 INFO L791 eck$LassoCheckResult]: Stem: 25203#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 25142#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24945#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24909#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 24910#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25054#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25013#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25014#L288-1 assume !(0 == ~M_E~0); 25083#L410-1 assume !(0 == ~T1_E~0); 25084#L415-1 assume !(0 == ~T2_E~0); 24981#L420-1 assume !(0 == ~T3_E~0); 24982#L425-1 assume !(0 == ~E_1~0); 24954#L430-1 assume !(0 == ~E_2~0); 24955#L435-1 assume !(0 == ~E_3~0); 25093#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25041#L189 assume !(1 == ~m_pc~0); 24983#L189-2 is_master_triggered_~__retres1~0 := 0; 24984#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25060#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 24963#L502 assume !(0 != activate_threads_~tmp~1); 24964#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25078#L208 assume !(1 == ~t1_pc~0); 25191#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 25192#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25002#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25003#L510 assume !(0 != activate_threads_~tmp___0~0); 24893#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24894#L227 assume !(1 == ~t2_pc~0); 24958#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 24959#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25126#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 24895#L518 assume !(0 != activate_threads_~tmp___1~0); 24896#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25004#L246 assume !(1 == ~t3_pc~0); 25005#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 25085#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25086#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25128#L526 assume !(0 != activate_threads_~tmp___2~0); 25179#L526-2 assume !(1 == ~M_E~0); 25137#L453-1 assume !(1 == ~T1_E~0); 25089#L458-1 assume !(1 == ~T2_E~0); 25090#L463-1 assume !(1 == ~T3_E~0); 25205#L468-1 assume !(1 == ~E_1~0); 25047#L473-1 assume !(1 == ~E_2~0); 25048#L478-1 assume !(1 == ~E_3~0); 25072#L644-1 [2021-10-28 09:21:49,746 INFO L793 eck$LassoCheckResult]: Loop: 25072#L644-1 assume !false; 25442#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 25430#L385 assume !false; 25431#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25426#L301 assume !(0 == ~m_st~0); 25427#L305 assume !(0 == ~t1_st~0); 25423#L309 assume !(0 == ~t2_st~0); 25424#L313 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 25425#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25783#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 25654#L338 assume !(0 != eval_~tmp~0); 25655#L400 start_simulation_~kernel_st~0 := 2; 25650#L266-1 start_simulation_~kernel_st~0 := 3; 25651#L410-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25646#L410-4 assume !(0 == ~T1_E~0); 25647#L415-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25642#L420-3 assume !(0 == ~T3_E~0); 25643#L425-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25638#L430-3 assume !(0 == ~E_2~0); 25639#L435-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25634#L440-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25635#L189-12 assume !(1 == ~m_pc~0); 25630#L189-14 is_master_triggered_~__retres1~0 := 0; 25631#L200-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25626#L201-4 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25627#L502-12 assume !(0 != activate_threads_~tmp~1); 25621#L502-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25622#L208-12 assume !(1 == ~t1_pc~0); 25616#L208-14 is_transmit1_triggered_~__retres1~1 := 0; 25617#L219-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25610#L220-4 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25611#L510-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25602#L510-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25603#L227-12 assume !(1 == ~t2_pc~0); 25588#L227-14 is_transmit2_triggered_~__retres1~2 := 0; 25589#L238-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25576#L239-4 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25577#L518-12 assume !(0 != activate_threads_~tmp___1~0); 25563#L518-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25564#L246-12 assume !(1 == ~t3_pc~0); 25553#L246-14 is_transmit3_triggered_~__retres1~3 := 0; 25554#L257-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25545#L258-4 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25546#L526-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25537#L526-14 assume 1 == ~M_E~0;~M_E~0 := 2; 25538#L453-3 assume !(1 == ~T1_E~0); 25529#L458-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25530#L463-3 assume !(1 == ~T3_E~0); 25522#L468-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25523#L473-3 assume !(1 == ~E_2~0); 25514#L478-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25515#L483-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25502#L301-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25500#L323-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25487#L324-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 25488#L663 assume !(0 == start_simulation_~tmp~3); 25475#L663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25476#L301-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25464#L323-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25465#L324-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 25457#L618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25458#L625 stop_simulation_#res := stop_simulation_~__retres2~0; 25450#L626 start_simulation_#t~ret18 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 25451#L676 assume !(0 != start_simulation_~tmp___0~1); 25072#L644-1 [2021-10-28 09:21:49,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:49,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 4 times [2021-10-28 09:21:49,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:49,747 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184107170] [2021-10-28 09:21:49,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:49,747 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:49,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:49,759 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:49,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:49,794 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:49,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:49,799 INFO L85 PathProgramCache]: Analyzing trace with hash -1778530697, now seen corresponding path program 1 times [2021-10-28 09:21:49,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:49,799 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937517828] [2021-10-28 09:21:49,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:49,800 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:49,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:49,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:49,843 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:49,843 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937517828] [2021-10-28 09:21:49,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937517828] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:49,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:49,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:49,844 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164364631] [2021-10-28 09:21:49,844 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 09:21:49,845 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:49,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:49,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:49,846 INFO L87 Difference]: Start difference. First operand 1687 states and 2301 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:49,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:49,934 INFO L93 Difference]: Finished difference Result 2626 states and 3527 transitions. [2021-10-28 09:21:49,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:49,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2626 states and 3527 transitions. [2021-10-28 09:21:49,963 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2563 [2021-10-28 09:21:49,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2626 states to 2626 states and 3527 transitions. [2021-10-28 09:21:49,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2626 [2021-10-28 09:21:49,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2626 [2021-10-28 09:21:49,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2626 states and 3527 transitions. [2021-10-28 09:21:49,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:49,999 INFO L681 BuchiCegarLoop]: Abstraction has 2626 states and 3527 transitions. [2021-10-28 09:21:50,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states and 3527 transitions. [2021-10-28 09:21:50,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2534. [2021-10-28 09:21:50,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2534 states, 2534 states have (on average 1.3460931333859512) internal successors, (3411), 2533 states have internal predecessors, (3411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:50,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2534 states to 2534 states and 3411 transitions. [2021-10-28 09:21:50,069 INFO L704 BuchiCegarLoop]: Abstraction has 2534 states and 3411 transitions. [2021-10-28 09:21:50,069 INFO L587 BuchiCegarLoop]: Abstraction has 2534 states and 3411 transitions. [2021-10-28 09:21:50,070 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 09:21:50,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2534 states and 3411 transitions. [2021-10-28 09:21:50,084 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2471 [2021-10-28 09:21:50,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:50,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:50,085 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:50,085 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:50,086 INFO L791 eck$LassoCheckResult]: Stem: 29531#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 29465#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29263#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29228#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 29229#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29376#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29334#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29335#L288-1 assume !(0 == ~M_E~0); 29403#L410-1 assume !(0 == ~T1_E~0); 29404#L415-1 assume !(0 == ~T2_E~0); 29298#L420-1 assume !(0 == ~T3_E~0); 29299#L425-1 assume !(0 == ~E_1~0); 29272#L430-1 assume !(0 == ~E_2~0); 29273#L435-1 assume !(0 == ~E_3~0); 29413#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29360#L189 assume !(1 == ~m_pc~0); 29300#L189-2 is_master_triggered_~__retres1~0 := 0; 29301#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29383#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29280#L502 assume !(0 != activate_threads_~tmp~1); 29281#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29399#L208 assume !(1 == ~t1_pc~0); 29517#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 29518#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29322#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 29323#L510 assume !(0 != activate_threads_~tmp___0~0); 29212#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29213#L227 assume !(1 == ~t2_pc~0); 29276#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 29277#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29451#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29216#L518 assume !(0 != activate_threads_~tmp___1~0); 29217#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29324#L246 assume !(1 == ~t3_pc~0); 29325#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 29405#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29406#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29452#L526 assume !(0 != activate_threads_~tmp___2~0); 29499#L526-2 assume !(1 == ~M_E~0); 29463#L453-1 assume !(1 == ~T1_E~0); 29409#L458-1 assume !(1 == ~T2_E~0); 29410#L463-1 assume !(1 == ~T3_E~0); 29532#L468-1 assume !(1 == ~E_1~0); 29367#L473-1 assume !(1 == ~E_2~0); 29368#L478-1 assume !(1 == ~E_3~0); 29395#L644-1 assume !false; 30614#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 30608#L385 [2021-10-28 09:21:50,086 INFO L793 eck$LassoCheckResult]: Loop: 30608#L385 assume !false; 30607#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30572#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30569#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30566#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30564#L338 assume 0 != eval_~tmp~0; 30562#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 30563#L346 assume !(0 != eval_~tmp_ndt_1~0); 30659#L343 assume !(0 == ~t1_st~0); 30651#L357 assume !(0 == ~t2_st~0); 30649#L371 assume !(0 == ~t3_st~0); 30608#L385 [2021-10-28 09:21:50,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:50,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 1 times [2021-10-28 09:21:50,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:50,087 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995190024] [2021-10-28 09:21:50,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:50,088 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:50,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,099 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:50,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,119 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:50,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:50,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1333816928, now seen corresponding path program 1 times [2021-10-28 09:21:50,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:50,121 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890031284] [2021-10-28 09:21:50,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:50,121 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:50,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,125 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:50,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,130 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:50,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:50,131 INFO L85 PathProgramCache]: Analyzing trace with hash 451456974, now seen corresponding path program 1 times [2021-10-28 09:21:50,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:50,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886769288] [2021-10-28 09:21:50,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:50,132 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:50,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:50,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:50,164 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:50,164 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886769288] [2021-10-28 09:21:50,164 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886769288] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:50,164 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:50,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:50,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695259220] [2021-10-28 09:21:50,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:50,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:50,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:50,266 INFO L87 Difference]: Start difference. First operand 2534 states and 3411 transitions. cyclomatic complexity: 884 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:50,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:50,344 INFO L93 Difference]: Finished difference Result 4612 states and 6120 transitions. [2021-10-28 09:21:50,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:50,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4612 states and 6120 transitions. [2021-10-28 09:21:50,374 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 4282 [2021-10-28 09:21:50,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4612 states to 4612 states and 6120 transitions. [2021-10-28 09:21:50,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4612 [2021-10-28 09:21:50,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4612 [2021-10-28 09:21:50,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4612 states and 6120 transitions. [2021-10-28 09:21:50,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:50,469 INFO L681 BuchiCegarLoop]: Abstraction has 4612 states and 6120 transitions. [2021-10-28 09:21:50,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4612 states and 6120 transitions. [2021-10-28 09:21:50,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4612 to 4514. [2021-10-28 09:21:50,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4514 states, 4514 states have (on average 1.3278688524590163) internal successors, (5994), 4513 states have internal predecessors, (5994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:50,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4514 states to 4514 states and 5994 transitions. [2021-10-28 09:21:50,699 INFO L704 BuchiCegarLoop]: Abstraction has 4514 states and 5994 transitions. [2021-10-28 09:21:50,699 INFO L587 BuchiCegarLoop]: Abstraction has 4514 states and 5994 transitions. [2021-10-28 09:21:50,699 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 09:21:50,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4514 states and 5994 transitions. [2021-10-28 09:21:50,727 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 4184 [2021-10-28 09:21:50,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:50,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:50,729 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:50,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:50,729 INFO L791 eck$LassoCheckResult]: Stem: 36702#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 36627#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36421#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36383#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 36384#L273-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 36641#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38727#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38726#L288-1 assume !(0 == ~M_E~0); 38725#L410-1 assume !(0 == ~T1_E~0); 38724#L415-1 assume !(0 == ~T2_E~0); 38723#L420-1 assume !(0 == ~T3_E~0); 38722#L425-1 assume !(0 == ~E_1~0); 38721#L430-1 assume !(0 == ~E_2~0); 38720#L435-1 assume !(0 == ~E_3~0); 38719#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38718#L189 assume !(1 == ~m_pc~0); 38717#L189-2 is_master_triggered_~__retres1~0 := 0; 38716#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38715#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 38714#L502 assume !(0 != activate_threads_~tmp~1); 38713#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38712#L208 assume !(1 == ~t1_pc~0); 38711#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 38710#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38709#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38708#L510 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36366#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36367#L227 assume !(1 == ~t2_pc~0); 36434#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 36435#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36608#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 36370#L518 assume !(0 != activate_threads_~tmp___1~0); 36371#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36481#L246 assume !(1 == ~t3_pc~0); 36482#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 36564#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36565#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36612#L526 assume !(0 != activate_threads_~tmp___2~0); 36669#L526-2 assume !(1 == ~M_E~0); 36684#L453-1 assume !(1 == ~T1_E~0); 36568#L458-1 assume !(1 == ~T2_E~0); 36569#L463-1 assume !(1 == ~T3_E~0); 36703#L468-1 assume !(1 == ~E_1~0); 36529#L473-1 assume !(1 == ~E_2~0); 36530#L478-1 assume !(1 == ~E_3~0); 36553#L644-1 assume !false; 38635#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 38630#L385 [2021-10-28 09:21:50,730 INFO L793 eck$LassoCheckResult]: Loop: 38630#L385 assume !false; 38628#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38629#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 39213#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 39212#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 38607#L338 assume 0 != eval_~tmp~0; 38608#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 38553#L346 assume !(0 != eval_~tmp_ndt_1~0); 37202#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 37197#L360 assume !(0 != eval_~tmp_ndt_2~0); 37198#L357 assume !(0 == ~t2_st~0); 38634#L371 assume !(0 == ~t3_st~0); 38630#L385 [2021-10-28 09:21:50,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:50,731 INFO L85 PathProgramCache]: Analyzing trace with hash 216645527, now seen corresponding path program 1 times [2021-10-28 09:21:50,731 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:50,732 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771523176] [2021-10-28 09:21:50,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:50,732 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:50,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:50,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:50,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:50,765 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771523176] [2021-10-28 09:21:50,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771523176] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:50,766 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:50,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:50,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1577054255] [2021-10-28 09:21:50,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 09:21:50,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:50,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1605322485, now seen corresponding path program 1 times [2021-10-28 09:21:50,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:50,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897189785] [2021-10-28 09:21:50,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:50,769 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:50,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,774 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:50,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:50,781 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:50,953 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:50,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:50,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:50,954 INFO L87 Difference]: Start difference. First operand 4514 states and 5994 transitions. cyclomatic complexity: 1491 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:51,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:51,005 INFO L93 Difference]: Finished difference Result 3690 states and 4920 transitions. [2021-10-28 09:21:51,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:51,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3690 states and 4920 transitions. [2021-10-28 09:21:51,035 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3617 [2021-10-28 09:21:51,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3690 states to 3690 states and 4920 transitions. [2021-10-28 09:21:51,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3690 [2021-10-28 09:21:51,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3690 [2021-10-28 09:21:51,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3690 states and 4920 transitions. [2021-10-28 09:21:51,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:51,094 INFO L681 BuchiCegarLoop]: Abstraction has 3690 states and 4920 transitions. [2021-10-28 09:21:51,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3690 states and 4920 transitions. [2021-10-28 09:21:51,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3690 to 3690. [2021-10-28 09:21:51,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3690 states, 3690 states have (on average 1.3333333333333333) internal successors, (4920), 3689 states have internal predecessors, (4920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:51,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3690 states to 3690 states and 4920 transitions. [2021-10-28 09:21:51,217 INFO L704 BuchiCegarLoop]: Abstraction has 3690 states and 4920 transitions. [2021-10-28 09:21:51,217 INFO L587 BuchiCegarLoop]: Abstraction has 3690 states and 4920 transitions. [2021-10-28 09:21:51,217 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 09:21:51,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3690 states and 4920 transitions. [2021-10-28 09:21:51,238 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3617 [2021-10-28 09:21:51,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:51,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:51,240 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:51,240 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:51,241 INFO L791 eck$LassoCheckResult]: Stem: 44898#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 44831#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44633#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44593#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 44594#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44744#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44702#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44703#L288-1 assume !(0 == ~M_E~0); 44770#L410-1 assume !(0 == ~T1_E~0); 44771#L415-1 assume !(0 == ~T2_E~0); 44667#L420-1 assume !(0 == ~T3_E~0); 44668#L425-1 assume !(0 == ~E_1~0); 44640#L430-1 assume !(0 == ~E_2~0); 44641#L435-1 assume !(0 == ~E_3~0); 44782#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44728#L189 assume !(1 == ~m_pc~0); 44669#L189-2 is_master_triggered_~__retres1~0 := 0; 44670#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44751#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 44648#L502 assume !(0 != activate_threads_~tmp~1); 44649#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44767#L208 assume !(1 == ~t1_pc~0); 44883#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 44884#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44690#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44691#L510 assume !(0 != activate_threads_~tmp___0~0); 44576#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44577#L227 assume !(1 == ~t2_pc~0); 44646#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 44647#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44815#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 44580#L518 assume !(0 != activate_threads_~tmp___1~0); 44581#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44692#L246 assume !(1 == ~t3_pc~0); 44693#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 44772#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44773#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 44820#L526 assume !(0 != activate_threads_~tmp___2~0); 44869#L526-2 assume !(1 == ~M_E~0); 44828#L453-1 assume !(1 == ~T1_E~0); 44776#L458-1 assume !(1 == ~T2_E~0); 44777#L463-1 assume !(1 == ~T3_E~0); 44901#L468-1 assume !(1 == ~E_1~0); 44736#L473-1 assume !(1 == ~E_2~0); 44737#L478-1 assume !(1 == ~E_3~0); 44762#L644-1 assume !false; 45502#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 45500#L385 [2021-10-28 09:21:51,241 INFO L793 eck$LassoCheckResult]: Loop: 45500#L385 assume !false; 45499#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45498#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45497#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 45496#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 45495#L338 assume 0 != eval_~tmp~0; 45494#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 45493#L346 assume !(0 != eval_~tmp_ndt_1~0); 45491#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 45488#L360 assume !(0 != eval_~tmp_ndt_2~0); 45460#L357 assume !(0 == ~t2_st~0); 45461#L371 assume !(0 == ~t3_st~0); 45500#L385 [2021-10-28 09:21:51,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:51,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 2 times [2021-10-28 09:21:51,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:51,243 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195699248] [2021-10-28 09:21:51,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:51,243 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:51,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:51,260 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:51,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:51,296 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:51,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:51,299 INFO L85 PathProgramCache]: Analyzing trace with hash -1605322485, now seen corresponding path program 2 times [2021-10-28 09:21:51,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:51,299 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513157475] [2021-10-28 09:21:51,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:51,300 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:51,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:51,307 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:51,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:51,314 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:51,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:51,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1106290013, now seen corresponding path program 1 times [2021-10-28 09:21:51,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:51,316 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544207987] [2021-10-28 09:21:51,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:51,316 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:51,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:51,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:51,373 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:51,374 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544207987] [2021-10-28 09:21:51,374 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544207987] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:51,374 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:51,374 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:21:51,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318240788] [2021-10-28 09:21:51,556 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:51,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:51,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:51,558 INFO L87 Difference]: Start difference. First operand 3690 states and 4920 transitions. cyclomatic complexity: 1237 Second operand has 3 states, 3 states have (on average 19.666666666666668) internal successors, (59), 3 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:51,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:51,643 INFO L93 Difference]: Finished difference Result 6249 states and 8277 transitions. [2021-10-28 09:21:51,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:51,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6249 states and 8277 transitions. [2021-10-28 09:21:51,748 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6151 [2021-10-28 09:21:51,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6249 states to 6249 states and 8277 transitions. [2021-10-28 09:21:51,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6249 [2021-10-28 09:21:51,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6249 [2021-10-28 09:21:51,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6249 states and 8277 transitions. [2021-10-28 09:21:51,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:51,822 INFO L681 BuchiCegarLoop]: Abstraction has 6249 states and 8277 transitions. [2021-10-28 09:21:51,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6249 states and 8277 transitions. [2021-10-28 09:21:51,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6249 to 5969. [2021-10-28 09:21:51,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5969 states, 5969 states have (on average 1.3313787904171552) internal successors, (7947), 5968 states have internal predecessors, (7947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:52,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5969 states to 5969 states and 7947 transitions. [2021-10-28 09:21:52,022 INFO L704 BuchiCegarLoop]: Abstraction has 5969 states and 7947 transitions. [2021-10-28 09:21:52,022 INFO L587 BuchiCegarLoop]: Abstraction has 5969 states and 7947 transitions. [2021-10-28 09:21:52,022 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 09:21:52,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5969 states and 7947 transitions. [2021-10-28 09:21:52,062 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 5871 [2021-10-28 09:21:52,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:52,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:52,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:52,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:52,064 INFO L791 eck$LassoCheckResult]: Stem: 54846#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 54780#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 54577#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 54539#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 54540#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54685#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54643#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54644#L288-1 assume !(0 == ~M_E~0); 54716#L410-1 assume !(0 == ~T1_E~0); 54717#L415-1 assume !(0 == ~T2_E~0); 54610#L420-1 assume !(0 == ~T3_E~0); 54611#L425-1 assume !(0 == ~E_1~0); 54584#L430-1 assume !(0 == ~E_2~0); 54585#L435-1 assume !(0 == ~E_3~0); 54727#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54669#L189 assume !(1 == ~m_pc~0); 54612#L189-2 is_master_triggered_~__retres1~0 := 0; 54613#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54693#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 54592#L502 assume !(0 != activate_threads_~tmp~1); 54593#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 54713#L208 assume !(1 == ~t1_pc~0); 54832#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 54833#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54631#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 54632#L510 assume !(0 != activate_threads_~tmp___0~0); 54524#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 54525#L227 assume !(1 == ~t2_pc~0); 54590#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 54591#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54765#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54528#L518 assume !(0 != activate_threads_~tmp___1~0); 54529#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54633#L246 assume !(1 == ~t3_pc~0); 54634#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 54718#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54719#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 54771#L526 assume !(0 != activate_threads_~tmp___2~0); 54815#L526-2 assume !(1 == ~M_E~0); 54778#L453-1 assume !(1 == ~T1_E~0); 54722#L458-1 assume !(1 == ~T2_E~0); 54723#L463-1 assume !(1 == ~T3_E~0); 54850#L468-1 assume !(1 == ~E_1~0); 54677#L473-1 assume !(1 == ~E_2~0); 54678#L478-1 assume !(1 == ~E_3~0); 54705#L644-1 assume !false; 56008#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 55999#L385 [2021-10-28 09:21:52,064 INFO L793 eck$LassoCheckResult]: Loop: 55999#L385 assume !false; 56000#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 55979#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 55980#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 55968#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 55969#L338 assume 0 != eval_~tmp~0; 55961#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 55963#L346 assume !(0 != eval_~tmp_ndt_1~0); 55954#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 55955#L360 assume !(0 != eval_~tmp_ndt_2~0); 56017#L357 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 55553#L374 assume !(0 != eval_~tmp_ndt_3~0); 56006#L371 assume !(0 == ~t3_st~0); 55999#L385 [2021-10-28 09:21:52,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:52,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 3 times [2021-10-28 09:21:52,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:52,066 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89523236] [2021-10-28 09:21:52,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:52,066 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:52,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:52,079 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:52,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:52,111 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:52,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:52,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1774485897, now seen corresponding path program 1 times [2021-10-28 09:21:52,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:52,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921578124] [2021-10-28 09:21:52,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:52,113 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:52,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:52,119 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:52,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:52,125 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:52,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:52,126 INFO L85 PathProgramCache]: Analyzing trace with hash -64872585, now seen corresponding path program 1 times [2021-10-28 09:21:52,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:52,127 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66821198] [2021-10-28 09:21:52,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:52,127 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:52,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:21:52,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:21:52,168 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:21:52,168 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66821198] [2021-10-28 09:21:52,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66821198] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:21:52,168 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:21:52,169 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:21:52,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082757201] [2021-10-28 09:21:52,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:21:52,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:21:52,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:21:52,381 INFO L87 Difference]: Start difference. First operand 5969 states and 7947 transitions. cyclomatic complexity: 1985 Second operand has 3 states, 2 states have (on average 30.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:52,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:21:52,497 INFO L93 Difference]: Finished difference Result 9386 states and 12488 transitions. [2021-10-28 09:21:52,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:21:52,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9386 states and 12488 transitions. [2021-10-28 09:21:52,710 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 9268 [2021-10-28 09:21:52,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9386 states to 9386 states and 12488 transitions. [2021-10-28 09:21:52,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9386 [2021-10-28 09:21:52,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9386 [2021-10-28 09:21:52,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9386 states and 12488 transitions. [2021-10-28 09:21:52,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 09:21:52,797 INFO L681 BuchiCegarLoop]: Abstraction has 9386 states and 12488 transitions. [2021-10-28 09:21:52,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9386 states and 12488 transitions. [2021-10-28 09:21:52,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9386 to 9386. [2021-10-28 09:21:52,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9386 states, 9386 states have (on average 1.3304922224589815) internal successors, (12488), 9385 states have internal predecessors, (12488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:21:53,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9386 states to 9386 states and 12488 transitions. [2021-10-28 09:21:53,023 INFO L704 BuchiCegarLoop]: Abstraction has 9386 states and 12488 transitions. [2021-10-28 09:21:53,024 INFO L587 BuchiCegarLoop]: Abstraction has 9386 states and 12488 transitions. [2021-10-28 09:21:53,024 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 09:21:53,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9386 states and 12488 transitions. [2021-10-28 09:21:53,131 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 9268 [2021-10-28 09:21:53,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 09:21:53,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 09:21:53,133 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:53,133 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:21:53,133 INFO L791 eck$LassoCheckResult]: Stem: 70218#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 70150#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 69942#L607 havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 69905#L266 assume 1 == ~m_i~0;~m_st~0 := 0; 69906#L273-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70055#L278-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70012#L283-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70013#L288-1 assume !(0 == ~M_E~0); 70085#L410-1 assume !(0 == ~T1_E~0); 70086#L415-1 assume !(0 == ~T2_E~0); 69976#L420-1 assume !(0 == ~T3_E~0); 69977#L425-1 assume !(0 == ~E_1~0); 69949#L430-1 assume !(0 == ~E_2~0); 69950#L435-1 assume !(0 == ~E_3~0); 70096#L440-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70039#L189 assume !(1 == ~m_pc~0); 69978#L189-2 is_master_triggered_~__retres1~0 := 0; 69979#L200 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70063#L201 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69958#L502 assume !(0 != activate_threads_~tmp~1); 69959#L502-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70082#L208 assume !(1 == ~t1_pc~0); 70206#L208-2 is_transmit1_triggered_~__retres1~1 := 0; 70207#L219 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70000#L220 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 70001#L510 assume !(0 != activate_threads_~tmp___0~0); 69887#L510-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69888#L227 assume !(1 == ~t2_pc~0); 69956#L227-2 is_transmit2_triggered_~__retres1~2 := 0; 69957#L238 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70131#L239 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69891#L518 assume !(0 != activate_threads_~tmp___1~0); 69892#L518-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70002#L246 assume !(1 == ~t3_pc~0); 70003#L246-2 is_transmit3_triggered_~__retres1~3 := 0; 70087#L257 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70088#L258 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70136#L526 assume !(0 != activate_threads_~tmp___2~0); 70190#L526-2 assume !(1 == ~M_E~0); 70147#L453-1 assume !(1 == ~T1_E~0); 70091#L458-1 assume !(1 == ~T2_E~0); 70092#L463-1 assume !(1 == ~T3_E~0); 70221#L468-1 assume !(1 == ~E_1~0); 70047#L473-1 assume !(1 == ~E_2~0); 70048#L478-1 assume !(1 == ~E_3~0); 70073#L644-1 assume !false; 78267#L645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 74241#L385 [2021-10-28 09:21:53,134 INFO L793 eck$LassoCheckResult]: Loop: 74241#L385 assume !false; 78263#L334 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 78261#L301 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 78259#L323 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 78256#L324 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 78254#L338 assume 0 != eval_~tmp~0; 78252#L338-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 78250#L346 assume !(0 != eval_~tmp_ndt_1~0); 78247#L343 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 78245#L360 assume !(0 != eval_~tmp_ndt_2~0); 78191#L357 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 78187#L374 assume !(0 != eval_~tmp_ndt_3~0); 77960#L371 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 74240#L388 assume !(0 != eval_~tmp_ndt_4~0); 74241#L385 [2021-10-28 09:21:53,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:53,135 INFO L85 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 4 times [2021-10-28 09:21:53,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:53,137 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798324406] [2021-10-28 09:21:53,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:53,137 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:53,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,155 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:53,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,173 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:53,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:53,174 INFO L85 PathProgramCache]: Analyzing trace with hash -825512478, now seen corresponding path program 1 times [2021-10-28 09:21:53,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:53,175 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454893145] [2021-10-28 09:21:53,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:53,176 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:53,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,180 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:53,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,186 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:53,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:21:53,187 INFO L85 PathProgramCache]: Analyzing trace with hash -2011050572, now seen corresponding path program 1 times [2021-10-28 09:21:53,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:21:53,188 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693061286] [2021-10-28 09:21:53,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:21:53,188 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:21:53,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,201 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:21:53,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:21:53,227 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:21:55,487 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 09:21:55 BoogieIcfgContainer [2021-10-28 09:21:55,487 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 09:21:55,488 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 09:21:55,488 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 09:21:55,489 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 09:21:55,490 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:21:45" (3/4) ... [2021-10-28 09:21:55,494 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 09:21:55,582 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/witness.graphml [2021-10-28 09:21:55,583 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 09:21:55,586 INFO L168 Benchmark]: Toolchain (without parser) took 12691.19 ms. Allocated memory was 130.0 MB in the beginning and 385.9 MB in the end (delta: 255.9 MB). Free memory was 96.5 MB in the beginning and 257.2 MB in the end (delta: -160.7 MB). Peak memory consumption was 94.6 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,587 INFO L168 Benchmark]: CDTParser took 0.31 ms. Allocated memory is still 86.0 MB. Free memory is still 42.5 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:21:55,588 INFO L168 Benchmark]: CACSL2BoogieTranslator took 707.83 ms. Allocated memory is still 130.0 MB. Free memory was 96.5 MB in the beginning and 103.6 MB in the end (delta: -7.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,589 INFO L168 Benchmark]: Boogie Procedure Inliner took 124.44 ms. Allocated memory is still 130.0 MB. Free memory was 103.6 MB in the beginning and 100.4 MB in the end (delta: 3.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,590 INFO L168 Benchmark]: Boogie Preprocessor took 108.68 ms. Allocated memory is still 130.0 MB. Free memory was 100.4 MB in the beginning and 97.4 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,590 INFO L168 Benchmark]: RCFGBuilder took 1185.52 ms. Allocated memory is still 130.0 MB. Free memory was 97.4 MB in the beginning and 69.8 MB in the end (delta: 27.7 MB). Peak memory consumption was 27.3 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,591 INFO L168 Benchmark]: BuchiAutomizer took 10456.77 ms. Allocated memory was 130.0 MB in the beginning and 385.9 MB in the end (delta: 255.9 MB). Free memory was 69.8 MB in the beginning and 260.4 MB in the end (delta: -190.6 MB). Peak memory consumption was 99.6 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,592 INFO L168 Benchmark]: Witness Printer took 95.15 ms. Allocated memory is still 385.9 MB. Free memory was 260.4 MB in the beginning and 257.2 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:21:55,597 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31 ms. Allocated memory is still 86.0 MB. Free memory is still 42.5 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 707.83 ms. Allocated memory is still 130.0 MB. Free memory was 96.5 MB in the beginning and 103.6 MB in the end (delta: -7.1 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 124.44 ms. Allocated memory is still 130.0 MB. Free memory was 103.6 MB in the beginning and 100.4 MB in the end (delta: 3.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 108.68 ms. Allocated memory is still 130.0 MB. Free memory was 100.4 MB in the beginning and 97.4 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1185.52 ms. Allocated memory is still 130.0 MB. Free memory was 97.4 MB in the beginning and 69.8 MB in the end (delta: 27.7 MB). Peak memory consumption was 27.3 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 10456.77 ms. Allocated memory was 130.0 MB in the beginning and 385.9 MB in the end (delta: 255.9 MB). Free memory was 69.8 MB in the beginning and 260.4 MB in the end (delta: -190.6 MB). Peak memory consumption was 99.6 MB. Max. memory is 16.1 GB. * Witness Printer took 95.15 ms. Allocated memory is still 385.9 MB. Free memory was 260.4 MB in the beginning and 257.2 MB in the end (delta: 3.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 9386 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.2s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 5.4s. Construction of modules took 0.6s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 16 MinimizatonAttempts, 3132 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 1.0s Buchi closure took 0.0s. Biggest automaton had 9386 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 6363 SDtfs, 7434 SDslu, 5941 SDs, 0 SdLazy, 358 SolverSat, 165 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 333]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=13780} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=13780, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55899b22=0, E_3=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@747ae3a9=0, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@435630a3=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c0f0697=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e2bdbe=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@726b2302=0, NULL=13781, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, NULL=13782, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=13783, t2_i=1, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@769fb81b=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7efeec90=0, t2_pc=0, tmp___1=0, T3_E=2, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@608b5ef7=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3ff70016=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b88ec31=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 333]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int E_1 = 2; [L34] int E_2 = 2; [L35] int E_3 = 2; [L689] int __retres1 ; [L602] m_i = 1 [L603] t1_i = 1 [L604] t2_i = 1 [L605] t3_i = 1 [L630] int kernel_st ; [L631] int tmp ; [L632] int tmp___0 ; [L636] kernel_st = 0 [L273] COND TRUE m_i == 1 [L274] m_st = 0 [L278] COND TRUE t1_i == 1 [L279] t1_st = 0 [L283] COND TRUE t2_i == 1 [L284] t2_st = 0 [L288] COND TRUE t3_i == 1 [L289] t3_st = 0 [L410] COND FALSE !(M_E == 0) [L415] COND FALSE !(T1_E == 0) [L420] COND FALSE !(T2_E == 0) [L425] COND FALSE !(T3_E == 0) [L430] COND FALSE !(E_1 == 0) [L435] COND FALSE !(E_2 == 0) [L440] COND FALSE !(E_3 == 0) [L493] int tmp ; [L494] int tmp___0 ; [L495] int tmp___1 ; [L496] int tmp___2 ; [L186] int __retres1 ; [L189] COND FALSE !(m_pc == 1) [L199] __retres1 = 0 [L201] return (__retres1); [L500] tmp = is_master_triggered() [L502] COND FALSE !(\read(tmp)) [L205] int __retres1 ; [L208] COND FALSE !(t1_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L508] tmp___0 = is_transmit1_triggered() [L510] COND FALSE !(\read(tmp___0)) [L224] int __retres1 ; [L227] COND FALSE !(t2_pc == 1) [L237] __retres1 = 0 [L239] return (__retres1); [L516] tmp___1 = is_transmit2_triggered() [L518] COND FALSE !(\read(tmp___1)) [L243] int __retres1 ; [L246] COND FALSE !(t3_pc == 1) [L256] __retres1 = 0 [L258] return (__retres1); [L524] tmp___2 = is_transmit3_triggered() [L526] COND FALSE !(\read(tmp___2)) [L453] COND FALSE !(M_E == 1) [L458] COND FALSE !(T1_E == 1) [L463] COND FALSE !(T2_E == 1) [L468] COND FALSE !(T3_E == 1) [L473] COND FALSE !(E_1 == 1) [L478] COND FALSE !(E_2 == 1) [L483] COND FALSE !(E_3 == 1) [L644] COND TRUE 1 [L647] kernel_st = 1 [L329] int tmp ; Loop: [L333] COND TRUE 1 [L298] int __retres1 ; [L301] COND TRUE m_st == 0 [L302] __retres1 = 1 [L324] return (__retres1); [L336] tmp = exists_runnable_thread() [L338] COND TRUE \read(tmp) [L343] COND TRUE m_st == 0 [L344] int tmp_ndt_1; [L345] tmp_ndt_1 = __VERIFIER_nondet_int() [L346] COND FALSE !(\read(tmp_ndt_1)) [L357] COND TRUE t1_st == 0 [L358] int tmp_ndt_2; [L359] tmp_ndt_2 = __VERIFIER_nondet_int() [L360] COND FALSE !(\read(tmp_ndt_2)) [L371] COND TRUE t2_st == 0 [L372] int tmp_ndt_3; [L373] tmp_ndt_3 = __VERIFIER_nondet_int() [L374] COND FALSE !(\read(tmp_ndt_3)) [L385] COND TRUE t3_st == 0 [L386] int tmp_ndt_4; [L387] tmp_ndt_4 = __VERIFIER_nondet_int() [L388] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 09:21:55,716 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60c54dd7-7167-4d0f-8936-53f63c9a2a8e/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...